Integrated circuit timing power optimization system

Abstract

The application discloses an integrated circuit timing power consumption optimization system and relates to the technical field of power consumption optimization.The system comprises a power supply noise space-time mapping modeling module, a cross-domain drive chain reorganization cancellation module, a dynamic threshold migration control module, a variable impedance return-to-on module and an energy return phase compensation module; the power supply noise space-time mapping modeling module is based on the dynamic coupling characteristics of multiple voltage domains in the integrated circuit, constructs a space-time mapping model of power supply noise propagation, and jointly solves the transient current density distribution and the ground potential gradient distribution of each voltage domain through the space-time mapping model.The application constructs a power supply noise space-time mapping and a drive chain phase reorganization mechanism, realizes dynamic inhibition of voltage reference surface offset and stable control of on-conduction, forms an energy closed loop through a variable impedance and a return-to-on structure, inhibits reverse-phase coupling propagation, and significantly improves the timing stability, anti-interference ability and energy efficiency balance of the integrated circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit power consumption optimization technology, and more specifically to an integrated circuit timing power consumption optimization system. Background Technology

[0002] Integrated circuit timing and power optimization refers to establishing a unified joint modeling, analysis, and closed-loop optimization system for timing and power consumption throughout the entire chip design process, from RTL to back-end convergence, targeting the synergistic optimization goals of performance, power consumption, and area. This process, under multi-condition and multi-corner modeling (MCMM) conditions, comprehensively considers static timing analysis results (such as WNS / TNS, clock skew, crosstalk noise, etc.), power distribution characteristics (including dynamic power consumption, leakage power consumption, activity factor, IR drop, and electromigration hotspots), and physical implementation constraints (such as wiring congestion, cell density, and delay distribution) to accurately locate critical paths and energy hotspots.

[0003] Building upon this foundation, through multiple iterations in the synthesis, placement, clocking, and routing stages, the system employs methods such as gate-level retiming, gate size adjustment and threshold voltage hybrid replacement, clock gating and multi-voltage domain allocation, buffering and foldback strategies, placement rearrangement, and congestion mitigation at the path and region granularity. These are combined with power grid hardening and clock tree shaping to suppress signal integrity and power noise risks. The system relies on heuristic algorithms and machine learning-driven multi-objective search to generate optimized solutions that satisfy equivalence and constraint consistency. Ultimately, through ECO (Engineering Change Optimization), it achieves a balance between timing closure and optimal power consumption, outputting verifiable netlist and layout results, thus realizing comprehensive synergistic optimization of performance, energy efficiency, and area.

[0004] The existing technology has the following shortcomings:

[0005] In the process of optimizing the timing and power consumption of integrated circuits, as the scale of multi-voltage domain designs continues to expand, complex power coupling effects are easily generated in different voltage domains during dynamic operation. When the cross-domain intersection area is simultaneously affected by transient power noise, dynamic load fluctuations, and ground potential drift, the local voltage reference plane will shift nonlinearly, causing the effective drive polarity of some gate-level drive units to momentarily reverse. This phenomenon not only disrupts the logical consistency of the original signal propagation direction but also triggers phase misalignment and edge drift in critical timing links, ultimately leading to unpredictable logic flips. Such problems are sudden and insidious, often triggered during power peak switching or dynamic voltage drop recovery, and are difficult to capture in time by traditional static timing analysis. Once it occurs, it will cause disordered logic link states, abnormal register latches, and disordered signal transmission at the functional level, leading to irreversible collapse of the system's logic level and seriously threatening the timing stability and overall functional reliability of the chip. Summary of the Invention

[0006] The purpose of this invention is to provide an integrated circuit timing and power consumption optimization system to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: an integrated circuit timing power consumption optimization system, including a power supply noise spatiotemporal mapping modeling module, a cross-domain drive chain renormalization cancellation module, a dynamic threshold migration control module, a variable impedance foldback conduction module, and an energy foldback phase compensation module;

[0008] The power supply noise spatiotemporal mapping modeling module constructs a spatiotemporal mapping model for power supply noise propagation based on the dynamic coupling characteristics of multiple voltage domains in integrated circuits. The spatiotemporal mapping model obtains the corresponding voltage reference surface offset distribution by jointly solving the transient current density distribution and ground potential gradient distribution of each voltage domain, which is used to determine the potential triggering region.

[0009] The cross-domain drive chain reorganization and cancellation module reorganizes the drive chain in the potential trigger region according to the voltage reference surface offset distribution, forming a phase conjugate drive cancellation structure, and embeds charge balance nodes in the drive chain to absorb the anti-phase coupling energy caused by the voltage reference surface offset, so as to weaken the cross-domain coupling effect.

[0010] The dynamic threshold migration control module establishes a dynamic threshold migration mechanism based on the energy absorption characteristics of the charge balance node. According to the transient potential changes in the potential trigger region, it adaptively adjusts the threshold voltage range of the driving transistor in real time, so that the driving transistor maintains a stable conduction state during the voltage reference plane offset, thereby maintaining the logic polarity consistency of the driving chain.

[0011] The variable impedance back-turn-on module, based on the stable conduction state formed by the dynamic threshold migration mechanism, sets a variable impedance distribution path in the power network and constructs an adaptive back-turn-on structure, so that the current flow after being adjusted by the charge balance node is concentrated in the local low coupling loop, thereby further weakening the propagation of anti-coupling energy in the power network.

[0012] The energy foldback phase compensation module utilizes the current constraint characteristics of local low-coupling loops to perform a coordinated control process of energy foldback and phase compensation. By dynamically migrating the conduction phase of the drive chain in a nonlinear time grid, it achieves steady-state control in the entire time domain, thereby avoiding logic flips and improving the timing stability and power consumption optimization of the integrated circuit.

[0013] Preferably, the process of constructing a spatiotemporal mapping model of power supply noise propagation includes the following steps:

[0014] For the multi-voltage domain design structure inside the integrated circuit, based on the chip planar layout data, power supply network routing information and the interface positions of different voltage domains, the power distribution path and ground loop of each voltage domain are extracted in layers, the spatial adjacency relationship between voltage domains is established, and a multi-voltage domain power supply topology description is formed.

[0015] After obtaining the power supply path and coupling relationship of each voltage domain, transient features are extracted for the current transmission state of each voltage domain under dynamic operating conditions to obtain the raw data of transient current density distribution and ground potential gradient distribution.

[0016] By jointly analyzing the transient current density distribution and ground potential gradient distribution of multiple voltage domains, dynamic power supply noise coupling regions between adjacent voltage domains are identified, and comprehensive distribution information on the propagation direction of power supply noise and the trend of ground potential drift is obtained.

[0017] Based on the temporal correlation and spatial distribution information obtained from the joint analysis, a spatiotemporal mapping of the power supply noise propagation process is constructed to generate the voltage reference surface offset distribution and determine the potential triggering region for driving polarity reversal.

[0018] Preferably, during the generation of the voltage reference surface offset distribution, the transient current density and ground potential change results of each voltage domain at different time periods are layered and superimposed to form a three-dimensional mapping structure with time as the vertical dimension and spatial distribution as the horizontal dimension. Regions whose offset amplitude exceeds the threshold voltage stability range of the driving transistor are marked to determine the potential triggering region for driving polarity reversal.

[0019] Preferably, the process of embedding a charge balance node in the drive chain to absorb the anti-coupling energy caused by the voltage reference plane offset includes the following steps:

[0020] After obtaining the voltage reference surface offset distribution, the topology of the drive chain in the potential triggering region is analyzed step by step. The drive chain from high voltage domain to low voltage domain and the feedback chain from low voltage domain to high voltage domain in the cross-voltage domain signal path are extracted. The delay relationship of the drive unit and the difference in voltage reference surface position are recorded. High-risk nodes are identified and grouped according to the offset direction.

[0021] After completing the topology identification and grouping of the drive chain, the drive chain in the potential triggering area is restructured. A phase conjugate relationship is established between drive units with opposite offset directions or complementary potential drifts. A phase conjugate drive cancellation structure is constructed, and current compensation is achieved through the conjugate path to offset potential changes.

[0022] After the reconstruction of the phase conjugate drive cancellation structure is completed, a charge balance node is embedded at the location where the potential changes drastically between the main drive path and the conjugate path. This node is used to absorb and release energy when the voltage reference plane shifts, so as to maintain the potential stability and conduction polarity consistency of the drive chain.

[0023] Preferably, the charge balance node is turned on synchronously when the main driving path and the conjugate path are aligned in conduction phase. It achieves energy storage and release through the characteristics of variable capacitor, and forms a buffer potential layer with the low coupling region during the offset phase to block the further propagation of the reverse energy, ensuring that the drive chain maintains a stable conduction state under voltage reference plane fluctuation conditions.

[0024] Preferably, the process of keeping the driving transistor in a stable on-state during voltage reference plane offset includes the following steps:

[0025] Based on the phase conjugate drive cancellation structure and charge balance node, the key drive unit with the largest voltage reference plane offset amplitude and the highest ground potential fluctuation frequency is selected. The charge balance node is electrically coupled to the source and substrate regions of the drive transistor, so that the inverted energy absorbed by the charge balance node is converted into transistor potential compensation.

[0026] A dynamic potential interaction is formed between the charge balance node and the driving transistor. A dynamic threshold migration mechanism is established based on the transient potential change characteristics of the potential trigger region, so that the threshold voltage of the transistor can be dynamically adjusted with the potential change to maintain conduction stability.

[0027] After achieving dynamic migration within the threshold voltage range, the threshold migration characteristics are linked with the energy absorption and release behavior of the charge balance node to form a two-way balance mechanism between energy and threshold, maintaining the consistency of the driving chain signal timing.

[0028] After achieving threshold migration balance, timing correction is performed on the entire drive chain. The conduction phase of the drive unit is adjusted according to the voltage reference plane offset distribution, so that the drive chain maintains stable logic polarity and continuous conduction state during voltage offset.

[0029] Preferably, during the process of forming dynamic potential interaction between the charge balance node and the driving transistor, a controllable potential buffer channel is set to match the charge flow rate with the potential change rate, thereby avoiding conduction delay or conduction surge caused by threshold voltage change, and enabling the driving transistor to maintain continuous conduction and stable threshold migration during voltage reference plane offset.

[0030] Preferably, the process of concentrating the current flow after charge balance node regulation into a local low-coupling loop includes the following steps:

[0031] Under the condition of forming a stable conduction state based on the dynamic threshold migration mechanism, the power supply path and return path of each voltage domain in the power network are identified, the transient conduction resistance is calibrated according to the current direction and amplitude of the driving transistor, and the transient impedance distribution map of the power network is obtained to obtain the impedance distribution characteristics.

[0032] After obtaining the impedance distribution characteristics, a variable impedance distribution path is set in the power supply path and the return path, so that the current automatically adjusts the flow direction during the voltage reference plane offset stage, thereby achieving dynamic balance of current density and suppression of local overload.

[0033] After the variable impedance distribution path is formed, an adaptive foldback conduction structure is established through path reconstruction, so that the current forms a closed foldback loop when it is transmitted across the voltage domain, and energy phase consistency compensation is achieved with the help of charge balance nodes.

[0034] Based on the adaptive foldback conduction structure, the current flow direction is optimized, and the adjusted current is directed to the local low-coupling loop with smaller potential fluctuations, so that the energy is dissipated in the local low-coupling loop and the network's self-inhibition capability is enhanced.

[0035] After the current distribution is concentrated, the loop potential change rate and current phase difference are monitored, and the variable impedance distribution path is finely adjusted to maintain a constant current distribution ratio, thereby achieving spatial suppression and closed-loop control of energy propagation.

[0036] Preferably, the variable impedance distribution path and the adaptive foldback conduction structure are electrically connected through a charge balance node. During the voltage reference plane offset phase, the impedance value is automatically adjusted according to the current phase difference, so that the current flows preferentially to the energy foldback path in the local low coupling loop. During the foldback process, the charge balance node synchronously releases compensation energy to maintain the consistency between the current flow direction and the conduction phase, thereby enhancing the energy closed-loop stability of the power network.

[0037] Preferably, the process of performing coordinated control of energy foldback and phase compensation by utilizing the current constraint characteristics of local low-coupling loops includes the following steps:

[0038] In the established local low-coupling loop, the current propagation boundary and phase distribution law of the energy return path are determined based on its current constraint characteristics, and the current phase change sequence and phase difference distribution are recorded to form the energy return propagation rhythm.

[0039] After obtaining the phase distribution law of the low-coupling loop, an active energy return control process is executed to match the transient energy with the conduction period of the drive chain. The phase-reverse current pulse is used to cancel the local potential change and achieve dynamic balance of energy flow.

[0040] After the energy return process stabilizes, phase compensation control is executed to align the drive chain conduction phase with the return energy phase delay. The conduction timing is dynamically adjusted through the phase delay control unit to keep the signal propagation phase synchronized with the energy propagation phase.

[0041] After the energy return and phase compensation are completed in coordination, the nonlinear time grid is used to dynamically migrate the driving chain to turn on the phase, so that the driving polarity of the cross-voltage domain intersection region remains in a steady state throughout the entire time domain, thereby realizing the dynamic coordinated control of signal transmission and energy compensation.

[0042] In the above technical solution, the technical effects and advantages provided by the present invention are as follows:

[0043] This invention establishes a spatiotemporal mapping model for power supply noise propagation and a phase conjugate renormalization mechanism for cross-domain drive chains under dynamic multi-voltage domain operating conditions, enabling real-time quantification and dynamic suppression of voltage reference plane offset characteristics. In this system, the energy absorption of charge balance nodes and the adaptive shift of drive thresholds form a closed-loop response, allowing power supply noise to be locally absorbed and canceled in the early stages of propagation, avoiding drive polarity reversal caused by transient offset accumulation. This achieves spatial constraints on potential fluctuations across multiple voltage domains and proactive maintenance of timing stability, ensuring the chip maintains consistency in logic conduction direction and reliability of signal propagation even during high-power switching phases.

[0044] This invention achieves directional foldback and energy self-balancing control of anti-phase coupled energy through the synergistic effect of a variable impedance distribution path and an adaptive foldback conduction structure. The low-coupling loop forms an energy-constrained closed loop across the entire time domain, ensuring dynamic consistency between the current flow direction and the drive phase. This physically suppresses the spread of power supply noise and logic phase drift, effectively improving the anti-interference performance and timing stability of the integrated circuit under dynamic power consumption fluctuations. Simultaneously, it reduces the energy loss of the drive chain, achieving synergistic optimization of performance, power consumption, and stability. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0046] Figure 1 This is a schematic diagram of the integrated circuit timing and power consumption optimization system of the present invention.

[0047] Figure 2 This is a flowchart of the integrated circuit timing and power consumption optimization system of the present invention.

[0048] Figure 3 The flowchart illustrates the construction of a spatiotemporal mapping model for power supply noise propagation in this invention.

[0049] Figure 4 The flowchart illustrates the process of establishing a dynamic threshold migration mechanism to maintain a stable conduction state of the driving transistor during voltage reference plane offset. Detailed Implementation

[0050] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0051] This invention provides, for example Figures 1 to 4 The integrated circuit timing power optimization system shown includes a power noise spatiotemporal mapping modeling module, a cross-domain drive chain renormalization cancellation module, a dynamic threshold migration control module, a variable impedance foldback conduction module, and an energy foldback phase compensation module.

[0052] The power supply noise spatiotemporal mapping modeling module constructs a spatiotemporal mapping model for power supply noise propagation based on the dynamic coupling characteristics of multiple voltage domains in integrated circuits. The spatiotemporal mapping model obtains the corresponding voltage reference surface offset distribution by jointly solving the transient current density distribution and ground potential gradient distribution of each voltage domain, which is used to determine the potential triggering region for driving polarity reversal.

[0053] The voltage reference surface offset distribution is obtained by jointly solving the transient current density distribution and ground potential gradient distribution in each voltage domain. The specific implementation steps are as follows:

[0054] For multi-voltage domain design structures within integrated circuits, based on the chip's planar layout data, power supply network routing information, and interface locations between different voltage domains, the power distribution paths and ground loops of each voltage domain are extracted hierarchically. The specific process includes: dividing the entire chip's power network into several independent voltage domain power supply regions, each region containing corresponding power supply lines, ground lines, load logic units, and cross-domain interface nodes. Then, the electrical paths from power supply pins to load logic units in each voltage domain are extracted, and the series resistance, parasitic inductance, and geometric positions of interconnecting conductors on each path are recorded. Next, based on the shared ground regions and intersecting power paths between different voltage domains, spatial adjacency relationships between voltage domains are established, clarifying the range of potential dynamic coupling. By calibrating the boundaries of these coupling regions, a complete multi-voltage domain power supply topology description is formed. After this step, spatial layout data reflecting the physical distribution and electrical interconnection relationships of each voltage domain can be obtained, providing an accurate boundary basis for subsequent dynamic characteristic calculations.

[0055] After obtaining the power supply paths and coupling relationships of each voltage domain, transient features are extracted for the current transmission state of each voltage domain under dynamic operating conditions. Specifically, this includes selecting multiple representative logic load nodes within the voltage domain, statistically analyzing their instantaneous current change trends under typical operating conditions, and calculating the current distribution of the region at different time points based on the operating clock, load switching frequency, and logic flip density. Simultaneously, the spatial distribution of the ground network is analyzed, identifying each grounding point, cross-layer connection point, and shared return path to determine the relative differences in ground potential between different regions. Then, the intersection areas between voltage domains are highlighted, recording the shared length of ground connections, conductor width, and electrical contact area with adjacent domains within these areas for subsequent assessment of ground potential shift sensitivity. By simultaneously extracting the transient current change trends and ground distribution patterns of different voltage domains, raw data on transient current density distribution and ground potential gradient distribution can be obtained, providing input conditions for dynamic coupling characteristic analysis.

[0056] Building upon the aforementioned approach, a joint analysis of transient current density distributions and ground potential gradient distributions across multiple voltage domains is performed to construct the temporal and spatial propagation characteristics of power supply noise. Specifically, within each voltage domain, the direction and amplitude of transient current density changes are tracked sequentially over time, while simultaneously recording the relative changes in ground potential within the corresponding time period. By comparing the current change directions and ground potential drift directions across different voltage domains, regions exhibiting opposite trends between adjacent voltage domains are identified, determining the potential conditions for dynamic power supply noise coupling. Next, the temporal overlap intervals of transient current changes in adjacent voltage domains are compared to identify regions where current fluctuations overlap across multiple voltage domains within the same time period; these regions typically correspond to the paths where power supply noise propagation is most intense. Simultaneously, the spatial orientation of the shared ground wire region is analyzed to ensure consistency with the current flow direction. If a local potential increase occurs in the ground wire segment under conditions of reverse current flow, it indicates a potential risk of ground reference drift at that location. Through the joint comparison of the aforementioned temporal overlap characteristics and spatial orientation relationships, comprehensive distribution information on the propagation direction of power supply noise and the trend of ground potential drift can be obtained. This process transforms the coupling behavior between multiple voltage domains from a static topological relationship into dynamic propagation characteristics, allowing the propagation path of power supply noise and the ground potential offset region to be clearly presented throughout the chip space.

[0057] Finally, based on the temporal correlation and spatial distribution information obtained from the joint analysis, a spatiotemporal mapping of the power supply noise propagation process is constructed to generate the voltage reference surface offset distribution. The specific implementation process includes: layering and superimposing the transient current density and ground potential change results at different time periods within each voltage domain, using time as the vertical dimension and spatial distribution as the horizontal dimension to form a three-dimensional mapping structure. Each location point in the mapping structure corresponds to the voltage reference surface offset value of a specific region in a voltage domain at a specific time. By performing continuity analysis on these voltage reference surface offset values, regions with drastic offset changes, long durations, or propagation paths spanning multiple voltage domains can be identified. Within these regions, due to the superposition effect of the power supply noise propagation path and the ground potential drift direction, the voltage reference surface is prone to nonlinear offset, leading to a temporary decrease or even a reverse change in the effective driving voltage of the driving unit. Therefore, in the mapping model, regions with offset amplitudes exceeding the threshold voltage stability range of the driving transistor are marked as potential trigger regions, and by combining their offset duration with the coupling direction of adjacent regions, the path range where offset energy may concentrate and propagate is further determined. Through this process, a voltage reference surface offset distribution with temporal continuity and spatial resolution can be obtained. This distribution intuitively reflects how power supply noise propagation causes nonlinear offset of the voltage reference surface and the concentrated area of ​​drive polarity reversal risk during the multi-voltage domain dynamic operation phase.

[0058] By implementing the above steps, precise reconstruction of power supply noise propagation behavior can be achieved in multi-voltage domain integrated circuits, fundamentally revealing the formation mechanism of voltage reference plane offset under dynamic coupling conditions. This specific implementation, through hierarchical division of the multi-voltage domain power supply network, joint analysis of transient electrical characteristics, and visual mapping of voltage reference plane offset, can identify high-risk regions of drive polarity reversal in advance during the chip design stage, effectively improving the timing stability and power consumption optimization capabilities of integrated circuits in complex power supply environments.

[0059] The cross-domain drive chain reorganization and cancellation module reorganizes the cross-voltage domain drive chain structure in the potential trigger region according to the voltage reference surface offset distribution, forming a phase conjugate drive cancellation structure, and embeds a charge balance node in the drive chain. The charge balance node is used to absorb the anti-phase coupling energy caused by the voltage reference surface offset, so as to weaken the cross-domain coupling effect.

[0060] A charge balancing node is embedded in the driving chain to absorb the anti-coupling energy caused by the voltage reference plane offset. The specific implementation steps are as follows:

[0061] After obtaining the voltage reference plane offset distribution, the topology of the drive chain within the potential trigger region is analyzed step-by-step to clarify the conduction characteristics of the signal drive path in the voltage domain intersection region. The specific process includes: within the potential trigger region, extracting the logic drive chains that conduct from the high voltage domain to the low voltage domain and the reverse drive chains that feed back from the low voltage domain to the high voltage domain in the cross-voltage domain signal paths. Each drive chain's constituent units are analyzed step-by-step, recording the number of drive units, inter-stage delay relationships, the positional differences between the input and output terminals on the voltage reference plane, and the sensitivity of each unit to power supply offset. For drive units located at the boundary of the intersection region, the relative offset magnitudes of their input and output terminals between different voltage reference planes are further identified, determining these units as high-risk nodes in the offset distribution. Subsequently, based on the spatial distribution pattern of the voltage reference plane offset, these high-risk nodes are grouped according to the offset direction, ensuring that the voltage reference offset change direction of each group of drive chain units is relatively consistent, providing a basis for subsequently establishing phase conjugate relationships. This step clarifies the offset-sensitive distribution of the driving chain within the potential triggering region and the correspondence between the driving signal propagation direction and the reference potential change, thus providing precise positioning for subsequent structural realignment.

[0062] After identifying and grouping the drive chain topology, the drive chains within the potential trigger region are restructured to form a phase conjugate drive cancellation structure. Specifically, a phase conjugate relationship is established between each group of drive chain units with opposite offset directions or complementary potential drift trends. Specifically, one drive path is designated as the main drive path, and the other, with opposite spatial location or signal direction, is designated as the conjugate path, ensuring that the two paths are in antiphase conduction in the logic signal propagation direction and maintain relative physical distribution. Subsequently, a charge transfer channel is established between the relative nodes of the two paths, enabling the conjugate path to generate opposite drive responses when the voltage reference plane shifts. Thus, when the main drive path experiences a transient reverse drive trend due to voltage reference plane shift, the conjugate path, through its antiphase conduction characteristics, immediately generates current compensation opposite to the offset direction, thereby canceling the potential jump in the main path caused by the reference plane change. To ensure the synchronicity of the compensation process, the conduction delay of each drive unit in the conjugate path is finely adjusted to keep its conduction phase consistent with that of the main path, thereby forming an electrically symmetrical response during the transient phase of power supply noise propagation. Through the above structural remodeling, the cross-voltage domain drive chain can form a dynamic equilibrium structure under voltage reference plane offset conditions, so that the anti-phase energy caused by the offset is instantly canceled, significantly weakening the cross-domain coupling effect.

[0063] After reconstructing the phase conjugate drive cancellation structure, charge balancing nodes are embedded at key nodes of the drive chain to balance the absorption and release of anti-phase coupling energy caused by voltage reference plane offset. Specifically, a charge balancing node is set at the intersection of the main drive path and the conjugate path where the potential change is most drastic. This node absorbs excess local charge and releases it to adjacent paths when the voltage reference plane shifts. The charge balancing node consists of electrical units with variable capacitance and conduction delay adjustment characteristics. During the transient phase, when the main path potential suddenly rises due to the offset, the charge balancing node immediately enters a charging state, temporarily storing excess energy. During the offset recovery phase, the stored energy is released evenly through the conjugate path, thus achieving bidirectional balanced conduction of anti-phase energy. To ensure the timing coordination of energy conduction, conduction adjustment units are set on both sides of the charge balancing node, enabling them to turn on synchronously when the conduction phases of the main path and the conjugate path are aligned, ensuring that no additional phase offset occurs during energy absorption and release. Furthermore, when the voltage reference plane offset lasts for a long period, the charge balance node forms a stable buffer potential layer through potential interaction with the surrounding low-coupling region, effectively blocking the propagation of reverse energy to more distant regions, thereby creating an electrical isolation effect in physical space. This step not only achieves instantaneous absorption and directional release of reverse energy, but also maintains the overall potential stability of the cross-voltage domain drive chain through the dynamic response characteristics of the balance node, ensuring that the drive polarity maintains a constant conduction direction under voltage reference plane fluctuations.

[0064] Through the specific implementation of the above steps, the structural reorganization of the cross-voltage domain drive chain, the establishment of phase conjugate drive cancellation relationship, and the embedding of charge balance node are completed in the potential trigger region. This enables the drive chain to actively absorb and compensate for anti-phase coupling energy in a dynamic offset environment. It not only effectively eliminates the risk of drive polarity reversal caused by voltage reference plane offset, but also enables the cross-voltage domain drive chain to have self-recovery and self-suppression capabilities through the construction of electrical symmetry structure and the introduction of charge balance mechanism. This significantly improves the logic consistency and power supply coupling stability of drive signal in the multi-voltage domain dynamic operation stage.

[0065] The dynamic threshold migration control module establishes a dynamic threshold migration mechanism based on the energy absorption characteristics of the charge balance node. According to the transient potential changes in the potential trigger region, it adaptively adjusts the threshold voltage range of the driving transistor in real time, so that the driving transistor maintains a stable conduction state during the voltage reference plane offset, thereby maintaining the logic polarity consistency of the driving chain.

[0066] A dynamic threshold migration mechanism is established to ensure that the driving transistor remains in a stable on-state during voltage reference plane shift. The specific implementation steps are as follows:

[0067] Based on the established phase conjugate drive cancellation structure and charge balance node, the key drive unit with the largest voltage reference plane offset and the highest ground potential fluctuation frequency is selected as the control object of the dynamic threshold migration mechanism within the drive chain in the potential trigger region. Through electrical coupling between the charge balance node and the source and substrate regions of the drive transistor, the inverted energy absorbed by the charge balance node during the transient phase is converted into a dynamic electric field that can be used to adjust the potential of the drive transistor. When the voltage reference plane offset causes a decrease in the effective gate-source voltage difference of the drive transistor, the energy stored in the charge balance node is immediately released to the transistor substrate region, rapidly compensating for the local potential and thus raising the effective gate voltage difference of the transistor, preventing it from entering the cutoff state due to a drop in drive potential. This process achieves direct linkage between the charge balance node and the transistor threshold characteristics, enabling the drive unit to maintain a stable initial response under offset conditions.

[0068] After establishing dynamic potential interaction between the charge balance node and the driving transistor, a dynamic threshold migration mechanism is further established based on the transient potential change characteristics within the potential trigger region. Specifically, a coupled electric field region capable of sensing potential changes is formed around the driving transistor. When the voltage reference plane experiences a nonlinear rise, the potential difference between the transistor substrate and the charge balance node increases, triggering an automatic decrease in the threshold voltage. When the voltage reference plane shifts in the opposite direction, the substrate potential decreases while the threshold voltage increases, thus maintaining constant conduction capability in both directions of potential change. To ensure the continuity of this threshold migration process, a controllable potential buffer channel is designed between the charge balance node and the substrate of the driving transistor, matching the charge flow rate with the potential change rate to prevent conduction delay or overshoot caused by sudden threshold voltage changes. Through this process, the threshold voltage range of the driving transistor is no longer fixed to a single static value, but rather forms a dynamically adjustable threshold range under transient offset, ensuring stable conduction of the transistor during voltage reference plane fluctuations.

[0069] After achieving dynamic migration within the threshold voltage range of the driving transistor, this migration characteristic is further linked with the energy absorption and release behavior of the aforementioned charge balance node to achieve a bidirectional coupling balance between energy and threshold. Specifically, when the voltage reference plane shift causes an increase in energy storage in the charge balance node, the node outputs some potential compensation energy to the substrate region of the driving transistor, causing the threshold voltage of the transistor to shift downward, ensuring its normal conduction under low potential shift conditions. When the voltage reference plane recovers or shifts in the reverse direction, the threshold voltage of the driving transistor shifts upward as the substrate potential recovers, preventing excessive current conduction that could lead to reverse leakage. Simultaneously, in the driving chain branches on both sides of the charge balance node, conduction delay matching ensures that the time response of the threshold migration is consistent with the timing of energy release, forming a dynamic closed-loop self-balancing mechanism. This closed-loop process ensures that the driving transistor will neither turn off prematurely nor overconduct due to an excessively low threshold throughout the entire shift period, maintaining the timing consistency of the rising and falling edges of the driving chain signal, thereby maintaining the stability of the logic polarity.

[0070] After achieving dynamic threshold voltage shift and energy balance, the entire drive chain undergoes timing correction to ensure the continuity and phase consistency of logic transmission. Specifically, in the potential trigger region, all drive transistors with threshold shift characteristics are arranged in layers. The region with the strongest potential fluctuation in the voltage reference plane offset distribution is designated as the correction reference layer, and the potential change of this layer serves as the time reference for threshold shift. Then, based on the conduction phase difference between adjacent drive units in different voltage domains, the response start point of their threshold shift is finely adjusted step by step, enabling each drive unit to synchronously enter the conduction balance state when voltage reference plane shift occurs. To avoid current surges caused by inconsistencies in threshold adjustment between different voltage domains, a conduction damping structure is introduced in the cross-domain boundary region to smooth the current transition. After this stage of calibration, the entire drive chain can form a continuous conduction path during the dynamic process of voltage reference plane shift. The logic polarity of the drive signal remains strictly consistent across different voltage domains, maintaining the correct propagation direction and phase synchronization of the logic signal even during instantaneous ground potential drift or power consumption surges.

[0071] Through the continuous implementation of the above steps, this invention realizes a dynamic threshold migration mechanism based on charge balance nodes, enabling the driving transistor to automatically adjust the threshold voltage range during voltage reference plane shift, thereby maintaining stable conduction and consistency of logic polarity. This process not only effectively suppresses the driving instability caused by reference potential drift in the multi-voltage domain intersection region, but also achieves adaptive compensation for the impact of power supply noise at the device level, enabling the driving chain to have self-adjustment and self-stabilization capabilities in dynamic working environments.

[0072] The variable impedance back-turn-on module, based on the stable conduction state formed by the dynamic threshold migration mechanism, sets a variable impedance distribution path in the power network and constructs an adaptive back-turn-on structure, so that the current flow after being adjusted by the charge balance node is concentrated in the local low coupling loop, thereby further weakening the propagation of anti-coupling energy in the power network.

[0073] The specific steps to concentrate the current flow after adjustment by the charge balance node into a local low-coupling loop are as follows:

[0074] Under the premise of establishing a stable conduction state based on a dynamic threshold migration mechanism, the main power supply paths and return paths of each voltage domain in the power network are re-identified and their electrical characteristics are calibrated. Specifically, by detecting the current conduction direction and current amplitude of the driving transistor in the offset stable state, the dominant energy transfer path in each voltage domain is determined, and the transient on-resistance value of this path is calibrated based on the potential difference and conduction duration between upstream and downstream nodes of the driving chain. Simultaneously, the branch currents connected to the charge balance node are tracked to clarify the direction of the current formed by charge release under voltage reference plane offset conditions and its distribution ratio in the power network. Through comprehensive analysis of this information, a transient impedance distribution map of the power network under dynamic conduction conditions can be obtained, thereby determining which regions have high electrical coupling and which regions are current concentration areas. This step provides a foundation for subsequent variable impedance distribution path settings, enabling the power network to structurally redistribute current flow.

[0075] After obtaining the transient impedance distribution characteristics of the power network, variable impedance distribution paths are set in the main power supply and return paths of each voltage domain to dynamically guide the current flow. The specific implementation process is as follows: adjustable electrical conduction units are introduced at key locations in the power supply and return paths. By controlling the range of their on-resistance variation, the path automatically adjusts its impedance during voltage reference plane offset phases. When the potential in a certain region of the power network rises due to offset, causing local current accumulation, the variable impedance distribution path in that region automatically increases its impedance value to weaken the current accumulation effect; conversely, when the potential drops, causing current sparseness, the impedance path automatically decreases its impedance to enhance current conduction capability. In this way, a self-balancing impedance distribution is formed between different regions, making the current density tend to be uniform throughout the power network. Simultaneously, the variable impedance distribution path maintains an electrical connection with the charge balance node. When the charge balance node releases energy, its output current preferentially flows through the path with lower impedance, thereby achieving real-time adjustment of the current flow direction. This step transforms the conduction characteristics of the power network from static distribution to dynamic controllability, ensuring a more orderly energy flow during the offset phase and avoiding local current overload and ground potential abrupt changes.

[0076] After the variable impedance distribution path is formed, an adaptive foldback conduction structure is established through electrical reconfiguration between paths. This allows the current to form a stable foldback loop during propagation, thus avoiding the reverse diffusion caused by large-scale energy propagation along a straight path. Specifically, the current conduction path between the high-voltage and low-voltage domains is reorganized by forming a ring-shaped electrical connection between path nodes, allowing the current to partially fold back to the low-coupling region during cross-domain transmission. Spatially, this foldback structure exhibits an arc-shaped return of current flow, and electrically, it exhibits local self-limitation of energy transmission. To ensure the sustainability of the foldback conduction, multiple potential balancing nodes are introduced into the ring path to maintain a gradual change in the potential distribution within the loop, preventing the formation of high-potential abrupt change regions. The charge balancing nodes act as energy bridges in this structure. When the main path current flows through the foldback region, the charge balancing nodes can absorb or release some energy through a potential exchange mechanism, ensuring that the current phase in the foldback path remains consistent with the main path. By implementing this step, the cross-voltage domain current no longer propagates unidirectionally in the power network, but forms a controllable closed energy circulation path, thereby effectively limiting the conduction range of anti-coupling energy.

[0077] Based on the established adaptive foldback conduction structure, the concentrated current flow direction in low-coupling loops is further optimized, allowing the current regulated by the charge balancing node to preferentially flow to low-noise, low-potential-drift regions, achieving regionalized energy distribution. Specifically, local loops with low coupling and small potential fluctuations are identified in the power network, such as branch regions located between different voltage domain boundaries but not directly overlapping with the main current path. The end of the foldback structure is directed to these regions, allowing the regulated current to circulate in closed loops within these low-coupling loops. Due to the high potential stability of these loops, when reverse-phase energy flows in, it is quickly dissipated into balancing current, thus weakening the back propagation of coupled energy. Simultaneously, the charge balancing node acts as an energy buffer in the low-coupling loops, creating a phase difference between energy absorption and release, resulting in flexible current flow characteristics—rapid response during high-potential fluctuations and slow return in steady state—thereby improving the overall power network's self-suppression capability against noise disturbances. This process concentrates current energy in locally stable loops, forming a natural electrical buffer zone and providing spatial isolation to prevent reverse coupling.

[0078] It should be noted that:

[0079] Low-coupling loops refer to local closed current loops in a power network that have low electrical coupling to major current paths, voltage domain boundaries, or high-noise areas, experience less potential fluctuation, and are generally more stable. These loops are typically located outside the voltage domain boundary region and do not directly carry large current switching. Therefore, when transient power supply noise or ground potential drift occurs, their potential changes are smoother and they are less susceptible to strong coupling interference. Due to this inherent low-coupling characteristic, current propagation is more stable and phase disturbances are smaller, making them ideal as buffers for energy foldback and phase compensation. This allows the current, after being regulated by the charge balance node, to loop in a closed loop, thereby blocking the diffusion of reverse-phase energy to sensitive areas and enhancing the overall stability of the power supply and timing.

[0080] After the current distribution is concentrated in the low-coupling loop, the energy propagation state of the entire power network is adaptively balanced to ensure stable operation of the foldback conduction structure under dynamic conditions. Specifically, by monitoring the potential change rate and current phase difference in different loops, the resistance distribution of the variable impedance distribution path is finely adjusted to keep the current distribution ratio between the foldback path and the main conduction path constant. Simultaneously, a conduction delay control node is set at the loop junction to adjust the phase matching of energy flow, ensuring that the current propagating in the loop does not superimpose interference with the main path current. After continuous adjustment, the foldback conduction structure can maintain a low-impedance closed state throughout the entire cycle of power noise propagation, allowing the reverse-phase energy to be absorbed and dissipated locally without spreading to other voltage domains. Ultimately, the power network forms a multi-level, distributed energy circulation system, in which high-frequency transient energy is locally absorbed by the foldback structure, and low-frequency energy is evenly distributed in the variable impedance distribution path, thereby achieving spatial suppression and energy loop closure of power noise propagation as a whole.

[0081] This step, based on the dynamic threshold migration mechanism to form a stable conduction state, realizes the adaptive reconstruction of current flow direction and the directional foldback of reverse energy in the power network. It transforms the electrical coupling between voltage domains from open propagation to closed-loop dissipation, which not only significantly reduces the propagation intensity of reverse energy in the power network, but also effectively suppresses transient interference caused by voltage reference plane offset through the local energy concentration effect of low coupling loop. This improves the power stability, timing consistency and overall energy efficiency of integrated circuits under dynamic operation in multiple voltage domains.

[0082] The energy foldback phase compensation module utilizes the current constraint characteristics of the low-coupling loop to perform a coordinated control process of energy foldback and phase compensation. By dynamically migrating the conduction phase of the drive chain in the nonlinear time grid, it achieves full-time steady-state control of the drive polarity across the voltage domain intersection region, thereby avoiding logic flips and improving the timing stability and power consumption optimization of the integrated circuit.

[0083] By utilizing the current constraint characteristics of the low-coupling loop, a coordinated control process of energy foldback and phase compensation is executed. The specific implementation steps are as follows:

[0084] In the established low-coupling loop, its current constraint characteristics are utilized to determine the current propagation boundary and phase distribution law of the energy return path. Specifically, by analyzing the current density change of the low-coupling loop under voltage reference plane offset, the dominant direction of current flow and the boundary of the energy return region in the loop are identified. The low-coupling loop is usually located in the outer region of the cross-voltage domain current return path, with high conduction impedance but small potential fluctuation amplitude, thus serving as a buffer for energy return. In this stage, the sequence of current phase changes and phase difference distribution at different locations in the loop are recorded to clarify the phase delay law within the energy return path. When the charge balance node releases energy into the loop, a set of phase-lagging current trains is formed in the low-coupling loop, exhibiting energy return layer by layer in space and gradual delay in time. Through this analysis, the effective range of energy return can be defined in the spatial dimension, and the propagation rhythm of the returned energy can be determined in the temporal dimension, providing a synchronization reference for subsequent phase compensation and conduction migration. This step couples the energy return process with the current constraint characteristics, providing a physical basis for forming a controllable energy feedback path.

[0085] After obtaining the current phase distribution pattern of the low-coupling loop, an active energy foldback control process is executed to match the transient energy in the power network with the conduction cycle of the drive chain in time. Specifically, at the starting point of the foldback path, the phase triggering sequence of each conducting node in the loop is adjusted according to the time sequence of energy release from the charge balance node, allowing energy foldback to gradually transfer from areas with high current density to areas with sparse current. Thus, when power supply noise propagation causes a brief potential rise in a certain area, the energy compensation flow in the foldback path can form a current pulse with a reverse phase in time, thereby offsetting the effect of local potential abrupt changes. Simultaneously, as the folded energy is transferred step-by-step within the loop, its current amplitude gradually decreases, and its phase lag gradually increases, thus forming an energy diffusion gradient from high-potential to low-potential regions in space. The existence of this gradient allows energy to be gradually absorbed and dissipated during the foldback process without forming new anti-coupling sources. Through this process, the energy return path and the current constraint effect of the low-coupling loop are combined to achieve an adaptive balance of energy flow in the power network, so that energy compensation and potential fluctuations are in a dynamic state of mutual cancellation, providing a stable electrical environment for the phase synchronization of the subsequent drive chain.

[0086] After stable conduction is achieved during the energy return process, phase compensation control is further implemented to keep the conduction phase of the drive chain dynamically synchronized with the energy return phase under dynamic voltage reference plane offset conditions. Specifically, the conduction phase of each stage of the drive chain is aligned with the phase delay of energy propagation in the return path. When the returned energy enters a certain voltage domain boundary, the conduction phase of the drive unit in that voltage domain immediately generates corresponding delay compensation, thereby ensuring that the signal propagation phase is consistent with the energy propagation phase. To achieve this synchronization, a phase delay control unit is introduced at the key nodes of the drive chain. This unit dynamically adjusts the conduction timing of the corresponding drive unit by detecting the transient offset direction and magnitude of the voltage reference plane. When the voltage reference plane rises, the conduction phase of the drive unit is slightly advanced to offset the delay effect caused by the offset; when the voltage reference plane falls, the conduction phase is correspondingly delayed to avoid logic overlap caused by premature conduction. This process establishes a mutually compensating relationship between the drive signal and the folded-back energy in the time dimension. Specifically, when the energy folded-back wave lags behind signal propagation, synchronization is achieved by advancing the conduction phase; when the energy folded-back wave leads, balance is maintained through phase delay. Ultimately, a time-locked state is formed between the drive chain and the energy folded-back loop, ensuring that signal transmission and energy compensation across voltage domain intersections are always dynamically coordinated, preventing signal phase misalignment and energy overshoot.

[0087] After the energy return and phase compensation are completed in tandem, steady-state control of the drive phase across voltage domain intersection regions is achieved by dynamically migrating the conduction phase of the drive chain within a nonlinear time grid. Specifically, the phase compensation result is mapped onto a time grid, and the grid spacing is dynamically adjusted based on the nonlinear variation of the voltage reference plane offset. In voltage domain intersection regions, due to the nonlinear superposition of ground potential drift and power consumption changes, traditional linear time-stepping methods cannot maintain conduction stability. However, through a nonlinear time grid migration mechanism, the conduction phase migration step size can be automatically adjusted according to the potential change rate in different regions. When a rapid potential change occurs in a voltage domain, the corresponding time grid is locally compressed, causing the drive unit's conduction phase to migrate rapidly to follow the potential change. When the potential returns to stability, the time grid spacing is stretched, allowing the drive phase to gradually return to the stable range. Through this dynamic migration method, the drive chain forms a continuous conduction phase band between different voltage domain intersection regions, ensuring that the signal propagation direction and drive polarity remain consistent throughout the entire time domain. Meanwhile, the low-coupling loop continuously provides energy support and a phase reference through current constraint, ensuring steady-state operation throughout the conduction process even under dynamic offset conditions. This step achieves full-time domain control of the drive polarity, effectively suppressing logic flips and enabling dynamic energy recovery and balancing at the power consumption optimization level, thus ensuring stable timing characteristics of the integrated circuit under high load and multi-domain coupling conditions.

[0088] This process utilizes the current constraint characteristics of low-coupling loops to construct a time- and energy-dimensional adaptive control mechanism through the synergistic effect of energy foldback and phase compensation. This mechanism enables the cross-voltage domain drive chain to maintain full-time stability of logic conduction polarity in the environment of dynamic power supply noise and ground potential drift. It not only suppresses anti-phase coupling at the energy transfer level but also establishes a real-time correspondence between signal propagation and potential changes at the timing control level. This ensures that the drive chain maintains phase continuity and conduction consistency throughout the entire operating cycle, fundamentally avoiding logic flipping and register misalignment problems.

[0089] This invention establishes a spatiotemporal mapping model for power supply noise propagation and a phase conjugate renormalization mechanism for cross-domain drive chains under dynamic multi-voltage domain operating conditions, enabling real-time quantification and dynamic suppression of voltage reference plane offset characteristics. In this system, the energy absorption of charge balance nodes and the adaptive shift of drive thresholds form a closed-loop response, allowing power supply noise to be locally absorbed and canceled in the early stages of propagation, avoiding drive polarity reversal caused by transient offset accumulation. This achieves spatial constraints on potential fluctuations across multiple voltage domains and proactive maintenance of timing stability, ensuring the chip maintains consistency in logic conduction direction and reliability of signal propagation even during high-power switching phases.

[0090] This invention achieves directional foldback and energy self-balancing control of anti-phase coupled energy through the synergistic effect of a variable impedance distribution path and an adaptive foldback conduction structure. The low-coupling loop forms an energy-constrained closed loop across the entire time domain, ensuring dynamic consistency between the current flow direction and the drive phase. This physically suppresses the spread of power supply noise and logic phase drift, effectively improving the anti-interference performance and timing stability of the integrated circuit under dynamic power consumption fluctuations. Simultaneously, it reduces the energy loss of the drive chain, achieving synergistic optimization of performance, power consumption, and stability.

[0091] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. An integrated circuit timing and power consumption optimization system, characterized in that, It includes a power supply noise spatiotemporal mapping modeling module, a cross-domain drive chain renormalization cancellation module, a dynamic threshold migration control module, a variable impedance foldback conduction module, and an energy foldback phase compensation module; The power supply noise spatiotemporal mapping modeling module constructs a spatiotemporal mapping model for power supply noise propagation based on the dynamic coupling characteristics of multiple voltage domains in integrated circuits. The spatiotemporal mapping model obtains the corresponding voltage reference surface offset distribution by jointly solving the transient current density distribution and ground potential gradient distribution of each voltage domain, which is used to determine the potential triggering region. The cross-domain drive chain reorganization and cancellation module reorganizes the drive chain in the potential trigger region according to the voltage reference surface offset distribution, forming a phase conjugate drive cancellation structure, and embeds charge balance nodes in the drive chain to absorb the anti-coupling energy caused by the voltage reference surface offset. The dynamic threshold migration control module establishes a dynamic threshold migration mechanism based on the energy absorption characteristics of the charge balance node. According to the transient potential changes in the potential trigger region, it adaptively adjusts the threshold voltage range of the driving transistor in real time, so that the driving transistor maintains a stable conduction state during the voltage reference plane offset. The variable impedance foldback conduction module sets a variable impedance distribution path in the power network based on the formed stable conduction state and constructs an adaptive foldback conduction structure so that the current flow after being regulated by the charge balance node is concentrated in the local low coupling loop. The energy return phase compensation module utilizes the current constraint characteristics of local low-coupling loops to perform a coordinated control process of energy return and phase compensation. By dynamically migrating the conduction phase of the drive chain in a nonlinear time grid, it achieves steady-state control in the entire time domain.

2. The integrated circuit timing and power consumption optimization system according to claim 1, characterized in that, The process of constructing a spatiotemporal mapping model for power supply noise propagation includes: For the multi-voltage domain design structure inside the integrated circuit, the power distribution path and ground loop of each voltage domain are extracted in layers, the spatial adjacency relationship between voltage domains is established, and a multi-voltage domain power supply topology description is formed. After obtaining the power supply path and coupling relationship of each voltage domain, transient features are extracted for the current transmission state of each voltage domain under dynamic operating conditions to obtain the raw data of transient current density distribution and ground potential gradient distribution. By jointly analyzing the transient current density distribution and ground potential gradient distribution of multiple voltage domains, dynamic power supply noise coupling regions between adjacent voltage domains are identified, and comprehensive distribution information on the propagation direction of power supply noise and the trend of ground potential drift is obtained. Based on the temporal correlation and spatial distribution information obtained from the joint analysis, a spatiotemporal mapping of the power supply noise propagation process is constructed to generate the voltage reference surface offset distribution and determine the potential triggering region for driving polarity reversal.

3. The integrated circuit timing and power consumption optimization system according to claim 2, characterized in that, In the process of generating the voltage reference plane offset distribution, the transient current density and ground potential change results of each voltage domain at different time periods are superimposed in layers to form a three-dimensional mapping structure with time as the vertical dimension and spatial distribution as the horizontal dimension. The regions where the offset amplitude exceeds the threshold voltage stability range of the driving transistor are marked to determine the potential triggering region for driving polarity reversal.

4. The integrated circuit timing and power consumption optimization system according to claim 2, characterized in that, The process of embedding charge balance nodes in the drive chain to absorb anti-coupling energy caused by voltage reference plane offset includes: After obtaining the voltage reference surface offset distribution, the topology of the drive chain in the potential triggering region is analyzed step by step. The drive chain from high voltage domain to low voltage domain and the feedback chain from low voltage domain to high voltage domain in the cross-voltage domain signal path are extracted. The delay relationship of the drive unit and the difference in voltage reference surface position are recorded. High-risk nodes are identified and grouped according to the offset direction. After completing the topology identification and grouping of the drive chain, the drive chain in the potential triggering area is restructured. A phase conjugate relationship is established between drive units with opposite offset directions or complementary potential drifts. A phase conjugate drive cancellation structure is constructed, and current compensation is achieved to cancel potential abrupt changes through the conjugate path. After reconstructing the phase conjugate drive cancellation structure, a charge balance node is embedded at the location of drastic potential change between the main drive path and the conjugate path, absorbing and releasing energy when the voltage reference plane shifts.

5. The integrated circuit timing and power consumption optimization system according to claim 4, characterized in that, The charge balance node is activated synchronously when the main driving path and the conjugate path are aligned in conduction phase. It achieves energy storage and release through variable capacitance characteristics and forms a buffer potential layer with the low coupling region during the offset phase to block the propagation of reverse energy.

6. The integrated circuit timing and power consumption optimization system according to claim 4, characterized in that, The process of keeping the driving transistor in a stable on-state during voltage reference plane shift includes: Based on the phase conjugate drive cancellation structure and charge balance node, the key drive unit with the largest voltage reference plane offset amplitude and the highest ground potential fluctuation frequency is selected. The charge balance node is electrically coupled to the source and substrate regions of the drive transistor, so that the inverted energy absorbed by the charge balance node is converted into transistor potential compensation. A dynamic potential interaction is formed between the charge balance node and the driving transistor. A dynamic threshold migration mechanism is established based on the transient potential change characteristics of the potential trigger region, so that the threshold voltage of the transistor can be dynamically adjusted with the potential change to maintain conduction stability. After achieving dynamic migration within the threshold voltage range, the threshold migration characteristics are linked with the energy absorption and release behavior of the charge balance node to form a two-way balance mechanism between energy and threshold, maintaining the consistency of the driving chain signal timing. After achieving threshold migration balance, timing correction is performed on the entire drive chain. The conduction phase of the drive unit is adjusted according to the voltage reference plane offset distribution, so that the drive chain maintains stable logic polarity and continuous conduction state during voltage offset.

7. The integrated circuit timing and power consumption optimization system according to claim 6, characterized in that, During the process of dynamic potential interaction between the charge balance node and the driving transistor, a controllable potential buffer channel is set up to match the charge flow rate with the potential change rate.

8. The integrated circuit timing and power consumption optimization system according to claim 6, characterized in that, The process of concentrating the current flow after charge balance node regulation into a local low-coupling loop includes: Under the condition of forming a stable conduction state based on the dynamic threshold migration mechanism, the power supply path and return path of each voltage domain in the power network are identified, the transient conduction resistance is calibrated according to the current direction and amplitude of the driving transistor, and the transient impedance distribution map of the power network is obtained to obtain the impedance distribution characteristics. After obtaining the impedance distribution characteristics, a variable impedance distribution path is set in the power supply path and the return path so that the current automatically adjusts its flow direction during the voltage reference plane offset stage. After the variable impedance distribution path is formed, an adaptive foldback conduction structure is established through path reconstruction, so that the current forms a closed foldback loop when it is transmitted across the voltage domain, and energy phase consistency compensation is achieved with the help of charge balance nodes. Based on the adaptive foldback conduction structure, the current flow direction is optimized, and the adjusted current is directed to the local low-coupling loop with small potential fluctuations, so that the energy is dissipated within the local low-coupling loop. After the current distribution is concentrated, the loop potential change rate and current phase difference are monitored, and the variable impedance distribution path is finely adjusted to keep the current distribution ratio constant.

9. The integrated circuit timing and power consumption optimization system according to claim 8, characterized in that, The variable impedance distribution path and the adaptive foldback conduction structure are electrically connected through the charge balance node. During the voltage reference plane offset stage, the impedance value is automatically adjusted according to the current phase difference, so that the current flows preferentially to the energy foldback path in the local low coupling loop, and the charge balance node releases compensation energy synchronously during the foldback process.

10. The integrated circuit timing and power consumption optimization system according to claim 8, characterized in that, The coordinated control process of energy foldback and phase compensation, utilizing the current constraint characteristics of locally low-coupling loops, includes: In the established local low-coupling loop, the current propagation boundary and phase distribution law of the energy return path are determined based on its current constraint characteristics, and the current phase change sequence and phase difference distribution are recorded to form the energy return propagation rhythm. After obtaining the phase distribution law of the low-coupling loop, an active energy return control process is executed to match the transient energy with the conduction period of the drive chain, and the local potential change is canceled by the phase reverse current pulse. After the energy return process stabilizes, phase compensation control is executed to align the drive chain conduction phase with the return energy phase delay. The conduction timing is dynamically adjusted through the phase delay control unit to keep the signal propagation phase synchronized with the energy propagation phase. After the energy return and phase compensation are completed in tandem, the nonlinear time grid is used to dynamically migrate the driving chain to turn on the phase, so that the driving polarity of the cross-voltage domain intersection region can remain in a steady state throughout the entire time domain.

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