Display driving circuit and display device

Abstract

The invention provides a display driving circuit and a display device, and the display driving circuit comprises a control module, a gate driving circuit, a source driving circuit, and a common voltage generation circuit. The gate drive circuit is connected with the control module and is used for outputting a gate drive signal under the control of the control module; the source electrode driving circuit is connected with the control module and is used for outputting a source electrode driving signal under the control of the control module; the common voltage generation circuit is connected with the control module and is used for receiving an initial voltage signal output by the control module, performing signal processing on the initial voltage signal and then performing signal bias generation and outputting a common voltage signal, and the initial voltage signal is obtained by the control module through pulse width modulation; wherein the output gate driving signal, the source driving signal and the common voltage signal are used for driving a cholesterol liquid crystal display panel. According to the technical scheme, the purpose of reducing the production cost of the display driving circuit for driving the cholesterol liquid crystal display panel can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display driving circuit and a display device. BACKGROUND

[0002] With the development of the times, the application range of display screens is wider and wider, among which, low-power display screens have certain market demand, such as advertisement screens, electronic tags, etc.

[0003] In some implementations, a cholesteric liquid crystal display panel can be used in a low-power display screen, and when the display driving circuit in the display screen drives the cholesteric liquid crystal display panel to provide the required common voltage signal (ACVCOM) to the cholesteric liquid crystal display panel, the display driving circuit generally needs to be driven by elements such as a control module, a digital-to-analog converter, and an operational amplifier. For example, the control module converts the voltage data into a voltage analog signal through the digital-to-analog converter, and then the signal processing is performed to obtain the common voltage signal for driving the cholesteric liquid crystal display panel. During the conception and implementation of the present application, the inventors found that at least the following problems exist: there are too many elements in the current display driving circuit, which leads to high cost, so how to reduce the production cost of the display driving circuit for driving the cholesteric liquid crystal display panel is a technical problem that needs to be solved by those skilled in the art.

[0004] The foregoing narrative is to provide general background information and does not necessarily constitute the prior art. SUMMARY

[0005] In view of the above technical problems, the present application provides a display driving circuit and a display device, which can achieve the purpose of reducing the production cost of the display driving circuit for driving the cholesteric liquid crystal display panel.

[0006] The present application provides a display driving circuit, comprising: a control module, a gate driving circuit, a source driving circuit, and a common voltage generating circuit; the gate driving circuit is connected with the control module and is used for outputting a gate driving signal controlled by the control module; the source driving circuit is connected with the control module and is used for outputting a source driving signal controlled by the control module; the common voltage generating circuit is connected with the control module, is used for receiving an initial voltage signal output by the control module, and generates and outputs a common voltage signal after signal processing of the initial voltage signal, wherein the initial voltage signal is obtained by pulse width modulation (PWM) of the control module; and the output gate driving signal, source driving signal, and common voltage signal are used for driving the cholesteric liquid crystal display panel.

[0007] Preferably, the signal processing includes signal biasing and / or signal amplification.

[0008] Preferably, the control module includes a timing controller and / or a control unit.

[0009] Preferably, the control module generates and outputs an initial voltage signal by performing pulse width modulation through either a timing controller or a control unit.

[0010] Preferably, the control module further includes a memory connected to the timing controller; the memory is used to store image data and output settings, so that the timing controller can acquire the image data and output settings, and output source control signals to the source drive circuit, output gate control signals to the gate drive circuit and / or output initial voltage signals to the common voltage generation circuit according to the image data and output settings.

[0011] Preferably, the common voltage generation circuit includes an operational amplifier and a bias circuit; the bias circuit is connected to the first input terminal of the operational amplifier and one of the timing controller and the control unit, and is used to receive the initial voltage signal output by the timing controller and the control unit, and to bias the initial voltage signal so as to transmit the biased initial voltage signal to the first input terminal of the operational amplifier; the operational amplifier also includes an output terminal and an enable terminal, and is used to amplify the biased initial voltage signal and output the amplified voltage signal through the output terminal when the enable terminal receives an enable signal, and / or output a ground signal when the enable terminal receives a disable signal; wherein, the amplified voltage signal and / or the ground signal constitute the common voltage signal.

[0012] Preferably, the common voltage generation circuit includes a comparator constructed using an operational amplifier. The comparator includes a first comparison input, a second comparison input, a first voltage input, a second voltage input, an enable input, and an output. The first comparison input of the comparator is connected to either a timing controller or a control unit. The second comparison input of the comparator receives a reference voltage. The first voltage input of the comparator receives a first output voltage, and the second voltage input of the comparator receives a second output voltage. When the enable input receives an enable signal, the comparator compares a comparison voltage obtained based on an initial voltage signal with a reference voltage. If the comparison voltage is greater than the reference voltage, the comparator outputs a first output voltage through the output terminal. If the comparison voltage is less than the reference voltage, the comparator outputs a second output voltage through the output terminal, thereby obtaining an amplified voltage signal. And / or, the comparator outputs a ground signal when the enable input receives a disable signal. The amplified voltage signal and / or the ground signal constitute a common voltage signal.

[0013] Preferably, the above-mentioned display driving circuit includes at least two common voltage generation circuits; the common voltage signals output by each common voltage generation circuit are different, and the common voltage signals output by each common voltage generation circuit are respectively output to different cholesterol liquid crystal display panels.

[0014] Preferably, the source drive signal consists of a DC voltage signal and a ground signal.

[0015] Preferably, the common voltage signal consists of a DC voltage signal and a grounding signal.

[0016] Preferably, within one waveform transmission cycle, the common voltage signal includes a first DC voltage signal, a second DC voltage signal, and a first ground signal; When controlling the liquid crystal in the pixels of the cholesterol liquid crystal display panel to be in a planar textured state, within one waveform cycle, the source drive signal includes a third DC voltage signal, a fourth DC voltage signal, and a second ground signal. The third DC voltage signal and the fourth DC voltage signal have the same duration and opposite polarity. The third DC voltage signal is time-synchronized with the first DC voltage signal and has opposite polarity. The fourth DC voltage signal is time-synchronized with the second DC voltage signal and has opposite polarity. When the liquid crystal in the pixels of the cholesterol liquid crystal display panel is controlled to be in a focal conic texture state, within one waveform cycle, the source drive signal includes a third DC voltage signal, a fourth DC voltage signal, a third ground signal, a fifth DC voltage signal, a sixth DC voltage signal, and a fourth ground signal. Among them, the third DC voltage signal and the fourth DC voltage signal have the same duration and opposite polarity, the fifth DC voltage signal and the sixth DC voltage signal have the same duration and opposite polarity, the fifth DC voltage signal has opposite polarity to the third DC voltage signal, the third DC voltage signal is time-synchronized with the first DC voltage signal and has opposite polarity, and the fourth DC voltage signal is time-synchronized with the second DC voltage signal and has opposite polarity.

[0017] Preferably, within one waveform cycle, the duration of the source drive signal is the same as the duration of the common voltage signal; and / or, the durations of the first DC voltage signal and the second DC voltage signal are both 8 frames; and / or, the durations of the third DC voltage signal and the fourth DC voltage signal are both 8 frames; and / or, the duration of the first ground signal is 49 frames; and / or, the duration of the second ground signal is 49 frames; and / or, the durations of the fifth DC voltage signal and the sixth DC voltage signal are both 12 frames; and / or, the duration of the third ground signal is 12 frames; and / or, the duration of the fourth ground signal is 13 frames; and / or, the refresh rate corresponding to the cholesteric liquid crystal display panel is 32Hz; and / or, the voltage fluctuation range of the common voltage signal received by the common electrode of the cholesteric liquid crystal display panel is +15V to -15V; and / or, the voltage fluctuation range of the source drive signal received by the pixel electrode of the pixel in the cholesteric liquid crystal display panel is +25V to -25V.

[0018] This application also provides a display device, comprising the display driving circuit described in any of the above claims and at least one cholesteric liquid crystal display panel.

[0019] This application provides a display driving circuit and a display device. The display driving circuit includes a control module, a gate driving circuit, a source driving circuit, and a common voltage generation circuit. The gate driving circuit is connected to the control module and is used to output a gate driving signal under the control of the control module. The source driving circuit is connected to the control module and is used to output a source driving signal under the control of the control module. The common voltage generation circuit is connected to the control module and is used to receive an initial voltage signal output by the control module, process the initial voltage signal, bias the signal to generate a common voltage signal, and output the common voltage signal. The initial voltage signal is obtained by the control module through pulse width modulation. The output gate driving signal, source driving signal, and common voltage signal are used to drive a cholesteric liquid crystal display panel. In the technical solution of this application, the initial voltage signal generated by pulse width modulation in the display driving circuit is an analog signal, which can be directly input to the common voltage generation circuit to generate and output a common voltage signal, avoiding the digital-to-analog conversion process. Therefore, the technical solution of this application avoids configuring a digital-to-analog converter in the common voltage generation circuit of the display driving circuit, thus achieving the goal of reducing the production cost of the display driving circuit for driving cholesteric liquid crystal display panels. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0021] Figure 1 This is a first structural schematic diagram of the display driving circuit provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the second structure of the display driving circuit provided in an embodiment of this application.

[0023] Figure 3 This is a schematic diagram of the third structure of some implemented display driver circuits.

[0024] Figure 4 This is a fourth structural schematic diagram of the display driving circuit provided in an embodiment of this application.

[0025] Figure 5This is a fifth structural schematic diagram of the display driving circuit provided in an embodiment of this application.

[0026] Figure 6 This is a first structural schematic diagram of the common voltage generation circuit provided in an embodiment of this application.

[0027] Figure 7 This is a schematic diagram of the second structure of the common voltage generation circuit provided in the embodiments of this application.

[0028] Figure 8 This is a key waveform comparison diagram of the initial voltage signal and the common voltage signal used as examples in this application.

[0029] Figure 9 This is the first key waveform diagram for realizing the planar texture state by the common voltage signal and the source drive signal in the embodiments of this application.

[0030] Figure 10 This is the first key waveform diagram for realizing the focal cone texture state by the common voltage signal and the source drive signal in the embodiments of this application.

[0031] Figure 11 This is a third structural schematic diagram of the common voltage generation circuit provided in the embodiments of this application.

[0032] Figure 12 This is the second key waveform diagram showing how the common voltage signal and the source drive signal achieve the planar texture state in the embodiments of this application.

[0033] Figure 13 This is the second key waveform diagram showing how the common voltage signal and the source drive signal achieve the focal cone texture state in the embodiments of this application.

[0034] Figure 14 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0035] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0037] It should be understood that although the terms first, second, third, etc., may be used in this document to describe various information, elements, units, or modules, these information, elements, units, or modules should not be limited to these terms. These terms are only used to distinguish information, elements, units, or modules of the same type from one another.

[0038] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Optionally, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which needs to be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0039] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0040] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0041] Please see Figure 1 , Figure 1 This is a schematic diagram of a display driving circuit structure provided in an embodiment of this application. The display driving circuit includes: a control module 100, a gate driving circuit 200, a source driving circuit 300, and a common voltage generation circuit 400.

[0042] The gate drive circuit 200 is connected to the control module 100 and is used to control the output gate drive signal control module 100 via the control module 100.

[0043] The source drive circuit 300 is connected to the control module 100 and is used to control the output of the source drive signal control module 100 via the control module 100.

[0044] The common voltage generation circuit 400 is connected to the control module 100 and is used to receive the initial voltage signal output by the control module 100, process the initial voltage signal to generate and output the common voltage signal. The initial voltage signal is obtained by the control module 100 through pulse width modulation.

[0045] The gate drive signal, source drive signal, and common voltage signal output by the display driver circuit are used to drive the cholesterol liquid crystal display panel.

[0046] Understandably, the display driving circuit outputs a gate driving signal to the gate line of the cholesteric liquid crystal display panel, the display driving circuit outputs a source driving signal to the pixel electrode of the pixel of the cholesteric liquid crystal display panel, and the display driving circuit outputs a common voltage signal to the common electrode of the cholesteric liquid crystal display panel, driving the pixels of the cholesteric liquid crystal display panel to be in a planar textured state and / or a focal conic textured state, so that the cholesteric liquid crystal display panel displays the set image.

[0047] Understandably, after receiving the gate drive signal, source drive signal and common voltage signal, the cholesteric liquid crystal display panel can cause all or part of its pixels to change the arrangement of cholesteric liquid crystal in each pixel through the action of the electric field to present a planar texture or a focal cone texture, thereby causing each pixel to present the corresponding color, and thus causing the cholesteric liquid crystal display panel to display the set image.

[0048] In one embodiment, the control module 100 can be characterized by being able to output signals to control the gate drive circuit 200, the source drive circuit 300, and the common voltage generation circuit 400 to operate, so as to realize the driving of one or more components / circuits or a collection of components / circuits of the cholesterol liquid crystal display panel.

[0049] Understandably, pulse width modulation (PWM) can characterize the logic level transitions between two level states to form the control process of an analog signal. For example, a logic level transition between 0V and VCC forms an analog signal (e.g., an analog waveform signal in the form of a square wave).

[0050] Understandably, the initial voltage signal obtained by the control module 100 through pulse width modulation is an analog signal. Therefore, the initial voltage signal can be directly input to the common voltage generation circuit 400 to generate and output a common voltage signal, thus avoiding the digital-to-analog conversion process.

[0051] In one embodiment, signal processing of the initial voltage signal can characterize one or more processing methods that process the initial voltage signal into a common voltage signal that can be output to a common electrode of a specific cholesterol liquid crystal display panel and support its display as intended.

[0052] In one embodiment, signal processing of the initial voltage signal includes, but is not limited to, signal biasing and / or signal amplification, and may also include signal grounding. Signal biasing can characterize a signal processing method that applies an additional DC voltage to the voltage signal through a circuit or component to change the level position of the voltage signal. Signal amplification can characterize a signal processing method that amplifies the amplitude of the voltage signal through a circuit or component to achieve a desired amplitude range. Signal grounding can characterize a signal processing method that adds a ground signal to any position (e.g., the beginning position, the end position, the middle position, etc.) of the voltage signal through a circuit or component.

[0053] For example, signal processing to process an initial voltage signal into a common voltage signal can be one of the following (the following examples are not exhaustive; various signal processing methods or combinations of multiple signal processing methods can be used according to actual needs to process the initial voltage signal into a common voltage signal): The initial voltage signal is biased, the biased initial voltage signal is amplified, and the amplified initial voltage signal is grounded to obtain a common voltage signal that supports the display of a specific cholesterol liquid crystal display panel according to the expected design. The initial voltage signal is biased, and the biased initial voltage signal is used as a common voltage signal to support the display of a specific cholesterol liquid crystal display panel according to the expected design. The initial voltage signal is amplified, and the amplified initial voltage signal is used as a common voltage signal to support the display of a specific cholesterol liquid crystal display panel according to the expected design. The initial voltage signal is biased, the biased initial voltage signal is amplified, and the amplified initial voltage signal is used as a common voltage signal to support the display of a specific cholesterol liquid crystal display panel according to the expected design.

[0054] In one embodiment, the common voltage generation circuit 400 primarily functions to generate and output a common voltage signal based on the initial voltage signal and / or other control signals output by the control module 100. Optionally, these other control signals include, but are not limited to, an enable signal (OE, Output Enable) or a horizontal synchronization signal (STV, Start of Vertical Signal).

[0055] In one embodiment, the specific structure of the common voltage generation circuit 400 can be configured according to the signal processing means required to process the initial voltage signal into a common voltage signal. For example, if signal biasing is required to process the initial voltage signal into a common voltage signal, a bias circuit 420 can be configured in the common voltage generation circuit 400; as another example, if signal amplification is required to process the initial voltage signal into a common voltage signal, a signal amplification circuit or an operational amplifier 410 can be configured in the common voltage generation circuit 400; and as yet another example, if both signal biasing and signal amplification are required to process the initial voltage signal into a common voltage signal, a bias circuit 420, a signal amplification circuit, or an operational amplifier 410 can be configured in the common voltage generation circuit 400.

[0056] In one embodiment, the gate driving circuit 200 is a component of the display driving circuit, and its main function is to generate and output a gate driving signal based on the control signal (e.g., a gate control signal) output by the control module 100. It should be understood that the specific structure of the gate driving circuit 200 can refer to currently mature technical solutions, and will not be described in detail here.

[0057] In one embodiment, the gate control signal includes, but is not limited to, the start of vertical signal (STV), the gate clock signal (GCLK), and the mode signal (Mode).

[0058] In one embodiment, the source drive circuit 300 is a component of the display drive circuit, and its main function is to generate and output a source drive signal based on the control signal (e.g., a source control signal) output by the control module 100. It should be understood that the specific structure of the source drive circuit 300 can refer to currently mature technical solutions, and will not be elaborated further here.

[0059] In one embodiment, the source control signal includes, but is not limited to, the source transition signal (STL), the output enable signal (OE), the line enable signal (LE), the clock signal (CLK), and the data signal (Data).

[0060] In one embodiment, the cholesterol liquid crystal display panel may be excluded from the display driving circuit (i.e., the cholesterol liquid crystal display panel is a characteristic of the display driving circuit's operating environment), or it may be included in the display driving circuit.

[0061] In one embodiment, the cholesteric liquid crystal molecules of each pixel in the cholesteric liquid crystal display panel have P-states (Planar, reflective state), FC-states (Focal Conic, hazy state), and / or H-states (transparent state). Both FC and H-states are transparent. Under a certain electric field, these three states can interconvert. The P-states (Planar, reflective state) and FC-states (Focal Conic, hazy state) are stable textures and do not require voltage to maintain, while the H-state (transparent state) requires voltage to maintain.

[0062] The gate drive signal, source drive signal, and common voltage signal output by the display driving circuit are used to drive the pixels in the cholesteric liquid crystal display panel to switch between the P state, FC state, and H state, thereby enabling the cholesteric liquid crystal display panel to achieve display effects or other working effects.

[0063] In the above technical solution of this embodiment, the display driving circuit includes: a control module 100, a gate driving circuit 200, a source driving circuit 300, and a common voltage generation circuit 400; the gate driving circuit 200 is connected to the control module 100 and is used to output a gate driving signal under the control of the control module 100; the source driving circuit 300 is connected to the control module 100 and is used to output a source driving signal under the control of the control module 100; the common voltage generation circuit 400 is connected to the control module 100 and is used to receive the initial voltage signal output by the control module 100, perform signal processing on the initial voltage signal, generate a signal bias, and output a common voltage signal, wherein the initial voltage signal is obtained by the control module 100 through pulse width modulation; wherein the output gate driving signal, source driving signal, and common voltage signal are used to drive the cholesteric liquid crystal display panel. Therefore, in the technical solution of this embodiment, the initial voltage signal generated by the control module 100 after pulse width modulation in the display driving circuit is an analog signal, which can be directly input to the common voltage generation circuit 400 to generate and output a common voltage signal, avoiding the digital-to-analog conversion process. Therefore, the technical solution of this embodiment avoids configuring a digital-to-analog converter in the common voltage generation circuit 400 of the display driving circuit. Thus, the technical solution of this embodiment can achieve the purpose of reducing the production cost of the display driving circuit for driving the cholesterol liquid crystal display panel.

[0064] In one embodiment, see Figure 2 The control module 100 may include a timing controller 101 (or TCON) and / or a control unit 104. Optionally, the control unit 104 may be an MCU (microcontroller).

[0065] In one embodiment, the control module 100 generates and outputs an initial voltage signal by performing pulse width modulation on either the timing controller 101 or the control unit 104.

[0066] In one embodiment, the control module 100 may further include a memory 103 connected to the timing controller 101; the memory 103 includes a first memory 1031 and a second memory 1032, the first memory 1031 is used to store image data and the second memory 1032 is used to store output settings, so that the timing controller 101 can acquire the image data and output settings, and output source control signals to the source drive circuit 300, output gate control signals to the gate drive circuit 200 and / or output initial voltage signals to the common voltage generation circuit 400 according to the image data and output settings.

[0067] For example, when the control module 100 performs pulse width modulation through the timing controller 101 to generate and output an initial voltage signal, the control unit 104 may not be configured in the control module 100. Thus, the display driving circuit provided by this embodiment can further reduce production costs compared to existing display driving circuits configured with a control unit 104.

[0068] For example, when the control module 100 generates and outputs an initial voltage signal by performing pulse width modulation through the control unit 104, the control unit 104 is connected to the timing controller 101 in the control module 100 and receives the line synchronization signal (STV) or enable signal (OE) output by the timing controller 101 to trigger the control unit 104 to perform pulse width modulation to generate and output the initial voltage signal.

[0069] In one embodiment, the display driving circuit further includes a power converter 102, which provides the voltages required by components or circuits such as the control module 100, gate driving circuit 200, source driving circuit 300, common voltage generation circuit 400, and memory 103 for operation.

[0070] In one embodiment, the memory 103 can be a FLASH memory or other type of memory. The timing controller 101 and the memory 103 can communicate via I2C or SPI for transmitting image data and output settings.

[0071] In one embodiment, the output settings may include output setting rules for the source drive circuit 300, which are preset, for example, based on the source drive signal required for displaying a specific cholesteric liquid crystal display panel. Exemplarily, the output setting rules for the source drive circuit 300 include settings for the voltage value, frame rate, and duration of at least one DC signal to support switching between planar texture mode and focal cone texture mode.

[0072] In one embodiment, the output settings may include output setting rules for the gate drive circuit 200, which may be preset, for example, based on the gate drive signal required for displaying a specific cholesterol liquid crystal display panel.

[0073] In one embodiment, the output settings may include output setting rules for an initial voltage signal, which may be preset, for example, based on the input voltage signal required when the common voltage generation circuit 400 generates a common voltage signal required for displaying a specific cholesterol liquid crystal display panel. Exemplarily, the output setting rules for the initial voltage signal include settings for the voltage value, frame rate, and duration of at least one DC signal.

[0074] Please see Figure 3 In some implementations, the display driving circuit includes: a timing controller 101a, a power converter 102a, a memory 103a, a control unit 104a, a gate driver 200a, a source driver 300a, and a common voltage generation circuit 400a, wherein the common voltage generation circuit 400a includes a digital-to-analog converter 401a. When the display driver circuit controls the display panel to display an image, the timing controller 101a needs to obtain image data and output settings from the memory 103a. Based on the image data and output settings, it outputs gate control signals, source control signals, and common voltage control signals to the gate driver 200a, source driver 300a, and control unit 104a, respectively. The control unit 104a triggers the output of voltage data to the common voltage generation circuit 400a based on the common voltage control signal. This controls the common voltage generation circuit 400a to convert the voltage data into an analog signal through the digital-to-analog converter 401a, and then process the analog signal into a common voltage signal. Finally, the display panel is driven by the gate drive signal output by the gate driver 200a and the source drive signal output by the source driver 300a.

[0075] In summary, compared to some display driver circuits used in other implementations, the display driver circuit provided in this embodiment (see [link to implementation details]) is superior. Figure 4 The control unit 104 can perform pulse width modulation to generate and output an initial voltage signal to the common voltage generation circuit 400 to output a common voltage signal, thereby driving the cholesteric liquid crystal display panel. In this embodiment, the display driving circuit reduces the number of digital-to-analog converters; therefore, the technical solution of this embodiment can achieve the goal of reducing the production cost of the display driving circuit. Furthermore, compared to some implemented display driving circuits, the display driving circuit provided in this embodiment (see...) Figure 5The timing controller 101 can perform pulse width modulation to generate and output an initial voltage signal to the common voltage generation circuit 400 to output a common voltage signal, thereby driving the cholesterol liquid crystal display panel. The display driving circuit of this embodiment reduces the digital-to-analog converter and the control unit 104. Therefore, the technical solution of this embodiment can better achieve the purpose of reducing the production cost of the display driving circuit.

[0076] Please see Figure 6 , Figure 6 The first structural schematic diagram of the common voltage generation circuit 400 provided in the embodiment of this application is shown in the figure. The common voltage generation circuit 400 includes an operational amplifier 410 and a bias circuit 420.

[0077] The bias circuit 420 is connected to the first input terminal of the operational amplifier 410 and one of the timing controller 101 and the control unit 104. It is used to receive the initial voltage signal output by one of the timing controller 101 and the control unit 104, and to bias the initial voltage signal so as to transmit the biased initial voltage signal to the first input terminal of the operational amplifier 410.

[0078] The operational amplifier 410 also includes an output terminal and an enable terminal. When the enable terminal receives an enable signal, the operational amplifier 410 amplifies the initial voltage signal after signal bias and outputs the amplified voltage signal through the output terminal, and / or outputs a ground signal when the enable terminal receives a disable signal.

[0079] The second input terminal of the operational amplifier 410 can be connected to an input resistor to determine the amplification factor of the operational amplifier 410.

[0080] Among them, the voltage signal after signal amplification and / or the ground signal constitute the common voltage signal.

[0081] In one embodiment, the waveform of the voltage signal after signal amplification can be a square wave.

[0082] In one embodiment, the amplified voltage signal includes a DC voltage signal. It is understood that the common voltage signal may include a DC voltage signal and a ground signal; for example, the common voltage signal may consist of at least one DC voltage signal and a ground signal.

[0083] In one embodiment, the ground signal can characterize a zero-voltage state or a reference point for comparison and alternation between high-level and low-level voltages of a voltage signal.

[0084] The common voltage generation circuit 400 in the above technical solution enables the driving of common electrodes for different cholesteric liquid crystal display panels without the need to replace or develop operational amplifiers 410 of different specifications. By adjusting the bias circuit 420, input resistor, and / or initial voltage signal, the operational amplifier 410 can output common voltage signals of different voltage amplitudes to adapt to the display control requirements of different cholesteric liquid crystal display panels. Thus, the display driving circuit of this embodiment can drive various cholesteric liquid crystal display panels without replacing operational amplifiers 410 of different specifications, which not only reduces costs but also simplifies the manufacturing and material preparation process.

[0085] In one embodiment, the bias circuit 420 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a bias voltage source. One end of the third resistor R3 is connected to either the timing controller 101 or the control unit 104 to receive an initial voltage signal; the other end of the third resistor R3 is grounded through the fourth resistor. One end of the fifth resistor R5 is connected to the bias voltage source, and the other end of the fifth resistor R5 is connected between the third resistor R3 and the fourth resistor R4. The other end of the fifth resistor R5 is also connected to the first input terminal (e.g., the inverting input terminal) of the operational amplifier 410. The initial voltage signal, after being divided by resistors R3 and R4 and biased by the bias voltage source, reaches a level suitable for the operational amplifier 410 to process into a common voltage signal required for a specific cholesterol-based liquid crystal display panel.

[0086] The common voltage generation circuit 400 further includes a first resistor R1 and a second resistor R2. One end of the second resistor R2 is grounded, and the other end is connected to the second input terminal of the operational amplifier 410 (the second input terminal is a positive input terminal, so the second resistor R2 is an input resistor). One end of the first resistor R1 is grounded, and the other end is connected to the output terminal of the operational amplifier 410 and, through a fourth resistor R4, to the first input terminal of the operational amplifier 410 (i.e., the first resistor R1 is a feedback resistor). Therefore, the gain of the operational amplifier 410 can be determined by the ratio of the feedback resistor R1 to the input resistor R2.

[0087] In the specific structure of the common level generation circuit described above, the bias circuit 420 biases the initial voltage signal to a suitable level through the action of resistors R3 and R4 and the bias voltage source, ensuring that the signal is within the input range of the operational amplifier 410; the operational amplifier 410 sets the gain through the feedback resistor R1 and the input resistor R2, amplifies the biased initial voltage signal, and finally outputs the common voltage signal required by the specific cholesterol liquid crystal display panel.

[0088] In one embodiment, the resistance values ​​of the first resistor R1 and the second resistor R2 can be changed according to the actual operational needs to adjust the amplification factor of the operational amplifier 410.

[0089] In one embodiment, when the voltage signal in the common voltage signal generated by the common voltage generation circuit 400 can correspond to multiple voltage values, and the common voltage generation circuit 400 cannot obtain the aforementioned common voltage signal using a bias voltage source with a fixed voltage, the bias voltage source included in the bias circuit 420 in the common voltage generation circuit 400 can be configured as a variable voltage source. In this way, the voltage value corresponding to the voltage provided by the bias voltage source can be adjusted according to actual needs, so that the voltage signal in the common voltage signal can correspond to any number of voltage values.

[0090] In one embodiment, see Figure 7 A bias voltage source that can provide multiple voltage values ​​may include an analog switch (or Analog_Switch). The module switch includes a first control terminal EN, a second control terminal IN, a first input terminal NO, a second input terminal NC, and an output terminal.

[0091] In this circuit, the first control terminal EN and the second control terminal IN of the analog switch are connected to either the control unit or the timing controller. The first input terminal of the analog switch receives a first input voltage V1, and the second input terminal receives a second input voltage V2. The output terminal of the analog switch is connected to one end of a fifth resistor. The first input voltage V1 and the second input voltage V2 have different values.

[0092] The specific circuit principle of the analog switch is as follows: one of the timing controller 101 and the control unit 104 controls the analog switch to select to output V1 or V2 through the first control terminal EN and the second control terminal IN, so that the voltage signal in the common voltage signal generated by the common voltage generation circuit 400 can correspond to multiple voltage values.

[0093] For example, the analog switch can consist of two MOSFETs (one N-channel and one P-channel), and the signal switching is achieved by controlling the gate voltage. When the control signals received by the first control terminal EN and the second control terminal IN change, the corresponding MOSFET is turned on or off, thereby enabling the selection of the first input voltage V1 and the second input voltage V2.

[0094] For example, see Figure 8One of the timing controller 101 and the control unit 104 outputs an initial voltage signal including an initial square wave signal (e.g., the initial square wave switches between 0V and VCC (3.3V)). The common voltage generation circuit 400 can first bias and amplify the initial square wave signal in the initial voltage signal based on the first input voltage V1 (e.g., -1.65V) provided by the bias voltage source, and then generate and output a target square wave signal that is frequently switched between two DC voltage signals. After that, the enable terminal of the operational amplifier 410 in the common voltage generation circuit 400 receives a disable signal to output... The ground signal (or GND signal) is used as the initial voltage signal. Finally, either the timing controller 101 or the control unit 104 outputs an initial voltage signal, including an initial DC voltage signal (e.g., a DC voltage signal of VCC (3.3V)). The common voltage generation circuit 400 can bias and amplify the initial DC voltage signal in the initial voltage signal by using the second input voltage V2 (e.g., -2.9V) provided by the bias voltage source, generating and outputting a target DC voltage signal. This achieves the generation and output of a common voltage signal including a target square wave signal, a ground signal, and a target DC voltage signal. The voltage value corresponding to the target square wave signal is different from the voltage value corresponding to the target DC voltage signal. The initial square wave signal included in the initial voltage signal can be obtained by either the timing controller 101 or the control unit 104 switching between 0V and VCC according to a set program. The initial DC voltage signal included in the initial voltage signal can be a 0V or VCC voltage signal output by either the timing controller 101 or the control unit 104 according to a set program.

[0095] Figure 9 This is the first key waveform diagram for realizing the planar texture state by the common voltage signal and the source drive signal in the embodiments of this application.

[0096] Please see Figure 9 Within one waveform transmission cycle, the common voltage signal includes a first DC voltage signal, a second DC voltage signal, and a ground signal presented sequentially; within one waveform transmission cycle, the source drive signal includes a third DC voltage signal, a fourth DC voltage signal, and a ground signal presented sequentially.

[0097] The first DC voltage signal and the second DC voltage signal can be matched with the waveform of the source drive signal. The third DC voltage signal and the fourth DC voltage signal have the same duration and opposite polarity. The third DC voltage signal is synchronized with the first DC voltage signal in time and opposite polarity. The fourth DC voltage signal is synchronized with the second DC voltage signal in time and opposite polarity. The ground signal of the common voltage signal is matched with the ground signal in the source drive signal to make the transparent liquid crystal form a planar textured liquid crystal.

[0098] For example, see Figure 9When the liquid crystal in the pixels of the cholesterol liquid crystal display panel is in a planar textured state, the duration of the first DC voltage signal and the second DC voltage signal is 25 frames, and the duration of the ground signal in the common voltage signal is 16 frames; the duration of the third DC voltage signal and the fourth DC voltage signal is 25 frames, and the duration of the ground signal in the source drive signal is 16 frames; thus, within one waveform sending cycle, the display drive circuit consumes power for only 66 frames when outputting the common voltage signal, and the rest of the time is static power consumption.

[0099] For example, see Figure 9 Taking a 32Hz refresh rate for a cholesteric liquid crystal display panel as an example, when controlling the liquid crystal in the pixels of the cholesteric liquid crystal display panel to be in a planar textured state, within one waveform sending cycle, the source drive signal sequentially outputs a positive voltage for 25 frames, a negative voltage for 25 frames, and a ground voltage for 16 frames. The common voltage signal sequentially outputs a negative voltage for 25 frames, a positive voltage for 25 frames, and a ground voltage for 16 frames. The waveforms of the source drive signal and the common voltage signal are opposite, and the waveforms reverse once every 25 frames, so that the liquid crystal in the pixel forms an electric field that appears transparent. Then, the ground signal of the source drive signal and the ground signal of the common voltage signal work together to make the liquid crystal in the pixel form a planar textured state (the aforementioned frame times can be adjusted according to actual needs). Thus, experimental verification shows that this can achieve the best display effect for the cholesteric liquid crystal display panel. The voltage fluctuation range of the common voltage signal received by the common electrode of the aforementioned cholesteric liquid crystal display panel can be +25V to -25V; and / or, the voltage fluctuation range of the source drive signal received by the pixel electrode of the pixel in the cholesteric liquid crystal display panel is +15V to -15V (it should be understood that the voltage fluctuation range of the common voltage signal and the voltage fluctuation range of the source drive signal can be adjusted according to the needs of different cholesteric liquid crystal display panels).

[0100] Figure 10 This is the first key waveform diagram for realizing the focal cone texture state by the common voltage signal and the source drive signal in the embodiments of this application.

[0101] Please see Figure 10 Within one waveform transmission cycle, the common voltage signal includes, in sequence, a first DC voltage signal, a second DC voltage signal, a ground signal, a third DC voltage signal, and a ground signal. Within one waveform transmission cycle, the source drive signal includes, in sequence, a fourth DC voltage signal, a fifth DC voltage signal, a ground signal, a sixth DC voltage signal, a seventh DC voltage signal, and a ground signal.

[0102] The first DC voltage signal and the second DC voltage signal can be combined with the waveform of the source drive signal to form an electric field that controls the liquid crystal in the pixel to be in a transparent state; the ground signal, the third DC voltage signal and the ground signal presented in sequence by the common voltage signal can be combined with the waveform of the source drive signal to form an electric field that controls the liquid crystal in the pixel to be in a focal cone texture state.

[0103] Specifically, the fourth DC voltage signal and the fifth DC voltage signal have the same duration but opposite polarities. The fourth DC voltage signal is time-synchronized with the first DC voltage signal but has opposite polarities, and the fifth DC voltage signal is time-synchronized with the second DC voltage signal but has opposite polarities, in order to form an electric field that controls the liquid crystal in the pixel to be in a transparent state.

[0104] Specifically, the absolute values ​​of the first and second DC voltage signals in the common voltage signal are the same, while the absolute value of the third DC voltage signal is different from that of the first and second DC voltage signals, and the duration of the third DC voltage signal is different from that of the first and second DC voltage signals. The sum of the durations of the sixth and seventh DC voltage signals in the source drive signal is equal to the duration of the third DC voltage signal. The durations of the sixth and seventh DC voltage signals are the same but their polarities are opposite. Thus, the ground signal, the third DC voltage signal, and the ground signal presented sequentially in the common voltage signal, in conjunction with the ground signal, the sixth DC voltage signal, the seventh DC voltage signal, and the ground signal presented sequentially in the source drive signal, can form an electric field that controls the liquid crystal in the pixel to exhibit a focal conic texture.

[0105] For example, see Figure 10 When the liquid crystals in the pixels of the cholesterol liquid crystal display panel are in a focal conic texture state, the duration of the first and second DC voltage signals is 25 frames, the duration of the third DC voltage signal is 10 frames, and the duration of the two ground signals in the common voltage signal is 3 frames; the duration of the fourth and fifth DC voltage signals is 25 frames; the duration of the sixth and seventh DC voltage signals is 5 frames; and the duration of the two ground signals in the source drive signal is 3 frames. Thus, within one waveform sending cycle, the display drive circuit consumes power for only 66 frames when outputting the common voltage signal, with the remaining time being static power consumption.

[0106] For example, see Figure 10Taking a 32Hz refresh rate for a cholesterol liquid crystal display panel as an example, when the liquid crystal in the pixels of the cholesterol liquid crystal display panel is controlled to be in a focal conic texture state, within one waveform cycle, the source drive signal is to output a positive voltage for 25 frames, a negative voltage for 25 frames, a ground voltage for 3 frames, a positive voltage for 5 frames, a negative voltage for 5 frames, and a ground voltage for 3 frames in sequence. The common voltage signal is to output a negative voltage (-25V) for 25 frames, a positive voltage (+25V) for 25 frames, a ground voltage for 3 frames, a negative voltage (=6V) for 10 frames, and a ground voltage for 3 frames in sequence. In this process, the waveforms of the source drive signal and the common voltage signal are reversed for the first 50 frames, and then reversed once every 25 frames to create an electric field that makes the liquid crystal of the pixel appear transparent. Then, the ground voltage for 3 frames, the negative voltage (=6V) for 10 frames, and the ground voltage for 3 frames of the common voltage signal are combined with the ground voltage for 3 frames, the positive voltage for 5 frames, the negative voltage for 5 frames, and the ground voltage for 3 frames of the source drive signal to create a focal cone texture in the liquid crystal of the pixel (the aforementioned frame times can be adjusted according to actual needs). Thus, within one waveform sending cycle, only 66 frames (approximately 2.046s, 31ms / frame, i.e., 32Hz) consume power; the rest of the time is static power consumption. Experiments have verified that this allows the aforementioned cholesteric liquid crystal display panel to achieve the best display effect. The voltage fluctuation range of the common voltage signal received by the common electrode of the aforementioned cholesteric liquid crystal display panel can be +25V to -25V; and / or, the voltage fluctuation range of the source drive signal received by the pixel electrode of the pixel in the cholesteric liquid crystal display panel is +15V to -15V (it should be understood that the voltage fluctuation range of the common voltage signal and the voltage fluctuation range of the source drive signal can be adjusted according to the requirements of different cholesteric liquid crystal display panels). Please refer to... Figure 11 , Figure 11 This is a third structural schematic diagram of the common voltage generation circuit 400 provided in the embodiments of this application, as shown below. Figure 11 As shown, the common voltage generation circuit 400 includes a comparator 411 constructed by an operational amplifier 410; the comparator 411 includes a first comparison input terminal (such as an inverting input terminal), a second comparison input terminal (such as a non-inverting input terminal), a first voltage input terminal, a second voltage input terminal, an enable terminal, and an output terminal.

[0107] The comparator 411 has its first comparison input connected to either the timing controller 101 or the control unit 104. Its second comparison input receives a reference voltage. Its first voltage input receives a first output voltage VS+, and its second voltage input receives a second output voltage VS-. When the comparator receives an enable signal at its enable terminal, it compares the comparison voltage obtained based on the initial voltage signal with the reference voltage. If the comparison voltage is greater than the reference voltage, it outputs the first output voltage VS+ through its output terminal; if the comparison voltage is less than the reference voltage, it outputs the second output voltage VS- through its output terminal, thus obtaining an amplified voltage signal. Alternatively, the comparator 411 can output a ground signal when the enable terminal receives a disable signal.

[0108] Among them, the voltage signal after signal amplification and / or the ground signal constitute the common voltage signal.

[0109] In one embodiment, the amplified voltage signal is a DC voltage signal. It is understood that the common voltage signal may include a DC voltage signal and a ground signal; for example, the common voltage signal may consist of at least one DC voltage signal and a ground signal.

[0110] The common voltage generation circuit 400 in the above technical solution enables the driving of common electrodes for different cholesteric liquid crystal display panels without the need to replace or develop operational amplifiers 410 of different specifications. By adjusting the reference voltage received at the second comparison input terminal, the first output voltage VS+ received at the first voltage input terminal, the second output voltage VS- received at the second voltage input terminal, and / or the initial voltage signal, the operational amplifier 410 can output common voltage signals of different voltage amplitudes to adapt to the display control requirements of different cholesteric liquid crystal display panels. Thus, the display driving circuit of this embodiment can drive various cholesteric liquid crystal display panels without replacing operational amplifiers 410 of different specifications, which not only reduces costs but also simplifies the manufacturing and material preparation process.

[0111] In one embodiment, the reference voltage received at the second comparison input terminal may be generated and output by the power supply circuit 430.

[0112] In one embodiment, the power supply circuit 430 includes a sixth resistor R6 and a seventh resistor R7. One end of the sixth resistor R6 receives the power supply voltage VCC, and the other end of the sixth resistor is grounded through the seventh resistor R7. The other end of the sixth resistor is also connected to the second comparison input terminal of comparator 411 to output a reference voltage to the second comparison input terminal of comparator 411. The sixth resistor R6 and the seventh resistor R7 divide the power supply voltage VCC to provide a required reference voltage for comparator 411.

[0113] In one embodiment, the common voltage generation circuit 400 may further include an eighth resistor R8. The first comparison input terminal of the comparator 411 is connected to the timing controller 101 or the control unit 104 through the eighth resistor R8 to receive the initial voltage signal. The eighth resistor R8 can appropriately attenuate the initial voltage signal, making its amplitude suitable for the input range of the operational amplifier 410 or reducing signal interference from the timing controller 101 or the control unit 104.

[0114] In one embodiment, the common voltage generation circuit 400 may further include a ninth resistor R9, and the output of the comparator 411 is grounded through the ninth resistor R9 to achieve a stable output common voltage signal.

[0115] In one embodiment, the common voltage signal generated by the display driving circuit in this embodiment can be composed of a DC voltage signal and a ground signal. Furthermore, to cooperate with the aforementioned common voltage signal in driving the cholesteric liquid crystal display panel, the source driving signal generated by the display driving circuit in this embodiment can also be composed of a DC voltage signal and a ground signal. The signals generated by the display driving circuit in this embodiment can avoid using AC signals, thereby achieving the purpose of saving power consumption, and thus saving power costs through the display driving circuit provided in this embodiment.

[0116] Figure 12 This is the second key waveform diagram showing how the common voltage signal and the source drive signal achieve the planar texture state in the embodiments of this application. Figure 13 This is the second key waveform diagram showing how the common voltage signal and the source drive signal achieve the focal cone texture state in the embodiments of this application.

[0117] Please see Figure 12 and Figure 13 Within one waveform cycle, the common voltage signal includes a first DC voltage signal, a second DC voltage signal, and a ground signal, which are presented sequentially. The first and second DC voltage signals, in conjunction with the source drive signal waveform, form an electric field that controls the liquid crystal in the pixel to be in a transparent state. The first ground signal, in conjunction with the source drive signal waveform, forms an electric field that controls the liquid crystal in the pixel to be in a planar textured state and / or a focal cone textured state. The first and second DC voltage signals have opposite polarities.

[0118] In one embodiment, the duration of the source drive signal is the same as the duration of the common voltage signal within one waveform cycle.

[0119] In one embodiment, when the display driving circuit controls the display screen of the cholesteric liquid crystal display panel, the waveform of the output common voltage signal in one waveform sending cycle is sequentially a DC voltage signal, a DC voltage signal, a first ground signal, and a stop output signal. In this way, power is consumed only when the DC voltage signal is output, and static consumption occurs at other times, which can reduce energy consumption. Therefore, the display driving circuit provided in this embodiment can save power consumption costs.

[0120] In one embodiment, see Figure 12 When controlling the liquid crystal in the pixels of the cholesterol liquid crystal display panel to be in a planar textured state, within one waveform cycle, the source driving signal includes a third DC voltage signal, a fourth DC voltage signal, and a second ground signal. The third DC voltage signal and the fourth DC voltage signal have the same duration and opposite polarities. The third DC voltage signal is time-synchronized with the first DC voltage signal and has opposite polarities. The fourth DC voltage signal is time-synchronized with the second DC voltage signal and has opposite polarities. The ground signal of the common voltage signal cooperates with the ground signal in the source driving signal to make the transparent liquid crystal form a planar textured state.

[0121] For example, see Figure 12 When the liquid crystal in the pixels of the cholesterol liquid crystal display panel is in a planar textured state, the duration of the first DC voltage signal and the second DC voltage signal is 8 frames, and the duration of the first ground signal is 49 frames; the duration of the third DC voltage signal and the fourth DC voltage signal is 8 frames, and the duration of the second ground signal is 49 frames. Thus, within one waveform sending cycle, the display driving circuit consumes power for only 16 frames when outputting the common voltage signal, and the other time (49 frames) is static power consumption.

[0122] For example, see Figure 12Taking a 32Hz refresh rate for a cholesteric liquid crystal display panel as an example, when controlling the liquid crystal in the pixels of the cholesteric liquid crystal display panel to be in a planar textured state, within one waveform sending cycle, the source drive signal sequentially outputs a positive voltage for 8 frames, a negative voltage for 8 frames, and a second ground voltage for 49 frames. The common voltage signal sequentially outputs a negative voltage for 8 frames, a positive voltage for 8 frames, and a first ground voltage for 49 frames. The waveforms of the source drive signal and the common voltage signal are opposite, and the waveforms are reversed once every 8 frames, so that the liquid crystal in the pixel forms an electric field that appears transparent. Then, the first ground signal of the source drive signal and the second ground signal of the common voltage signal work together to make the liquid crystal in the pixel form a planar textured state (the aforementioned frame times can be adjusted according to actual needs). Thus, within one waveform sending cycle, only 16 frames (approximately 496ms, 31ms / frame, i.e., 32Hz) consume power, while the rest of the time is static power consumption. Experiments have verified that this is the optimal energy consumption configuration. The voltage fluctuation range of the common voltage signal received by the common electrode of the aforementioned cholesteric liquid crystal display panel can be +15V to -15V; and / or, the voltage fluctuation range of the source drive signal received by the pixel electrode of the pixel in the cholesteric liquid crystal display panel is +25V to -25V (it should be understood that the voltage fluctuation range of the common voltage signal and the voltage fluctuation range of the source drive signal can be adjusted according to the needs of different cholesteric liquid crystal display panels).

[0123] In one embodiment, see Figure 13 When controlling the liquid crystal in the pixels of the cholesteric liquid crystal display panel to form a focal conic texture, within one waveform cycle, the source drive signal includes a third DC voltage signal, a fourth DC voltage signal, a third ground signal, a fifth DC voltage signal, a sixth DC voltage signal, and a fourth ground signal. Among them, the third DC voltage signal and the fourth DC voltage signal have the same duration and opposite polarities, the fifth DC voltage signal and the sixth DC voltage signal have the same duration and opposite polarities, the fifth DC voltage signal and the third DC voltage signal have opposite polarities, the third DC voltage signal and the first DC voltage signal are time-synchronized and opposite in polarity, the fourth DC voltage signal and the second DC voltage signal are time-synchronized and opposite in polarity, and the first ground signal of the common voltage signal cooperates with the fifth DC voltage signal, the sixth DC voltage signal and the ground signal in the source drive signal to form a focal conic texture in the liquid crystal in the transparent state.

[0124] The durations of the third grounding signal and the fourth grounding signal may be the same or different.

[0125] For example, see Figure 13When the liquid crystals in the pixels of the cholesterol liquid crystal display panel are in a focal conic texture state, the duration of the first DC voltage signal and the second DC voltage signal is 8 frames, and the duration of the first ground signal is 49 frames; the duration of the third DC voltage signal and the fourth DC voltage signal is 8 frames; the duration of the fifth DC voltage signal and the sixth DC voltage signal is 12 frames; the duration of the third ground signal is 12 frames; and the duration of the fourth ground signal is 13 frames. Thus, within one waveform sending cycle, the display driving circuit consumes power for only 16 frames when outputting the common voltage signal, and the remaining time (49 frames) is static power consumption.

[0126] For example, see Figure 12 Taking a 32Hz refresh rate for a cholesteric liquid crystal display panel as an example, when controlling the liquid crystal in the pixels of the cholesteric liquid crystal display panel to be in a focal conic texture state, within one waveform cycle, the source drive signal is to sequentially output a positive voltage for 8 frames, a negative voltage for 8 frames, a ground voltage for 12 frames (i.e., the third ground signal), a positive voltage for 12 frames, a negative voltage for 12 frames, and a ground voltage for 13 frames (i.e., the fourth ground signal), and the common voltage signal is to sequentially output a negative voltage for 8 frames, a positive voltage for 8 frames, and a ground voltage for 49 frames. (i.e., the first ground signal); wherein, the waveform of the source drive signal and the waveform of the common voltage signal are reversed in the first 16 frames, and reversed once every 8 frames, so that the liquid crystal of the pixel forms an electric field that presents a transparent state. Then, the first ground signal of the common voltage signal is combined with the ground voltage of the source drive signal for 12 frames (i.e., the third ground signal), the positive voltage for 12 frames, the negative voltage for 12 frames, and the ground voltage for 13 frames (i.e., the fourth ground signal) to make the liquid crystal of the pixel form a focal cone texture state (the aforementioned frame time can be adjusted according to actual needs). In this way, within one waveform sending cycle, only 16 frames, approximately 496ms (31ms / frame, i.e., 32Hz), consume power, and the rest of the time is static consumption. Experiments have verified that this is the optimal energy consumption configuration. The voltage fluctuation range of the common voltage signal received by the common electrode of the aforementioned cholesteric liquid crystal display panel can be +15V to -15V; and / or, the voltage fluctuation range of the source drive signal received by the pixel electrode of the pixel in the cholesteric liquid crystal display panel is +25V to -25V (it should be understood that the voltage fluctuation range of the common voltage signal and the voltage fluctuation range of the source drive signal can be adjusted according to the needs of different cholesteric liquid crystal display panels).

[0127] Understandably, different voltage fluctuation ranges for the common voltage signal and / or source drive signal can be selected based on actual needs such as device selection.

[0128] Please see Figure 14 , Figure 14This is a schematic diagram of the structure of the display device provided in the embodiments of this application, such as... Figure 14 As shown ( Figure 14 The example shows that the display driving circuit drives two or two different cholesterol liquid crystal display panels. This embodiment provides a display driving circuit that can be configured with at least two common voltage generation circuits 400; the common voltage signals output by each common voltage generation circuit 400 are different, and the common voltage signals output by each common voltage generation circuit 400 are output to different cholesterol liquid crystal display panels.

[0129] In one embodiment, the display driving circuit can be configured with at least two common voltage generation circuits 400 to drive cholesteric liquid crystal display panels with different driving attributes respectively. In this case, the display driving circuit can configure a corresponding number of gate driving circuits 200 and source driving circuits 300 according to the number of cholesteric liquid crystal display panels with different driving attributes, so that various cholesteric liquid crystal display panels driven by the same display driving circuit can obtain the corresponding gate driving signal, source driving signal and common voltage signal, thereby displaying an image. Optionally, multiple common voltage generation circuits 400, gate driving circuits 200 and source driving circuits 300 can share a control module 100 or share a control unit 104 / timing controller 101 in the control module 100 for control. In this way, the display driving circuit provided in this embodiment can drive cholesteric liquid crystal display panels with multiple driving attributes and can share control elements or control circuits, thereby reducing costs.

[0130] For example, see Figure 14The display driving circuit is equipped with a common voltage generation circuit 400-1 and a common voltage generation circuit 400-2. The control unit 104 or timing controller 101 in the control module 100 of the display driving circuit can output initial voltage signal 1 and initial voltage signal 2, respectively, to the common voltage generation circuit 400-1 and the common voltage generation circuit 400-2. The common voltage generation circuit 400-1 can output a common voltage signal ACVCOM1 to the common electrode of the first cholesterol liquid crystal display panel P1 based on the initial voltage signal 1, so that the first cholesterol liquid crystal display panel P1 is driven according to the common voltage signal ACVCOM1 and the received source electrode. The first cholesterol liquid crystal display panel P1 and the second cholesterol liquid crystal display panel P2 are used for display operations based on the initial voltage signal 2 and the gate drive signal. The common voltage generation circuit 400-2 can output a common voltage signal ACVCOM2 to the common electrode of the second cholesterol liquid crystal display panel P2 based on the initial voltage signal 2. This allows the second cholesterol liquid crystal display panel P2 to perform display operations based on the common voltage signal ACVCOM2 and the received source drive signal and gate drive signal. The first cholesterol liquid crystal display panel P1 and the second cholesterol liquid crystal display panel P2 have different driving attributes (e.g., the required common voltage signal amplitude is different, the required gate drive signal control logic is different, the required source drive signal voltage amplitude is different, etc.).

[0131] In one embodiment, the same common voltage generation circuit 400 in the display driving circuit can output a common voltage signal to multiple cholesteric liquid crystal display panels with the same driving properties, so as to drive multiple cholesteric liquid crystal display panels with the same driving properties.

[0132] In summary, the technical solution of this embodiment can achieve at least one of the following beneficial effects: (1) The display driving circuit of this embodiment can save a digital-to-analog converter compared with some display driving circuits, thereby reducing production costs; (2) The technical solution of this embodiment proposes several operational amplifier driving schemes to be applied to the common voltage production circuit of the display driving circuit, so as to realize that a common voltage signal with various voltage amplitudes can be output using a specific specification operational amplifier with a lower cost, thereby avoiding the problem of difficult preparation of operational amplifiers and reducing the limitations of common voltage signal driving. (3) When the common voltage generation circuit of the display driving circuit in this embodiment outputs the common voltage signal, it can reduce the good points when sending the waveform and can ensure that the static consumption is longer. (4) The display driving circuit of this embodiment can also drive a multilayer cholesteric liquid crystal panel, reducing control components or control circuits, thereby saving costs; (5) When the display driving circuit of this embodiment is applied to a display device with a cholesteric liquid crystal display panel, the common voltage generation circuit consumes energy only when sending waveform to drive the cholesteric liquid crystal display panel to display images. At other times after the images are displayed, the cholesteric liquid crystal display panel maintains the image display by relying on the characteristics of cholesteric liquid crystal. Thus, the technical solution of this embodiment can make the display device more energy-efficient.

[0133] In one embodiment, the same common voltage generation circuit 400 in the display driving circuit can drive multiple identical cholesteric liquid crystal display panels.

[0134] This application also provides a display device, characterized by the above-described display driving circuit and at least one cholesterol liquid crystal display panel.

[0135] This application provides a display driving circuit, including: a control module, a gate driving circuit, a source driving circuit, and a common voltage generation circuit; the gate driving circuit is connected to the control module and is used to output a gate driving signal under the control of the control module; the source driving circuit is connected to the control module and is used to output a source driving signal under the control of the control module; the common voltage generation circuit is connected to the control module and is used to receive an initial voltage signal output by the control module, and generate and output a common voltage signal by amplifying the initial voltage signal through signal bias, wherein the initial voltage signal is obtained by the control module through pulse width modulation; wherein the output gate driving signal, source driving signal, and common voltage signal are used to drive a cholesteric liquid crystal display panel, consuming power only when switching display content, maintaining a fixed display content for a long time, and reducing the components required for the display driving circuit. The effect is more obvious in display panels using multi-channel display driving circuits, which can meet display requirements, while having low hardware cost and low power consumption.

[0136] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0137] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display driving circuit, characterized in that, include: Control module, gate drive circuit, source drive circuit and common voltage generation circuit; The gate drive circuit is connected to the control module and is used to output a gate drive signal under the control of the control module. The source drive circuit is connected to the control module and is used to output a source drive signal under the control of the control module. A common voltage generation circuit is connected to the control module and is used to receive the initial voltage signal output by the control module, process the initial voltage signal to generate and output a common voltage signal, wherein the initial voltage signal is obtained by the control module through pulse width modulation. The output gate drive signal, source drive signal, and common voltage signal are used to drive the cholesterol liquid crystal display panel.

2. The display driving circuit according to claim 1, characterized in that, The control module includes a timing controller and / or a control unit; The control module generates and outputs the initial voltage signal by performing pulse width modulation on either the timing controller or the control unit.

3. The display driving circuit according to claim 2, characterized in that, The control module also includes a memory connected to the timing controller; The memory is used to store image data and output settings, so that the timing controller can acquire the image data and the output settings, and output a source control signal to the source drive circuit, output a gate control signal to the gate drive circuit, and / or output the initial voltage signal to the common voltage generation circuit according to the image data and the output settings.

4. The display driving circuit according to claim 2, characterized in that, The common voltage generation circuit includes an operational amplifier and a bias circuit; The bias circuit is connected to the first input terminal of the operational amplifier and one of the timing controller and the control unit. It is used to receive the initial voltage signal output by one of the timing controller and the control unit, and to bias the initial voltage signal so as to transmit the biased initial voltage signal to the first input terminal of the operational amplifier. The operational amplifier further includes an output terminal and an enable terminal, and the operational amplifier is used to amplify the initial voltage signal after signal biasing when the enable terminal receives an enable signal, and then output the amplified voltage signal through the output terminal, and / or output a ground signal when the enable terminal receives a disable signal; The amplified voltage signal and / or the grounding signal constitute the common voltage signal.

5. The display driving circuit according to claim 2, characterized in that, The common voltage generation circuit includes a comparator constructed using an operational amplifier, the comparator including a first comparison input terminal, a second comparison input terminal, a first voltage input terminal, a second voltage input terminal, an enable terminal, and an output terminal; The first comparison input terminal of the comparator is connected to one of the timing controller and the control unit; the second comparison input terminal of the comparator receives a reference voltage; the first voltage input terminal of the comparator receives a first output voltage; and the second voltage input terminal of the comparator receives a second output voltage. The comparator is used to compare the comparison voltage obtained based on the initial voltage signal with the reference voltage when the enable terminal receives the enable signal, and output the first output voltage through the output terminal when the comparison voltage is greater than the reference voltage, and output the second output voltage through the output terminal when the comparison voltage is less than the reference voltage, so as to obtain the voltage signal after signal amplification. And / or, The comparator is used to output a ground signal when the enable terminal receives a disable signal; The amplified voltage signal and / or the grounding signal constitute the common voltage signal.

6. The display driving circuit according to any one of claims 1 to 5, characterized in that, Includes at least two of the aforementioned common voltage generation circuits; The common voltage signals output by each of the common voltage generation circuits are different, and the common voltage signals output by each of the common voltage generation circuits are output to different cholesterol liquid crystal display panels.

7. The display driving circuit according to any one of claims 1 to 5, characterized in that, The source drive signal consists of a DC voltage signal and a ground signal; The common voltage signal consists of a DC voltage signal and a ground signal.

8. The display driving circuit according to claim 7, characterized in that, Within one waveform transmission cycle, the common voltage signal includes a first DC voltage signal, a second DC voltage signal, and a first ground signal; When controlling the liquid crystal in the pixels of the cholesterol liquid crystal display panel to be in a planar textured state, within one waveform cycle, the source drive signal includes a third DC voltage signal, a fourth DC voltage signal, and a second ground signal, wherein the third DC voltage signal and the fourth DC voltage signal have the same duration and opposite polarity, the third DC voltage signal is time-synchronized with the first DC voltage signal and has opposite polarity, and the fourth DC voltage signal is time-synchronized with the second DC voltage signal and has opposite polarity; When the liquid crystal in the pixels of the cholesterol liquid crystal display panel is controlled to be in a focal conic texture state, within one waveform cycle, the source drive signal includes a third DC voltage signal, a fourth DC voltage signal, a third ground signal, a fifth DC voltage signal, a sixth DC voltage signal, and a fourth ground signal. The third and fourth DC voltage signals have the same duration but opposite polarities; the fifth and sixth DC voltage signals have the same duration but opposite polarities; the fifth DC voltage signal has opposite polarities to the third DC voltage signal; the third DC voltage signal is time-synchronized with the first DC voltage signal but has opposite polarities; and the fourth DC voltage signal is time-synchronized with the second DC voltage signal but has opposite polarities.

9. The display driving circuit according to claim 8, characterized in that, Within one waveform cycle, the duration of the source drive signal is the same as the duration of the common voltage signal; The duration of both the first DC voltage signal and the second DC voltage signal is 8 frames; and / or, The duration of both the third DC voltage signal and the fourth DC voltage signal is 8 frames; and / or, The duration of the first ground signal is 49 frames; and / or, The duration of the second ground signal is 49 frames; and / or, The duration of both the fifth DC voltage signal and the sixth DC voltage signal is 12 frames; and / or, The duration of the third grounding signal is 12 frames; and / or, The duration of the fourth grounding signal is 13 frames; and / or, The refresh rate of the cholesterol-based liquid crystal display panel is 32Hz; and / or, The voltage fluctuation range of the common voltage signal received by the common electrode of the cholesterol liquid crystal display panel is +15V to -15V; and / or, The voltage fluctuation range of the source drive signal received by the pixel electrode of the pixel in the cholesterol liquid crystal display panel is +25V to -25V.

10. A display device, characterized in that, It includes a display driving circuit as described in any one of claims 1 to 9 and at least one cholesterol liquid crystal display panel.

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