Electronic device, control device and method for NFC automatic antenna tuning

Abstract

The application discloses an electronic device, a control device and a method for NFC automatic antenna tuning. The control device comprises a microcontroller unit, a boost circuit, a switch control circuit, at least one first type of switch circuit and at least one second type of switch circuit. The first type of switch circuit is used for controlling the signal input end and the signal output end to be connected or disconnected according to the potential of the first node; the second type of switch circuit is connected with the ground end and is used for controlling the ground end and the reference signal end to be connected or disconnected according to the potential of the second node.

Description

Technical Field

[0001] This invention relates to the field of near field communication (NFC) technology, and more particularly to an electronic device, a control device and method for NFC automatic antenna tuning. Background Technology

[0002] In NFC applications, external environmental factors (such as the proximity of a metal object) or changes in load impedance can cause the NFC antenna resonant frequency to shift. This will result in antenna mismatch, significantly reducing power transfer efficiency and potentially leading to communication interruption. Current mainstream NFC automatic antenna tuning solutions use an analog-to-digital converter (ADC) to control a voltage-controlled capacitor (VRC). The disadvantages of this approach are: the high cost of a single VRC and the limited range of capacitance variation for a single capacitor. To expand the tuning range, multiple VRCs need to be connected in parallel, further increasing system cost. Summary of the Invention

[0003] The purpose of this application is to provide an electronic device, a control device and method for NFC automatic antenna tuning.

[0004] This application discloses a control device for NFC automatic antenna tuning, including a microcontroller unit, a boost circuit, a switch control circuit, at least one first type of switch circuit and at least one second type of switch circuit. The microcontroller unit is used to output a pulse width modulation signal, a first input-output control signal, and a second input-output control signal; The boost circuit is used to receive the pulse width modulation signal and output a target voltage signal according to the pulse width modulation signal; The switch control circuit is connected to the first node and the second node, and is used to determine the potential of the first node according to the first input-output control signal and the target voltage signal, and to determine the potential of the second node according to the second input-output control signal and the target voltage signal; The first type of switching circuit is used to control the connection or disconnection of the signal input terminal and the signal output terminal according to the potential of the first node; The second type of switching circuit is connected to the ground terminal and is used to control the ground terminal to be connected or disconnected from the reference signal terminal according to the potential of the second node.

[0005] In some alternative embodiments, the boost circuit includes: An inverter, connected to a third node, is used to receive the pulse width modulation signal and transmit a complementary signal to the third node; A voltage doubler rectifier circuit, connected to the third node, is used to output the target voltage signal based on the complementary signal.

[0006] In some alternative embodiments, the inverter includes: A first transistor, the gate of the first transistor is connected to the pulse width modulation signal, the first terminal of the first transistor is connected to a first power supply terminal, and the second terminal of the first transistor is connected to the third node; The second transistor has its gate connected to the pulse width modulation signal, its first terminal grounded, and its second terminal connected to the third node.

[0007] In some alternative embodiments, the voltage doubler rectifier circuit includes: A first diode, a second diode, and a third diode are connected in series. The input terminal of the first diode is connected to the third node, and the output terminal of the third diode outputs the target voltage signal. The first capacitor has one plate for receiving the pulse width modulation signal and the other plate connected to the output terminal of the first diode. The second capacitor is connected between the input terminal of the first diode and the output terminal of the second diode; The third capacitor is connected between the input terminal of the second diode and the output terminal of the third diode.

[0008] In some alternative embodiments, the switch control circuit includes: The first control sub-circuit includes a third transistor, a first resistor, and a second resistor. The first terminal of the third transistor is connected to the first input / output control signal, the gate of the third transistor is connected to the first power supply terminal, and the second terminal of the third transistor is connected to the first node. The first resistor is connected between the first terminal and the gate of the third transistor. One end of the second resistor is connected to the first node, and the other end of the second resistor is connected to the target voltage signal. The second control sub-circuit includes a fourth transistor, a third resistor, and a fourth resistor. The first terminal of the fourth transistor is connected to the second input / output control signal, the gate of the fourth transistor is connected to the first power supply terminal, and the second terminal of the fourth transistor is connected to the second node. The third resistor is connected between the first terminal and the gate of the fourth transistor. One end of the fourth resistor is connected to the second node, and the other end of the fourth resistor is connected to the target voltage signal.

[0009] In some alternative embodiments, the number of the first type of switch circuits is the same as the number of the second type of switch circuits.

[0010] In some alternative embodiments, the signal input terminal includes a first input terminal and a second input terminal, the signal output terminal includes a first output terminal and a second output terminal, and the at least one first type of switching circuit includes two first type of switching circuits. A first type of switching circuit includes a fifth transistor and a sixth transistor, wherein the first terminal of the fifth transistor is connected to the first input terminal, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor, and the second terminal of the sixth transistor is connected to the first output terminal; the gates of both the fifth transistor and the sixth transistor are connected to the first node; Another of the first type of switching circuits includes a seventh transistor and an eighth transistor, wherein the first terminal of the seventh transistor is connected to the second input terminal, the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor, and the second terminal of the eighth transistor is connected to the second output terminal; the gates of both the seventh transistor and the eighth transistor are connected to the first node.

[0011] In some alternative embodiments, the reference signal terminal includes a first reference terminal and a second reference terminal, and the at least one second type of switch circuit includes two second type of switch circuits; A second type of switching circuit includes a ninth transistor, the first terminal of which is connected to the ground terminal, and the second terminal of which is connected to the first reference terminal; Another type-2 switching circuit includes a tenth transistor, the first terminal of which is connected to the ground terminal, and the second terminal of which is connected to the second reference terminal.

[0012] This application also discloses a control method for NFC automatic antenna tuning, the method employing the aforementioned control device, the control method comprising: The microcontroller unit outputs a pulse width modulation signal, a first input / output control signal, and a second input / output control signal. The boost circuit receives the pulse width modulation signal and outputs a target voltage signal according to the pulse width modulation signal; The switch control circuit determines the potential of the first node based on the first input / output control signal and the target voltage signal, and the switch control circuit determines the potential of the second node based on the second input / output control signal and the target voltage signal. The first type of switching circuit controls the connection or disconnection of the signal input terminal and the signal output terminal according to the potential of the first node; The second type of switching circuit controls the connection or disconnection of the ground terminal and the reference signal terminal according to the potential of the second node.

[0013] This application also discloses an electronic device, including the control device described above.

[0014] For the electronic devices, control devices and methods for NFC automatic antenna tuning disclosed herein, the microcontroller unit generally integrates a high-precision pulse width modulation (PWM) generator and a general-purpose input / output (I / O) interface. This disclosure outputs a pulse width modulation signal through the high-precision PWM generator of the microcontroller unit and outputs a first input / output control signal and a second input / output control signal using the general-purpose input / output (I / O) interface of the microcontroller unit, thus utilizing existing resources and saving costs.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0017] Figure 1 This is a block diagram of a control device for NFC automatic antenna tuning in an embodiment of this disclosure.

[0018] Figure 2 This is a circuit diagram of a control device for NFC automatic antenna tuning in an embodiment of this disclosure.

[0019] Figure 3 This is a schematic diagram of the first device and the second device in an embodiment of this disclosure.

[0020] Figure 4 The above are signal waveform diagrams of the first output terminal and the second output terminal in the embodiments of this disclosure.

[0021] Figure 5 The waveforms of the pulse width modulation signal and the target voltage signal in the embodiments of this disclosure are shown.

[0022] Reference numerals: SIGNAL1, first input terminal; SIGNAL2, first output terminal; SIGNAL5, second input terminal; SIGNAL6, second output terminal; SIGNAL3, first reference terminal; SIGNAL4, second reference terminal; N1, first node; N2, second node; N3, third node; 1, boost circuit; 2, switch control circuit; 3, first type of switch circuit; 4, second type of switch circuit; 5, first device; 6, second device; MCU, microcontroller unit; PWM, pulse width modulation signal; IO1, first input / output control signal; IO2, second input / output control signal; VCC, first power supply terminal; Vdd, target voltage signal; GND, ground terminal; t1, first stage; t2, second stage; t3, third stage; t4, fourth stage. Detailed Implementation

[0023] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0024] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0025] like Figure 1 and Figure 2 As shown, this disclosure provides a control device for NFC automatic antenna tuning. The control device for NFC automatic antenna tuning includes a microcontroller unit (MCU), a boost circuit 1, a switch control circuit 2, at least one first-type switch circuit 3, and at least one second-type switch circuit 4, wherein: The microcontroller unit (MCU) outputs a pulse width modulation (PWM) signal, a first input / output control signal (IO1), and a second input / output control signal (IO2). The boost circuit 1 receives the PWM signal and outputs a target voltage signal (Vdd) based on the PWM signal. The switch control circuit 2 is connected to the first node N1 and the second node N2, and is used to determine the potential of the first node N1 based on the first input / output control signal (IO1) and the target voltage signal (Vdd), and to determine the potential of the second node N2 based on the second input / output control signal (IO2) and the target voltage signal (Vdd). The first type of switch circuit 3 controls the connection or disconnection of the signal input terminal and the signal output terminal based on the potential of the first node N1. The second type of switch circuit 4 is connected to the ground terminal (GND) and controls the connection or disconnection of the ground terminal (GND) and the reference signal terminal based on the potential of the second node N2.

[0026] like Figure 3As shown, this disclosure applies to devices including NFC functionality (first device 5, such as a card reader Poller). The first device 5 includes a general-purpose NFC Poller circuit and the aforementioned control device for automatic NFC antenna tuning. Another device (second device 6) is a general-purpose NFC Tag. The first device 5 also includes a capacitor array comprising capacitors Cs1, Cs2, Cp1, and Cp2. In application, a first-type switch circuit 3 can be connected between capacitor Cs1 and inductor L_EMC1, and a second-type switch circuit 4 can be connected between capacitor Cp1 and ground terminal GND. The tuning process includes two parts: resonant frequency detection and resonant point control. The microcontroller unit (MCU) monitors the antenna resonant state through a detection circuit; when the detected resonant frequency deviation exceeds a preset threshold, the MCU calculates the required tuning parameters and then controls the on / off states of the first-type switch circuit 3 and the second-type switch circuit 4 to change the capacitance value connected to the antenna network, thereby achieving automatic adjustment of the resonant point.

[0027] The following is a detailed description of the various parts of a control device for NFC automatic antenna tuning according to an embodiment of the present disclosure: like Figure 1 and Figure 2 As shown, the boost circuit 1 described above may include an inverter. This inverter is connected to a third node N3 and is used to receive a pulse width modulation (PWM) signal and transmit a complementary signal to the third node N3. Specifically, the inverter may include a first transistor and a second transistor. The gate of the first transistor is connected to the PWM signal, the first terminal of the first transistor is connected to the first power supply terminal VCC, and the second terminal of the first transistor is connected to the third node N3. The first transistor may be a PMOS transistor. The gate of the second transistor is connected to the PWM signal, the first terminal of the second transistor is grounded, and the second terminal of the second transistor is connected to the third node N3. The second transistor may be an NMOS transistor. For both the first and second transistors, one of the first and second terminals of each transistor is the source, and the other is the drain.

[0028] like Figure 1 and Figure 2As shown, the boost circuit 1 may further include a voltage doubler rectifier circuit. This voltage doubler rectifier circuit is connected to the third node N3 and is used to output a target voltage signal Vdd based on a complementary signal. Specifically, the voltage doubler rectifier circuit may include a first diode, a second diode, and a third diode, which are connected in series. The input terminal of the first diode is connected to the third node N3, and the output terminal of the third diode outputs the target voltage signal Vdd. The voltage doubler rectifier circuit may also include a first capacitor, a second capacitor, and a third capacitor. One plate of the first capacitor is used to input a pulse width modulation signal PWM, and the other plate of the first capacitor is connected to the output terminal of the first diode. The second capacitor is connected between the input terminal of the first diode and the output terminal of the second diode. The third capacitor is connected between the input terminal of the second diode and the output terminal of the third diode. The voltage doubler rectifier circuit disclosed herein is a multi-stage voltage doubler rectifier circuit (triple voltage). The waveform relationship between the pulse width modulation signal PWM and the target voltage signal Vdd of the boost circuit 1 is as follows: Figure 5 As shown.

[0029] like Figure 1 and Figure 2 As shown, the aforementioned switch control circuit 2 may include a first control sub-circuit. This first control sub-circuit may include a third transistor, a first resistor, and a second resistor. The first terminal of the third transistor is connected to a first input / output control signal IO1, the gate of the third transistor is connected to a first power supply terminal VCC, and the second terminal of the third transistor is connected to a first node N1. The first resistor is connected between the first terminal and the gate of the third transistor. One end of the second resistor is connected to the first node N1, and the other end is connected to a target voltage signal Vdd. The first power supply terminal VCC is a high-level signal. The third transistor may be an NMOS transistor. The first terminal of the third transistor may be the source, and the second terminal may be the drain. When the first input / output control signal IO1 is low, the source-gate voltage difference of the third transistor exceeds a threshold, the third transistor is turned on, and the drain of the third transistor becomes low (approximately 0V). When the first input / output control signal IO1 is high, the source-gate voltage difference of the third transistor is 0, the third transistor is turned off, and the drain voltage of the third transistor is Vdd. The drain potential of the third transistor is the potential of the first node N1.

[0030] like Figure 1 and Figure 2As shown, the aforementioned switch control circuit 2 may further include a second control sub-circuit. This second control sub-circuit may include a fourth transistor, a third resistor, and a fourth resistor. The first terminal of the fourth transistor is connected to the second input / output control signal IO2, the gate of the fourth transistor is connected to the first power supply terminal VCC, and the second terminal of the fourth transistor is connected to the second node N2. The third resistor is connected between the first terminal and the gate of the fourth transistor. One end of the fourth resistor is connected to the second node N2, and the other end of the fourth resistor is connected to the target voltage signal Vdd. The fourth transistor may be an NMOS transistor. The first terminal of the fourth transistor may be the source, and the second terminal may be the drain. When the second input / output control signal IO2 is low, the source-gate voltage difference of the fourth transistor exceeds a threshold, the fourth transistor is turned on, and the drain of the fourth transistor becomes low (approximately 0V). When the second input / output control signal IO2 is high, the source-gate voltage difference of the fourth transistor is 0, the fourth transistor is turned off, and the drain voltage of the fourth transistor is Vdd. The drain potential of the fourth transistor is the potential of the aforementioned second node N2.

[0031] like Figure 1 and Figure 2 As shown, the signal input terminals include a first input terminal SIGNAL1 and a second input terminal SIGNAL5. The signal output terminals include a first output terminal SIGNAL2 and a second output terminal SIGNAL6. At least one type of first-class switching circuit 3 includes two type-first-class switching circuits 3. In the two type-first-class switching circuits 3, one type-first-class switching circuit 3 includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is connected to the first input terminal SIGNAL1, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor, and the second terminal of the sixth transistor is connected to the first output terminal SIGNAL2. The gates of both the fifth and sixth transistors are connected to the first node N1. The first terminal of the fifth transistor is the source, and the second terminal is the drain; the first terminal of the sixth transistor is the drain, and the second terminal is the source. This arrangement allows the parasitic diode in the fifth transistor and the parasitic diode in the sixth transistor to form a back-to-back connection, which can effectively block the leakage of AC signals in the off state. The first input terminal SIGNAL1 is connected to a 13.56MHz signal with an amplitude ≥10V (for example, the first input terminal SIGNAL1 can be...). Figure 3 (A node between capacitor Cs1 and inductor L_EMC1), the first output terminal SIGNAL2 can be Figure 3 Another node between capacitor Cs1 and inductor L_EMC1, that is, the fifth and sixth transistors can be connected to Figure 3The capacitor Cs1 is connected to the inductor L_EMC1. Furthermore, the first output terminal SIGNAL2 can be located on the side of the first input terminal SIGNAL1 that is closer to or further away from capacitor Cs1. Operating principle: When the first node N1 is high (Vdd), the fifth and sixth transistors are turned on; when the first node N1 is low, one of the fifth and sixth transistors is turned off (depending on the level state of the first input terminal SIGNAL1).

[0032] like Figure 1 and Figure 2 As shown, another first-type switching circuit 3 includes a seventh transistor and an eighth transistor. The first terminal of the seventh transistor is connected to the second input terminal SIGNAL5, the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor, and the second terminal of the eighth transistor is connected to the second output terminal SIGNAL6. The gates of both the seventh and eighth transistors are connected to the first node N1. The first terminal of the seventh transistor is the source, and the second terminal is the drain; the first terminal of the eighth transistor is the drain, and the second terminal is the source. This configuration allows the parasitic diodes in the seventh and eighth transistors to form a back-to-back connection, effectively blocking AC signal leakage in the off state. The second input terminal SIGNAL5SIG receives a 13.56MHz signal with an amplitude ≥10V (for example, the second input terminal SIGNAL5 can be...). Figure 3 (A node between capacitor Cs2 and inductor L_EMC2), the second output terminal SIGNAL6 can be Figure 3 Another node between capacitor Cs2 and inductor L_EMC2, that is, the seventh and eighth transistors can be connected to Figure 3 The capacitor Cs2 is located between the capacitor and the inductor L_EMC2. Furthermore, the second output terminal SIGNAL6 can be located on the side of the second input terminal SIGNAL5 that is closer to or further away from capacitor Cs2. Operating principle: When the first node N1 is high (Vdd), the seventh and eighth transistors are turned on; when the first node N1 is low, one of the seventh and eighth transistors is turned off (depending on the level of the second input terminal SIGNAL5).

[0033] like Figure 1 and Figure 2As shown, the aforementioned reference signal terminals include a first reference terminal SIGNAL3 and a second reference terminal SIGNAL4. At least one second-type switching circuit 4 includes two second-type switching circuits 4. One second-type switching circuit 4 includes a ninth transistor, the first terminal of which is connected to ground GND, and the second terminal of which is connected to the first reference terminal SIGNAL3. This ninth transistor can be an NMOS transistor. The first terminal of the ninth transistor is the source, and the second terminal is the drain. Operating principle: When the second node N2 is high (Vdd), the ninth transistor is turned on; when the second node N2 is low, the ninth transistor is turned off. In one embodiment, the ninth transistor can be connected to... Figure 3 The capacitor Cp1 is connected to the ground terminal GND.

[0034] like Figure 1 and Figure 2 As shown, another type 2 switching circuit 4 includes a tenth transistor. The first terminal of the tenth transistor is connected to ground (GND), and the second terminal is connected to the second reference terminal (SIGNAL4). This tenth transistor can be an NMOS transistor. The first terminal of the tenth transistor is the drain, and the second terminal is the source. Operating principle: When the second node N2 is high (Vdd), the tenth transistor is turned on; when the second node N2 is low, the tenth transistor is turned off. In another embodiment, the tenth transistor can be connected to... Figure 3 The capacitor Cp2 is connected to the ground terminal GND. Figure 4 The waveforms of the first output terminal SIGNAL2 and the second output terminal SIGNAL6 are schematically shown. When the first input / output control signal IO1 is high and the second input / output control signal IO2 is low, the signals of the first output terminal SIGNAL2 and the second output terminal SIGNAL6 are shown in the first stage t1; when the first input / output control signal IO1 is low and the second input / output control signal IO2 is low, the signals of the first output terminal SIGNAL2 and the second output terminal SIGNAL6 are shown in the second stage t2; when the first input / output control signal IO1 is low and the second input / output control signal IO2 is high, the signals of the first output terminal SIGNAL2 and the second output terminal SIGNAL6 are shown in the third stage t3; and when the first input / output control signal IO1 is high and the second input / output control signal IO2 is high, the signals of the first output terminal SIGNAL2 and the second output terminal SIGNAL6 are shown in the fourth stage t4. In practical applications, the switching state corresponds to the connection state of the capacitor array, directly affecting the antenna impedance and resonant frequency.

[0035] This disclosure also provides a control method for NFC automatic antenna tuning. The method employs the control device described in any of the preceding claims, and includes: causing a microcontroller unit (MCU) to output a pulse width modulation (PWM) signal, a first input / output control signal (IO1), and a second input / output control signal (IO2); causing a boost circuit 1 to receive the PWM signal and output a target voltage signal (Vdd) based on the PWM signal; causing a switch control circuit 2 to determine the potential of a first node N1 based on the first input / output control signal (IO1) and the target voltage signal (Vdd), and causing the switch control circuit 2 to determine the potential of a second node N2 based on the second input / output control signal (IO2) and the target voltage signal (Vdd); causing a first type of switch circuit 3 to connect or disconnect a signal input terminal from a signal output terminal based on the potential of the first node N1; and causing a second type of switch circuit 4 to connect or disconnect a ground terminal (GND) from a reference signal terminal based on the potential of the second node N2. Since the control method of this disclosure employs the aforementioned control device, it has the same beneficial effects.

[0036] This disclosure also provides an electronic device that may include the control device described in any of the above-mentioned embodiments. The electronic device may be... Figure 2 The first device 5 in the process. The first device 5 can be a mobile phone, etc.

[0037] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A control device for NFC automatic antenna tuning, characterized in that, It includes a microcontroller unit, a boost circuit, a switch control circuit, at least one type-1 switch circuit, and at least one type-2 switch circuit; The microcontroller unit is used to output a pulse width modulation signal, a first input-output control signal, and a second input-output control signal; The boost circuit is used to receive the pulse width modulation signal and output a target voltage signal according to the pulse width modulation signal; The switch control circuit is connected to the first node and the second node, and is used to determine the potential of the first node according to the first input-output control signal and the target voltage signal, and to determine the potential of the second node according to the second input-output control signal and the target voltage signal; The first type of switching circuit is used to connect or disconnect the input and output terminals of the control signal according to the potential of the first node; the first node is located between the switch control circuit and the first type of switching circuit. The second type of switching circuit is connected to the ground terminal and is used to control the ground terminal to be connected or disconnected from the reference signal terminal according to the potential of the second node; the second node is located between the switch control circuit and the second type of switching circuit; The signal input terminal includes a first input terminal and a second input terminal, the signal output terminal includes a first output terminal and a second output terminal, and the at least one first type of switch circuit includes two first type of switch circuits. A first type of switching circuit includes a fifth transistor and a sixth transistor, wherein the first terminal of the fifth transistor is connected to the first input terminal, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor, and the second terminal of the sixth transistor is connected to the first output terminal; the gates of both the fifth transistor and the sixth transistor are connected to the first node; Another of the first type of switching circuits includes a seventh transistor and an eighth transistor, wherein the first terminal of the seventh transistor is connected to the second input terminal, the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor, and the second terminal of the eighth transistor is connected to the second output terminal; the gates of both the seventh transistor and the eighth transistor are connected to the first node.

2. The control device according to claim 1, characterized in that, The boost circuit includes: An inverter, connected to a third node, is used to receive the pulse width modulation signal and transmit a complementary signal to the third node; A voltage doubler rectifier circuit, connected to the third node, is used to output the target voltage signal based on the complementary signal.

3. The control device according to claim 2, characterized in that, The inverter includes: A first transistor, the gate of the first transistor is connected to the pulse width modulation signal, the first terminal of the first transistor is connected to a first power supply terminal, and the second terminal of the first transistor is connected to the third node; The second transistor has its gate connected to the pulse width modulation signal, its first terminal grounded, and its second terminal connected to the third node.

4. The control device according to claim 2, characterized in that, The voltage doubler rectifier circuit includes: A first diode, a second diode, and a third diode are connected in series. The input terminal of the first diode is connected to the third node, and the output terminal of the third diode outputs the target voltage signal. The first capacitor has one plate for receiving the pulse width modulation signal and the other plate connected to the output terminal of the first diode. The second capacitor is connected between the input terminal of the first diode and the output terminal of the second diode; The third capacitor is connected between the input terminal of the second diode and the output terminal of the third diode.

5. The control device according to claim 1, characterized in that, The switch control circuit includes: The first control sub-circuit includes a third transistor, a first resistor, and a second resistor. The first terminal of the third transistor is connected to the first input / output control signal, the gate of the third transistor is connected to the first power supply terminal, and the second terminal of the third transistor is connected to the first node. The first resistor is connected between the first terminal and the gate of the third transistor. One end of the second resistor is connected to the first node, and the other end of the second resistor is connected to the target voltage signal. The second control sub-circuit includes a fourth transistor, a third resistor, and a fourth resistor. The first terminal of the fourth transistor is connected to the second input / output control signal, the gate of the fourth transistor is connected to the first power supply terminal, and the second terminal of the fourth transistor is connected to the second node. The third resistor is connected between the first terminal and the gate of the fourth transistor. One end of the fourth resistor is connected to the second node, and the other end of the fourth resistor is connected to the target voltage signal.

6. The control device according to claim 1, characterized in that, The number of the first type of switch circuits is the same as the number of the second type of switch circuits.

7. The control device according to claim 1, characterized in that, The reference signal terminal includes a first reference terminal and a second reference terminal, and the at least one second type of switch circuit includes two second type of switch circuits. A second type of switching circuit includes a ninth transistor, the first terminal of which is connected to the ground terminal, and the second terminal of which is connected to the first reference terminal; Another type-2 switching circuit includes a tenth transistor, the first terminal of which is connected to the ground terminal, and the second terminal of which is connected to the second reference terminal.

8. A control method for NFC automatic antenna tuning, characterized in that, The method employs the control device according to any one of claims 1-7, and the control method includes: The microcontroller unit outputs a pulse width modulation signal, a first input / output control signal, and a second input / output control signal. The boost circuit receives the pulse width modulation signal and outputs a target voltage signal according to the pulse width modulation signal; The switch control circuit determines the potential of the first node based on the first input / output control signal and the target voltage signal, and the switch control circuit determines the potential of the second node based on the second input / output control signal and the target voltage signal. The first type of switching circuit controls the connection or disconnection of the signal input terminal and the signal output terminal according to the potential of the first node; The second type of switching circuit controls the connection or disconnection of the ground terminal and the reference signal terminal according to the potential of the second node.

9. An electronic device, characterized in that, Includes the control device as described in any one of claims 1-7.

Images