NOR flash memory device and preparation method thereof

Abstract

The invention provides a NOR flash memory device and a preparation method thereof, the NOR flash memory device comprises a substrate and a plurality of gate stack structures, each gate stack structure comprises a tunneling oxide layer, a floating gate, an interlayer dielectric layer and a control gate which are formed in sequence, the tunneling oxide layer is formed on the substrate, the floating gate is formed on the tunneling oxide layer, the interlayer dielectric layer is formed on the floating gate, and the control gate is formed on the interlayer dielectric layer. The interlayer dielectric layer covers the top surfaces of the floating gates, the interlayer dielectric layer also covers at least one side wall of the floating gates, the control gates are formed on the interlayer dielectric layer, and the distance between the adjacent floating gates is greater than the distance between the adjacent control gates. According to the invention, the distance between the adjacent floating gates is greater than the distance between the adjacent control gates, and the size of the floating gates is optimized, so that the adjacent floating gates are prevented from generating interference, and the reliability of the storage unit is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to a NOR flash memory device and its fabrication method. Background Technology

[0002] Flash memory is a type of non-volatile semiconductor memory that retains data for a long lifespan even when power is off. It is a form of electronically erasable programmable read-only memory that allows for multiple erasures and writes during operation. NOR and NAND are the two main non-volatile flash memory technologies on the market. NOR flash memory devices consist of several memory cells, each including a floating gate and a control gate. When erasing data, electrons are transferred from the floating gate to the silicon substrate through the tunneling effect; when writing data, electrons from the channel are captured into the floating gate through a "hot electron injection" mechanism to program the bit state of the corresponding memory cell to '0'. When reading data, the signal identification of 0 and 1 is achieved by detecting changes in the conduction level of the floating gate. However, as the size of memory cells continues to shrink, the distance between memory cells gradually decreases, and interference between bits during operation becomes more significant, affecting the accuracy of data reading, writing, and erasing. Specifically, the memory cell includes a control gate and a floating gate, with the control gate completely covering the floating gate and isolated by an interlayer dielectric layer. When data is written, the corresponding word line / bit line is pressurized and electrons are injected into the target bit. If the two word lines are too close, the adjacent bits may be interfered with, leading to reliability failure. Summary of the Invention

[0003] This application provides a NOR flash memory device and its fabrication method. By making the spacing between adjacent floating gates larger than the spacing between adjacent control gates, the floating gate size is optimized, thereby preventing interference between adjacent floating gates and improving the reliability of the memory cell.

[0004] According to some embodiments of this application, one aspect of this application provides a NOR flash memory device including a substrate and a plurality of gate stack structures, wherein each gate stack structure includes a tunneling oxide layer, a floating gate, an interlayer dielectric layer and a control gate formed sequentially. The tunneling oxide layer is formed on the substrate, the floating gate is formed on the tunneling oxide layer, the interlayer dielectric layer covers the top surface of the floating gate and also covers at least one sidewall of the floating gate, and the control gate is formed on the interlayer dielectric layer. The spacing between adjacent floating gates is greater than the spacing between adjacent control gates.

[0005] Optionally, in a NOR flash memory device, the interlayer dielectric layer covers at least one sidewall of the floating gate and at least one sidewall of the tunneling oxide layer; the control gate covers the upper surface of the interlayer dielectric layer.

[0006] Optionally, in a NOR flash memory device, the interlayer dielectric layer covers at least one sidewall of the floating gate, as well as at least one sidewall of the tunneling oxide layer and a portion of the substrate surface; the control gate covers the upper surface of the interlayer dielectric layer and at least one sidewall of the interlayer dielectric layer, and the control gate also covers the region of the interlayer dielectric layer located above the substrate.

[0007] Optionally, in a NOR flash memory device, an interlayer dielectric layer covers at least one sidewall of the floating gate and contacts the top surface of the tunneling oxide layer; a control gate covers the upper surface of the interlayer dielectric layer and at least one sidewall of the interlayer dielectric layer, and the control gate also covers a portion of the upper surface of the tunneling oxide layer.

[0008] Optionally, in a NOR flash memory device, an interlayer dielectric layer covers at least one sidewall of the floating gate and a portion of the top surface of the tunneling oxide layer; a control gate covers the upper surface of the interlayer dielectric layer and at least one sidewall of the interlayer dielectric layer, and the control gate also covers a portion of the upper surface of the interlayer dielectric layer above the tunneling oxide layer.

[0009] Optionally, in NOR flash memory devices, the interlayer dielectric layer is an ONO dielectric layer.

[0010] According to some embodiments of this application, another aspect of this application also provides a method for fabricating any of the above-mentioned NOR flash memory devices, comprising:

[0011] A substrate is provided; a plurality of gate stack structures are formed on the substrate, wherein each gate stack structure includes a tunneling oxide layer, a floating gate, an interlayer dielectric layer and a control gate formed sequentially, the tunneling oxide layer is formed on the substrate, the floating gate is formed on the tunneling oxide layer, the interlayer dielectric layer covers the top surface of the floating gate and also covers at least one sidewall of the floating gate, and the control gate is formed on the interlayer dielectric layer.

[0012] Optionally, in the fabrication method of NOR flash memory device, the step of forming multiple gate stack structures on the substrate includes: sequentially forming a tunneling oxide layer material and a floating gate material layer on the substrate; performing photolithography and etching processes to pattern the floating gate material layer and the tunneling oxide layer material to form a first opening exposed on the substrate surface, the width of the first opening being used to define the spacing between adjacent floating gates; forming an interlayer dielectric layer material, the interlayer dielectric layer material covering the floating gate material layer and covering the top surface and sidewalls of the first opening; forming a control gate material layer, the control gate material layer covering the interlayer dielectric layer material; performing photolithography and etching processes to pattern the control gate material layer, the interlayer dielectric layer material, the floating gate material layer, and the tunneling oxide layer material to form a second opening exposed on the substrate surface, to form a tunneling oxide layer, a floating gate, an interlayer dielectric layer, and a control gate, the width of the second opening being smaller than the width of the first opening, the width of the second opening being used to define the spacing between adjacent control gates.

[0013] Optionally, in the fabrication method of NOR flash memory device, after the tunneling oxide layer material and the floating gate material layer are sequentially formed on the substrate, and before the floating gate material layer and the tunneling oxide layer material are patterned, the method further includes: performing a chemical mechanical polishing process on the floating gate material layer.

[0014] Optionally, in the fabrication method of NOR flash memory device, after forming the tunneling oxide layer, floating gate, interlayer dielectric layer and control gate, the method further includes: performing an ion implantation process to form source and drain regions in the substrate.

[0015] The technical solution provided in this application has at least the following advantages: In NOR flash memory devices, the interlayer dielectric layer covers the top surface of the floating gate, and the interlayer dielectric layer also covers at least one sidewall of the floating gate. The spacing between adjacent floating gates is greater than the spacing between adjacent control gates, which optimizes the floating gate size and prevents interference between adjacent floating gates, thereby improving the reliability of the memory cell. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a cross-sectional schematic diagram of a memory cell in a relevant NOR flash memory device;

[0018] Figure 2 This is a cross-sectional schematic diagram of a NOR flash memory device provided in this embodiment 1;

[0019] Figure 3 This is a cross-sectional schematic diagram of a NOR flash memory device provided in this second embodiment;

[0020] Figure 4 This is a cross-sectional schematic diagram of a NOR flash memory device provided in this embodiment three;

[0021] Figure 5 This is a cross-sectional schematic diagram of a NOR flash memory device provided in Embodiment 4;

[0022] Figure 6 This is a cross-sectional schematic diagram of a NOR flash memory device provided in Embodiment 5;

[0023] Figures 7A-7FThis is a cross-sectional schematic diagram of each step in the fabrication method of the NOR flash memory device provided in this embodiment.

[0024] Explanation of icon numbers:

[0025] 10-Substrate; 11-Drain region; 12-Source region; 20-Tunneling oxide layer; 30-Floating gate; 40-Interlayer dielectric layer; 50-Control gate; 60-Contact hole plug; 70-Interconnect; 21-Tunneling oxide layer material; 31-Floating gate material layer; 41-Interlayer dielectric layer material; 51-Control gate material layer. Detailed Implementation

[0026] In related NOR flash memory devices, such as Figure 1 As shown, the memory cell includes a control gate 05 and a floating gate 03. To miniaturize NOR flash memory devices, the distance between memory cells is getting closer, causing the spacing L between the floating gates 03 to also become closer. This spacing L directly affects the device's performance. When data is written, the corresponding entire word line is voltaged, and electrons are injected into the target bit. For example, the word line is voltaged to 4V, which is then transferred to the drain region, causing the drain region to also be voltaged to 4V. Electrons are injected into the target bit, and the control gate 05 is voltaged to 10V. If two adjacent word lines are too close, parasitic capacitive coupling occurs, causing electrons to diffuse into the area between adjacent floating gates 03. This alters the threshold voltage of the memory cells already written to on adjacent word lines, leading to a failure in the reliability of the memory function.

[0027] Based on the above research, this application provides a NOR flash memory device and its fabrication method. In the NOR flash memory device, an interlayer dielectric layer covers the top surface of the floating gate, and the interlayer dielectric layer also covers at least one sidewall of the floating gate. The spacing between adjacent floating gates is greater than the spacing between adjacent control gates. This larger spacing between adjacent floating gates optimizes the floating gate size, thereby preventing interference between adjacent floating gates and improving the reliability of the memory cell.

[0028] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0029] In the following text, the terms "first," "second," etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, used in this way, can be substituted where appropriate.

[0030] Similarly, if the method herein comprises a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which these steps can be performed, and some steps may be omitted and / or other steps not described herein may be added to the method, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being “on” a substrate, layer (or film), region, and / or pattern, it may be directly located on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being “under” another layer, it may be directly located under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to “on” and “under” layers may be made based on the accompanying drawings.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] Example 1

[0034] like Figure 2 As shown, the NOR flash memory device provided in this application embodiment includes a substrate 10 and a plurality of gate stack structures. Each gate stack structure includes a tunneling oxide layer 20, a floating gate 30, an interlayer dielectric layer 40, and a control gate 50 formed sequentially. The tunneling oxide layer 20 is formed on the substrate 10, the floating gate 30 is formed on the tunneling oxide layer 20, the interlayer dielectric layer 40 covers the top surface of the floating gate 30, and the interlayer dielectric layer 40 also covers at least one sidewall of the floating gate 30. The control gate 50 is formed on the interlayer dielectric layer 40, and the spacing between adjacent floating gates 30 is greater than the spacing between adjacent control gates 50.

[0035] like Figure 2 As shown, a source region 12 and a drain region 11 are formed in the substrate 10 provided in this embodiment. A channel region is formed between the source region 12 and the drain region 11, and a gate stack structure is formed above the channel region. The source region 12, the drain region 11, and the gate stack structure on the substrate 10 together constitute a transistor structure.

[0036] The substrate 10 may be made of at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. The substrate 10 may also be a multilayer structure composed of these semiconductor materials, or may be silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeO), etc.

[0037] like Figure 2 As shown, in this embodiment, at least one sidewall of the floating gate 30 is covered by an interlayer dielectric layer 40, and a control gate 50 is formed on the interlayer dielectric layer 40. The spacing L1 between adjacent floating gates 30 is greater than the spacing L2 between adjacent control gates 50, thereby improving the anti-interference between adjacent floating gates. In this embodiment, the anti-interference between floating gates is achieved by increasing the distance between adjacent floating gates.

[0038] Furthermore, the interlayer dielectric layer 40 at least covers the sidewalls of the source side of the floating gate 30. By covering the sidewalls of the floating gate 30 with the interlayer dielectric layer 40, electrical isolation is achieved between adjacent floating gates 30, thereby achieving anti-interference between the floating gates 30. Since the spacing between adjacent floating gates 30 is greater than the spacing between adjacent control gates 50, and consequently greater than the word line spacing of the corresponding control gates 50, the increased spacing of the floating gates 30 exponentially reduces the electric field strength and charge tunneling probability between them. Thus, by increasing the distance between adjacent floating gates 30, the parasitic capacitance between them decreases. Even if a voltage change on one word line is capacitively coupled to an adjacent word line, the resulting interference signal is less likely to affect adjacent floating gates.

[0039] In one embodiment, such as Figure 2 As shown, the interlayer dielectric layer 40 covers at least one sidewall of the floating gate 30, as well as at least one sidewall of the tunneling oxide layer 20 and a portion of the surface of the substrate 10; the control gate 50 covers the upper surface of the interlayer dielectric layer 40 and at least one sidewall of the interlayer dielectric layer 40, and the control gate 50 also covers the region of the interlayer dielectric layer 40 located above the substrate 10.

[0040] The floating gate 30 can be made of doped polysilicon, metal, or polysilicon-metal silicide. In this embodiment, the floating gate 30 is made of doped polysilicon, which can effectively prevent charge from leaking back into the channel through trap-assisted tunneling, ensuring long-term data storage, low cost, high manufacturability, good conductivity, and high reliability. Furthermore, the doped polysilicon can be phosphorus-doped polysilicon, the metal can be TiN, TaN, or Ru, and the polysilicon-metal silicide composite structure can be NiSi / Poly-Si or CoSi2 / Poly-Si.

[0041] The interlayer dielectric layer 40 can be one of an oxide-nitride-oxide composite material, a silicon oxynitride material, or a high-k dielectric material. In one embodiment, the interlayer dielectric layer 40 is an ONO dielectric layer.

[0042] The control gate 50 can be made of at least one of doped polysilicon, metal, or polysilicon-metal silicide. Optionally, the doped polysilicon can be phosphorus-doped polysilicon, the metal can be TiN, TaN, or Ru, and the polysilicon-metal silicide composite structure can be NiSi / Poly-Si or CoSi2 / Poly-Si.

[0043] The tunneling oxide layer 20 can be made of thermally oxidized silicon, silicon oxynitride, or a high-k dielectric material.

[0044] As shown in Figure 7, the NOR flash memory device also includes an interconnect structure, which includes a contact hole plug 60 and an interconnect line 70. The interconnect line 70 is electrically connected to the drain region 11 through the contact hole plug 60.

[0045] In one embodiment, the NOR flash memory device includes a plurality of memory cells, each memory cell including a gate stack structure. The memory cells are arranged in rows and columns to form a memory array, the control gate 50 of the memory cells in the same row is connected to the same word line, the drain of the memory cells in the same column is coupled to the same bit line, and all source regions 12 are coupled to a common source line.

[0046] This embodiment optimizes the floating gate size by making the spacing between adjacent floating gates greater than the spacing between adjacent control gates, thereby preventing interference between adjacent floating gates and improving the reliability of the memory cell.

[0047] Figures 7A-7F This is a flowchart illustrating the steps of the fabrication method for the NOR flash memory device provided in this embodiment. The fabrication method for the NOR flash memory device provided in this application embodiment may include the following steps:

[0048] S11: Provide a substrate 10;

[0049] S12: A plurality of gate stack structures are formed on the substrate, wherein each gate stack structure includes a tunneling oxide layer 20, a floating gate 30, an interlayer dielectric layer 40 and a control gate 50 formed sequentially. The tunneling oxide layer 20 is formed on the substrate 10, the floating gate 30 is formed on the tunneling oxide layer 20, the interlayer dielectric layer 40 covers the top surface of the floating gate 30, and the interlayer dielectric layer 40 also covers at least one sidewall of the floating gate 30. The control gate 50 is formed on the interlayer dielectric layer 40.

[0050] The following is based on Figure 2 The NOR flash memory device structure shown is used as an example for detailed explanation.

[0051] First, such as Figure 7A As shown, a tunneling oxide layer material 21 and a floating gate material layer 31 are sequentially formed on the substrate 10.

[0052] Next, photolithography and etching processes are performed, such as... Figure 7B As shown, the patterned floating gate material layer 21 and the tunneling oxide layer material 31 form a first opening A exposed on the substrate surface. The width of the first opening A is used to define the spacing between adjacent floating gates 30. Further, the etching process employs either a dry etching process or a wet etching process to form isolation trenches. When using a dry etching process, reactive ion etching or inductively coupled plasma etching can be employed. When using a wet etching process, the wet etching solution may include tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

[0053] Next, as Figure 7C As shown, an interlayer dielectric layer material 41 is formed, which covers the floating gate material layer 31 and the top surface and sidewalls of the first opening A. Further, the interlayer dielectric layer material 41 is formed using chemical vapor deposition, atomic layer deposition, or high-density plasma chemical vapor deposition processes.

[0054] Next, as Figure 7D As shown, a control gate material layer 51 is formed, and the control gate material layer 51 covers the interlayer dielectric layer material 41.

[0055] Next, photolithography and etching processes are performed, such as... Figure 7E As shown, the patterned control gate material layer 51, interlayer dielectric layer material 41, floating gate material layer 31, and tunneling oxide layer material 21 form a second opening B exposed on the surface of the substrate 10 to form the tunneling oxide layer 20, floating gate 30, interlayer dielectric layer 40, and control gate 50. The width of the second opening B is smaller than the width of the first opening A, and the width of the second opening B is used to define the spacing between adjacent control gates 50. Furthermore, the photolithography and etching processes can be performed using 193nm ArF photolithography, extreme ultraviolet photolithography, or self-aligned multiple patterning techniques.

[0056] The process includes, after the tunneling oxide layer material 21 and the floating gate material layer 31 are sequentially formed on the substrate 10, and before the floating gate material layer 31 and the tunneling oxide layer material 21 are patterned, performing a chemical mechanical polishing process on the floating gate material layer 31.

[0057] Next, after forming the tunneling oxide layer 20, the floating gate 30, the interlayer dielectric layer 40, and the control gate 50, an ion implantation process is performed to form the source region 12 and the drain region 11 in the substrate 10. Further, a channel region is located below the gate stack structure between the source region 12 and the drain region 11.

[0058] Next, as Figure 7F As shown, an interconnection structure is formed by the contact hole plug 60 and the interconnect line 70, which connects the control gate 50, the drain of the drain region 11 and the source of the source region 12 to the corresponding word line, bit line and common source line respectively through the interconnection structure.

[0059] Example 2

[0060] In this embodiment, as Figure 3 As shown, the interlayer dielectric layer 40 covers at least one sidewall of the floating gate 30 and at least one sidewall of the tunneling oxide layer 20, while the control gate 50 covers the upper surface of the interlayer dielectric layer 40. This embodiment focuses on the... Figure 2 The differences are minor, and the parts with the same structure will not be repeated.

[0061] Example 3

[0062] like Figure 4 As shown, the interlayer dielectric layer 40 covers at least one sidewall of the floating gate 30 and is in contact with the top surface of the tunneling oxide layer 20; the control gate 50 covers the upper surface of the interlayer dielectric layer 40 and at least one sidewall of the interlayer dielectric layer 40, and the control gate 50 also covers a portion of the upper surface of the tunneling oxide layer 20.

[0063] Example 4

[0064] like Figure 5 As shown, the interlayer dielectric layer 40 covers at least one sidewall of the floating gate 30 and a portion of the top surface of the tunneling oxide layer 20; the control gate 50 covers the upper surface of the interlayer dielectric layer 40 and at least one sidewall of the interlayer dielectric layer 40, and the control gate 50 also covers a portion of the upper surface of the interlayer dielectric layer 40 above the tunneling oxide layer 20.

[0065] Example 5

[0066] like Figure 6 As shown, the top surface of the tunneling oxide layer 20 is partially open. The interlayer dielectric layer 40 covers at least one sidewall of the floating gate 30 and covers the top surface partial opening of the tunneling oxide layer 20; the control gate 50 covers the upper surface of the interlayer dielectric layer 40 and at least one sidewall of the interlayer dielectric layer 40, and the control gate 50 also covers a portion of the upper surface of the interlayer dielectric layer 40 above the tunneling oxide layer 20.

[0067] The above describes several gate stacking structures of NOR flash memory devices according to embodiments of the present invention. All of them can achieve the purpose of the spacing between adjacent floating gates 30 being greater than the spacing between adjacent control gates 50, and can improve the anti-interference purpose between adjacent floating gates.

[0068] In summary, by adopting the technical solution provided in this embodiment, the interlayer dielectric layer covers the top surface of the floating gate and also covers at least one sidewall of the floating gate, with the control gate formed on the interlayer dielectric layer. This optimizes the local floating gate size, making the spacing between adjacent floating gates larger than the spacing between adjacent control gates. Because the floating gates maintain a relatively large distance from each other, interference with adjacent floating gates is prevented, thereby improving the reliability of the memory cell.

[0069] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A NOR flash memory device, characterized by, The application relates to a flash memory device, comprising a substrate and a plurality of gate stack structures, wherein each of the gate stack structures comprises a tunneling oxide layer, a floating gate, an interlayer dielectric layer and a control gate which are sequentially formed, the tunneling oxide layer is formed on the substrate, the floating gate is formed on the tunneling oxide layer, the interlayer dielectric layer covers the top surface of the floating gate and at least one sidewall of the floating gate, and the control gate is formed on the interlayer dielectric layer, the distance between adjacent floating gates is greater than the distance between adjacent control gates.

2. The NOR flash memory device of claim 1, wherein, The interlayer dielectric layer covers at least one sidewall of the floating gate and at least one sidewall of the tunneling oxide layer; and the control gate covers the upper surface of the interlayer dielectric layer.

3. The NOR flash memory device of claim 1, wherein, The interlayer dielectric layer covers at least one sidewall of the floating gate and at least one sidewall of the tunneling oxide layer and part of the surface of the substrate; and the control gate covers the upper surface of the interlayer dielectric layer and at least one sidewall of the interlayer dielectric layer, and the control gate also covers the region of the interlayer dielectric layer above the substrate.

4. The NOR flash memory device of claim 1, wherein, The interlayer dielectric layer covers at least one sidewall of the floating gate and contacts the top surface of the tunneling oxide layer; and the control gate covers the upper surface of the interlayer dielectric layer and at least one sidewall of the interlayer dielectric layer, and the control gate also covers part of the upper surface of the tunneling oxide layer.

5. The NOR flash memory device of claim 1, wherein, The interlayer dielectric layer covers at least one sidewall of the floating gate and covers part of the top surface of the tunneling oxide layer; and the control gate covers the upper surface of the interlayer dielectric layer and at least one sidewall of the interlayer dielectric layer, and the control gate also covers part of the upper surface of the interlayer dielectric layer above the tunneling oxide layer.

6. The NOR flash memory device of claim 1, wherein, The interlayer dielectric layer is an ONO dielectric layer.

7. A method of forming a NOR flash memory device as claimed in any one of claims 1 to 6, characterized in that, The application relates to a flash memory device, comprising a substrate and a plurality of gate stack structures, wherein each of the gate stack structures comprises a tunneling oxide layer, a floating gate, an interlayer dielectric layer and a control gate which are sequentially formed, the tunneling oxide layer is formed on the substrate, the floating gate is formed on the tunneling oxide layer, the interlayer dielectric layer covers the top surface of the floating gate and at least one sidewall of the floating gate, and the control gate is formed on the interlayer dielectric layer, the distance between adjacent floating gates is greater than the distance between adjacent control gates. The application relates to a flash memory device, comprising a substrate and a plurality of gate stack structures, wherein each of the gate stack structures comprises a tunneling oxide layer, a floating gate, an interlayer dielectric layer and a control gate which are sequentially formed, the tunneling oxide layer is formed on the substrate, the floating gate is formed on the tunneling oxide layer, the interlayer dielectric layer covers the top surface of the floating gate and at least one sidewall of the floating gate, and the control gate is formed on the interlayer dielectric layer, the distance between adjacent floating gates is greater than the distance between adjacent control gates. Sequentially forming a tunneling oxide layer material and a floating gate material layer on the substrate; 8. The method of claim 7, wherein the method further comprises: Performing a photolithography and etching process to pattern the floating gate material layer and the tunneling oxide layer material to form a first opening which exposes the surface of the substrate, and the width of the first opening is used to define the distance between adjacent floating gates; Forming an interlayer dielectric layer material which covers the floating gate material layer and covers the top surface and sidewall of the first opening; Forming a control gate material layer which covers the interlayer dielectric layer material; and Forming a control gate material layer which covers the interlayer dielectric layer material; and ​ performing a lithography and etching process to pattern the control gate material layer, the interlayer dielectric material, the floating gate material layer, and the tunnel oxide material to form second openings exposing the substrate surface to form the tunnel oxide, the floating gate, the interlayer dielectric, and the control gate, the second openings having a width less than the width of the first openings, the width of the second openings defining a pitch between adjacent control gates.

9. The method for fabricating a NOR flash memory device according to claim 8, characterized in that, After sequentially forming the tunnel oxide material and the floating gate material layer on the substrate, before patterning the floating gate material layer and the tunnel oxide material, further comprising: performing a chemical mechanical polishing process on the floating gate material layer.

10. The method for fabricating a NOR flash memory device according to claim 7, characterized in that, After forming the tunnel oxide, the floating gate, the interlayer dielectric, and the control gate, further comprising: performing an ion implantation process to form source and drain regions in the substrate.

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