An LDMOS device structure resistant to single event radiation

Abstract

The application discloses an anti-single-particle-radiation LDMOS device structure and belongs to the technical field of semiconductor power devices. The device comprises a P-type substrate, an N-type buried layer, a P-type epitaxial layer, an N-type deep well, a P-type deep well, an STI shallow trench isolation oxide layer, a gate oxide layer, an HTO oxide layer, polycrystalline silicon, an N-type well region, a P-type well region, a P-type buried layer, an N-type drift region, a P-type body region, a source region N+ injection, a drain region N+ injection, a body region P+ injection, an isolation N+ injection and an isolation P+ injection. The single-drain region is changed into a double-drain region, the parasitic triode is a double-collector, plays a role of current sharing, can reduce a drain end electric field peak, suppresses a Kirk effect and thus improves the anti-single-particle-radiation capability of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to an LDMOS device structure resistant to single-event radiation. Background Technology

[0002] LDMOS (Laterally Diffused Metal-Oxide Semiconductor) devices are key components in aerospace analog circuits, and their operational stability is crucial to the overall circuit function. However, in the complex radiation environment of space (such as high-energy particle radiation and proton radiation), LDMOS devices are highly susceptible to Single Event Burnout (SEB). When a high-energy particle strikes the device, it generates a large instantaneous current inside the device, leading to localized overheating, permanent degradation of electrical parameters, or even complete damage, ultimately causing device failure. This can paralyze the entire power management system or gate drive circuit, seriously threatening the safety and reliability of aerospace missions. Therefore, developing LDMOS devices with SEB resistance for the space radiation environment has become an urgent need to ensure the stable operation of aerospace electronic systems and is also an important research topic in the field of power semiconductors. Summary of the Invention

[0003] To address the single-event burn-out problem of LDMOS devices under space radiation, this invention proposes a novel structure with the core objective of reducing the drain-side spike electric field through current shunting. In the space environment, high-energy particles (such as protons and heavy ions) enter the LDMOS, exciting a large number of electron-hole pairs through energy deposition. Driven by the device's built-in electric field, electrons migrate towards the drain, and holes move towards the source. Some holes flow into the P-well (parasitic transistor base region) and out through the body electrode P+. The hole current generates a voltage drop in the P-well. When it reaches a threshold, it forward-biases the P-well / N+ source junction, triggering the parasitic transistor to turn on. After the parasitic transistor turns on, N+ electrons from the source are injected into the drift region through the P-well, inducing the Kirk effect, further intensifying ionization and generating more electron-hole pairs. The newly generated holes move towards the source, providing positive feedback current to the parasitic transistor base region, causing a surge in device current, ultimately leading to overheating and burn-out. To address the aforementioned failure paths, this invention optimizes the structure, transforming the single-drain region into a dual-drain region. The parasitic transistor then functions as a dual-collector electrode, acting as a current shunt. This reduces drain-side electric field spikes, suppresses the Kirk effect, and effectively improves the LDMOS's resistance to single-event burnout. To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0004] A single-particle-resistant LDMOS device structure includes a first conductivity type substrate 1, a second conductivity type buried layer 2, a first conductivity type epitaxial layer 3, a second conductivity type deep well 4, a first conductivity type deep well 5, a second conductivity type well region 6, a first conductivity type well region 7, a first conductivity type buried layer 8, a second conductivity type drift region 9, a first conductivity type body region 10, an STI shallow trench isolation oxide layer 11, a second conductivity type isolation injection region 12, a first conductivity type isolation injection region 13, a second conductivity type dual drain region 14, a second conductivity type source region 15, a first conductivity type body injection region 16, an HTO field oxide layer region 17, a gate oxide layer region 18, and a polysilicon gate electrode 19.

[0005] The first conductivity type substrate 1 is located at the bottom layer, and the second conductivity type buried layer 2 is stacked on top; the first conductivity type epitaxial layer 3 is located to the upper left of the second conductivity type buried layer 2; the first conductivity type deep well 5 is close to the right boundary of the first conductivity type epitaxial layer 3 and is located to its right; the second conductivity type deep well 4 is close to the right boundary of the first conductivity type deep well 5 and is located to its right; the second conductivity type well region 6 is located above the second conductivity type deep well 4, and the first conductivity type well region 7 is located above the first conductivity type deep well 5; the first conductivity type buried layer 8 is located inside the first conductivity type epitaxial layer 3 at a slightly lower right position, and is adjacent to the first conductivity type deep well 5 on its right; the second conductivity type drift region 9 is located in the first conductivity type buried layer 3. Above layer 8; the first conductivity type body region 10 is located inside the first conductivity type epitaxial layer 3 at the upper left, and slightly spaced from the second conductivity type drift region 9 on the right; the first STI shallow trench isolation oxide layer 11 is located inside the second conductivity type drift region 9 at the upper right, not adjacent to its right boundary; the second STI shallow trench isolation oxide layer 11 spans over the first conductivity type well region 7 and the second conductivity type drift region 9, covering part of the first conductivity type well region 7 and the second conductivity type drift region 9; the third STI shallow trench isolation oxide layer 11 spans over the second conductivity type well region 6 and the first conductivity type well region 7, covering part of the second conductivity type well region 6 and the first conductivity type well region 7; the second conductivity type body region 10 is located inside the first conductivity type epitaxial layer 3 at the upper left, and slightly spaced from the second conductivity type drift region 9 on the right; the second conductivity type body region 10 is located inside the second conductivity type drift region 6 ... Type isolation injection region 12 is located above the interior of the second conductivity type well region 6, adjacent to the right side of the third STI shallow trench isolation oxide layer 11; the first conductivity type isolation injection region 13 is located above the first conductivity type well region 7, with its left and right sides adjacent to the right side of the second STI shallow trench isolation oxide layer 11 and the left side of the third STI shallow trench isolation oxide layer 11, respectively; the first second conductivity type drain region 14 is adjacent to the left side of the first STI shallow trench isolation oxide layer 11, and the second second conductivity type drain region 14 is located above and to the right of the second conductivity type drift region 9, with its left and right sides adjacent to the right side of the first STI shallow trench isolation oxide layer 11 and the left side of the second STI shallow trench isolation oxide layer 11, respectively; The first conductivity type body injection region 16 is located to the upper left of the first conductivity type body region 10, and its left boundary is the same as that of the first conductivity type body region 10; the second conductivity type source region 15 is adjacent to the right side of the first conductivity type body injection region 16; the HTO field oxide layer region 17 is located above the second conductivity type drift region 9; the gate oxide layer region 18 is located above the second conductivity type drift region 9, and its right boundary is adjacent to the left boundary of the HTO field oxide layer region 17, and its height is lower than that of the HTO field oxide layer region 17; the polysilicon gate electrode 19 is located above the HTO field oxide layer region 17 and the gate oxide layer region 18, and its left boundary is the same as the left boundary of the gate oxide layer region 18, and its right boundary does not exceed the right boundary of the HTO field oxide layer region 17.

[0006] As a preferred embodiment, the first second conductivity type drain region 14 is located immediately to the left of the first STI shallow trench isolation oxide layer 11.

[0007] As a preferred embodiment, the second second conductivity type drain region 14 is located to the upper right of the second conductivity type drift region 9, and its left and right sides are adjacent to the right side of the first STI shallow trench isolation oxide layer 11 and the left side of the second STI shallow trench isolation oxide layer 11, respectively.

[0008] As a preferred embodiment, the right boundary of the source region 15 of the second conductivity type is the same as the left boundary of the gate oxide region 18 and the polysilicon gate electrode 19.

[0009] As a preferred embodiment, the polysilicon gate electrode 19 is located above the HTO field oxide layer region 17 and the gate oxide layer region 18, with its left boundary being the same as the left boundary of the gate oxide layer region 18 and its right boundary not exceeding the right boundary of the HTO field oxide layer region 17.

[0010] As a preferred embodiment, when the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

[0011] The beneficial effects of this invention are:

[0012] This invention provides a highly reliable LDMOS device structure resistant to single-event radiation. By introducing an additional STI shallow trench isolation oxide layer in the drift region, the original single drain is separated into a dual drain, and the parasitic transistor becomes a dual collector. When the source-end electrons are injected into the drift region due to the single-event effect, it plays a shunt role, which can effectively reduce the drain-end electric field spike, suppress the Kirk effect, and prevent positive feedback that causes single-event burnout, thereby improving the device's resistance to single-event radiation. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the LDMOS device structure described in this invention.

[0014] Figure 2 This is a schematic diagram illustrating the fabrication process of the STI shallow trench isolation oxide layer in the LDMOS device described in this invention.

[0015] Figure 3 This is a schematic diagram of the injection of the source region, drain region, and isolation region of the second conductivity type of LDMOS described in this invention.

[0016] The reference numerals used in the accompanying drawings are as follows:

[0017] 1-First conductivity type substrate, 2-Second conductivity type buried layer, 3-First conductivity type epitaxial layer, 4-Second conductivity type deep well, 5-First conductivity type deep well, 6-Second conductivity type well region, 7-First conductivity type well region, 8-First conductivity type buried layer, 9-Second conductivity type drift region, 10-First conductivity type body region, 11-Shallow trench isolation oxide layer, 12-Second conductivity type isolation implantation region, 13-First conductivity type isolation implantation region, 14-Second conductivity type drain region, 15-Second conductivity type source region, 16-First conductivity type body implantation region, 17-HTO field oxide layer region, 18-Gate oxide layer region, 19-Polysilicon gate electrode. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0019] This embodiment provides an LDMOS device resistant to single-event radiation, such as... Figure 1 As shown, it includes a first conductivity type substrate 1, a second conductivity type buried layer 2, a first conductivity type epitaxial layer 3, a second conductivity type deep well 4, a first conductivity type deep well 5, a second conductivity type well region 6, a first conductivity type well region 7, a first conductivity type buried layer 8, a second conductivity type drift region 9, a first conductivity type body region 10, an STI shallow trench isolation oxide layer 11, a second conductivity type isolation implantation region 12, a first conductivity type isolation implantation region 13, a second conductivity type dual drain region 14, a second conductivity type source region 15, a first conductivity type body implantation region 16, an HTO field oxide layer region 17, a gate oxide layer region 18, and a polysilicon gate electrode 19.

[0020] The first conductivity type substrate 1 is located at the bottom layer, and the second conductivity type buried layer 2 is stacked on top; the first conductivity type epitaxial layer 3 is located to the upper left of the second conductivity type buried layer 2; the first conductivity type deep well 5 is close to the right boundary of the first conductivity type epitaxial layer 3 and is located to its right; the second conductivity type deep well 4 is close to the right boundary of the first conductivity type deep well 5 and is located to its right; the second conductivity type well region 6 is located above the second conductivity type deep well 4, and the first conductivity type well region 7 is located above the first conductivity type deep well 5; the first conductivity type buried layer 8 is located inside the first conductivity type epitaxial layer 3 on the right side, and is adjacent to the first conductivity type deep well 5 on the right; the second conductivity type drift region 9 is located inside the first conductivity type buried layer 3 on the right side. Above layer 8; the first conductivity type body region 10 is located inside the first conductivity type epitaxial layer 3 at the upper left, and slightly spaced from the second conductivity type drift region 9 on the right; the first STI shallow trench isolation oxide layer 11 is located inside the second conductivity type drift region 9 at the upper right, not adjacent to its right boundary; the second STI shallow trench isolation oxide layer 11 spans over the first conductivity type well region 7 and the second conductivity type drift region 9, covering part of the first conductivity type well region 7 and the second conductivity type drift region 9; the third STI shallow trench isolation oxide layer 11 spans over the second conductivity type well region 6 and the first conductivity type well region 7, covering part of the second conductivity type well region 6 and the first conductivity type well region 7; the second conductivity type body region 10 is located inside the first conductivity type epitaxial layer 3 at the upper left, and slightly spaced from the second conductivity type drift region 9 on the right; the second conductivity type body region 10 is located inside the second conductivity type drift region 6 ... Type isolation injection region 12 is located above the interior of the second conductivity type well region 6, adjacent to the right side of the third STI shallow trench isolation oxide layer 11; the first conductivity type isolation injection region 13 is located above the first conductivity type well region 7, with its left and right sides adjacent to the right side of the second STI shallow trench isolation oxide layer 11 and the left side of the third STI shallow trench isolation oxide layer 11, respectively; the first second conductivity type drain region 14 is adjacent to the left side of the first STI shallow trench isolation oxide layer 11, and the second second conductivity type drain region 14 is located above and to the right of the second conductivity type drift region 9, with its left and right sides adjacent to the right side of the first STI shallow trench isolation oxide layer 11 and the left side of the second STI shallow trench isolation oxide layer 11, respectively; The first conductivity type body injection region 16 is located to the upper left of the first conductivity type body region 10, and its left boundary is the same as that of the first conductivity type body region 10; the second conductivity type source region 15 is adjacent to the right side of the first conductivity type body injection region 16; the HTO field oxide layer region 17 is located above the second conductivity type drift region 9; the gate oxide layer region 18 is located above the second conductivity type drift region 9, and its right boundary is adjacent to the left boundary of the HTO field oxide layer region 17, and its height is lower than that of the HTO field oxide layer region 17; the polysilicon gate electrode 19 is located above the HTO field oxide layer region 17 and the gate oxide layer region 18, and its left boundary is the same as the left boundary of the gate oxide layer region 18, and its right boundary does not exceed the right boundary of the HTO field oxide layer region 17.

[0021] The first second conductivity type drain region 14 is adjacent to the left side of the first STI shallow trench isolation oxide layer 11.

[0022] The second second conductivity type drain region 14 is located to the upper right of the second conductivity type drift region 9, and its left and right sides are adjacent to the right side of the first STI shallow trench isolation oxide layer 11 and the left side of the second STI shallow trench isolation oxide layer 11, respectively.

[0023] The right boundary of the source region 15 of the second conductivity type is the same as the left boundary of the gate oxide region 18 and the polysilicon gate electrode 19.

[0024] The polysilicon gate electrode 19 is located above the HTO field oxide layer region 17 and the gate oxide layer region 18. Its left boundary is the same as the left boundary of the gate oxide layer region 18, and its right boundary does not exceed the right boundary of the HTO field oxide layer region 17.

[0025] When the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

[0026] like Figure 2 As shown, in preparing the shallow trench isolation oxide layer, firstly, a nitride layer is deposited on the upper surfaces of the first conductivity type epitaxial layer 3, the second conductivity type deep well 4, and the first conductivity type deep well 5. Then, the shallow trench isolation oxide layer is etched to break the STI shallow trench isolation oxide layer 11, located above the subsequently doped second conductivity type drift region 9 and the first conductivity type well region 7, into two parts. Then, a thick oxide layer is deposited and CMP smoothed, breaking the STI shallow trench isolation oxide layer 11, located above the second conductivity type drift region 9 and the first conductivity type well region 7, into two parts, forming a segmented STI shallow trench isolation oxide layer. Figure 3 The diagram shown is a schematic of the injection of the source, drain, and isolation regions of the second conductivity type of LDMOS according to the present invention.

[0027] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A single-event radiation resistant LDMOS device structure, characterized in that, It includes a first conductivity type substrate (1), a second conductivity type buried layer (2), a first conductivity type epitaxial layer (3), a second conductivity type deep well (4), a first conductivity type deep well (5), a second conductivity type well region (6), a first conductivity type well region (7), a first conductivity type buried layer (8), a second conductivity type drift region (9), a first conductivity type body region (10), an STI shallow trench isolation oxide layer (11), a second conductivity type isolation implantation region (12), a first conductivity type isolation implantation region (13), a second conductivity type dual drain region (14), a second conductivity type source region (15), a first conductivity type body implantation region (16), an HTO field oxide layer region (17), a gate oxide layer region (18), and a polysilicon gate electrode (19). A first conductivity type substrate (1) is located at the bottom layer, and a second conductivity type buried layer (2) is stacked on the first conductivity type substrate (1); a first conductivity type epitaxial layer (3) is located at the upper left of the second conductivity type buried layer (2); The first conductivity type deep well (5) is located near the right boundary of the first conductivity type epitaxial layer (3) and is situated to its right. The second type of conductivity deep well (4) is close to the right boundary of the first type of conductivity deep well (5) and is located to its right. The second conductivity type well region (6) is located above the second conductivity type deep well (4), and the first conductivity type well region (7) is located above the first conductivity type deep well (5); the first conductivity type buried layer (8) is located inside the first conductivity type epitaxial layer (3) at a slightly lower right position, and is adjacent to the first conductivity type deep well (5) on the right; the second conductivity type drift region (9) is located above the first conductivity type buried layer (8); the first conductivity type body region (10) is located inside the first conductivity type epitaxial layer (3) at a slightly upper left position, and is separated from the second conductivity type drift region (9) on the right; the first STI shallow trench isolation oxide layer (11) is located inside the second conductivity type drift region (9) at a slightly upper right position, and is not adjacent to it. The right boundary is adjacent; the second STI shallow trench isolation oxide layer (11) is connected across the first conductivity type well region (7) and the second conductivity type drift region (9), covering part of the first conductivity type well region (7) and part of the second conductivity type drift region (9); the third STI shallow trench isolation oxide layer (11) is connected across the second conductivity type well region (6) and the first conductivity type well region (7), covering part of the second conductivity type well region (6) and part of the first conductivity type well region (7); the second conductivity type isolation injection region (12) is located above the interior of the second conductivity type well region (6), adjacent to the right side of the third STI shallow trench isolation oxide layer (11); the first conductivity type isolation injection region ( 13) Located above the first conductivity type well region (7), its left and right sides are adjacent to the right side of the second STI shallow trench isolation oxide layer (11) and the left side of the third STI shallow trench isolation oxide layer (11), respectively; the first second conductivity type drain region (14) is adjacent to the left side of the first STI shallow trench isolation oxide layer (11), and the second second conductivity type drain region (14) is located above the right of the second conductivity type drift region (9), its left and right sides are adjacent to the right side of the first STI shallow trench isolation oxide layer (11) and the left side of the second STI shallow trench isolation oxide layer (11), respectively; the first conductivity type body injection region (16) is located above the left of the first conductivity type body region (10), and its left boundary is adjacent to the right side of the first conductivity type body region (10). The left boundary of the first conductivity type body region (10) is the same; the second conductivity type source region (15) is adjacent to the right side of the first conductivity type body injection region (16); the HTO field oxide layer region (17) is located above the second conductivity type drift region (9); the gate oxide layer region (18) is located above the second conductivity type drift region (9), and its right boundary is adjacent to the left boundary of the HTO field oxide layer region (17), and its height is lower than that of the HTO field oxide layer region (17); the polysilicon gate electrode (19) is located above the HTO field oxide layer region (17) and the gate oxide layer region (18), and its left boundary is the same as the left boundary of the gate oxide layer region (18), and its right boundary does not exceed the right boundary of the HTO field oxide layer region (17).

2. The LDMOS device structure resistant to single-event radiation according to claim 1, characterized in that, The right boundary of the source region (15) of the second conductivity type is the same as the left boundary of the gate oxide region (18) and the polysilicon gate electrode (19).

3. The LDMOS device structure resistant to single-event radiation according to claim 1, characterized in that: When the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

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