Back contact cell with reduced thickness difference between n-type and p-type regions and preparation and use thereof

Abstract

The present application belongs to the technical field of back contact cells, and particularly relates to a back contact cell with reduced thickness difference between N-type and P-type regions, preparation and application, comprising a crystalline silicon substrate, an amorphous silicon layer and a conductive film layer arranged in sequence on the back of the crystalline silicon substrate, wherein the side surface of the amorphous silicon layer away from the crystalline silicon substrate has alternately formed N-type and P-type regions, the N-type region comprises an N-type doped base layer and an N-type transition layer, and the P-type region comprises a P-type doped base layer and a P-type transition layer; wherein the phosphorus-silicon content ratio in the N-type doped base layer is less than 1, the phosphorus-silicon content ratio in the N-type transition layer is greater than 1, the boron-silicon content ratio in the P-type doped base layer is less than 1, and the boron-silicon content ratio in the P-type transition layer is greater than 1. The present application can reduce the thickness difference between the N-type and P-type regions, significantly reduce the longitudinal contact resistance, obtain high cell conversion efficiency, improve the stability and service life of the cell, reduce the risk of film explosion in the subsequent process, and alleviate the edge recombination problem.

Description

Technical Field

[0001] This invention belongs to the field of back contact battery technology, specifically relating to a back contact battery that reduces the thickness difference between the N-type and P-type regions, as well as its preparation and application. Background Technology

[0002] In the field of solar cells, back-contact cells are valued for their high efficiency and low series resistance. However, in traditional back-contact cell designs, the P-type region is typically thicker than the N-type region to ensure efficient hole transport and reduce the difficulty of fine patterning etching on the back side.

[0003] However, in existing back-contact battery structures, the thickness difference between the N-type and P-type regions leads to a series of technical problems. First, this thickness difference causes stress concentration at the N / P region interface, which not only exacerbates edge recombination but also affects the long-term stability of the battery. Second, due to the thickness difference, the morphology of the back reflective layer is uneven, which reduces back reflectivity and decreases the battery's photoelectric conversion efficiency. Finally, stress mismatch can also lead to film delamination in subsequent processes, increasing the risks and costs in the production process.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of conventional back-contact battery structures in the prior art, such as edge recombination, reduced back reflectivity leading to low battery conversion efficiency, and increased risk of membrane bursting. This invention provides a back-contact battery with reduced thickness difference between the N-type and P-type regions, along with its fabrication and application. This invention can significantly reduce longitudinal contact resistance while reducing the thickness difference between the N-type and P-type regions, achieving high battery conversion efficiency, and simultaneously improving battery stability and lifespan. Furthermore, it can reduce stress mismatch and stress concentration problems, lowering the risk of membrane bursting in subsequent processes and mitigating edge recombination issues.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a back contact battery for reducing the thickness difference between N-type and P-type regions, comprising a crystalline silicon substrate, an amorphous silicon layer and a conductive film layer sequentially disposed on the back side of the crystalline silicon substrate, wherein the surface of the amorphous silicon layer away from the crystalline silicon substrate has alternately formed N-type and P-type regions, and an intermediate isolation region disposed between the N-type and P-type regions, wherein at least a portion outside the intermediate isolation region is not provided with a conductive film layer to form an isolation trench, wherein the N-type region comprises an N-type doped base layer and an N-type transition layer sequentially disposed from the inside to the outside, and the P-type region comprises a P-type doped base layer and a P-type transition layer sequentially disposed from the inside to the outside; wherein the phosphorus-silicon content ratio in the N-type doped base layer is less than 1 by atomic percentage, the phosphorus-silicon content ratio in the N-type transition layer is greater than 1 by atomic percentage, the boron-silicon content ratio in the P-type doped base layer is less than 1 by atomic percentage, and the boron-silicon content ratio in the P-type transition layer is greater than 1 by atomic percentage.

[0007] In some preferred embodiments of the present invention, the phosphorus-silicon content ratio in the N-type doped base layer is 0.01-0.6 in atomic percentage, and the phosphorus-silicon content ratio in the N-type transition layer is ≥8 in atomic percentage.

[0008] In some preferred embodiments of the present invention, the borosilicate content ratio in the P-type doped base layer is 0.01-0.6 in atomic percentage, and the borosilicate content ratio in the P-type transition layer is greater than 10 in atomic percentage.

[0009] In some preferred embodiments of the present invention, the ratio of borosilicate content in the P-type doped base layer and the P-type transition layer, expressed as atomic percentage, is denoted as P1 and P2, respectively, which satisfies that P2:P1 is (5-1000):1.

[0010] In some preferred embodiments of the present invention, the phosphorus doping concentration in the N-type transition layer is 5e20cm. -3 -5e22cm -3 The hydrogen doping concentration is 1e20cm. -3 -5e22cm -3 ; and / or, the boron doping concentration in the P-type transition layer is 5e20cm. -3 -5e22cm -3 The hydrogen doping concentration is 1e20cm. -3 -5e22cm -3 .

[0011] In some preferred embodiments of the present invention, the phosphorus doping concentration in the N-type doped substrate is 1e20cm⁻¹. -3 -8e21cm -3 The hydrogen doping concentration is 1e20cm. -3 -5e22cm -3 ; and / or, the boron doping concentration in the P-type doped substrate is 1e20cm⁻¹ -3-5e21cm -3 The hydrogen doping concentration is 1e20cm. -3 -5e22cm -3 .

[0012] In some preferred embodiments of the present invention, the ratio of the thickness of the N-type transition layer to the thickness of the N-type doped base layer is (0.01-5):1.

[0013] In some preferred embodiments of the present invention, the thickness of the N-type transition layer is 0.2-4 nm, and the thickness of the N-type doped substrate is 3-20 nm.

[0014] In some preferred embodiments of the present invention, the ratio of the thickness of the P-type transition layer to the thickness of the P-type doped base layer is (0.01-5):1.

[0015] In some preferred embodiments of the present invention, the thickness of the P-type transition layer is 0.2-4 nm, and the thickness of the P-type doped substrate is 4-30 nm.

[0016] In some preferred embodiments of the present invention, the width ratio of the intermediate isolation area, the N-type area and the P-type area is 1:(3-10):(5-15).

[0017] In some preferred embodiments of the present invention, the intermediate isolation region is an undoped amorphous region and / or a doped amorphous region.

[0018] In some preferred embodiments of the present invention, the back contact battery further has at least one of the following structures:

[0019] Structure 1: The width of the intermediate isolation zone is 50-150µm, the width of the N-type zone is 200-600µm, and the width of the P-type zone is 400-1000µm;

[0020] Structure 2: No conductive film layer is placed outside the intermediate isolation zone, forming an isolation groove;

[0021] Structure 3: The outer surfaces of the N-type and P-type regions are entirely planar.

[0022] Structure 4: The thickness of the amorphous silicon layer is 8-60 nm;

[0023] Structure 5: The thickness of the crystalline silicon substrate is 180-250µm;

[0024] Structure 6: The back contact cell also includes a passivation layer and an anti-reflection layer disposed on the front side of the crystalline silicon substrate;

[0025] Structure 7: The thickness of the conductive film is 60-100 nm;

[0026] Structure 8: The back contact battery also includes metal electrodes respectively disposed outside the conductive film layers corresponding to the N-type region and the P-type region.

[0027] Secondly, the present invention provides a method for preparing a back contact battery that reduces the thickness difference between the N-type and P-type regions, comprising the following steps:

[0028] S1. Provide a crystalline silicon substrate;

[0029] S2. Deposit an intrinsic amorphous silicon layer on the back side of a crystalline silicon substrate;

[0030] S3. The target region of the intrinsic amorphous silicon layer is ion-doped using a masking method to form a patterned N-type region and a P-type region, and an intermediate isolation region is set between the N-type region and the P-type region; wherein, the N-type region includes an N-type doped base layer and an N-type transition layer arranged sequentially from the inside to the outside, and the P-type region includes a P-type doped base layer and a P-type transition layer arranged sequentially from the inside to the outside.

[0031] Furthermore, during the formation of the N-type and P-type regions, the corresponding doping elements of the corresponding transition layers are controlled to be greater than the corresponding doping elements of the corresponding doped substrates, so that the phosphorus-silicon content ratio in the N-type doped substrate is less than 1 by atomic percentage, the phosphorus-silicon content ratio in the N-type transition layer is greater than 1 by atomic percentage, the boron-silicon content ratio in the P-type doped substrate is less than 1 by atomic percentage, and the boron-silicon content ratio in the P-type transition layer is greater than 1 by atomic percentage.

[0032] S4. A mask is placed outside the intermediate isolation area, and then a conductive film layer is deposited on the back side; the masked area of ​​the mask forms an isolation groove;

[0033] S5. Metal electrodes are respectively placed on the outside of the conductive film layers corresponding to the N-type region and the P-type region.

[0034] In some preferred embodiments of the present invention, the preparation method further includes at least one of the following processes:

[0035] Process 1: The ion doping is plasma doping. The conditions for plasma doping include: introducing a target doping element gas source, hydrogen and inert gas to form plasma, so that the target doping element is doped into the target region of the intrinsic amorphous silicon layer.

[0036] Process 2: The formation of the target patterned N-type and P-type regions, and the setting of an intermediate isolation area between the N-type and P-type regions; the process includes: forming the N-type region first and then forming the P-type region or forming the P-type region first and then forming the N-type region, wherein when forming the target region, a corresponding mask is placed on the non-target region, and the intermediate isolation area is naturally formed thereafter.

[0037] Process 3, the preparation method also includes forming a passivation layer and an antireflection layer on the front side of the crystalline silicon substrate.

[0038] Thirdly, the present invention provides a back contact battery that reduces the thickness difference between the N-type region and the P-type region, which is prepared by the preparation method of the back contact battery that reduces the thickness difference between the N-type region and the P-type region described in the second aspect.

[0039] Fourthly, the present invention provides a battery assembly comprising a back contact battery for reducing the thickness difference between the N-type region and the P-type region as described in the first aspect, or a back contact battery for reducing the thickness difference between the N-type region and the P-type region as described in the third aspect.

[0040] Beneficial effects:

[0041] This invention, through the aforementioned technical solution, particularly by setting an amorphous silicon layer with specific N-type and P-type regions, with the back side of the amorphous silicon layer being nearly planar and the N-type and P-type regions having virtually no thickness difference, effectively reduces stress concentration at the interface between the N-type and P-type regions, thereby mitigating edge recombination problems. Combined with a specifically structured N-type doped substrate and its N-type transition layer, P-type doped substrate and its P-type transition layer, and their respective dopant element ratios, it significantly reduces longitudinal contact resistance. Even with the same thickness, it achieves a low series resistance, forming a flat and uniform contact interface, reducing interface recombination, and thus improving battery conversion efficiency while also enhancing battery stability and lifespan. Simultaneously, due to the reduced thickness difference between the N-type and P-type regions, the morphology of the back reflective layer is flatter, thereby increasing back reflectivity and further improving battery conversion efficiency. Moreover, it reduces stress mismatch, lowering the risk of film bursting in subsequent processes, and reducing risks and costs in the production process. The present invention sets up a specific structure for the N-type doped substrate and its N-type transition layer, the P-type doped substrate and its P-type transition layer, and the content ratio of each dopant element, which can significantly reduce the longitudinal contact resistance. One possible speculation is that by controlling the atomic percentage ratio of phosphorus and silicon in the N-type doped substrate to be less than 1, the atomic percentage ratio of phosphorus and silicon in the N-type transition layer to be greater than 1, the atomic percentage ratio of boron and silicon in the P-type doped substrate to be less than 1, and the atomic percentage ratio of boron and silicon in the P-type transition layer to be greater than 1, a suitable gradient doping structure is constructed, the interlayer work function matching is optimized to reduce the contact barrier, and a good carrier transport environment is controlled to form a good electrical contact and reduce the contact resistance.

[0042] In the preparation method of this invention, the entire process does not require an annealing activation step. Although the conductivity on amorphous silicon is poor, the corresponding transition layer formed can significantly reduce the longitudinal contact resistance by having a higher phosphorus-silicon ratio or boron-phosphorus ratio relative to the corresponding doped substrate. This allows the doped amorphous silicon semiconductor layer without annealing to still achieve high battery conversion efficiency, while also improving battery stability and lifespan. At the same time, it can reduce stress mismatch and stress concentration problems, reduce the risk of film bursting in subsequent processes, mitigate edge recombination problems, and reduce risks and costs in the production process. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of a crystalline silicon substrate in one embodiment of the present invention.

[0045] Figure 2 This is a schematic diagram of the structure for forming an intrinsic amorphous silicon layer in one embodiment of the present invention.

[0046] Figure 3 This is a schematic diagram of the structure for placing the first mask A in one embodiment of the present invention.

[0047] Figure 4 This is a schematic diagram of the structure for forming a P-type doped base layer and a P-type transition layer in one embodiment of the present invention.

[0048] Figure 5 This is a schematic diagram of the structure for placing the second mask B in one embodiment of the present invention.

[0049] Figure 6 This is a schematic diagram of the structure for forming an N-type doped base layer and an N-type transition layer in one embodiment of the present invention.

[0050] Figure 7 This is a schematic diagram of the structure in which the third mask C is placed in one embodiment of the present invention.

[0051] Figure 8 This is a schematic diagram of the structure for forming a conductive film layer in one embodiment of the present invention.

[0052] Figure 9 This is a schematic diagram of the structure for forming a metal electrode in one embodiment of the present invention.

[0053] Explanation of reference numerals in the attached figures

[0054] 1. Crystalline silicon substrate; 2. Intrinsic amorphous silicon layer; 3.1. P-type doped base layer; 3.2. P-type transition layer; 4.1. N-type doped base layer; 4.2. N-type transition layer; 5. Conductive film layer; 6. Metal electrode; 7. First mask A; 8. Second mask B; 9. Third mask C. Detailed Implementation

[0055] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0056] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0057] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0058] In this invention, the area closer to the crystalline silicon substrate is considered the inside, and the area farther from the crystalline silicon substrate is considered the outside. The back side of the crystalline silicon substrate is the backlight surface, and the front side is the light-receiving surface.

[0059] In a first aspect, the present invention provides a back contact battery for reducing the thickness difference between N-type and P-type regions, comprising a crystalline silicon substrate, an amorphous silicon layer and a conductive film layer sequentially disposed on the back side of the crystalline silicon substrate, wherein the surface of the amorphous silicon layer away from the crystalline silicon substrate has alternately formed N-type and P-type regions, and an intermediate isolation region disposed between the N-type and P-type regions, wherein at least a portion outside the intermediate isolation region is not provided with a conductive film layer to form an isolation trench, wherein the N-type region comprises an N-type doped base layer and an N-type transition layer sequentially disposed from the inside to the outside, and the P-type region comprises a P-type doped base layer and a P-type transition layer sequentially disposed from the inside to the outside; wherein the phosphorus-silicon content ratio in the N-type doped base layer is less than 1 by atomic percentage, the phosphorus-silicon content ratio in the N-type transition layer is greater than 1 by atomic percentage, the boron-silicon content ratio in the P-type doped base layer is less than 1 by atomic percentage, and the boron-silicon content ratio in the P-type transition layer is greater than 1 by atomic percentage.

[0060] In this invention, it is understood that N-type transition layer and P-type transition layer refer to transition layers formed when the content of doping elements of the corresponding doping type (N / P) is relatively large compared to the corresponding doped substrate (such as N-type doped substrate and P-type doped substrate).

[0061] In this invention, the phosphorus-silicon content ratio in the N-type doped substrate, expressed as an atomic percentage, is less than 1. Specifically, it can be, for example, 0.01, 0.02, 0.05, 0.07, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, 0.20, 0.22, 0.25, 0.27, 0.3, 0.32, 0.35, 0.37, 0.4, 0.42, 0.45, 0.47, 0.5, 0.52, 0.55, 0.57, 0.58, 0.59, 0.6, 0.7, 0.8, 0.9, or 0.95, or any range between two values. In some preferred embodiments of this invention, the phosphorus-silicon content ratio in the N-type doped substrate, expressed as an atomic percentage, is 0.01-0.6.

[0062] In this invention, the phosphorus-silicon content ratio in the N-type transition layer, expressed as an atomic percentage, is greater than 1. Specifically, it can be 1.1, 1.5, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 30, 40, 50, 60, 70, 80, or 90, or any range between two values. Preferably, the phosphorus-silicon content ratio in the N-type transition layer, expressed as an atomic percentage, is ≥8.

[0063] In this invention, the borosilicate content ratio in the P-type doped substrate, expressed as an atomic percentage, is less than 1. Specifically, it can be, for example, 0.01, 0.02, 0.05, 0.07, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, 0.20, 0.22, 0.25, 0.27, 0.3, 0.32, 0.35, 0.37, 0.4, 0.42, 0.45, 0.47, 0.5, 0.52, 0.55, 0.57, 0.58, 0.59, 0.6, 0.7, 0.8, 0.9, or 0.95, or any range between two values. In some preferred embodiments of this invention, the borosilicate content ratio in the P-type doped substrate, expressed as an atomic percentage, is 0.01-0.6.

[0064] In this invention, the borosilicate content ratio in the P-type transition layer, expressed as an atomic percentage, is greater than 1. Specifically, it can be, for example, 1.1, 1.5, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 30, 40, 50, 60, 70, 80, 90, 100, 120, 150, 180, 200, 300, 400, 500, or 600, or any range between two such values. Preferably, the borosilicate content ratio in the P-type transition layer, expressed as an atomic percentage, is greater than 10; more preferably, it is greater than 100.

[0065] In some preferred embodiments of the present invention, the borosilicate content ratios (in atomic percentage) in the P-type doped base layer and the P-type transition layer are denoted as P1 and P2, respectively, satisfying that P2:P1 is (5-1000):1, more preferably (5-500):1, more preferably (60-500):1, more preferably (100-500):1, or (60-300):1. The present invention employs P-type doped base layers and P-type transition layers with suitable borosilicate content ratios, which is more conducive to promoting hole extraction.

[0066] In this invention, the N-type doped base layer, the N-type transition layer, the P-type doped base layer, and the P-type transition layer all contain hydrogen.

[0067] In some preferred embodiments of the present invention, the phosphorus doping concentration in the N-type transition layer is 5e20cm. -3 -5e22cm -3 And / or, the hydrogen doping concentration is 1e20cm -3 -5e22cm -3 .

[0068] Preferably, the boron doping concentration in the P-type transition layer of this invention is 5e20cm. -3 -5e22cm -3 And / or, the hydrogen doping concentration is 1e20cm-3 -5e22cm -3 .

[0069] In some preferred embodiments of the present invention, the phosphorus doping concentration in the N-type doped substrate is 1e20cm⁻¹. -3 -8e21cm -3 1e20cm is preferred -3 -5e21cm -3 And / or, the hydrogen doping concentration is 1e20cm -3 -5e22cm -3 ;

[0070] Preferably, in the P-type doped substrate of the present invention, the boron doping concentration is 1e20cm. -3 -5e21cm -3 And / or, the hydrogen doping concentration is 1e20cm -3 -5e22cm -3 .

[0071] In some preferred embodiments of the present invention, the thickness ratio of the N-type transition layer to the thickness of the N-type doped base layer is (0.01-5):1, specifically, for example, (0.01, 0.05, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.17, 0.19, 0.2, 0.3, 0.4, 0.5, 0.7, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, or 5):1. The present invention employs an N-type doped base layer and an N-type transition layer with a suitable thickness ratio, which is more conducive to matching the doping concentration and obtaining a higher field passivation effect.

[0072] In some preferred embodiments of the present invention, the thickness of the N-type transition layer is 0.2-4 nm.

[0073] Preferably, the thickness of the N-type doped substrate is 3-20 nm.

[0074] In some preferred embodiments of the present invention, the thickness ratio of the P-type transition layer to the thickness of the P-type doped substrate is (0.01-5):1, specifically, for example, (0.01, 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.17, 0.19, 0.2, 0.3, 0.4, 0.5, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, or 5):1. The present invention employs a suitable thickness ratio for the P-type doped substrate and the P-type transition layer, which is more conducive to matching the doping concentration and improving the built-in electric field.

[0075] In some preferred embodiments of the present invention, the thickness of the P-type transition layer is 0.2-4 nm, specifically, it can be 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 3.7 nm, or 4 nm, as well as any range between two point values.

[0076] Preferably, the thickness of the P-type doped substrate is 4-30 nm, specifically, it can be 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 14 nm, 15 nm, 17 nm, 20 nm, 22 nm, 25 nm, 27 nm, 28 nm, 29 nm or 30 nm, or any range between any two values.

[0077] In some preferred embodiments of the present invention, the width ratio of the intermediate isolation region, the N-type region, and the P-type region is 1:(3-10):(5-15), specifically, for example, it can be 1:(3, 3.1, 3.2, 3.5, 3.6, 3.7, 3.8, 3.9, 4, 5, 6, 7, 8, 9, or 10):(5, 6, 6.1, 6.2, 6.3, 6.4, 6.5, 6.7, 6.9, 7, 8, 9, 10, 11, 12, 13, 14, or 15). The present invention employs an intermediate isolation region, N-type region, and P-type region with a suitable width ratio, which is more conducive to carrier extraction and reduces carrier recombination.

[0078] The intermediate isolation region of this invention only needs to effectively isolate the N-type region from the P-type region. In some preferred embodiments of this invention, the intermediate isolation region is an undoped amorphous region and / or a doped amorphous region.

[0079] In some preferred embodiments of the present invention, the width of the intermediate isolation zone is 50-150µm.

[0080] Preferably, the width of the N-type region in this invention is 200-600µm.

[0081] Preferably, the width of the P-type region in this invention is 400-1000µm.

[0082] In some preferred embodiments of the present invention, no conductive film layer is provided outside the intermediate isolation zone, forming an isolation groove, which is more conducive to improving the insulation effect between the N-type region and the P-type region. The conductive film layers are respectively provided on the outer surfaces of the N-type region and the P-type region.

[0083] In some preferred embodiments of the present invention, the outer surfaces of the N-type and P-type regions are entirely planar. In the planar structure, the N-type and P-type regions have virtually no thickness difference, which effectively reduces stress concentration at the interface between the N-type and P-type regions, thereby alleviating edge recombination problems. At the same time, due to the reduction in the thickness difference between the N-type and P-type regions, the morphology of the back reflective layer is smoother, thereby improving the back reflectivity and further enhancing the battery conversion efficiency. Moreover, it can reduce stress mismatch, lower the risk of film bursting in subsequent processes, and reduce the risks and costs in the production process.

[0084] In some preferred embodiments of the present invention, the thickness of the amorphous silicon layer is 8-60 nm, which is more conducive to improving the passivation effect.

[0085] In some preferred embodiments of the present invention, the thickness of the crystalline silicon substrate is 100-250 µm. The crystalline silicon substrate may, for example, be a single-crystal silicon substrate.

[0086] In some preferred embodiments of the present invention, the back contact battery further includes a passivation layer and an antireflection layer disposed on the front side of the crystalline silicon substrate. The passivation layer and the antireflection layer are constructed in accordance with the prior art and will not be described in detail here.

[0087] In some preferred embodiments of the present invention, the thickness of the conductive film layer is 60-100 nm.

[0088] In some preferred embodiments of the present invention, the back contact battery further includes metal electrodes respectively disposed outside the conductive film layers corresponding to the N-type region and the P-type region.

[0089] Secondly, the present invention provides a method for preparing a back contact battery that reduces the thickness difference between the N-type and P-type regions, comprising the following steps:

[0090] S1. Provide a crystalline silicon substrate;

[0091] S2. Deposit an intrinsic amorphous silicon layer on the back side of a crystalline silicon substrate;

[0092] S3. The target region of the intrinsic amorphous silicon layer is ion-doped using a masking method to form a patterned N-type region and a P-type region, and an intermediate isolation region is set between the N-type region and the P-type region; wherein, the N-type region includes an N-type doped base layer and an N-type transition layer arranged sequentially from the inside to the outside, and the P-type region includes a P-type doped base layer and a P-type transition layer arranged sequentially from the inside to the outside.

[0093] Furthermore, during the formation of the N-type and P-type regions, the corresponding doping elements of the corresponding transition layers are controlled to be greater than the corresponding doping elements of the corresponding doped substrates, so that the phosphorus-silicon content ratio in the N-type doped substrate is less than 1 by atomic percentage, the phosphorus-silicon content ratio in the N-type transition layer is greater than 1 by atomic percentage, the boron-silicon content ratio in the P-type doped substrate is less than 1 by atomic percentage, and the boron-silicon content ratio in the P-type transition layer is greater than 1 by atomic percentage.

[0094] S4. A mask is placed outside the intermediate isolation area, and then a conductive film layer is deposited on the back side; the masked area of ​​the mask forms an isolation groove;

[0095] S5. Metal electrodes are respectively placed on the outside of the conductive film layers corresponding to the N-type region and the P-type region.

[0096] The intrinsic amorphous silicon layer in S2 of this invention can be deposited using existing methods such as PECVD.

[0097] In the S3 method of this invention, a dry masking method is used, that is, a mask is set in the non-target area.

[0098] In some preferred embodiments of the present invention, the ion doping is plasma doping. It is understood that the N-type region dopant ion is phosphorus, and the P-type region dopant ion is boron.

[0099] More preferably, the plasma doping conditions include: introducing a target dopant element gas source, hydrogen, and an inert gas to form plasma, allowing the target dopant element to be doped into the target region of the intrinsic amorphous silicon layer. In this invention, the formation of the corresponding doped substrate or the corresponding transition layer is controlled by adjusting the flow rate or concentration of the target dopant element. It is understood that the flow rate or concentration of the target dopant element in the corresponding transition layer is greater than the flow rate or concentration of the corresponding target dopant element in the corresponding doped substrate.

[0100] The target doping element gas source can be, for example, a phosphorus source or a boron source. The inert gas can be, for example, at least one of argon, helium, etc. The plasma can be formed using existing methods such as radio frequency power supply, low frequency power supply, or DC power supply.

[0101] In this invention, the flow rates of the target doping element gas source, hydrogen, and inert gas can refer to the ranges of existing technologies, as long as a target film layer with the target doping concentration can be obtained; for example, the flow rate of the target doping element gas source is 100-2000 sccm, the flow rate of hydrogen is 1000-100000 sccm, and the flow rate of inert gas is 2000-100000 sccm.

[0102] In some preferred embodiments of the present invention, the process of forming a target patterned N-type region and a P-type region, and setting an intermediate isolation region between the N-type region and the P-type region includes: forming the N-type region first and then forming the P-type region or forming the P-type region first and then forming the N-type region, wherein when forming the target region, a corresponding mask is placed on the non-target region, and the intermediate isolation region is naturally formed thereafter.

[0103] In some preferred embodiments, the P-type region is formed first, followed by the N-type region. More preferably, the process of forming the target patterned N-type and P-type regions, with an intermediate isolation region between them, includes: placing a first mask A on the non-P-type region outside the intrinsic amorphous silicon layer; introducing a mixed gas containing a boron source (such as diborane or trimethylborane TMB) and hydrogen, and introducing at least one inert gas (such as argon, helium, etc.); forming a plasma, allowing boron ions to enter a portion of the intrinsic amorphous silicon layer to form a P-type doped base layer; increasing the boron source concentration in the later stages of the reaction to form a P-type transition layer; then removing the first mask A, placing a second mask B on the non-N-type region outside the intrinsic amorphous silicon layer, introducing a phosphorus source (such as phosphine) and hydrogen, and introducing at least one inert gas to form a plasma, allowing phosphorus ions to enter a portion of the intrinsic amorphous silicon layer to form an N-type doped base layer; increasing the phosphine concentration in the later stages of the reaction to form an N-type transition layer; and finally removing the second mask B. Conversely, an N-type region (i.e., N-type doped base layer and N-type transition layer) can be formed first, followed by a P-type region (i.e., P-type doped base layer and P-type transition layer). This can be achieved by simply placing the corresponding mask on the non-target region outside the intrinsic amorphous silicon layer. It is understood that the non-target region includes the area of ​​the intermediate isolation region and the region of non-target doped elements. The mask and the intrinsic amorphous silicon layer can be in contact or maintained at a certain distance (this distance is relatively narrow). When in contact, the intermediate isolation region is an undoped amorphous region; when spaced out, the intermediate isolation region is a doped amorphous region (which is phosphorus and boron doped).

[0104] The formation and type of the conductive film layer in S4 of this invention can refer to existing methods, such as physical vapor deposition (PVD) or activated plasma deposition (RPD). For example, the conductive film layer is a transparent conductive film layer. More preferably, the material of the conductive film layer can be an indium oxide-based thin film doped with at least one of tin, tungsten, titanium, zinc, and gallium, or a zinc oxide-based thin film doped with at least one of aluminum, gallium, and boron.

[0105] In some preferred embodiments of the present invention, the fabrication method further includes forming a passivation layer and an antireflection layer on the front side of a crystalline silicon substrate. The steps of forming the passivation layer and the antireflection layer can be performed in S1, or after the formation of the N-type region and the P-type region in S3.

[0106] In this invention, the metal electrode can be, for example, an existing electrode such as a silver paste electrode.

[0107] Thirdly, the present invention provides a back contact battery that reduces the thickness difference between the N-type and P-type regions, which is prepared by the method for preparing a back contact battery that reduces the thickness difference between the N-type and P-type regions described in the second aspect. The back contact battery of this third aspect has the same structure and performance as the back contact battery of the first aspect, and will not be described again here.

[0108] Fourthly, the present invention provides a battery assembly comprising a back contact battery for reducing the thickness difference between the N-type region and the P-type region as described in the first aspect, or a back contact battery for reducing the thickness difference between the N-type region and the P-type region as described in the third aspect.

[0109] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0110] Example 1

[0111] A back-contact battery is prepared by the following method:

[0112] S1, such as Figure 1 As shown, a crystalline silicon substrate 1 (using a single-crystal silicon substrate) is provided, and the thickness of the crystalline silicon substrate 1 is 150µm;

[0113] S2, such as Figure 2 As shown, an intrinsic amorphous silicon layer 2 is deposited on the back side of a crystalline silicon substrate 1 using a PECVD method. The thickness of the intrinsic amorphous silicon layer 2 is 13 nm.

[0114] S3. Place the first mask A on the non-P-type region (i.e., the preset N-type region and the preset intermediate isolation region) outside the intrinsic amorphous silicon layer 2, such as... Figure 3 A mixed gas of 200 sccm of diborane and 15000 sccm of hydrogen is introduced, along with 6000 sccm of argon. A plasma is generated using a radio frequency power supply, allowing boron ions to enter a portion of the intrinsic amorphous silicon layer 2 to form a P-type doped substrate 3.1. In the later stages of the reaction, the diborane flow rate is increased to 400 sccm to form a P-type transition layer 3.2. The P-type transition layer 3.2 is located outside the P-type doped substrate 3.1, and the two together form a P-type region. Afterwards, the first mask A is removed, as shown... Figure 4 In the P-type doped base layer 3.1, the boron-silicon content ratio (P1:P1) is 0.1 (atomic percentage), and in the P-type transition layer 3.2, the boron-silicon content ratio (P2:P1) is 12 (atomic percentage). The ratio of P2 to P1 is 120:1. The boron doping concentration in the P-type transition layer 3.2 is 3e22cm³. -3 The hydrogen doping concentration is 5.2e21cm. -3 The boron doping concentration in the P-type doped substrate 3.1 is 5e21cm. -3The hydrogen doping concentration is 5.2e21cm. -3 The thickness of the P-type transition layer 3.2 is 0.5 nm, the thickness of the P-type doped base layer 3.1 is 6 nm, and the ratio of the thickness of the P-type transition layer 3.2 to the thickness of the P-type doped base layer 3.1 is 0.08:1.

[0115] Then, a second mask B is placed on the non-N-type region (i.e., the preset P-type region and the preset intermediate isolation region) outside the intrinsic amorphous silicon layer 2, as shown below. Figure 5 A mixed gas of phosphine (400 sccm), hydrogen (16000 sccm), and argon (6000 sccm) was introduced. A plasma was generated using a radio frequency power supply, allowing phosphorus ions to enter a portion of the intrinsic amorphous silicon layer 2 to form an N-type doped substrate 4.1. In the later stages of the reaction, the phosphine flow rate was increased to 700 sccm to form an N-type transition layer 4.2. The N-type transition layer 4.2 is located outside the N-type doped substrate 4.1, and the two together form an N-type region. Then, the second mask B was removed. Figure 6 An intermediate isolation region naturally forms between the N-type and P-type regions, with a width of 100 µm. The width ratio of the intermediate isolation region to the width of the N-type region is 1:3:5. Specifically, the phosphorus-silicon content ratio (N1 to N2) in the N-type doped base layer 4.1 is 0.16 (atomic percentage), and the phosphorus-silicon content ratio (N2 to N2) in the N-type transition layer 4.2 is 8 (atomic percentage). The phosphorus doping concentration in the N-type transition layer 4.2 is 2e22cm³. -3 The hydrogen doping concentration is 3e21cm -3 The phosphorus doping concentration in the N-type doped substrate 4.1 is 8e21cm. -3 The hydrogen doping concentration is 3e21cm -3 The thickness of the N-type transition layer 4.2 is 0.7 nm, the thickness of the N-type doped base layer 4.1 is 5 nm, and the ratio of the thickness of the N-type transition layer 4.2 to the thickness of the N-type doped base layer 4.1 is 0.14:1.

[0116] Subsequently, a passivation layer and an antireflection layer are sequentially formed on the front side of the crystalline silicon substrate 1;

[0117] S4, such as Figure 7 As shown, a third mask C is attached outside the intermediate isolation zone; then as follows... Figure 8 As shown, a conductive film layer 5 (ITO) with a thickness of 80 nm is deposited on the back side; an isolation trench is formed in the mask area of ​​the third mask C; the conductive film layer 5 is located outside the N-type and P-type regions.

[0118] S5, such as Figure 9 As shown, metal electrodes 6 are respectively disposed outside the conductive film layers 5 corresponding to the N-type region and the P-type region.

[0119] Example 2

[0120] The procedure was carried out in accordance with Example 1, except that the phosphorus-silicon content ratio (atomic percentage) in the N-type transition layer 4.2 was adjusted to 10, corresponding to a phosphorus doping concentration of 2.5e22cm in the N-type transition layer 4.2. -3 The hydrogen doping concentration is 3.5e21cm. -3 The corresponding preparation process parameters that need to be adjusted to meet this condition are: increasing the phosphine flow rate to 800 sccm in the later stage of the reaction to form an N-type transition layer 4.2.

[0121] Example 3

[0122] The experiment was conducted in accordance with Example 1, except that the boron-silicon content ratio (atomic percentage) in the P-type transition layer 3.2 was adjusted to 15, corresponding to a boron doping concentration of 3.7e22cm in the P-type transition layer 3.2. -3 The hydrogen doping concentration is 5.5e21cm. -3 The corresponding preparation process parameters that need to be adjusted to meet this condition are: increasing the diborane flow rate to 500 sccm in the later stage of the reaction to form a P-type transition layer 3.2. Under this condition, the calculated P2:P1 ratio is 150:1.

[0123] Example 4

[0124] The process was carried out in accordance with Example 1, except that the thickness of the N-type transition layer 4.2 was adjusted to 0.5 nm, so that the ratio of the thickness of the N-type transition layer 4.2 to the thickness of the N-type doped base layer 4.1 was 0.1:1. The corresponding preparation process parameter that needs to be adjusted to meet this condition is: the deposition time is shortened by 20%.

[0125] Example 5

[0126] The process was carried out in accordance with Example 1, except that the thickness of the P-type transition layer 3.2 was adjusted to 0.7 nm, so that the ratio of the thickness of the P-type transition layer 3.2 to the thickness of the P-type doped base layer 3.1 was 0.12:1. The corresponding fabrication process parameter that needs to be adjusted to meet this condition is: the deposition time is extended by 10%.

[0127] Example 6

[0128] The same procedure was followed as in Example 1, except that the width of the intermediate isolation zone was adjusted to 80µm, so that the ratio of the width of the intermediate isolation zone, the N-type zone and the P-type zone was 1:3.75:6.25.

[0129] Comparative Example 1

[0130] A conventional back-contact battery is prepared by the following method:

[0131] S101, Provides a crystalline silicon substrate;

[0132] S102. A first semiconductor layer and a mask layer are sequentially formed on the back side of a crystalline silicon substrate. The first semiconductor layer is an intrinsic amorphous silicon layer (thickness is the same as the intrinsic amorphous silicon layer in Example 1) and an N-type doped amorphous silicon layer (thickness and doping concentration are the same as the N-type doped base layer in Example 1).

[0133] S103. The back side obtained in S102 is etched with a first opening to form a second semiconductor opening region;

[0134] S104. Texturing and cleaning: Remove the mask layer and the first semiconductor layer remaining in the second semiconductor opening area, and form a textured surface on the front side of the crystalline silicon substrate and the second semiconductor opening area. Then, completely remove the mask layer.

[0135] S105. A passivation layer and an anti-reflection layer are formed on the front side of the crystalline silicon substrate after texturing and cleaning in S104. Then, the wrapping plating on the back side of the crystalline silicon substrate is removed by cleaning.

[0136] S106. Deposit a second semiconductor layer on the back side obtained in S105; the second semiconductor layer is an intrinsic amorphous silicon layer (thickness is the same as the intrinsic amorphous silicon layer in Example 1) and a P-type doped amorphous silicon layer (doping concentration is the same as the P-type doped base layer in Example 1, and the thickness is 13nm).

[0137] S107. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0138] S108. Deposit a transparent conductive film layer on the back side obtained in S107;

[0139] S109. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0140] S110, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0141] Comparative Example 2

[0142] The same procedure is followed as in Example 1, except that the N-type transition layer 4.2 is not provided, and the P-type transition layer 3.2 is not provided.

[0143] Comparative Example 3

[0144] The reaction was carried out in accordance with Example 1, except that the phosphine flow rate was adjusted in the later stage of the reaction so that the phosphorus-silicon content ratio in the N-type transition layer 4.2, expressed as an atomic percentage, was less than 1 and was 0.5, which was greater than the phosphorus-silicon content ratio in the N-type doped base layer 4.1, expressed as an atomic percentage.

[0145] Comparative Example 4

[0146] The reaction was carried out in accordance with Example 1, except that the borane flow rate was adjusted in the later stage of the reaction so that the borosilicate content ratio in the P-type transition layer 3.2, expressed as an atomic percentage, was less than 1 and was 0.5, which was greater than the borosilicate content ratio in the P-type doped base layer 3.1, expressed as an atomic percentage.

[0147] Test case

[0148] The back contact batteries obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The method for testing the risk of film bursting is as follows: After scratching the surface of the test sample with a blade, special adhesive tape was applied and quickly peeled off. The morphology of the cut line edge was observed under an optical microscope. The appearance of serrated cracks or slight curling or peeling of the cut line indicates poor surface adhesion and a high risk of film bursting. The appearance of neat cut line edges without curling or peeling indicates high surface adhesion and a low risk of film bursting.

[0149] Table 1

[0150]

[0151] The results above show that, compared to the comparative examples, the embodiments of the present invention can significantly reduce the longitudinal contact resistance while reducing the thickness difference between the N-type and P-type regions, achieving high battery conversion efficiency, low risk of membrane bursting, and improving battery stability and lifespan. Simultaneously, it can reduce stress mismatch and stress concentration problems, lowering the risk of membrane bursting in subsequent processes and mitigating edge recombination issues. In contrast, the conventional technology in Comparative Example 1 has high series resistance, high risk of membrane bursting, and low battery conversion efficiency, failing to meet the high series resistance requirements of Comparative Examples 2-4 of the present invention.

[0152] Furthermore, as can be seen from Examples 1 and 2-6, the preferred scheme of the present invention is more conducive to reducing series resistance and leakage current, and improving battery conversion efficiency.

[0153] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A back contact cell with reduced N-type region to P-type region thickness difference, characterized in that, The back contact cell comprises a crystalline silicon substrate, an amorphous silicon layer and a conductive film layer arranged in sequence on the back surface of the crystalline silicon substrate, wherein the side surface of the amorphous silicon layer away from the crystalline silicon substrate has N-type regions and P-type regions formed alternately, and an intermediate isolation region arranged between the N-type regions and the P-type regions, the intermediate isolation region is at least partially free of the conductive film layer to form an isolation groove, the N-type region comprises an N-type doped base layer and an N-type transition layer arranged in sequence from inside to outside, and the P-type region comprises a P-type doped base layer and a P-type transition layer arranged in sequence from inside to outside; wherein the phosphorus-silicon content ratio in the N-type doped base layer is less than 1 in atomic percentage, the phosphorus-silicon content ratio in the N-type transition layer is greater than 1 in atomic percentage, the boron-silicon content ratio in the P-type doped base layer is less than 1 in atomic percentage, and the boron-silicon content ratio in the P-type transition layer is greater than 1 in atomic percentage.

2. The back contact cell of claim 1, wherein the N-type region and the P-type region have a thickness difference of less than 1.5 microns. The phosphorus-silicon content ratio in the N-type doped base layer is 0.01-0.6 in atomic percentage, and the phosphorus-silicon content ratio in the N-type transition layer is greater than or equal to 8 in atomic percentage. And / or, The boron-silicon content ratio in the P-type doped base layer is 0.01-0.6 in atomic percentage, and the boron-silicon content ratio in the P-type transition layer is greater than 10 in atomic percentage.

3. The back contact cell of claim 1, wherein the N-type region and the P-type region have a thickness difference of less than 1.5 microns. The boron-silicon content ratios in the P-type doped base layer and the P-type transition layer are respectively denoted as P1 and P2 in atomic percentage, and P2:P1 is (5-1000):

1.

4. The back contact cell of reduced N-type region to P-type region thickness difference of claim 1 or 2, wherein, N-type transition layer has a phosphorus doping concentration of 5e20 cm -3 -5e22cm -3 , and a hydrogen doping concentration of 1e20 cm -3 -5e22cm -3 ; and / or, P-type transition layer has a boron doping concentration of 5e20 cm -3 -5e22cm -3 , and a hydrogen doping concentration of 1e20 cm -3 -5e22cm -3 .

5. The back contact cell of reduced N-type region to P-type region thickness difference of claim 1 or 2, wherein, N-type doped base layer with phosphorus doping concentration of 1e20 cm -3 -8e21 cm -3 , hydrogen doping concentration of 1e20 cm -3 -5e22 cm -3 ; and / or, P-type doped base layer with boron doping concentration of 1e20 cm -3 -5e21 cm -3 , hydrogen doping concentration of 1e20 cm -3 -5e22 cm -3 .

6. The back contact cell of reduced N-type region to P-type region thickness difference of claim 1 or 2, wherein, The ratio of the thickness of the N-type transition layer to the thickness of the N-type doped base layer is (0.01-5):1; and / or, The thickness of the N-type transition layer is 0.2-4 nm, and the thickness of the N-type doped base layer is 3-20 nm.

7. The back contact cell of reduced N-type region to P-type region thickness difference of claim 1 or 2, wherein, The ratio of the thickness of the P-type transition layer to the thickness of the P-type doped base layer is (0.01-5):1; and / or, The thickness of the P-type transition layer is 0.2-4 nm, and the thickness of the P-type doped base layer is 4-30 nm.

8. The back contact cell of claim 1, wherein the N-type region and the P-type region have a thickness difference of less than 1.0 microns. The ratio of the width of the intermediate isolation region to the width of the N-type region to the width of the P-type region is 1:(3-10):(5-15); and / or, The intermediate isolation region is an undoped amorphous region and / or a doped amorphous region.

9. The back contact cell of claim 1, wherein the N-type region and the P-type region have a thickness difference of less than 1.0 microns. The back contact cell further has at least one of the following structures: Structure one, the width of the intermediate isolation region is 50-150 µm, the width of the N-type region is 200-600 µm, and the width of the P-type region is 400-1000 µm; Structure two, the intermediate isolation region is free of the conductive film layer to form an isolation groove; Structure three, the outer surface of the N-type region and the P-type region is a plane as a whole; Structure four, the thickness of the amorphous silicon layer is 8-60 nm; Structure five, the thickness of the crystalline silicon substrate is 180-250 µm; Structure six, the back contact cell further comprises a passivation layer and an anti-reflection layer arranged on the front surface of the crystalline silicon substrate; Structure seven, the thickness of the conductive film layer is 60-100 nm; Structure eight, the back contact cell further comprises metal electrodes arranged outside the conductive film layer corresponding to the N-type region and the P-type region, respectively.

10. A method of fabricating a back contact cell with reduced thickness difference between N-type and P-type regions, comprising: The method comprises the following steps: ​ S1, providing a crystalline silicon substrate; S2, depositing an intrinsic amorphous silicon layer on the back surface of the crystalline silicon substrate; S3, using a mask method to ion dope the target region of the intrinsic amorphous silicon layer, forming a target patterned N-type region and P-type region, and setting an intermediate isolation region between the N-type region and the P-type region; wherein the N-type region comprises an N-type doped base layer and an N-type transition layer arranged from inside to outside, and the P-type region comprises a P-type doped base layer and a P-type transition layer arranged from inside to outside; And in the respective formation process of the N-type region and the P-type region, the corresponding doping elements of the corresponding transition layer are controlled to be greater than the corresponding doping elements of the corresponding doped base layer, so that the phosphorus silicon content ratio in the N-type doped base layer is less than 1, the phosphorus silicon content ratio in the N-type transition layer is greater than 1, the boron silicon content ratio in the P-type doped base layer is less than 1, and the boron silicon content ratio in the P-type transition layer is greater than 1; S4, setting a mask plate outside the intermediate isolation region, and then depositing a conductive film layer on the back surface; the mask area of the mask plate forms an isolation groove; S5, setting a metal electrode outside the conductive film layer corresponding to the N-type region and the P-type region, respectively.

11. The method of claim 10, wherein the thickness difference between the N-type region and the P-type region is reduced by forming the back contact cell by: The preparation method further comprises at least one of the following processes: Process one, the ion doping is plasma doping, and the conditions of the plasma doping include: introducing a target doping element gas source, hydrogen and an inert gas to form a plasma, so that the target doping element is doped into the target region of the intrinsic amorphous silicon layer; Process two, the formation of the target patterned N-type region and P-type region, and the setting of the intermediate isolation region between the N-type region and the P-type region; the process includes: first forming the N-type region and then forming the P-type region, or first forming the P-type region and then forming the N-type region, wherein a corresponding mask plate is placed on the non-target region when the target region is formed, and the intermediate isolation region is naturally formed; Process three, the preparation method further comprises forming a passivation layer and an anti-reflection layer on the front surface of the crystalline silicon substrate.

12. A back contact cell having a reduced difference in thickness between the N-type region and the P-type region, characterized by It is prepared by the preparation method of the back contact cell with reduced thickness difference between the N-type region and the P-type region as claimed in claim 10 or 11.

13. A battery assembly characterized by, It comprises the back contact cell with reduced thickness difference between the N-type region and the P-type region as claimed in any one of claims 1-9, or the back contact cell with reduced thickness difference between the N-type region and the P-type region as claimed in claim 12.

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