Digital-to-analog conversion chip test system and electronic equipment
The integrated digital-to-analog converter chip testing system solves the problems of low chip testing efficiency and high risk of damage, and achieves efficient and accurate verification of chip characteristics and functions.
Patent Information
- Application Number
- CN202410895724.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-04
- Publication Date
- 2026-01-06
AI Technical Summary
In existing technologies, chip testing is inefficient and chips are easily damaged during transfer between testing platforms, resulting in high testing costs and low efficiency.
A digital-to-analog converter chip testing system is adopted, including a host computer, a chip evaluation master board and multiple chip evaluation daughter boards. The measurement device is connected through a field-programmable gate array mezzanine card to realize integrated testing and analysis and reduce the chip transfer process.
It improves the efficiency and accuracy of chip testing, reduces the risk of chip damage, and enables efficient verification of chip characteristics and functions.
Smart Images
Figure CN121276288A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a digital-to-analog converter chip testing system and electronic device. Background Technology
[0002] With the development of automation in the electronics industry, the demand for chips in various industries is increasing. With the mass production of chips, before the chips are officially sold and applied, detailed testing of their characteristics and functions is required. For chip verification, the first batch of chips produced are blind-packaged chips, which have not undergone some chip attribute configurations and calibrations. Each chip used for verification needs to be manually operated. The number of chips ranges from hundreds to thousands, and each chip has many configurations. After configuration, the chip still needs to be verified and confirmed.
[0003] If a separate test platform is built for each chip testing item, then many test platforms need to be built, and the chip to be tested needs to be transferred between test platforms. The process of disassembling and installing the chip to be tested may damage the chip to be tested, resulting in low chip testing efficiency. Summary of the Invention
[0004] This application aims to at least partially address one of the technical problems in the related art.
[0005] Therefore, the first objective of this application is to propose a digital-to-analog converter chip testing system.
[0006] The second objective of this application is to propose an electronic device.
[0007] The third objective of this application is to provide a computer-readable storage medium.
[0008] To achieve the above objectives, a first aspect of this application provides a digital-to-analog converter chip testing system, comprising:
[0009] Host computer, chip evaluation master board, multiple chip evaluation daughter boards, measurement device;
[0010] The host computer is used to determine test instructions according to the test items, send the test instructions to the chip evaluation master, and receive test feedback data sent by the chip evaluation master;
[0011] The chip evaluation master board includes multiple interfaces for connecting to the measuring device and the chip evaluation daughter board, for performing test operations on the chip evaluation daughter board according to the test instructions, and for obtaining test feedback data from the measuring device;
[0012] The chip evaluation subboard is equipped with a chip to be tested, which is connected to the chip evaluation master board via a digital module.
[0013] Optionally, the chip evaluation master board and the chip evaluation daughter board are connected via a Field Programmable Gate Array (FMC) connector. The measurement devices connected to the chip evaluation master board include: a temperature sensor, a bit error rate tester, a power supply, a signal source, a spectrum analyzer, and a high-speed oscilloscope.
[0014] Optionally, in the scenario of temperature sensor accuracy testing, the chip evaluation master is set in a high and low temperature chamber;
[0015] The chip evaluation motherboard is connected to the temperature controller of the high and low temperature chamber, and is used to control the temperature of the high and low temperature chamber according to the test command, and to obtain the test feedback data generated by the temperature sensor in the chip under test;
[0016] The host computer is used to compare the test feedback data with the target temperature in the test command to generate an offset temperature drift curve.
[0017] Optionally, in a serialization-to-deserialization test scenario, the high-speed oscilloscope is connected to the serialization-to-deserialization transmission line at the input end and the serialization-to-deserialization transmission line at the output end of the chip under test, and the bit error rate tester is connected to the input end and the output end of the chip under test.
[0018] The chip evaluation motherboard is used to input a preset test signal into the input terminal of the chip under test according to the test command;
[0019] The host computer is used to generate an eye diagram based on the input and output waveforms acquired by the high-speed oscilloscope, and to read the corresponding performance indicators based on the eye diagram.
[0020] Optionally, in the analog-to-digital converter (ADC) performance testing scenario, the chip under test set on the chip evaluation sub-board is an ADC chip, the chip under test is connected to the output terminal of the power divider, and the input terminal of the power divider is connected to the output terminal of the signal source;
[0021] The signal source is used to output a test signal; the power divider is used to divide the test signal into multiple sub-test signals and output them to the chip under test.
[0022] The chip under test is used to process the sub-test signal and output a feedback signal to the chip evaluation motherboard through the digital module;
[0023] The chip evaluation motherboard is used to obtain a first output code value based on the feedback signal;
[0024] The host computer is used to perform Fourier analysis based on the first output code value to obtain ADC chip performance data.
[0025] Optionally, in the analog-to-digital AD passband test scenario, the signal source is used to increase the frequency of the test signal in fixed steps while keeping the output power constant;
[0026] The chip evaluation motherboard is used to obtain a second output code value based on the feedback signal;
[0027] The host computer is used to perform Fourier analysis based on the second output code value to obtain the frequency response curve, and to analyze the AD passband flatness and bandwidth range based on the frequency response curve.
[0028] Optionally, in the DAC performance testing scenario, the chip under test set on the chip evaluation sub-board is a DAC chip, the output terminal of the chip under test is connected to the transimpedance amplifier (TIA), and the output terminal of the TIA is connected to the spectrum analyzer.
[0029] The host computer is used to output test data, the spectrum analyzer is used to generate a spectrum based on the signal amplified by the TIA, and the spectrum is used to analyze and obtain DAC performance parameters.
[0030] Optionally, in the digital-to-analog converter (DAC) passband test scenario, the chip evaluation motherboard is used to increase the frequency of the output signal in fixed steps according to the instructions from the host computer, while the amplitude of the output signal remains unchanged.
[0031] The spectrum analyzer is used to generate the DAC output frequency response curve, which is used to determine the DAC passband flatness and bandwidth range.
[0032] To achieve the above objectives, a second aspect of this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;
[0033] The memory stores computer-executed instructions;
[0034] The processor executes computer execution instructions stored in the memory to implement the system as described in any one of the first aspects.
[0035] To achieve the above objectives, a third aspect of this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the system as described in any one of the first aspects.
[0036] The digital-to-analog converter chip testing system, apparatus, electronic equipment, and storage medium provided in this application integrate testing, analysis, and recording functions into the digital-to-analog converter chip testing system, thereby achieving efficient testing of the chip system and improving the efficiency of the chip testing process.
[0037] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0038] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:
[0039] Figure 1 This is a schematic diagram of the structure of a digital-to-analog converter chip testing system provided in an embodiment of this application;
[0040] Figure 2 This is a schematic diagram of the structure of a digital-to-analog converter chip testing system provided in an embodiment of this application;
[0041] Figure 3 This is a schematic diagram of the structure of a digital-to-analog converter chip testing system provided in an embodiment of this application;
[0042] Figure 4 This is a schematic diagram of the structure of a digital-to-analog converter chip testing system provided in an embodiment of this application. Detailed Implementation
[0043] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.
[0044] With the development of automation in the electronics industry, the demand for chips in various industries is increasing. With the mass production of chips, before the chips are officially sold and applied, detailed testing of their characteristics and functions is required. For chip verification, the first batch of chips produced are blind-packaged chips, which have not undergone some chip attribute configurations and calibrations. Each chip used for verification needs to be manually operated. The number of chips ranges from hundreds to thousands, and each chip has many configurations. After configuration, the chip still needs to be verified and confirmed.
[0045] If a separate test platform is built for each chip testing item, then many test platforms need to be built, and the chip to be tested needs to be transferred between test platforms. The process of disassembling and installing the chip to be tested may damage the chip to be tested, resulting in low chip testing efficiency.
[0046] To address this issue, embodiments of this application provide a digital-to-analog converter chip testing system. Figure 1 This is a schematic diagram of the structure of a digital-to-analog converter chip testing system provided in an embodiment of this application. Figure 1 As shown, the system includes: a host computer 10, a chip evaluation master board 20, multiple chip evaluation daughter boards 30, and a measuring device 40;
[0047] The host computer 10 is used to determine test instructions according to the test items, send the test instructions to the chip evaluation master 20, and receive test feedback data sent by the chip evaluation master 20.
[0048] The chip evaluation master board 20 includes multiple interfaces for connecting to the measurement device 40 and the chip evaluation daughter board 30, for performing test operations on the chip evaluation daughter board 30 according to the test instructions, and for obtaining test feedback data from the measurement device 40.
[0049] The chip evaluation sub-board 30 is equipped with a chip to be tested, which is connected to the chip evaluation master board 20 through a digital module.
[0050] In this embodiment, the chip evaluation master 2020 is a Field Programmable Gate Array (FPGA), an integrated circuit that can be configured and reconfigured by the user according to specific needs after manufacturing. FPGAs offer extremely high flexibility and programmability, allowing circuit functions to be changed without redesigning and manufacturing the hardware. Internally, an FPGA consists of a large number of basic logic units (such as lookup tables (LUTs) and flip-flops), programmable interconnect resources (switch networks for connecting logic units), input / output blocks (I / O blocks), and other programmable components (such as digital signal processors, memory blocks, high-speed transmission interfaces, etc.). The user writes code in a hardware description language (HDL, such as VHDL or Verilog) to describe the required logic functions, then uses compilation and adaptation tools to generate a configuration bitstream file, downloads this bitstream file to the FPGA, and completes the configuration of the FPGA, making it a user-defined application-specific integrated circuit.
[0051] Optionally, the chip evaluation master board 20 and the chip evaluation daughter board 30 are connected via a field-programmable gate array (FMC) connector. The measurement device 40 connected to the chip evaluation master board 20 includes: a temperature sensor, a bit error rate tester, a power supply, a signal source, a spectrum analyzer, and a high-speed oscilloscope.
[0052] Optionally, in the scenario of temperature sensor accuracy testing, the chip evaluation master 20 is placed in a high and low temperature chamber;
[0053] The chip evaluation motherboard is connected to the temperature controller of the high and low temperature chamber, and is used to control the temperature of the high and low temperature chamber according to the test command, and to obtain the test feedback data generated by the temperature sensor in the chip under test;
[0054] The host computer 10 is used to compare the test feedback data with the target temperature in the test command to generate an offset temperature drift curve.
[0055] In this embodiment, for the chip, the control of the operating temperature is related to the chip's operating stability. An important prerequisite for temperature control is accurate temperature testing. The chip evaluation motherboard is connected to the temperature controller of the high and low temperature chamber, which controls the high and low temperature chamber to create a certain temperature environment and obtains the test feedback data obtained by the temperature sensor in the chip under test. The test feedback data includes the temperature measured by the temperature sensor and the offset voltage or current corresponding to the temperature.
[0056] Offset temperature drift profiles are typically obtained during the characteristic testing of semiconductor devices or electronic components (such as operational amplifiers, sensors, etc.). They show the trend of offset voltage or offset current as a function of temperature.
[0057] Data Analysis and Plotting: Use charting software to plot a scatter plot with temperature on the x-axis and the offset voltage or current deviation on the y-axis. It may also be necessary to fit these data points to obtain a smooth curve reflecting the relationship between offset and temperature. Analyzing the slope of the curve yields the offset drift rate (e.g., μV / ℃), a crucial parameter for evaluating the stability of the chip under test at different temperatures.
[0058] This embodiment provides another testing system for digital-to-analog converter chips. Figure 2 This is a schematic diagram of the structure of a digital-to-analog converter chip testing system provided in an embodiment of this application. Figure 2 As shown, in the serialization-to-deserialization test scenario, the high-speed oscilloscope is connected to the serialization-to-deserialization transmission line at the input end and the serialization-to-deserialization transmission line at the output end of the chip under test, and the bit error rate tester is connected to the input end and the output end of the chip under test.
[0059] The chip evaluation motherboard is used to input a preset test signal into the input terminal of the chip under test according to the test command;
[0060] The host computer 10 is used to generate an eye diagram based on the input and output waveforms acquired by the high-speed oscilloscope, and to read the corresponding performance indicators based on the eye diagram.
[0061] In this embodiment, the eye diagram is formed by superimposing the waveforms of each symbol obtained from scanning due to the persistence of the oscilloscope. The eye diagram contains a wealth of information, from which the effects of inter-symbol interference and noise can be observed, reflecting the overall characteristics of the digital signal. Thus, the quality of the system can be estimated, making eye diagram analysis the core of signal integrity analysis in high-speed interconnect systems.
[0062] Reading the corresponding performance metrics based on the eye diagram includes at least one of the following steps:
[0063] Based on the eye diagram, the parameters of the digital waveform's level transformation, such as average rise time, fall time, overshoot, undershoot, and threshold / crossing percentage, are analyzed.
[0064] Rise time: The rise time of a pulse signal refers to the interval between the initial arrival of the pulse's instantaneous value at a specified lower limit and a specified upper limit. Unless otherwise specified, the lower limit and upper limit are defined as 10% and 90% of the pulse value amplitude, respectively.
[0065] Fall time: The fall time of a pulse signal refers to the time interval from 90% of the pulse peak amplitude to 10%.
[0066] Overshoot: also called overshoot, is when the first peak or valley value exceeds the set voltage. It is mainly manifested as a sharp pulse and can lead to the failure of circuit components.
[0067] Undershoot: refers to the next valley or peak value. Excessive overshoot can cause protection diodes to activate, leading to premature failure. Excessive undershoot can also cause false clock or data errors.
[0068] Threshold level: refers to the lowest received level that a receiver can achieve when the system transmission characteristics are inferior to a certain bit error rate.
[0069] The thickness and clarity of signal lines in an eye diagram are analyzed to determine signal quality. Due to the superposition of multiple signals, the signal lines in the eye diagram become thicker and appear blurred. Therefore, the eye diagram also reflects signal noise and jitter: on the vertical voltage axis, it is reflected as voltage noise; on the horizontal time axis, it is reflected as time-domain jitter.
[0070] When noise is present, it will be superimposed on the signal, making the observed eye diagram lines blurry. If intersymbol interference is also present, the "eye" will open even smaller. Generally, the larger the eye of the eye diagram and the higher the eye height, the better the signal quality.
[0071] This embodiment provides another testing system for digital-to-analog converter chips. Figure 3 This is a schematic diagram of the structure of a digital-to-analog converter chip testing system provided in an embodiment of this application. Figure 3 As shown, in the analog-to-digital converter (ADC) performance test scenario, the chip under test set on the chip evaluation sub-board 30 is an ADC chip. The chip under test is connected to the output terminal of the power divider, and the input terminal of the power divider is connected to the output terminal of the signal source.
[0072] The signal source is used to output a test signal; the power divider is used to divide the test signal into multiple sub-test signals and output them to the chip under test.
[0073] The chip under test is used to process the sub-test signal and output a feedback signal to the chip evaluation motherboard through the digital module;
[0074] The chip evaluation motherboard is used to obtain a first output code value based on the feedback signal;
[0075] The host computer 10 is used to perform Fourier analysis based on the first output code value to obtain ADC chip performance data.
[0076] In this embodiment, multiple chip evaluation sub-boards 30 are tested simultaneously. Each of these chip evaluation sub-boards 30 is equipped with an ADC chip, and optionally, 16 ADC chips are tested simultaneously. A power divider is a device that splits the energy of one input signal into two or more outputs of equal or unequal energy. Conversely, it can also combine multiple signal outputs into one output, in which case it can be called a combiner. A certain degree of isolation must be ensured between the output ports of a power divider. Power dividers are typically classified by output type, such as 1-to-2 (one input, two outputs) or 1-to-3 (one input, three outputs). The main technical parameters of a power divider include power loss (including insertion loss, distribution loss, and reflection loss), voltage standing wave ratio (VSWR) of each port, isolation between power distribution ports, amplitude balance, phase balance, power capacity, and bandwidth. In this embodiment, the output of the signal source needs to be divided into 16 parts and input into each ADC chip for processing, so a 1-to-16 power divider is required.
[0077] Add the power divider and signal source to the existing test platform. After setting up the test environment, turn on the clock signal source to configure the clock chip. The data input to the ADC chip is processed and the first output code value is obtained through the chip evaluation motherboard and fed back to the host computer 10. The host computer 10 performs FFT analysis on the saved data to obtain performance data such as signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), and ENOB (equivalent bit number).
[0078] ENOB is a performance metric for an ADC, representing the effective number of bits when an analog signal is converted to a digital signal. Calculating ENOB requires parameters such as signal-to-noise ratio and reference voltage, and can be performed using relevant functions in Matlab. The ADC performance is evaluated based on the calculated ENOB value. A higher ENOB indicates better ADC performance and a more accurate conversion between analog and digital signals.
[0079] SFDR is commonly used to measure the dynamic range available to a data converter before spurious components interfere with or distort the fundamental signal. SFDR is defined as the ratio of the root mean square (RMS) value of the fundamental sinusoidal signal to the RMS value of the peak spurious signal at the output, measured from 0 Hz (DC) to half the data converter sampling rate (e.g., fs / 2). Peak spurious components can be harmonic or non-harmonic.
[0080] SNR is the ratio of signal strength to noise strength. The SNR calculated by FFT is a combination of several noise sources. Possible noise sources include ADC quantization error, ADC internal noise, reference voltage noise, ADC differential nonlinearity error, and driver amplifier noise.
[0081] Optionally, different registers can be controlled to independently enable digital functions in the downlink, such as mixer, DDS, fractional delay, decimation filter, offset calibration, and DC calibration, to verify their functionality and compare them with the ADC results.
[0082] Optionally, in analog-to-digital AD passband testing scenarios, enable the clock signal source to configure the clock chip;
[0083] The signal source is used to increase the frequency of the test signal in fixed steps while keeping the output power constant;
[0084] The chip evaluation motherboard is used to obtain a second output code value based on the feedback signal;
[0085] The host computer 10 is used to perform Fourier analysis based on the second output code value to obtain the frequency response curve, and to analyze the AD passband flatness and bandwidth range based on the frequency response curve.
[0086] In this embodiment, FFT analysis is performed on the saved data to obtain the maximum spectral value and plot the Freq vs VIN curve, thus obtaining the AD passband flatness and bandwidth range. Passband flatness refers to the non-uniformity of the gain of an AD converter within a specified frequency range. An ideal AD converter should have the same gain across the entire passband, but in reality, due to non-ideal circuit characteristics, the gain will fluctuate. Passband flatness is usually expressed in decibels (dB); a smaller value indicates a flatter frequency response. Bandwidth refers to the frequency range within which the AD converter can accurately convert signals. Within this range, conversion errors and distortion can be kept within acceptable levels. Bandwidth is typically defined as the -3dB point, which is the frequency at which the output signal power drops by 3dB compared to the input signal power.
[0087] The analysis process for AD passband flatness and bandwidth range is as follows:
[0088] Record the amplitude of the AD output at different frequency points, and calculate the gain and distortion by comparing it with the input signal. Plot the frequency response curve with frequency on the x-axis and gain (or relative error) on the y-axis.
[0089] Find the maximum and minimum values of the gain within the passband, calculate the difference between them and convert it to dB to obtain the passband flatness.
[0090] Identify the frequency at which the gain drops to -3dB; this point is the -3dB bandwidth of the AD converter.
[0091] This embodiment provides another testing system for digital-to-analog converter chips. Figure 4This is a schematic diagram of the structure of a digital-to-analog converter chip testing system provided in an embodiment of this application. Figure 4 As shown, in the DAC performance test scenario, the chip under test set on the chip evaluation sub-board 30 is a DAC chip. The output terminal of the chip under test is connected to the transimpedance amplifier (TIA), and the output terminal of the TIA is connected to the spectrum analyzer.
[0092] The host computer 10 is used to output test data, and the spectrum analyzer is used to generate a spectrum based on the signal amplified by the TIA. The spectrum is used to analyze and obtain DAC performance parameters.
[0093] In this embodiment, the main function of the trans-impedance amplifier (TIA) is to convert the weak current signal output by the sensor into a voltage signal that is easy to process, while simultaneously providing gain. It is widely used in applications requiring high-sensitivity current detection, especially when used in conjunction with photodetectors (such as photodiodes) for the detection and conversion of optical signals.
[0094] The process of obtaining DAC performance parameters based on spectrum analysis is similar to the process of obtaining ADC chip performance data, and will not be elaborated here.
[0095] Optionally, different registers can be controlled to independently enable digital functions in the downlink, such as mixer, DDS, inverse sinc function, fractional delay, interpolation filter, offset calibration, and DC calibration, to verify their functional effects and compare them with DAC results.
[0096] Optionally, in the digital-to-analog converter (DAC) passband test scenario, the chip evaluation motherboard is used to increase the frequency of the output signal in fixed steps according to the instructions from the host computer, while the amplitude of the output signal remains unchanged.
[0097] The spectrum analyzer is used to generate the DAC output frequency response curve, which is used to determine the DAC passband flatness and bandwidth range.
[0098] In this embodiment, the process of determining the DA passband flatness and bandwidth range based on the frequency response curve is similar to the steps described above for analyzing the AD passband flatness and bandwidth range based on the frequency response curve, and will not be repeated here.
[0099] To implement the above embodiments, this application also proposes an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the system provided in the foregoing embodiments.
[0100] To implement the above embodiments, this application also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the system provided in the foregoing embodiments.
[0101] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in this application all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.
[0102] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.
[0103] This application is intended to provide an implementation scheme for users to selectively prevent the use or access to their personal information data. Specifically, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information is de-identified to protect user privacy.
[0104] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0105] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0106] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.
[0107] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.
[0108] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0109] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
[0110] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.
[0111] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.
Claims
1. A digital-to-analog conversion chip testing system, characterized by, The system comprises the following modules: a host computer, a chip evaluation master board, a plurality of chip evaluation sub-boards, and a measuring device; The host computer is configured to determine a test instruction according to a test item, and send the test instruction to the chip evaluation master board, and receive test feedback data sent by the chip evaluation master board; The chip evaluation master board comprises a plurality of interfaces configured to access the measuring device and the chip evaluation sub-boards, and perform a test operation on the chip evaluation sub-boards according to the test instruction, and obtain test feedback data of the measuring device; The chip evaluation sub-boards are provided with chips to be tested, and the chips to be tested are connected to the chip evaluation master board through a digital module.
2. The system of claim 1, wherein, The chip evaluation master board is connected to the chip evaluation sub-boards through a field programmable logic gate array (FMC) connector, and the measuring device accessed by the chip evaluation master board comprises a bit error rate tester, a power supply, a signal source, a spectrum analyzer, and a high-speed oscilloscope.
3. The system of claim 2, wherein, In a temperature sensor precision test scenario, the chip evaluation master board is arranged in a high-low temperature chamber; The chip evaluation master board is connected to a temperature controller of the high-low temperature chamber, and is configured to control the temperature of the high-low temperature chamber according to the test instruction, and obtain test feedback data generated by a temperature sensor in the chip to be tested; The host computer is configured to compare the test feedback data with a target temperature in the test instruction to generate a temperature drift curve.
4. The system of claim 2, wherein, In a serialization and deserialization test scenario, the high-speed oscilloscope is connected to a serialization and deserialization transmission line at an input end of the chip to be tested and a serialization and deserialization transmission line at an output end of the chip to be tested, and the bit error rate tester is connected to the input end and the output end of the chip to be tested; The chip evaluation master board is configured to input a preset test signal to the input end of the chip to be tested according to the test instruction; The host computer is configured to generate an eye diagram according to input waveforms and output waveforms collected by the high-speed oscilloscope, and read corresponding performance indicators according to the eye diagram.
5. The system of claim 2, wherein, In an analog-to-digital conversion (ADC) performance test scenario, the chip to be tested arranged on the chip evaluation sub-board is an ADC chip, the chip to be tested is connected to an output end of a power divider, and an input end of the power divider is connected to an output end of a signal source; The signal source is configured to output a test signal; The power divider is configured to divide the test signal into a plurality of sub-test signals, and output the sub-test signals to the chip to be tested; The chip to be tested is configured to process the sub-test signals and output a feedback signal to the chip evaluation master board through the digital module; The chip evaluation master board is configured to obtain a first output code value according to the feedback signal; The host computer is configured to perform Fourier analysis on the first output code value to obtain ADC chip performance data.
6. The system of claim 5, wherein, In an analog-to-digital (AD) passband test scenario, the signal source is configured to increase the frequency of the test signal in a fixed step, and keep the output power unchanged; The chip evaluation master board is configured to obtain a second output code value according to the feedback signal; The host computer is configured to perform Fourier analysis on the second output code value to obtain a frequency response curve, and analyze the AD passband flatness and bandwidth range according to the frequency response curve.
7. The system of claim 2, wherein, In a digital analog conversion (DAC) performance test scene, a to-be-tested chip disposed on the chip evaluation daughterboard is a DAC chip, an output end of the to-be-tested chip is connected with a transimpedance amplifier (TIA), and an output end of the TIA is connected with the spectrum analyzer; The host computer is configured to output test data, the spectrum analyzer is configured to generate a spectrum according to the signal amplified by the TIA, and the spectrum is configured to be analyzed to obtain a DAC performance parameter.
8. The system of claim 7, wherein, In a digital analog conversion (DAC) passband test scene, the chip evaluation motherboard is configured to increase a frequency of an output signal according to an instruction of the host computer in a fixed step, and an amplitude of the output signal remains unchanged. The spectrum analyzer is configured to generate a DAC output frequency response curve, and the frequency response curve is configured to determine a DAC passband flatness and a bandwidth range.
9. An electronic device, comprising: Comprise: a processor, and a memory connected with the processor in communication; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the system of any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by the processor to implement the system of any one of claims 1-8.