Accelerator, input-output memory management unit, and related devices and methods

Abstract

Embodiments of the present application provide an accelerator, an input / output memory management unit and related devices and methods. The accelerator comprises: a receiving unit that sequentially receives a first translation request and a second translation request, and virtual page numbers corresponding to the first translation request and the second translation request are recorded in a same first page table entry; a querying unit that queries whether the first page table entry exists in a first translation lookaside buffer of a level one cache, if not, acquires the first page table entry from outside the first translation lookaside buffer, and sends the first translation request to a prefetch unit; a deduplication unit that associates the second translation request with the first translation request, and after the querying unit acquires the first page table entry, acquires a translation result from the first page table entry. The prefetch unit initiates a prefetch operation after prefetch training is completed, acquires a second page table entry of a predicted translation request, and stores the second page table entry to a second translation lookaside buffer of a level two cache. The present scheme can improve the efficiency of virtual address translation.

Description

Technical Field

[0001] This application relates to the field of virtual memory technology, and in particular to an accelerator, an input / output memory management unit, and related devices and methods. Background Technology

[0002] In streaming access scenarios, input / output (I / O) devices access data sequentially and continuously. Based on memory management, address mapping is performed using fixed-size memory blocks, and the virtual addresses of continuously accessed data are typically concentrated within the same memory block. When a streaming device initiating an access sequentially retrieves the physical addresses corresponding to consecutive virtual addresses, it generates multiple consecutive virtual address translation requests for the same memory block.

[0003] Currently, to accelerate the process of translating virtual addresses to physical addresses, a Translation Lookaside Buffer (TLB) is used to cache recently used virtual and physical address mappings. Simultaneously, a Prefetch Unit (PFU) is employed to analyze memory access flow patterns and pre-load address mappings into the TLB to reduce the probability of subsequent TLB misses.

[0004] However, in high-concurrency streaming scenarios involving multiple streaming devices, when the address mapping of a virtual page is not cached in the translation back buffer, the first request for that page will trigger a page table traversal. Since subsequent translation requests for the same virtual page do not wait for the mapping table to be stored in the translation back buffer, page table traversal will be repeatedly triggered for the same page. Furthermore, PFU (Programmable Page Frame) is prone to misjudging consecutive same-page misses as cross-page accesses, triggering incorrect cross-page prefetching, resulting in a high overall average latency for address translation. Summary of the Invention

[0005] In view of this, embodiments of this application provide an accelerator, an input / output memory management unit, and related apparatus and methods to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, an accelerator is provided, comprising: a receiving unit, a querying unit, a deduplication unit, and a prefetching unit; the receiving unit is configured to sequentially receive a first translation request and a second translation request, wherein the first translation request and the second translation request are both virtual address translation requests, and the virtual page numbers corresponding to the first translation request and the second translation request are recorded in a first page table entry corresponding to the same memory block, the first page table entry being used to record the mapping relationship between the virtual page number and the physical page number of the memory block; the querying unit is configured to query whether the first page table entry exists in a first translation back buffer, and if the first page table entry does not exist in the first translation back buffer, then obtain the first page table entry from outside the first translation back buffer and send the first translation request to the prefetching unit, wherein the first translation back buffer is a translation back buffer of a level 1 cache; the deduplication unit is configured to... The second translation request is associated with the first translation request, and after the query unit obtains the first page table entry, the translation results of the first translation request and the second translation request are obtained from the first page table entry; the prefetch unit is used to determine the table entry corresponding to the first translation request after receiving the first translation request, and update the count value of the confidence counter stored in the table entry. After the updated count value meets the preset condition, a speculative prefetch request is initiated to obtain the second page table entry through the speculative prefetch request, and the second page table entry is stored in the second translation backup buffer. The second translation backup buffer is a translation backup buffer of the second-level cache. The second page table entry includes the virtual page number of the predicted translation request. The predicted translation request is a virtual address translation request that is predicted to be received by the receiving unit after the first translation request, and whose corresponding virtual page number is different from the virtual page number corresponding to the first translation request.

[0007] According to a second aspect of the embodiments of this application, an input / output memory management unit is provided, including: an accelerator as described in the first aspect above.

[0008] According to a third aspect of the embodiments of this application, a system-on-a-chip is provided, including: an input / output memory management unit as described in the second aspect above.

[0009] According to a fourth aspect of the embodiments of this application, a computing device is provided, including: a system-on-a-chip as described in the third aspect above.

[0010] According to a fifth aspect of the embodiments of this application, a method for accelerating virtual address translation is provided, comprising: sequentially receiving a first translation request and a second translation request, wherein the first translation request and the second translation request are both virtual address translation requests, and the virtual page numbers corresponding to the first translation request and the second translation request are recorded in a first page table entry corresponding to the same memory block, the first page table entry being used to record the mapping relationship between the virtual page number and the physical page number of the memory block; querying whether the first page table entry exists in a first translation back buffer; if the first page table entry does not exist in the first translation back buffer, obtaining the first page table entry from outside the first translation back buffer, and determining the entry corresponding to the first translation request; updating the count value of the confidence counter stored in the entry; and in... After the updated count value meets the preset conditions, a speculative prefetch request is initiated to obtain the second page table entry through the speculative prefetch request, and the second page table entry is stored in the second translation back buffer. The first translation back buffer is a translation back buffer of the first-level cache, and the second translation back buffer is a translation back buffer of the second-level cache. The second page table entry includes the virtual page number of the predicted translation request. The predicted translation request is a virtual address translation request that is predicted to be received after the first translation request and whose corresponding virtual page number is different from the virtual page number corresponding to the first translation request. The second translation request is associated with the first translation request, and after waiting to obtain the first page table entry, the translation results of the first translation request and the second translation request are obtained from the first page table entry.

[0011] According to the accelerated virtual address translation scheme provided in the embodiments of this application, in a multi-request concurrent scenario, when multiple access requests for the same page table entry fail to hit in the first translation back buffer, the access requests for the same page table entry are associated through the deduplication unit. On the one hand, this allows multiple requests that depend on the same page table entry to reuse the page table entry triggered by the first request to obtain the result, simplifying multiple redundant page table traversal operations for the same page table entry into a single retrieval operation. On the other hand, it allows the prefetch unit to only receive cross-page requests in streaming access, providing the prefetch unit with clean training data, ensuring the accuracy of prefetch training and prefetch operations, thereby shortening the average processing latency of streaming translation requests, improving the real-time response performance of streaming access, and thus improving the stability and throughput of the system under high-concurrency load scenarios. Compared with existing technologies, the accelerator provided in this application identifies and associates concurrent translation requests for the same virtual page number through a deduplication unit. This avoids repeated querying and retrieval operations for the same page table entry, optimizes the address translation efficiency within the same virtual page, and avoids erroneous prefetching operations caused by the prefetch unit misjudging a missed request on the same page as a cross-page access. Through accurate prefetching, it improves the address translation performance in cross-page scenarios and comprehensively accelerates the address translation performance of streaming access devices within the same virtual page and in cross-page scenarios. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1 This is a schematic diagram of a computing device used in one embodiment of this application;

[0014] Figure 2 This is a schematic diagram of an input / output memory management unit according to an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of an accelerator according to one embodiment of this application;

[0016] Figure 4 This is a schematic diagram of a prefetch unit according to an embodiment of this application;

[0017] Figure 5 This is a flowchart of an embodiment of the accelerated virtual address translation method of this application. Detailed Implementation

[0018] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0019] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0020] I / O address mapping: The correspondence between the I / O virtual address (IOVA) used by an input / output device and the actual physical address of the memory when the input / output device accesses memory through direct memory access.

[0021] Virtual Page Number (VPN): The part of a virtual address used to identify a virtual memory block. It is the high-order field of the virtual address and is used to index the corresponding physical page number in the page table.

[0022] Physical Page Number (PPN): The part of the physical address used to identify the physical memory block. It is the high-order field of the physical address and is mapped to the virtual page number through page table entries. It is used to locate the storage block of data in the actual physical memory.

[0023] Page Offset: The low-order field of a virtual or physical address, used to locate a specific byte address within a memory block. Its length is determined by the size of the memory block (e.g., the offset for a 4KB page is 12 bits). Combined with the virtual page number, it uniquely identifies the complete virtual address; combined with the physical page number, it uniquely identifies the complete physical address.

[0024] Page Table Walk: The process by which the Input / Output Memory Management Unit (I / O Memory) searches for the target page table entry level by level, starting from the root node of the page table and following a preset hierarchy (such as the root page table, intermediate page tables, and leaf page tables in a multi-level page table system), until it obtains the physical page number corresponding to the virtual page number.

[0025] Streaming access: A data access mode in which a device or process accesses adjacent or logically close data blocks in memory in a continuous and sequential manner. The virtual addresses of the access requests are usually concentrated in the same or contiguous memory blocks.

[0026] Figure 1A schematic block diagram of a computing device 10 is shown. The computing device 10 can be built based on a System-on-Chip (SoC) and driven by any operating system such as Windows, UNIX, or Linux. Furthermore, the computing device 10 can be implemented in hardware and / or software such as PCs, desktops, laptops, servers, and mobile communication devices.

[0027] like Figure 1 As shown, computing device 10 may include a system-on-a-chip (SoC) 12, a memory 14, and external devices 16. The SoC 12 includes one or more processors 121, and the memory 14 may serve as main memory (or simply main memory) for storing page tables that include the mapping between I / O virtual addresses and physical addresses. In another example, the memory 14 may be integrated with the processor 121 within the same SoC, and both the processor 121 and the memory 14 are coupled to the bus 11 of the SoC 12.

[0028] External devices 16 in computing device 10, also known as input / output (I / O) devices, may include storage devices, display devices, audio devices, mice / keyboards, etc. External devices 16 can connect to the system-on-a-chip (SoC) 12 via the I / O interfaces provided by the SoC 12, and can be coupled to bus 11 via high-speed interconnect standards such as Peripheral Component Interconnect (PCI), PCI Express (PCIe), etc., which are connected to the system bus. For example, storage devices may be hard disks, optical disks, flash memory, etc., used for information access, coupled to bus 11 through corresponding interfaces. Display devices can be coupled to bus 11 via the system-on-a-chip integrated display controller or an external discrete graphics card, and are used to display information according to the display signals provided by bus 11.

[0029] In some cases, some external devices 16 (such as storage devices) access memory using Direct Memory Access (DMA). Based on this, the system-on-a-chip 12 may include one or more Input-Output Memory Management Units (IOMMUs) 122 independent of the processor 121, with the IOMMUs 122 coupled to the bus 11. The IOMMUs 122 can access the memory 14 via the bus 11 to obtain page table information in the memory 14, and then translate the I / O virtual addresses used by the external devices 16 into physical addresses, enabling the external devices 16 using DMA to safely and efficiently read and write memory directly. For example, the external device 16 can first send a translation request containing the I / O virtual address to the I / O bridge 123. The I / O bridge 123 forwards the translation request to the IOMMU. After completing the address translation, the IOMMU returns the physical address to the IOM bridge 123, which then uses the physical address to access the memory 14 via the bus 11. External device 16 can also directly send the I / O virtual address to the IOMMU in the form of a translation request. After the IOMMU completes the address translation, it returns the corresponding physical address to the requesting device, which then accesses the memory 14 via bus 11 using this physical address. Alternatively, external device 16 can directly send the I / O virtual address to the IOMMU in the form of a translation request. After the IOMMU completes the address translation, it directly sends the corresponding physical address to bus 11, signifying that the device has completed access to the memory 14.

[0030] Furthermore, the computing device 10 may also include a communication device (not shown), enabling the computing device 10 to communicate with networks or other devices in various ways. The communication device may include one or more communication modules, and may include a wireless communication module adapted to a specific wireless communication protocol. For example, the communication device may include a WLAN module for implementing WiFi communication conforming to the IEEE 802.11 standard. The communication device may include a WWAN module for implementing wireless wide-area communication conforming to cellular or other wireless wide-area protocols. The communication device may also include a Bluetooth module or other communication modules employing other protocols, or other custom-type communication modules.

[0031] It should be noted that the structure of different computing devices 10 may vary depending on the motherboard, operating system, and instruction set architecture. For example, many current computing devices are equipped with an input / output control center connected between the bus 11 and various input / output devices, and this input / output control center may be integrated into the processor 121 or independent of the processor 121.

[0032] The Input / Output Memory Management Unit 122 is a hardware unit that provides memory management functions for the external device 16. It translates the I / O virtual address in the DMA request initiated by the external device 16 into the host physical address and performs permission checks during this process. In the ARM architecture, the Input / Output Memory Management Unit is also known as the System Memory Management Unit (SMMU).

[0033] Figure 2 This is a schematic block diagram of an input / output memory management unit according to an embodiment of this application. Figure 2 As shown, when implementing the translation of I / O virtual addresses to physical addresses, the input / output memory management unit 122 needs to access the memory 14 through the bus 11 and traverse the page table level by level to obtain the page table data in the memory 14. Since the access speed of the memory 14 is relatively slow and the page table lookup latency is relatively high, in order to alleviate the speed gap between the input / output memory management unit 122 and the memory 14, the input / output memory management unit 122 also includes a translation lookaside buffer (TLB) 1221 that is communicatively connected to the bus 11. The translation lookaside buffer 1221 is used to cache multiple page table entries (i.e., the mapping relationship between multiple I / O virtual page numbers and physical page numbers) in the memory 14 that may be repeatedly accessed.

[0034] The translation back buffer 1221 can be implemented using a storage device such as Static Random Access Memory (SRAM). The translation back buffer 1221 can be a multi-level structure, such as a two-level cache structure with a first-level translation back buffer (L1TLB) and a second-level translation back buffer (L2TLB). Figure 2 The two-level translation backup buffers L1TLB to L2TLB are shown. Figure 2 The translation back buffer 1221 (unified identifier in the code) can also be a cache structure of level two or higher or other types of cache structures. The translation back buffer 1221 can be fully or partially integrated into the input / output memory management unit 122.

[0035] Based on this, the input / output memory management unit 122 may include an accelerator 1222. The accelerator 1222 is used to query the translation backup buffer 1221 after obtaining a virtual address translation request, and translate the I / O virtual address corresponding to the virtual address translation request into the physical address mapped by the I / O virtual address.

[0036] The mapping between virtual and physical addresses is based on memory blocks (e.g., 4KB pages). The mapping relationship between the I / O virtual page number and the physical page number of each memory block is recorded in a page table entry data structure. This page table entry serves as the smallest unit for data exchange between the translation back buffer 1221 and memory 14. Memory 14 stores the complete page table, which consists of multiple page table entries. The page table records the mapping relationship between the I / O virtual page number and the physical page number of all allocated memory blocks. Each entry in the translation back buffer 1221 caches a copy of a frequently used page table entry, and different translation back buffer entries correspond to page table entries with different virtual page numbers.

[0037] Due to space and resource limitations, the translation back buffer 1221 cannot cache all page table entries in the page table of memory 14. That is, the storage capacity of the translation back buffer 1221 is typically smaller than that of memory 14, and the individual TLB entries provided by the translation back buffer 1221 cannot cache all page table entries in memory 14. When address translation is required, the accelerator 1222 first accesses the translation back buffer 1221 to determine whether the page table entry corresponding to the virtual address to be translated has been cached in the translation back buffer 1221. If the page table entry corresponding to the virtual address to be translated has been cached in the translation back buffer 1221, then the translation back buffer 1221 is hit. At this time, the accelerator 1222 directly retrieves the I / O address mapping relationship corresponding to the virtual address to be translated from the translation back buffer 1221 to complete the address translation. If the page table entry corresponding to the virtual address to be translated is not cached in the translation lookup buffer 1221, the accelerator 1222 needs to access the memory 14 via the bus 11 to find the page table entry corresponding to the virtual address to be translated in the page table of the memory 14. After loading the page table entry into the TLB entry of the translation lookup buffer 1221, the address translation is completed. Since the access rate of the translation lookup buffer 1221 is very fast, the efficiency of address translation can be significantly improved when the translation lookup buffer 1221 is hit, thereby improving the performance and efficiency of the entire computing device 10.

[0038] This application focuses on the accelerated address translation process of accelerator 1222, which will be described in detail later.

[0039] In streaming access scenarios, external devices 16 using direct memory access access data sequentially. Based on memory management and address mapping using fixed-size memory blocks, the virtual addresses of continuously accessed data are typically concentrated within the same memory block. When the streaming device initiating the access sequentially obtains the physical addresses corresponding to consecutive virtual addresses, it generates multiple consecutive virtual address translation requests for the same memory block.

[0040] Currently, to accelerate the translation of virtual addresses to physical addresses, a translation lookup buffer is used to cache recently used virtual and physical address mappings. Simultaneously, a prefetch unit analyzes memory access flow patterns and preloads address mappings into the translation lookup buffer to reduce the probability of subsequent translation lookup buffer misses. However, in high-concurrency streaming scenarios with multiple streaming devices, when the address mapping of a virtual page is not cached in the translation lookup buffer, the first request for that page will trigger a page table traversal. Since subsequent translation requests for the same virtual page do not wait for the mapping table to be stored in the translation lookup buffer, page table traversals will be repeatedly triggered for the same page. Furthermore, the prefetch unit is prone to misjudging consecutive same-page misses as cross-page accesses, triggering incorrect cross-page prefetches, resulting in a high overall average latency for address translation.

[0041] This application embodiment is designed to address the problem of low address translation efficiency caused by repeated page table traversal and erroneous prefetching due to consecutive misses of translation requests for the same memory block in streaming scenarios. It is mainly implemented through accelerator 1222. The internal structure of accelerator 1222 and the implementation process of this application embodiment are described in detail below.

[0042] Figure 3 This is a schematic diagram of the internal structure of an accelerator 1222 according to one embodiment of this application. Figure 3As shown, the accelerator 1222 includes a receiving unit 21, a query unit 22, a deduplication unit 23, and a prefetch unit 24. The receiving unit 21 can sequentially receive a first translation request and a second translation request. Both the first and second translation requests are virtual address translation requests, and the virtual page numbers corresponding to the first and second translation requests are recorded in the first page table entry corresponding to the same memory block. The first page table entry is used to record the virtual page number and physical page number in the memory block. The query unit 22 can query whether a first page table entry exists in the first translation back buffer. If the first page table entry does not exist in the first translation back buffer, it retrieves the first page table entry from outside the first translation back buffer and sends the first translation request to the prefetch unit 24. The first translation back buffer is a translation back buffer of the L1 cache. The deduplication unit 23 can associate the second translation request with the first translation request and wait for the query unit 22 to retrieve the first page table entry before retrieving the translation results of the first and second translation requests from the first page table entry. After receiving the first translation request, the prefetch unit 24 can determine the entry corresponding to the first translation request and update the count value of the confidence counter stored in the entry. After the updated count value meets the preset conditions, it can initiate a speculative prefetch request to obtain the second page entry through the speculative prefetch request and store the second page entry in the second translation back buffer. The second translation back buffer is a translation back buffer of the second-level cache. The second page entry includes the virtual page number of the predicted translation request. The predicted translation request is a virtual address translation request that is predicted to be received by the receiving unit 21 after the first translation request and whose corresponding virtual page number is different from the virtual page number corresponding to the first translation request.

[0043] In scenarios where multiple streaming devices continuously initiate a large number of streaming accesses, when virtual address translation requests for the same memory block arrive sequentially, the receiving unit 21 receives the first translation request and the second translation request in sequence. Both the first and second translation requests are requests to translate virtual addresses. Each translation request includes a virtual address that needs to be translated into a physical address. The virtual address includes a virtual page number and a page offset. Furthermore, the virtual addresses corresponding to the first and second translation requests belong to the same memory block, meaning they have the same virtual page number. The mapping relationship between their virtual page numbers and physical page numbers is recorded in the same first page table entry. By querying the first page table entry, the physical page number corresponding to the virtual page number of the memory block can be obtained. Therefore, the physical address corresponding to the virtual address can be obtained through the physical page number and the page offset in the virtual address. The memory block is a contiguous memory space of a preset size, such as a 4KB page, a 2MB page, or a 1GB page.

[0044] It should be noted that in this embodiment, the terms "first" and "second" are used to indicate the temporal order of arrival of requests and logical dependencies, but this is not a limitation on the number of requests. In fact, a second translation request represents one or more translation requests that arrive after the first translation request and share the same page table entry as the first translation request. In other words, "second translation request" is a generic concept that encompasses all subsequent translation requests for the same memory block that arrive before the translation result of the first translation request is ready.

[0045] After receiving unit 21 receives the first translation request, query unit 22 queries whether a first page table entry exists in the first translation backing buffer (i.e., the translation backing buffer T1TLB of the L1 cache). If the first page table entry does not exist in the first translation backing buffer, query unit 22 retrieves the first page table entry from outside the first translation backing buffer (such as the translation backing buffer T2TLB of the L2 cache or the page table in memory 14) and sends the first translation request to prefetch unit 24 so that prefetch unit 24 can perform prefetch logic judgment. Before the first page table entry is retrieved and backfilled into the first translation backing buffer, the first translation request is in a processing state of waiting for translation results, and the processing state of the first translation request waiting for translation results is recorded in the incomplete queue of deduplication unit 23. It can be understood that since the second translation request shares the same virtual page number as the first translation request, they both depend on the same first page table entry. When the first translation request is in the processing state of waiting for translation results, it indicates that there is no first page table entry in the first translation back buffer. At this time, the second translation request cannot query the first page table entry from the first translation back buffer to obtain the mapping result corresponding to its virtual page number.

[0046] After the second translation request is received by the receiving unit 21, the deduplication unit 23 queries the incomplete queue in the deduplication unit 23 using the virtual page number of the second translation request as the key. If the query finds that the first page table entry corresponding to the virtual page number is being retrieved, the second translation request is associated with the first translation request, so that the second translation request no longer triggers the query unit 22 to perform a duplicate retrieval operation for the first page table entry, but instead enters a waiting state. When the query unit 22 retrieves the first page table entry from outside the first translation back buffer, the deduplication unit 23 controls the first and second translation requests in the associated state to retrieve the physical page number corresponding to the common virtual page number from the first page table entry, and generates the corresponding physical address by combining it with the page offset in their respective virtual addresses, thereby completing the virtual address translation of multiple translation requests that depend on the same page table entry.

[0047] It should be noted that in high-concurrency scenarios with multi-stream devices, the incomplete queue in the deduplication unit 23 can record multiple translation requests corresponding to different virtual page numbers that are in a processing state waiting for translation results. Each virtual page number corresponds to an independent request association chain, and each request association chain is used to associate translation requests that share the same page table entry. After determining that a new translation request is not found in the first translation back buffer, if there is already an association chain corresponding to the virtual page number of the new translation request in the incomplete queue, that is, there is already a translation request in the same memory block waiting for its page table entry to be obtained, then the new translation request is associated with the existing request in the association chain, so that it enters a waiting state. When the query unit 22 successfully obtains the target page table entry, all translation requests in the waiting state on the association chain synchronously reuse the page table entry to obtain their respective translation results. If no corresponding association chain exists in the incomplete queue for a new translation request, meaning the new translation request is the first missed translation request for that memory block, a new association chain is created for the new translation request, its status of waiting for page table entry retrieval is recorded, and it is allowed to trigger the page table entry retrieval operation of query unit 22. Based on this design, deduplication unit 23 can simultaneously manage deduplication of translation requests for multiple different memory blocks, ensuring efficient reuse of requests for the same memory block without affecting the normal processing of requests for different memory blocks, thereby enhancing the system processing capabilities in high-concurrency scenarios of multi-streaming devices.

[0048] Upon receiving the first translation request, the prefetch unit 24 extracts the device identifier and process identifier from the first translation request. The device identifier indicates the streaming device that initiated the first translation request, and the process identifier indicates the running process to which the first translation request belongs. The prefetch unit 24 includes multiple entries, each associated with a specific combination of device and process, used to record historical access information corresponding to a specific process of a specific device. Based on the device identifier and process identifier in the first translation request, the prefetch unit 24 determines the entries associated with the device and process corresponding to the first translation request and updates the count value of the confidence counter stored in the entries. The count value of the confidence counter is used to quantify the regularity of changes in the virtual page number of the translation request for the device and process combination.

[0049] When the updated count value of the confidence counter meets the preset conditions, it indicates that the translation request of the device and process combination has shown a stable and predictable access pattern, and it is highly likely that a subsequent translation request (i.e., a predicted translation request) will be initiated that has a virtual page number associated with the first translation request. At this time, the prefetch unit 24 predicts that the receiving unit 21 will receive the translation request after the first translation request, and that the corresponding virtual page number is different from the virtual page number corresponding to the first translation request. A speculative prefetch request is generated and sent to the query unit 22. The query unit 22 retrieves the second page table entry, which includes the virtual page number corresponding to the speculative prefetch request, by querying the page table in the memory 14, and stores the second page table entry in the second translation backup buffer. This allows the second page table entry to be quickly retrieved directly from the second translation backup buffer when the predicted translation request actually arrives, if the first translation backup buffer does not contain the corresponding second page table entry.

[0050] It should be noted that the second page entry obtained by the speculative prefetch request is initially stored only in the second translation back buffer and not backfilled into the first translation back buffer. Only after the predicted translation request actually arrives and obtains the second page entry from the second translation back buffer is the second page entry backfilled into the first translation back buffer, so that subsequent translation requests in the same memory block as the predicted translation request can obtain translation results from the first translation back buffer. Thus, each first translation request across virtual pages will trigger a miss in the first translation back buffer, and there will be no corresponding incomplete request in the deduplication unit 23. Eventually, the first request across all pages will be received by the prefetch unit 24, thereby triggering the next speculative prefetch request for the subsequent new virtual page, forming a progressive prefetch mechanism.

[0051] Based on the deduplication unit 23, multiple concurrent translation requests for the same memory block are associated and deduplicated. The translation requests entering the prefetch unit 24 are all translation requests for different memory blocks (i.e., different virtual page numbers). This can effectively avoid a large number of translation requests for the same memory block triggering the first translation back buffer to miss and entering the prefetch unit 24 in a concentrated manner, which would cause the confidence counter in the prefetch unit 24 to be abnormally pulled up, thus deviating from the actual access pattern and triggering speculative prefetching. This can ensure that the confidence counter's quantitative judgment of the access pattern is objective and accurate, prevent the access pattern training process of the prefetch unit 24 from being interfered with, and improve the accuracy and hit rate of the prefetch operation.

[0052] In this embodiment, the receiving unit 21 can sequentially receive the first translation request and the second translation request, and the virtual page numbers corresponding to the first translation request and the second translation request are recorded in the same first page table entry. The query unit 22 can query whether the first page table entry exists in the first translation back buffer of the first-level cache. If it does not exist, it retrieves the first page table entry from outside the first translation back buffer and sends the first translation request to the prefetch unit 24. The deduplication unit 23 can associate the second translation request with the first translation request and wait for the query unit 22 to retrieve the first page table entry before retrieving the translation results of the first translation request and the second translation request from the first page table entry. The prefetch unit 24 can initiate a prefetch operation after the prefetch training is completed, retrieve the second page table entry of the predicted translation request, and store the second page table entry in the second translation back buffer of the second-level cache. Therefore, in multi-request concurrency scenarios, when multiple access requests for the same page table entry fail to be found in the first translation back buffer, the deduplication unit 23 associates the access requests for the same page table entry. On the one hand, this allows multiple requests that depend on the same page table entry to reuse the page table entry triggered by the first request to obtain the result, simplifying multiple redundant page table traversal operations for the same page table entry into a single retrieval operation. On the other hand, it allows the prefetch unit 24 to only receive cross-page requests in streaming access, providing clean training data for the prefetch unit 24, ensuring the accuracy of prefetch training and prefetch operations, thereby shortening the average processing latency of streaming translation requests, improving the real-time response performance of streaming access, and thus improving the stability and throughput of the system under high-concurrency load scenarios. Compared with the prior art, the accelerator 1222 provided in this application identifies and associates concurrent translation requests for the same virtual page number through the deduplication unit 23, which can avoid repeated query and retrieval operations for the same page table entry, optimize the address translation efficiency within the same virtual page, and avoid the erroneous prefetching operation caused by the prefetching unit 24 misjudging the same page miss request as a cross-page access. Through accurate prefetching, the address translation performance in cross-page scenarios is improved, and the address translation performance of streaming access devices in both the same virtual page and cross-page scenarios is comprehensively accelerated.

[0053] In one possible implementation, after determining that there is no first page table entry in the first translation backup buffer, the query unit 22 may query whether there is a first page table entry in the second translation backup buffer. If there is a first page table entry in the second translation backup buffer, the first page table entry is obtained from the second translation backup buffer. If there is no first page table entry in the second translation backup buffer, the first page table entry is obtained by querying the page table.

[0054] After determining that the first page table entry does not exist in the first translation back buffer, query unit 22 can query whether the first page table entry exists in the second translation back buffer. If prefetch unit 24 has completed prefetch training, that is, the updated count value meets the preset conditions, and has initiated a speculative prefetch request for the memory block that may be accessed subsequently, and has filled the prefetched page table entries (including possible first page table entries) back into the second translation back buffer, then the query unit 22's query on the second translation back buffer will directly hit the first page table entry. The first translation request can quickly obtain the first page table entry through the second translation back buffer without triggering the time-consuming main memory page table traversal process.

[0055] If the prefetch unit 24 has not completed the prefetch training, the first page table entry will also not exist in the second translation backup buffer. The query unit 22 will then access the page table in the memory 14, perform a page table traversal operation to obtain the first page table entry, and after obtaining the first page table entry, fill the first page table entry back into the first translation backup buffer and the second translation backup buffer to accelerate the subsequent translation access of the first page table entry corresponding to the same memory block.

[0056] It should be noted that speculative prefetch requests generated by prefetch unit 24 and normal translation requests that need to query the second translation back buffer or main memory page table due to a miss in the first translation back buffer will compete for access to the second translation back buffer. To avoid speculative prefetching interfering with the translation progress of normal translation requests and to maximize the processing progress of normal translation requests, the access arbitration between the two follows the rule that normal translation requests have higher priority than speculative prefetch requests. Specifically, normal translation requests are critical requests that need to obtain translation results in real time, while speculative prefetch requests are speculative operations initiated based on access pattern prediction and are not rigid requests that must be completed at present. Therefore, an arbitration mechanism is configured to prioritize normal translation requests over speculative prefetch requests. This prevents speculative prefetch requests from preempting the second translation back buffer entry resource. Instead, they continuously send access requests to the second translation back buffer until a higher-priority first translation back buffer is detected, indicating that no normal translation request is waiting to access the second translation back buffer. Only then is the request sent to the second translation back buffer to perform page table entry retrieval, thus avoiding interference with the processing progress of normal translation requests. Furthermore, since the deduplication unit 23 performs deduplication on multiple concurrent translation requests targeting the same memory block, only the first request for the same memory block will trigger a lookup in the second translation back buffer or main memory page table. Subsequent requests for the same memory block will enter a waiting state and will not enter the second translation back buffer. Therefore, the second translation back buffer entry will only intermittently receive normal translation requests across memory blocks, preventing continuous high traffic from causing speculative prefetch requests to fail arbitration for extended periods. This ensures that speculative prefetch requests can be successfully sent during periods of low traffic at the second translation back buffer entry.

[0057] In this embodiment, through a multi-level query mechanism in which the prefetch unit 24, the first translation backup buffer, and the second translation backup buffer work together, when the prefetch unit 24 accurately identifies a stable streaming access pattern and completes pre-filling, the translation request can be hit in the second translation backup buffer with a high probability even if it is not hit in the first translation backup buffer. This avoids high-latency main memory page table traversal operations, directly obtains the target page table entry, and accelerates the address translation efficiency in high-concurrency access scenarios of multi-streaming devices.

[0058] In one possible implementation, the query unit 22 can retrieve the translation results of the first translation request and the second translation request from the first page entry stored in the first translation backup buffer when the first page entry exists in the first translation backup buffer.

[0059] After receiving unit 21 receives the first translation request and the second translation request sequentially, query unit 22 first queries whether the first page table entry is cached in the first translation backup buffer. If query unit 22 determines that the first page table entry already exists in the first translation backup buffer, then query unit 22 directly reads the first page table entry from the first translation backup buffer. Based on the mapping relationship between the virtual page number and the physical page number recorded in the first page table entry, the physical page number corresponding to the virtual page number common to both the first and second translation requests is obtained. By concatenating the physical page number with the page offset in the virtual address of the first translation request, the physical address of the first translation request can be obtained, which serves as the translation result of the first translation request. By concatenating the physical page number with the page offset in the virtual address of the second translation request, the physical address of the second translation request can be obtained, which serves as the translation result of the second translation request.

[0060] In this embodiment of the application, when the first page entry is cached in the first translation back buffer, the query unit 22 can directly use the cached first page entry to quickly complete the translation, avoiding access to external storage, shortening the processing cycle of the translation request, thereby improving the address translation efficiency in multi-request concurrent scenarios and optimizing the real-time response performance of streaming access.

[0061] Figure 4 This is a schematic diagram of the internal structure of a prefetch unit according to an embodiment of this application. Figure 4As shown, the prefetch unit 24 includes an index subunit 241, an update subunit 242, and a request subunit 243. The index subunit 241 can calculate a hash value based on the device and process corresponding to the first translation request, and index the table entry corresponding to the first translation request based on the hash value. After the index subunit 241 indexes the table entry corresponding to the first translation request based on the hash value, the update subunit 242 compares the first virtual page number corresponding to the first translation request with the second virtual page number stored in the virtual page number field of the table entry. If the first virtual page number equals the second virtual page number plus one, and the count value of the positive confidence counter included in the table entry is less than the first saturation value, then the count value of the positive confidence counter is incremented by one, and the count value of the negative confidence counter included in the table entry is decremented by one. The second virtual page number stored in the virtual page number field is then updated to the first virtual page number. If the first virtual page number equals the second virtual page number plus one, and the positive confidence counter... If the counter value equals the first saturation value, the second virtual page number stored in the virtual page number field is updated to the first virtual page number. If the first virtual page number equals the second virtual page number minus one, and the count value of the reverse confidence counter is less than the second saturation value, the count value of the reverse confidence counter is incremented by one, and the count value of the forward confidence counter is decremented by one. The second virtual page number stored in the virtual page number field is then updated to the first virtual page number. If the first virtual page number equals the second virtual page number minus one, and the count value of the reverse confidence counter equals the second saturation value, the second virtual page number stored in the virtual page number field is updated to the first virtual page number. The request subunit 243 can initiate a forward speculative prefetch request after the count value of the forward confidence counter exceeds a first preset threshold, and initiate a reverse speculative prefetch request after the count value of the reverse confidence counter exceeds a second preset threshold, wherein the first preset threshold is less than the first saturation value, and the second preset threshold is less than the second saturation value.

[0062] Indexing subunit 241 can generate a hash value for indexing based on the device identifier and process identifier in the first translation request, by performing a hash operation on the device identifier and process identifier. Based on this hash value, indexing subunit 241 can quickly locate the target table entry corresponding to the current device and process combination, i.e., the table entry corresponding to the first translation request, among multiple table entries in prefetching unit 24. The table entry includes a virtual page number field, a forward confidence counter, and a reverse confidence counter. The virtual page number field stores the virtual page number corresponding to the translation request. The count value of the forward confidence counter quantifies the confidence that the streaming access exhibits a forward streaming trend, and the count value of the reverse confidence counter quantifies the confidence that the streaming access exhibits a reverse streaming trend. During system initialization, the initial value of the virtual page number field is 0, and the count values ​​of both the forward confidence counter and the reverse confidence counter are 0.

[0063] After index subunit 241 locates the target entry corresponding to the translation request (i.e., the first translation request) issued by the current device and process combination based on the hash value, update subunit 242 compares the first virtual page number corresponding to the first translation request with the second virtual page number stored in the virtual page number field of the entry, and executes the update logic based on the comparison result. The logic for comparing the first virtual page number and the second virtual page number depends on the size of the memory block. For example, in SV39 translation mode, the 39-bit virtual address is divided into a 27-bit virtual page number (VPN, vpn[26:0]) and a 12-bit page offset (offset[11:0]). If the memory block is a 4KB page, and the deduplication module and the prefetch module operate at a granularity of 4KB, then all 27 bits of VPN (vpn[26:0]) are compared. If the memory block is a 2MB page, only the high 18 bits of VPN (vpn[26:9]) are compared. If the memory block is a 1G page, only the high 9 bits of VPN (vpn[26:18]) are compared.

[0064] Based on the comparison results, the update logic is executed, specifically including: if the first virtual page number equals the second virtual page number plus one, and the count value of the positive confidence counter included in the entry is less than the first saturation value, it indicates that the streaming access is showing a positive increasing trend. The count value of the positive confidence counter included in the entry is incremented by one, and the count value of the negative confidence counter included in the entry is decremented by one (the lower limit of the negative confidence counter is 0; if the count value of the negative confidence counter is 0, it remains unchanged), to strengthen the credibility of the positive streaming access mode and weaken the credibility of the negative streaming mode. The second virtual page number stored in the virtual page number field is updated to the first virtual page number for future virtual page number comparisons. When the positive confidence counter equals the first saturation value, only the virtual page number field is updated to the first virtual page number; no increment or decrement of the counter is performed. Similarly, if the first virtual page number equals the second virtual page number minus one, and the count value of the reverse confidence counter included in the entry is less than the second saturation value, it indicates that the streaming access exhibits a reverse increasing trend. The count value of the reverse confidence counter included in the entry is incremented by one, and the count value of the positive confidence counter included in the entry is decremented by one (the lower limit of the positive confidence counter is 0; if the count value of the positive confidence counter is 0, it remains unchanged). This strengthens the credibility of the reverse streaming access pattern and weakens the credibility of the positive streaming pattern. The second virtual page number stored in the virtual page number field is updated to the first virtual page number for future virtual page number comparisons. When the reverse confidence counter equals the second saturation value, only the virtual page number field is updated to the first virtual page number; no increment or decrement of the counter is performed.

[0065] When the positive confidence counter value exceeds the first preset threshold, it indicates that the streaming access mode of the device and process combination has stably exhibited positive streaming characteristics, and there is a high probability that a translation request for virtual page number incrementing will be initiated subsequently. At this time, the request subunit 243 generates a positive speculative prefetch request, which is used to obtain the second page table entry corresponding to the virtual page number after the current second virtual page number. When the negative confidence counter value exceeds the second preset threshold, it indicates that the streaming access mode of the device and process combination has stably exhibited negative streaming characteristics, and there is a high probability that a translation request for virtual page number decrementing will be initiated subsequently. At this time, the request subunit 243 generates a negative speculative prefetch request, which is used to obtain the second page table entry corresponding to the virtual page number before the current second virtual page number. The first preset threshold is less than the first saturation value, and the second preset threshold is less than the second saturation value. The first and second preset thresholds are values ​​preset according to the actual application scenario (such as device access characteristics, system performance requirements, etc.). The values ​​of the two can be configured to be the same or different to flexibly adapt to the pattern judgment accuracy requirements under different streaming access scenarios. If the positive confidence counter is not greater than the first preset threshold and the negative confidence counter is not greater than the second preset threshold, the request subunit 243 will not generate any speculative prefetch requests.

[0066] Taking the forward streaming access mode as an example, the first virtual page number equals the second virtual page number plus one. When the forward confidence counter is less than the first preset threshold, it is a confidence accumulation process, i.e., a training process for the prefetch operation. The request subunit 243 does not generate any speculative prefetch requests, but only updates the count value of the forward confidence counter and the virtual page number stored in the virtual page number field. When the forward confidence counter is greater than the first preset threshold but less than the first saturation value, it indicates that the streaming access has reached a stable access mode. At this time, the request subunit 243 initiates a forward prefetch request and updates the count value of the forward confidence counter and the virtual page number stored in the virtual page number field. When the forward confidence counter equals the first saturation value, the request subunit 243 initiates a forward prefetch request, and the virtual page number stored in the virtual page number field is updated, but the count value of the forward confidence counter is no longer updated. That is, the first saturation value is the upper limit of the forward confidence counter.

[0067] The purpose of setting the first saturation value is twofold. First, when the positive confidence counter exceeds the first preset threshold, the streaming access has reached a stable access pattern. Continuing to increment the counter will not improve the accuracy of prefetch judgment. Therefore, stopping the increment when the counter equals the first saturation value avoids invalid counting, optimizes resource consumption, prevents counter overflow, and ensures hardware logic reliability. Second, in real-world scenarios, even stable streaming access may experience occasional non-streaming mode interference. If occasional interference causes the counter to fall below the first preset threshold, the request subunit 243 will mistakenly stop prefetching, resulting in efficiency loss. Setting the saturation value prevents the counter from easily falling below the first preset threshold under occasional interference, ensuring the continuity of the forward prefetching process. The purpose of setting the second saturation value is similar to the first saturation value, used to adapt to the logical constraints of the reverse confidence counter and the scenario requirements of reverse streaming access. The difference between the first saturation value and the first preset threshold, and the difference between the second saturation value and the second preset threshold, can be set according to the actual application scenario to adapt to the pattern judgment accuracy and anti-interference capability requirements under different scenarios. For example, in scenarios with more interference, the difference can be increased to improve anti-interference capability.

[0068] In this embodiment, generating entry indexes using a hash algorithm effectively reduces the probability of conflicts between streaming access streams of different devices and processes in multi-stream concurrent scenarios, improving the accuracy of tracking the state of each access stream. Furthermore, once the prefetch unit 24 completes the training and warm-up of the target streaming access pattern—that is, after stabilizing the identification of the streaming access pattern through the quantization and accumulation of forward / reverse confidence counters—it can pre-cache the page table entries corresponding to the predicted translation requests in the second translation back buffer. For continuous memory block-level streaming access, regardless of whether the access range is limited to the same memory block or spans different memory blocks, the corresponding page table entries have a very high probability of being directly hit in the first or second translation back buffer. This minimizes high-latency main memory page table traversal operations, thereby improving the address translation efficiency and overall system throughput when multiple streaming devices work together.

[0069] In one possible implementation, after the index subunit 242 indexes the table entry corresponding to the first translation request according to the hash value, if the first virtual page number is not equal to the second virtual page number plus or minus one, then the count value of the forward confidence counter and the count value of the reverse confidence counter are obtained. If the count value of the forward confidence counter and / or the count value of the reverse confidence counter are not 0, then the count value of the forward confidence counter is decremented by one, and the count value of the reverse confidence counter is also decremented by one. If the count value of the forward confidence counter and the count value of the reverse confidence counter are both 0, then the second virtual page number stored in the virtual page number field is updated to the first virtual page number.

[0070] After index subunit 241 locates the target entry corresponding to the translation request (i.e., the first translation request) issued by the current device and process combination based on the hash value, update subunit 242 compares the numerical relationship between the first virtual page number and the second virtual page number. If the first virtual page number is neither equal to the second virtual page number plus one nor equal to the second virtual page number minus one, it indicates that the virtual page number corresponding to the current translation request has no forward or reverse continuous relationship with the virtual page number stored in the virtual page number field. Update subunit 242 obtains the current count values ​​of the forward confidence counter and the reverse confidence counter in the entry. If the count value of the forward confidence counter is not 0, and / or the count value of the reverse confidence counter is not 0, then the count value of the forward confidence counter is decremented by one, and the count value of the reverse confidence counter is decremented by one (if the count value is 0, it remains unchanged), in order to weaken the credibility of the previously accumulated forward or reverse old streaming access trend. Furthermore, the second virtual page number stored in the virtual page number field is not updated at this time to ensure that the current streaming training benchmark is not easily replaced and to avoid irrelevant requests interfering with the training process of the valid stream. If both the forward confidence counter and the reverse confidence counter are 0, it indicates that the original virtual page number of this entry has deviated from the expected streaming mode and needs to be replaced with the virtual page number of the new request to restart the training process of the new streaming mode. At this time, the second virtual page number stored in the virtual page number field is updated to the first virtual page number as the training benchmark for the new access stream.

[0071] Understandably, based on the preset differences between the first saturation value and the first preset threshold, and between the second saturation value and the second preset threshold, occasional discontinuous access will only cause the counter to decrease once, preventing the count value from easily falling below the corresponding preset threshold. This avoids accidentally stopping the stable prefetching process. Furthermore, since the virtual page number of the table entry is not replaced, it will not disrupt the comparison of virtual page numbers for subsequent consecutive cross-page requests, preventing a single discontinuous access from interrupting the streaming mode that is still in training or has been stabilized. Only when multiple discontinuous accesses occur subsequently, i.e., not occasional interference but a real switch in the streaming access mode, will the two confidence counters continuously decrease until the count value falls below the corresponding preset threshold. At this time, the request subunit 243 stops the corresponding speculative prefetching request and enters a new prefetching training process, achieving flexible adaptation to access mode switching.

[0072] It should be noted that, in an ideal scenario, an unlimited number of entries can be configured, allowing each device and process combination to have its own independent entry, thus avoiding pattern interference. However, in real-world scenarios, due to hardware storage resource constraints, the number of entries is limited, which may lead to different devices and process combinations repeatedly indexing the same entry through hash mapping (i.e., hash collisions). In this case, by decrementing the counters as described above, the historical confidence data of the old pattern will be gradually cleared from the entry. Only when both counters reach zero can the virtual page number field be updated, thereby safely reusing the entry resources, re-adapting to the access characteristics of new device and process combinations, supporting the training and confidence accumulation of new patterns within the same entry, achieving efficient reuse of entry resources, and avoiding mutual interference between different patterns.

[0073] Based on the above implementation, after system initialization, the initial value of the virtual page number field is 0, and the count values ​​of both the forward confidence counter and the reverse confidence counter are 0. For the first translation request of the target table entry, it is not necessary to explicitly identify whether the request is the first request; it is only necessary to perform the virtual page number comparison and corresponding operation according to the aforementioned normal update logic. Specifically, if the virtual page number of the first request is not equal to 1, that is, the virtual page number corresponding to the translation request is not equal to the virtual page number stored in the virtual page number field +1 / -1, since the forward confidence counter and the reverse confidence counter of the initial state of the table entry are both 0, the update subunit 242 directly updates the virtual page number field to the virtual page number of the first request. If the virtual page number of the first request is equal to 1, that is, the initial value of the virtual page number field 0 and the virtual page number 1 of the first request satisfy the condition that "the virtual page number corresponding to the translation request is equal to the virtual page number stored in the virtual page number field +1", then the update logic of incrementing the forward confidence counter and decrementing the reverse confidence counter is triggered, thereby starting the training of the forward streaming access mode. Based on this, regardless of whether the virtual page number requested in the first request satisfies the continuity condition with the initial value of 0, its processing conforms to the conventional judgment logic of the update subunit 242. That is, it compares whether the first virtual page number and the second virtual page number stored in the table satisfy a forward or reverse increment relationship, and performs the corresponding operation based on the counter state. Through this design, the processing logic of the first request can automatically adapt to the conventional process without explicitly identifying the first request, thereby achieving the uniformity and simplicity of the design.

[0074] In this embodiment, by adjusting the counter decrement and updating the virtual page number baseline conditions in discontinuous access scenarios, the reliability of outdated streaming access trends can be accurately weakened, avoiding invalid speculative prefetching from occupying system resources. Furthermore, by relying on the difference between the saturation value and the preset threshold, the interference of occasional discontinuous access can be resisted, ensuring that the prefetching process corresponding to stable streaming access is not interrupted by mistake, thereby improving the continuity and reliability of prefetching, and thus improving the prefetching accuracy of address translation, the efficiency of system resource utilization, and the overall throughput performance of multi-device collaborative work.

[0075] In one possible implementation, a forward speculative prefetch request is used to retrieve a second page table entry where the corresponding virtual page number is greater than the virtual page number stored in the virtual page number field, and the difference between the corresponding virtual page number and the virtual page number stored in the virtual page number field is equal to the first page distance. A reverse speculative prefetch request is used to retrieve a second page table entry where the corresponding virtual page number is less than the virtual page number stored in the virtual page number field, and the difference between the corresponding virtual page number and the virtual page number stored in the virtual page number field is equal to the second page distance.

[0076] When the count value of the positive confidence counter exceeds the first preset threshold, the request subunit 243 generates a positive speculative prefetch request. The positive speculative prefetch request is used to obtain a second page table entry, wherein the virtual page number corresponding to the second page table entry is greater than the virtual page number corresponding to the translation request of the device and process combination that triggered the prefetch logic (i.e., the virtual page number stored in the virtual page number field), and the difference between the two is equal to the first page distance. In other words, the positive prefetch request is used to obtain the page table entry corresponding to the virtual page number after the virtual page number of the current translation request, and at a distance from the first page distance.

[0077] The configuration of the first page distance can be implemented through a dedicated register. The configuration logic is determined by the dwell time of the device and process combination in a single memory block and / or the time required for page table traversal. The dwell time of the device and process combination in a single memory block is the page consumption rate. For example, in a 4K page scenario, the time taken for the device to complete all operations on that 4K page from the start of access is determined by the device's access granularity, streaming access span, and data access frequency. Understandably, in high-concurrency access scenarios with multiple streaming devices, if the device's access granularity to the same memory block is fine, the access frequency is high, the access span is large, or the page consumption rate is fast while page table traversal is time-consuming, its dwell time in that memory block will be short. This may cause the translation request to advance to subsequent memory blocks, but the prefetch operation initiated with a smaller prefetch step size for subsequent memory blocks has not yet been completed. This causes the prefetch result to lag behind the access stream speed, leading to a translation request triggering a miss in the second translation back buffer and a query of the main memory page table. Based on this, the first page distance is used to set the prefetch step size to adapt to the forward streaming access rhythm, ensuring that the prefetched second page table entry has completed page table traversal lookup and has been cached in the second translation back buffer before the corresponding translation request arrives. For example, for devices and processes with extremely high access frequency, short dwell time in a single block, and / or fast page consumption but long page table traversal time, the first page distance can be set to 2 or 3, directly prefetching the page table entries of the next 2 or 3 memory blocks. For combinations with a slow access rhythm, long dwell time in a single block, and / or page consumption speed matching page table traversal time, the first page distance can be set to 1, prefetching the page table entry of the next adjacent memory block to ensure the effectiveness of forward prefetching.

[0078] When the count value of the reverse confidence counter exceeds the second preset threshold, request subunit 243 generates a reverse speculative prefetch request. The reverse speculative prefetch request is used to obtain a second page table entry, wherein the virtual page number corresponding to the second page table entry is less than the virtual page number corresponding to the translation request of the device and process combination that triggered the prefetch logic (i.e., the virtual page number stored in the virtual page number field), and the difference between the two is equal to the second page distance. In other words, the reverse prefetch request is used to obtain the page table entry corresponding to a virtual page number that is two pages apart from the virtual page number of the current translation request.

[0079] The configuration logic for the second page distance is the same as that for the first page distance, and it is also implemented independently through a dedicated register. The configuration logic is determined by the duration the device and process combination spends in a single memory block and / or the time required to traverse the page table. The second page distance is used to set the prefetch step size to adapt to the reverse streaming access rhythm. The second page distance and the first page distance can be configured independently according to the access characteristics of different device and process combinations; their values ​​can be the same or different.

[0080] For example, the forward speculative prefetch request initiated by request subunit 243 is configured to retrieve the second page table entry corresponding to the Nth new virtual page before the device-process combination accesses the Nth new virtual page, and store the second page table entry in the second translation back buffer, where N is the value of the first page distance. When the count value of the forward confidence counter is greater than the first preset threshold, the first cross-virtual page translation request that was not hit in the first translation back buffer is triggered (assuming the corresponding virtual page number is M, where M is a positive integer), which will trigger request subunit 243 to initiate the first forward speculative prefetch request to retrieve the page table entry corresponding to the virtual page with virtual page number M+N. The second cross-virtual page translation request (corresponding to virtual page number M+1) will trigger the request subunit 243 to initiate a second speculative prefetch request to obtain the page table entry corresponding to the virtual page with virtual page number M+N+1. In this manner, the request subunit 243 will initiate speculative prefetch requests for the page table entries corresponding to the virtual pages with virtual page numbers M+N+2, M+N+3, etc. in the future, according to the triggering order of the cross-virtual page translation requests initiated by the device-process combination.

[0081] When the device-process combination actually accesses the virtual page with virtual page number M+N, its corresponding cross-virtual page translation request will miss the first translation back buffer, thus triggering request subunit 243 to initiate a speculative prefetch request for the virtual page with virtual page number M+2N. Since the prefetch result is only stored in the second translation back buffer, each cross-virtual page translation request will trigger a miss in the first translation back buffer. This miss request can be received by request subunit 243 to trigger the next speculative prefetch request. Simultaneously, since request subunit 243 has pre-stored the page table entry corresponding to the virtual page with virtual page number M+N in the second translation back buffer, the translation request will hit the second translation back buffer to obtain the translation result. At this time, the translation result corresponding to the virtual page is cached in the first translation back buffer so that subsequent translation requests for the same memory block of the virtual page can hit the first translation back buffer to obtain the translation result. Based on this, after the request subunit 243 has been trained, each cross-virtual page translation request will result in a first translation backup buffer miss, and then a corresponding page table entry will be hit in the second translation backup buffer. At the same time, the request subunit 243 will be triggered to initiate a regular speculative prefetch request for the subsequent target virtual page according to the preset page distance.

[0082] In this embodiment, the prefetch step size of forward speculative prefetching is controlled by a configurable first page distance, and the prefetch step size of reverse speculative prefetching is controlled by a second page distance. This allows the forward and reverse prefetching operations to dynamically match the access rhythm of different devices and processes, ensuring that the prefetched second page table entries are cached in the second translation backup buffer before the corresponding translation request arrives. This reduces access latency caused by page table traversal and main memory lookup, thereby reducing the performance overhead of address translation in high-concurrency scenarios with multiple streaming devices.

[0083] Figure 5 This is a flowchart of an embodiment of an accelerated virtual address translation method, which can be executed by the accelerator 1222 in the above embodiment. Figure 5 As shown, this accelerated virtual address translation method includes the following steps:

[0084] Step 501: Receive the first translation request and the second translation request in sequence. Both the first translation request and the second translation request are virtual address translation requests. The virtual page numbers corresponding to the first translation request and the second translation request are recorded in the first page table entry corresponding to the same memory block. The first page table entry is used to record the mapping relationship between the virtual page number and the physical page number of the memory block.

[0085] Step 502: Query whether the first page entry exists in the first translation backup buffer. If the first page entry does not exist in the first translation backup buffer, obtain the first page entry from outside the first translation backup buffer, determine the entry corresponding to the first translation request, update the count value of the confidence counter stored in the entry, and after the updated count value meets the preset condition, initiate a speculative prefetch request to obtain the second page entry through the speculative prefetch request and store the second page entry in the second translation backup buffer.

[0086] Step 503: Associate the second translation request with the first translation request, and after waiting to obtain the first page table entry, obtain the translation results of the first translation request and the second translation request from the first page table entry.

[0087] In this embodiment, in a multi-request concurrent scenario, when multiple access requests for the same page table entry fail to hit in the first translation back buffer, by identifying and associating access requests for the same page table entry, on the one hand, multiple requests dependent on the same page table entry can reuse the page table entry retrieval result triggered by the first request, simplifying multiple redundant page table traversal operations for that page table entry into a single retrieval operation. On the other hand, it enables the prefetching process to only receive cross-page requests in streaming access, providing clean data for prefetching training and avoiding erroneous prefetching operations caused by misjudging a same-page miss request as a cross-page access, thus ensuring the accuracy of prefetching training and prefetching operations. Therefore, it can optimize the address translation efficiency within the same virtual page, shorten the average processing latency of streaming translation requests, and improve the real-time response performance of streaming access. It can also improve the address translation performance in cross-page scenarios through accurate prefetching, comprehensively accelerating the address translation efficiency of streaming access devices within the same virtual page and in cross-page scenarios, thereby improving the stability and throughput of the system under high-concurrency load scenarios. Compared with existing technologies, this application effectively avoids repeated querying and retrieval operations on the same page table entry by associating concurrent translation requests with the same page table entry. At the same time, it solves the misjudgment problem in the prefetch process, significantly reduces the performance overhead caused by frequent page table traversal, and achieves address translation acceleration in all scenarios.

[0088] It should be noted that the details of the accelerated virtual address translation method have been described in detail in the accelerator 1222 part of the above embodiment with reference to the structural diagram. For the specific process, please refer to the description in the aforementioned accelerator 1222 embodiment, and will not be repeated here.

[0089] This application also provides a computer-readable storage medium storing instructions for causing a machine to execute the accelerated virtual address translation method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0090] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of this application.

[0091] Storage media embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0092] This application also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0093] In addressing the low address translation efficiency in streaming access scenarios, this application's embodiments utilize a deduplication unit within the accelerator to identify and associate consecutive translation requests targeting the same memory block. This allows multiple requests dependent on page table entries corresponding to the same memory block to reuse the page table entry triggered by the first request, simplifying redundant page table traversal operations into a single fetch and avoiding performance overhead from repeated queries. Furthermore, the deduplication unit filters out a large number of translation requests targeting the same memory block, allowing only cross-page requests in streaming access to enter the prefetch process. This prevents same-page miss requests from interfering with the prefetch access pattern recognition and training process, providing clean data for prefetch training and ensuring the accuracy of prefetch training and prefetch operations. This solution, relying on the accelerator's deduplication mechanism and prefetch collaborative design, optimizes address translation efficiency within the same virtual page and improves address translation performance in cross-page scenarios through precise prefetching, comprehensively accelerating the address translation efficiency of streaming access devices both within the same virtual page and across page scenarios. Therefore, in scenarios with high concurrency access from multiple streaming devices, computing devices can significantly shorten the average address translation latency, improve the real-time response performance of streaming access, effectively reduce the performance loss caused by frequent page table traversal, and thus enhance the stability and throughput of the system under high load. It is suitable for a variety of computing devices and has broad application value.

[0094] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0095] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0096] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0097] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. An accelerator, characterized in that, include: The system comprises a receiving unit, a query unit, a deduplication unit, and a prefetching unit. The receiving unit is configured to receive a first translation request and a second translation request in sequence. Both the first translation request and the second translation request are virtual address translation requests, and the virtual page numbers corresponding to the first translation request and the second translation request are recorded in the first page table entry corresponding to the same memory block. The first page table entry is used to record the mapping relationship between the virtual page number and the physical page number of the memory block. The query unit is used to query whether the first page table entry exists in the first translation backup buffer. If the first page table entry does not exist in the first translation backup buffer, the first page table entry is obtained from outside the first translation backup buffer, and the first translation request is sent to the prefetch unit. The first translation backup buffer is a translation backup buffer of the first-level cache. The deduplication unit is used to associate the second translation request with the first translation request, and after the query unit obtains the first page table entry, it obtains the translation results of the first translation request and the second translation request from the first page table entry; The prefetch unit is configured to, upon receiving the first translation request, determine the entry corresponding to the first translation request, update the count value of the confidence counter stored in the entry, and, after the updated count value meets a preset condition, initiate a speculative prefetch request to obtain the second page entry through the speculative prefetch request, and store the second page entry in a second translation backup buffer. The second translation backup buffer is a translation backup buffer of a level 2 cache. The second page entry includes the virtual page number of the predicted translation request. The predicted translation request is a virtual address translation request that is predicted to be received by the receiving unit after the first translation request, and whose corresponding virtual page number is different from the virtual page number corresponding to the first translation request.

2. The accelerator according to claim 1, characterized in that, The query unit is configured to, after determining that the first page table entry does not exist in the first translation backup buffer, query whether the first page table entry exists in the second translation backup buffer; if the first page table entry exists in the second translation backup buffer, retrieve the first page table entry from the second translation backup buffer; if the first page table entry does not exist in the second translation backup buffer, query the page table to retrieve the first page table entry.

3. The accelerator according to claim 1, characterized in that, The query unit is used to retrieve the translation results of the first translation request and the second translation request from the first page table entry stored in the first translation backup buffer when the first page table entry exists in the first translation backup buffer.

4. The accelerator according to claim 1, characterized in that, The prefetching unit includes: The index subunit is used to calculate a hash value based on the device and process corresponding to the first translation request, and to index the table entry corresponding to the first translation request based on the hash value. The update subunit is configured to, after the index subunit indexes the table entry corresponding to the first translation request according to the hash value, compare the first virtual page number corresponding to the first translation request with the second virtual page number stored in the virtual page number field of the table entry. If the first virtual page number is equal to the second virtual page number plus one, and the count value of the positive confidence counter included in the table entry is less than the first saturation value, then the count value of the positive confidence counter is incremented by one, the count value of the negative confidence counter included in the table entry is decremented by one, and the second virtual page number stored in the virtual page number field is updated to the first virtual page number. If the first virtual page number is equal to the second virtual page number plus one, and the count value of the positive confidence counter is less than the first saturation value, then the count value of the positive confidence counter is incremented by one, the count value of the negative confidence counter is decremented by one, and the second virtual page number stored in the virtual page number field is updated to the first virtual page number. If the value is equal to the first saturation value, then the second virtual page number stored in the virtual page number field is updated to the first virtual page number. If the first virtual page number is equal to the second virtual page number minus one, and the count value of the reverse confidence counter is less than the second saturation value, then the count value of the reverse confidence counter is incremented by one, and the count value of the forward confidence counter is decremented by one. The second virtual page number stored in the virtual page number field is updated to the first virtual page number. If the first virtual page number is equal to the second virtual page number minus one, and the count value of the reverse confidence counter is equal to the second saturation value, then the second virtual page number stored in the virtual page number field is updated to the first virtual page number. The request subunit is configured to initiate a forward speculative prefetch request after the count value of the forward confidence counter is greater than a first preset threshold, and to initiate a reverse speculative prefetch request after the count value of the reverse confidence counter is greater than a second preset threshold, wherein the first preset threshold is less than the first saturation value and the second preset threshold is less than the second saturation value.

5. The accelerator according to claim 4, characterized in that, The update subunit is configured to, after the index subunit indexes the table entry corresponding to the first translation request according to the hash value, if the first virtual page number is not equal to the second virtual page number plus or minus one, obtain the count value of the positive confidence counter and the count value of the negative confidence counter; if the count value of the positive confidence counter and / or the count value of the negative confidence counter are not 0, decrement the count value of the positive confidence counter and the count value of the negative confidence counter by one; if the count value of the positive confidence counter and the count value of the negative confidence counter are both 0, update the second virtual page number stored in the virtual page number field to the first virtual page number.

6. The accelerator according to claim 4, characterized in that, The positive speculative prefetch request is used to obtain the second page table entry whose corresponding virtual page number is greater than the virtual page number stored in the virtual page number field, and whose difference between the corresponding virtual page number and the virtual page number stored in the virtual page number field is equal to the first page distance. The reverse speculative prefetch request is used to obtain the second page table entry whose corresponding virtual page number is less than the virtual page number stored in the virtual page number field, and whose difference between the corresponding virtual page number and the virtual page number stored in the virtual page number field is equal to the second page distance.

7. An input / output memory management unit, characterized in that, include: The accelerator as described in any one of claims 1-6.

8. A system-on-a-chip, characterized in that, include: The input / output memory management unit as described in claim 7.

9. A computing device, characterized in that, include: The system-on-a-chip as described in claim 8.

10. A method for accelerating virtual address translation, characterized in that, include: The system receives a first translation request and a second translation request in sequence. Both the first translation request and the second translation request are virtual address translation requests. The virtual page numbers corresponding to the first translation request and the second translation request are recorded in the first page table entry corresponding to the same memory block. The first page table entry is used to record the mapping relationship between the virtual page number and the physical page number of the memory block. The system checks whether the first page table entry exists in the first translation back buffer. If the first page table entry does not exist in the first translation back buffer, the first page table entry is retrieved from outside the first translation back buffer, and the table entry corresponding to the first translation request is determined. The count value of the confidence counter stored in the table entry is updated. After the updated count value meets a preset condition, a speculative prefetch request is initiated to retrieve the second page table entry through the speculative prefetch request, and the second page table entry is stored in the second translation back buffer. The first translation back buffer is a translation back buffer of the first-level cache, and the second translation back buffer is a translation back buffer of the second-level cache. The second page table entry includes the virtual page number of the predicted translation request. The predicted translation request is a virtual address translation request that is predicted to be received after the first translation request and whose corresponding virtual page number is different from the virtual page number corresponding to the first translation request. Associate the second translation request with the first translation request, and after waiting to obtain the first page table entry, retrieve the translation results of the first translation request and the second translation request from the first page table entry.

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