Vector access method, device, apparatus and storage medium

Abstract

The application discloses a vector memory access method and device, equipment and a storage medium, and relates to the technical field of computers. The method of the receiving end comprises the following steps: receiving a memory access request; translating the memory access addresses in the memory access request to obtain a translation result of each memory access address; judging whether the memory access request hits according to the translation result; if the memory access request hits, performing a read or write operation on the data in the storage unit group corresponding to the current memory access request according to the translation result corresponding to the current memory access request. The technical scheme of the embodiment of the application realizes single memory access of multiple memory access addresses, and greatly improves the execution efficiency of the memory access request.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a vector memory access method, device, equipment and storage medium. BACKGROUND

[0002] The RISC-V architecture has the characteristics of simplicity, open source and scalability. The VLIW (Very Long Instruction Word) structure can increase the parallelism of instructions and improve the performance of the RISC-V processor without increasing the hardware complexity.

[0003] At present, the vector memory access instructions of the RISC-V can be divided into three addressing forms: the first is a standard step addressing mode, which starts from a base address and continuously increases the address according to the data size. The second is a fixed step addressing mode, which starts from a base address and increases the address according to a given step. The third is an index addressing mode, which starts from a base address and adds the offset address corresponding to each subsequent address to obtain the destination address.

[0004] However, although the VLIW structure improves the parallelism of the instructions of the RISC-V processor, AI computing has a higher demand for data parallelism, and the data memory access parallelism still needs to be improved. SUMMARY

[0005] The present application provides a vector memory access method, device, equipment and storage medium to solve the problem of poor data memory access parallelism under the RISC-V architecture.

[0006] In a first aspect, the present application provides a vector memory access method applied to a receiving end of a memory access request, comprising:

[0007] receiving a memory access request, wherein each memory access request includes a plurality of different memory access addresses;

[0008] translating the memory access addresses in the memory access request to obtain a translation result of each memory access address;

[0009] determining whether the memory access request hits according to the translation result, and if so, performing a read or write operation on the data in a storage unit group corresponding to the current memory access request according to the translation result corresponding to the current memory access request for each memory access request, wherein the number of storage units in each storage unit group is a plurality, and the receiving end of the memory access request includes a plurality of storage unit groups.

[0010] In a second aspect, the present application provides a vector memory access method applied to a sending end of a memory access request, comprising:

[0011] generating an initial access request, wherein the initial access request includes a plurality of access addresses;

[0012] processing a first access request and a second access request in the initial access request by using different preset channels to obtain corresponding target access requests, wherein the probability of the second access request crossing a cache line access is greater than that of the first access request;

[0013] sending the target access requests to a receiving end of the access request, wherein each target access request accesses data in a same cache line, and the receiving end is determined by the vector access method of the first aspect, and the target access request is an access request in the vector access method of the first aspect.

[0014] In a third aspect, the present application provides a vector access device applied to a receiving end of an access request, comprising:

[0015] a request receiving module configured to receive access requests, wherein each access request includes a plurality of different access addresses;

[0016] a translation module configured to translate the access addresses in the access requests to obtain translation results of each access address;

[0017] an access module configured to determine whether the access requests hit according to the translation results, and if so, perform read or write operations on data in a storage unit group corresponding to the current access request according to the translation result corresponding to the current access request for each access request, wherein the number of storage units in each storage unit group is a plurality, and the receiving end of the access request includes a plurality of storage unit groups.

[0018] In a fourth aspect, the present application provides a vector access device applied to a sending end of an access request, comprising:

[0019] a request generating module configured to generate an initial access request, wherein the initial access request includes a plurality of access addresses;

[0020] a processing module configured to process a first access request and a second access request in the initial access request by using different preset channels to obtain corresponding target access requests, wherein the probability of the second access request crossing a cache line access is greater than that of the first access request;

[0021] The sending module is configured to send the target memory access request to a receiving end of the memory access request, wherein each target memory access request accesses data in a same cache line, and the receiving end is determined by the vector memory access method of the first aspect, and the target memory access request is the memory access request in the vector memory access method of the first aspect.

[0022] In a fifth aspect, the present application provides an electronic device, which comprises:

[0023] at least one processor;

[0024] and a memory connected to the at least one processor in communication;

[0025] wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the vector memory access method of the first aspect and / or the vector memory access method of the second aspect.

[0026] In a sixth aspect, the present application provides a computer readable storage medium storing computer instructions for enabling a processor to implement the vector memory access method of the first aspect and / or the vector memory access method of the second aspect when executed by the processor.

[0027] The vector memory access scheme provided by the present application is applied to the receiving end and the sending end of a memory access request. After receiving the vector memory access request, the receiving end can access the corresponding storage unit according to the memory access address in the memory access request and return the corresponding data or write the corresponding data. After receiving the scalar memory access request, the receiving end can return the cache line of the memory access address. The receiving end realizes single memory access to multiple memory access addresses, greatly improving the execution efficiency of the memory access request. Because there may be multiple memory access addresses accessing different cache lines, the sending end can process such requests to generate a memory access request containing multiple memory access addresses and accessing the same cache line, realizing single request access to multiple memory access addresses, and greatly improving the execution efficiency of the memory access request.

[0028] It should be understood that the content described in this part is not intended to identify key or important features of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0030] Figure 1 is a flow chart of a vector access method according to an embodiment of the present application;

[0031] Figure 2 is a flow chart of a vector access method according to an embodiment of the present application;

[0032] Figure 3 is a flow chart of a vector access method according to an embodiment of the present application;

[0033] Figure 4 is a flow chart of a vector access method according to an embodiment of the present application;

[0034] Figure 5 is a structural schematic diagram of a sending end of an access request according to an embodiment of the present application;

[0035] Figure 6 is a structural schematic diagram of a vector access device according to an embodiment of the present application;

[0036] Figure 7 is a structural schematic diagram of a vector access device according to an embodiment of the present application;

[0037] Figure 8 is a structural schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein. In the description of the present application, "a plurality of" means two or more, unless otherwise specified. The association relationship of the associated objects described by "and / or" indicates that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after it. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] Embodiment one

[0041] Figure 1 A flowchart of a vector access method is provided for the first embodiment of the present application. The embodiment can be applicable to the case of accessing vector data, and is applied to the receiving end of the access request. The method can be executed by a vector access device, which can be realized in the form of hardware and / or software. The vector access device can be configured in an electronic device, which can be composed of two or more physical entities, or can be composed of one physical entity.

[0042] As Figure 1 shown, the vector access method provided by the first embodiment of the present application specifically includes the following steps:

[0043] S101, receiving an access request, wherein each of the access requests includes a plurality of different access addresses.

[0044] For example, each access request can include 8 different access addresses. The receiving end of the access request can receive multiple access requests simultaneously, and can process these access requests in parallel.

[0045] S102, translating the access addresses in the access request to obtain the translation result of each access address.

[0046] In the embodiment, the address translation group can be used to simultaneously translate the memory addresses in the memory access requests to obtain the translation results of each memory address. The number of translation units in the address translation group can be consistent with the number of memory addresses in the memory access requests. The translation result of the memory address includes a Tag field and a Set field.

[0047] In the embodiment, the translation result can be used to determine whether the memory access request hits. If the memory access request hits, the data in the memory cell group corresponding to the current memory access request can be read or written according to the translation result corresponding to the current memory access request. The number of memory cells in each memory cell group is multiple, and the receiving end of the memory access request includes multiple memory cell groups.

[0048] In the embodiment, the translation result can be used to determine whether the memory access request hits. If the memory access request hits, the data in the memory cell group corresponding to the current memory access request can be read or written according to the translation result corresponding to the current memory access request. The number of memory cells in each memory cell group is multiple, and the receiving end of the memory access request includes multiple memory cell groups.

[0049] For example, if a 256-bit cache line can be divided into 8 columns, 8 vector data are stored, and the number of memory cells in each memory cell group is 8.

[0050] The technical scheme of the embodiment can access the corresponding memory cell according to the memory address in the memory access request after receiving the vector memory access request, return the corresponding data or write the corresponding data, and return the cache line of the memory address after receiving the scalar memory access request. The scheme realizes single memory access of multiple memory addresses, and greatly improves the execution efficiency of the memory access request.

[0051] Embodiment two

[0052] Figure 2 The flowchart of the vector memory access method provided by the embodiment two of the application is based on the above-mentioned optional technical schemes applied to the receiving end of the memory access request, and further optimizes the specific way of accessing vector data.

[0053] Optionally, the method further includes the following steps: determining a starting memory address in each memory access request as a target memory address, and determining the translation result of the target memory address as a target translation result, wherein the target memory address is the starting address in each memory access request, and the starting memory address is the starting address of the cache line of the memory access; and determining whether the memory access request hits by using the target translation result.

[0054] Optionally, after judging whether the memory access request hits according to the translation result, the method further comprises: if not, sending a missing flag to a sending end of the memory access request to prompt that the memory access request sent by the sending end does not hit.

[0055] As shown in Figure 2 Embodiment two of the present application provides a vector memory access method, which specifically comprises the following steps:

[0056] S201, receiving a memory access request, wherein each memory access request comprises a plurality of different memory access addresses.

[0057] S202, translating the memory access addresses in the memory access request to obtain a translation result of each memory access address.

[0058] S203, determining a starting memory access address in each memory access request as a target memory access address, and determining a translation result of the target memory access address as a target translation result.

[0059] The target memory access address is the starting address in each memory access request, and the starting memory access address is the starting address of a cache line.

[0060] For example, if the memory access addresses included in each memory access request are 8 columns, specifically column 0, column 1, …, column 7. The memory cells accessed are also 8 columns. Each column of memory access addresses corresponds to a vector element (32 bits). The memory access addresses of each memory access request access the same cache line. Each column of memory access addresses corresponds to a translation unit in an address translation group. The address translation unit translates the received memory access address into a Tag field (tag field) and a Set field (group field). The starting memory access address in the memory access request is the column 0 memory access address, and the memory cell corresponding to the memory access address is the column 0 memory cell.

[0061] S204, determining whether the memory access request hits by using the target translation result, if yes, performing step S205, and if not, performing step S206.

[0062] S205, for each memory access request, performing read or write operation on data in a memory cell group corresponding to the current memory access request according to the translation result corresponding to the current memory access request, wherein the number of memory cells in each memory cell group is a plurality, and the receiving end of the memory access request comprises a plurality of memory cell groups.

[0063] S206, sending a missing flag to a sending end of the memory access request to prompt that the memory access request sent by the sending end does not hit.

[0064] Specifically, if a miss occurs, the receiving end can return a missing flag bit to the sending end in the same cycle as the access request to prompt the sending end that the access request sent by the sending end misses.

[0065] The vector access method provided by the embodiment of the present application can quickly determine whether an access request hits, is compatible with vector access and scalar access, realizes that a single vector access instruction can load or store multiple data at the same time, has greater advantages in AI computing scenarios, and also sends a prompt to the sending end of the access request in a timely manner after access failure.

[0066] Embodiment three

[0067] Figure 3 A flowchart of a vector access method is provided for the third embodiment of the present application. The present embodiment can be applied to the case of generating an access vector request. The method is applied to the sending end of an access request and can be executed by a vector access device. The vector access device can be realized in the form of hardware and / or software. The vector access device can be configured in an electronic device, which can be composed of two or more physical entities or one physical entity.

[0068] As shown in Figure 3 , the vector access method provided by the third embodiment of the present application specifically includes the following steps:

[0069] S301, generating an initial access request, wherein the initial access request includes multiple access addresses.

[0070] In the present embodiment, the request generation unit in the sending end can generate access addresses according to the addressing mode of the access request to obtain an initial access request. The sending end of the access request in the present embodiment can be the sending end in the above embodiments.

[0071] S302, processing a first access request and a second access request in the initial access request by using different preset channels to obtain corresponding target access requests, respectively, wherein the probability of the second access request crossing cache line access is greater than that of the first access request.

[0072] In the present embodiment, different preset channels can be set in the sending end of the access request, and the first access request and the second access request in the initial access request can be processed by using different preset channels to obtain target access requests. The second access request is a request that is prone to cross cache line access. The first access request is a request that is not prone to cross cache line access.

[0073] S303, sending the target access requests to the receiving end of the access request, wherein each target access request accesses data in the same cache line.

[0074] The receiving end is determined by the vector memory access method described in Embodiment 1 or 2 above, and the target memory access request is the memory access request in the vector memory access method described in Embodiment 1 or 2 above.

[0075] Specifically, the receiving end of the memory access request is the receiving end that applies the vector memory access method described in Embodiment 1 or 2 above.

[0076] The technical solution of this invention processes a single memory access request that accesses different cache lines, generating a memory access request that contains multiple memory access addresses and accesses the same cache line. This enables a single request to access multiple memory access addresses, greatly improving the execution efficiency of memory access requests.

[0077] Example 4

[0078] Figure 4 This is a flowchart of a vector memory access method provided in Embodiment 4 of the present invention. The technical solution of the present invention is further optimized based on the above-mentioned optional technical solutions applied to the sending end of the memory access request, and provides a specific method for generating a memory access vector request.

[0079] Optionally, the step of processing the first memory access request and the second memory access request in the initial memory access request using different preset channels to obtain corresponding target memory access requests includes: processing the first memory access request in the initial memory access request using a standard load channel and a standard storage channel to obtain a first target memory access request, wherein the first memory access request includes a scalar memory access request and a vector memory access request in standard step-size addressing mode; splitting the second memory access request in the initial memory access request into multiple elements using a vector-dedicated load channel, and integrating the elements to obtain a second target memory access request, wherein the second memory access request includes a vector memory access request in non-standard step-size addressing mode.

[0080] Optionally, the initial memory access request further includes a blocking flag, and the blocking flag value of the second memory access request is a first preset value; wherein, sending the target memory access request to the receiving end of the memory access request includes: when the blocking flag value of the second memory access request is a second preset value, sending the second target memory access request corresponding to the second memory access request to the receiving end of the memory access request, wherein the first preset value and the second preset value are different, and the change of the blocking flag value of the second memory access request is determined according to the memory access process of the channel for the first memory access request.

[0081] like Figure 4 As shown, the vector memory access method provided in Embodiment 4 of the present invention specifically includes the following steps:

[0082] S401, generating an initial memory access request, wherein the initial memory access request includes a plurality of memory access addresses and a blocking flag, and the blocking flag value of the second memory access request is a first preset value.

[0083] Specifically, since the non-standard step addressing mode vector memory access request occupies more resources, the request generation unit in the sending end will increase the blocking flag when generating the initial memory access request. The blocking flag is used to prevent the sending of the target memory access request corresponding to the non-standard step addressing mode vector memory access before the completion of the previous memory access request.

[0084] S402, processing the first memory access request in the initial memory access request by using a standard load channel and a standard store channel to obtain a first target memory access request, wherein the first memory access request includes a scalar memory access request and a standard step addressing mode vector memory access request.

[0085] S403, splitting the second memory access request in the initial memory access request into a plurality of elements by using a vector dedicated load channel, and integrating the elements to obtain a second target memory access request, wherein the second memory access request includes a non-standard step addressing mode vector memory access request.

[0086] Exemplarily, Figure 5 A structural schematic diagram of a sending end of a memory access request. As Figure 5As shown, the sending end can include a load-store queue 50 and a load queue 51, and the sending end specifically includes a register group 52, a request generation unit 53, a channel arbitration (unit) 54, a destination register number (determination unit) 55, a standard load channel 56, a standard store channel 57, a vector-specific load channel 58, a request arbitration (unit) 59, and a write-back arbitration (unit) 60. The channel arbitration is used to distribute the initial memory access request to the standard load channel, the standard store channel, or the vector-specific load channel according to the memory access type and the addressing mode. Among them, the scalar memory access request and the vector memory access request of the standard step addressing mode are distributed to the standard load channel and the standard store channel, and the vector memory access request of the non-standard step addressing mode is distributed to the vector-specific load channel. The address bit width and the data bit width of the standard load channel are widened, which is used to process the vector load request and the scalar load request of the standard step. The address bit width and the data bit width of the standard store channel are widened, which is used to process the vector store request and the scalar store request of the standard step. Since the memory access request of the fixed step addressing mode and the memory access request of the index addressing mode may cross the cache line during memory access, a vector-specific channel can be added to split the initial memory access request into elements, and the elements are integrated to obtain a second target memory access request containing memory access addresses accessing the same cache line. The write-back arbitration widens the data bit width to realize the arbitration of the write-back of the vector register. Among them, the load-store queue and the load queue of the sending end can be multiple. The number of the standard load channel, the standard store channel, and the vector-specific load channel can be multiple.

[0087] For example, the specific load channel includes a register group, a cache line and column arbitration, and a register. The register group is used to save the initial memory access request and the destination register number. The initial memory access request includes 1) the size of the accessed data, which can support three sizes of 8 bits, 16 bits, and 32 bits; 2) the memory access address, when the size of the accessed data is 8 bits, 32 memory access addresses can be included, when the size of the accessed data is 16 bits, 16 memory access addresses can be included, and when the size of the accessed data is 32 bits, 8 memory access addresses can be included; 3) the operation type, including read or write operation; 4) the stored data when the storage operation is performed, and the data bit width is 256 bits. Among them, the memory access addresses of different columns of the same cache line can be sent in the same memory access request. If the memory access request corresponding to the memory access address hits (i.e., the missing flag sent by the receiving end is received) after being sent, the placeholder in the corresponding position of the register is set to 0. The memory access request is only allowed to be sent when the blocking flag bit is 0.

[0088] S404, when the blocking flag bit value of the second memory access request is a second preset value, sending the second target memory access request corresponding to the second memory access request to the receiving end of the memory access request.

[0089] The first target access request and the second target access request are access requests in the vector access method in Embodiment 1 or Embodiment 2.

[0090] The first preset value and the second preset value are different, the change of the blocking flag value of the second access request is determined according to the access process of the first access request by the channel, and each target access request accesses data in a same cache line.

[0091] For example, the (initial) value of the blocking flag of the second access request can be 1, and the second target access request can be sent to the receiving end of the access request only when the value of the blocking flag of the second access request is 0. The value of the blocking flag of the second access request can be set to the second preset value after the access of the first access request is completed.

[0092] The vector access method provided in the embodiment of the application generates a blocking flag at the same time of generating an access application, avoids occupying more resources when the vector access request in the non-standard step addressing mode accesses, and ensures the efficiency of the scalar access instruction and the vector access instruction in the standard step addressing mode. By setting the standard load channel and the standard storage channel, the vector access in the standard step addressing mode is realized, the resource reuse of the scalar access and the vector access in the standard step addressing mode is realized, the hardware complexity is reduced, and the vector access in the non-standard step addressing mode in the RISC-V vector expansion is realized through the newly added vector dedicated load channel.

[0093] Embodiment five

[0094] Figure 6 A structure schematic diagram of a vector access device provided for the embodiment five of the application is shown in the figure. Figure 6 As shown in the figure, the device is applied to the receiving end of an access request, and specifically includes a request receiving module 601, a translation module 602 and an access module 603, wherein:

[0095] The request receiving module is used for receiving access requests, wherein each access request includes a plurality of different access addresses;

[0096] The translation module is used for translating the access addresses in the access requests to obtain translation results of each access address;

[0097] The access module is used for judging whether the access requests hit according to the translation results, and if the access requests hit, performing read or write operations on data in a storage unit group corresponding to the current access request according to the translation result corresponding to the current access request for each access request, wherein the number of storage units in each storage unit group is a plurality, and the receiving end of the access request includes a plurality of storage unit groups.

[0098] The vector access device provided by the embodiment of the present application can access corresponding storage units according to the access addresses in the access request after receiving the vector access request, and return corresponding data or write corresponding data, and the receiving end can return the cache line of the access address after receiving the scalar access request, so that the device realizes single access of multiple access addresses, and greatly improves the execution efficiency of the access request.

[0099] Optionally, the access module comprises:

[0100] The target translation result determination unit is configured to determine the starting access address in each of the access requests as a target access address, and determine the translation result of the target access address as a target translation result, wherein the target access address is the starting address in each of the access requests, and the starting access address is the starting address of the cache line of the access;

[0101] The hit determination unit is configured to determine whether the access request hits by using the target translation result.

[0102] Optionally, the device further comprises:

[0103] The missing flag module is configured to send a missing flag to the sending end of the access request to prompt that the access request sent by the sending end does not hit after determining that the access request does not hit according to the translation result.

[0104] The vector access device provided by the embodiment of the present application can execute the vector access method provided by any embodiment of the present application, and has the corresponding function modules and beneficial effects of the execution method.

[0105] Embodiment six

[0106] Figure 7 A structural schematic diagram of a vector access device provided for the embodiment six of the present application is shown in FIG. 7. Figure 7 As shown in the figure, the device is applied to the sending end of an access request, and specifically comprises a request generation module 701, a processing module 702 and a request sending module 703, wherein:

[0107] The request generation module is configured to generate an initial access request, wherein the initial access request comprises multiple access addresses;

[0108] The processing module is configured to process a first access request and a second access request in the initial access request by using different preset channels respectively to obtain corresponding target access requests respectively, wherein the probability of the second access request crossing the cache line access is greater than that of the first access request.

[0109] The request sending module is configured to send the target memory access request to a receiving end of the memory access request, wherein each target memory access request accesses data in a same cache line, the receiving end is determined by the vector memory access method in the first or second embodiment, and the target memory access request is a memory access request in the vector memory access method in the first or second embodiment.

[0110] The vector memory access device provided in the embodiment of the application can process requests for accessing different cache lines with multiple memory access addresses in the sending end, generate memory access requests containing multiple memory access addresses and accessing a same cache line, and thus achieve single request access to multiple memory access addresses, and greatly improve the execution efficiency of the memory access request.

[0111] Optionally, the processing module comprises:

[0112] The standard processing unit is configured to process a first memory access request in the initial memory access request by using a standard load channel and a standard storage channel to obtain a first target memory access request, wherein the first memory access request comprises a scalar memory access request and a vector memory access request in a standard step length addressing mode.

[0113] The special processing unit is configured to split a second memory access request in the initial memory access request into multiple elements by using a vector special load channel, and integrate the elements to obtain a second target memory access request, wherein the second memory access request comprises a vector memory access request in a non-standard step length addressing mode.

[0114] Optionally, the initial memory access request further comprises a blocking flag, and a blocking flag value of the second memory access request is a first preset value; wherein the request sending module is specifically configured to send a second target memory access request corresponding to the second memory access request to the receiving end of the memory access request when the blocking flag value of the second memory access request is a second preset value, wherein the first preset value and the second preset value are different, and the change of the blocking flag value of the second memory access request is determined according to the memory access process of the channel to the first memory access request.

[0115] The vector memory access device provided in the embodiment of the application can execute the vector memory access method provided in any embodiment of the application, and has the corresponding function modules and beneficial effects of the execution method.

[0116] Embodiment seven

[0117] Figure 8A structural diagram of an electronic device 80 that can be used to implement embodiments of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices (e.g., headsets, glasses, watches, etc.), and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit the implementations of the present application described and / or claimed in this document.

[0118] As shown in Figure 8 The electronic device 80 includes at least one processor 81 and memory, such as read-only memory (ROM) 82, random access memory (RAM) 83, etc., communicatively connected to the at least one processor 81, where the memory stores computer programs executable by the at least one processor. The processor 81 can perform various appropriate actions and processes according to the computer programs stored in the read-only memory (ROM) 82 or loaded from the storage unit 88 into the random access memory (RAM) 83. Various programs and data required for the operation of the electronic device 80 can also be stored in the RAM 83. The processor 81, the ROM 82, and the RAM 83 are connected to each other through a bus 84. An input / output (I / O) interface 85 is also connected to the bus 84.

[0119] Various components in the electronic device 80 are connected to the I / O interface 85, including an input unit 86, such as a keyboard, a mouse, etc., an output unit 87, such as various types of displays, speakers, etc., a storage unit 88, such as a magnetic disk, an optical disk, etc., and a communication unit 89, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 89 allows the electronic device 80 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0120] The processor 81 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 81 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 81 performs various methods and processes described above, such as the vector memory access method applied to the receiving end of a memory access request and / or the vector memory access method applied to the sending end of a memory access request.

[0121] In some embodiments, the vector access method can be implemented as a computer program tangibly embodied in a computer readable storage medium, e.g., storage unit 88. In some embodiments, portions of the computer program, or all of the computer program, can be loaded onto the electronic device 80 via, e.g., ROM 82 and / or communication unit 89. When the computer program is loaded onto RAM 83 and executed by processor 81, one or more of the steps of the vector access method described above can be performed. Alternatively, in other embodiments, processor 81 can be configured to perform the vector access method by any other suitable means, e.g., by way of firmware.

[0122] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a system on a chip, a complex programmable logic device (CPLD), a computer hardware, a firmware, a software, and / or a combination of them. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0123] Computer programs used to implement the methods of the application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program, when executed, implements the functions / acts specified in the flowcharts and / or block diagrams. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, or entirely on a remote machine or server.

[0124] The computer device provided above can be used to execute the vector access method provided by any of the embodiments above, and has the corresponding functions and advantages.

[0125] Embodiment Eight

[0126] In the context of the present application, the computer readable storage medium can be a tangible medium, the computer executable instructions of which, when executed by a computer processor, are used to perform a vector access method applied to a receiving end of a memory access request and / or a vector access method applied to a sending end of a memory access request.

[0127] The vector memory access method applied to a receiving end of a memory access request comprises:

[0128] receiving memory access requests, wherein each of the memory access requests comprises a plurality of different memory access addresses;

[0129] translating the memory access addresses in the memory access requests to obtain a translation result of each of the memory access addresses;

[0130] judging whether the memory access requests hit according to the translation result, and if so, performing a read or write operation on data in a memory cell group corresponding to a current memory access request according to the translation result corresponding to the current memory access request, wherein the number of memory cells in each of the memory cell groups is a plurality, and the receiving end of the memory access request comprises a plurality of memory cell groups.

[0131] The vector memory access method applied to a sending end of a memory access request comprises:

[0132] generating an initial memory access request, wherein the initial memory access request comprises a plurality of memory access addresses;

[0133] processing a first memory access request and a second memory access request in the initial memory access request by using different preset channels to obtain corresponding target memory access requests, wherein the probability of the second memory access request crossing a cache line memory access is greater than that of the first memory access request;

[0134] sending the target memory access requests to a receiving end of a memory access request, wherein each of the target memory access requests accesses data in a same cache line, the receiving end is determined by the vector memory access method in Embodiment 1 or 2, and the target memory access request is a memory access request in the vector memory access method in Embodiment 1 or 2.

[0135] In the context of the present application, a computer readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium can be a machine readable signal medium. More specific examples of the machine readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disc read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0136] The computer device provided in the above can be used to execute the vector access method provided in any of the above embodiments, and has the corresponding functions and advantages.

[0137] It is worth noting that the embodiments of the above vector access device include various units and modules only according to the logical division of functions, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of each functional unit are only for the convenience of mutual differentiation, and are not used to limit the protection scope of the present application.

[0138] Note that the above are only preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A vector access method applied to a receiving end of an access request, characterized in that, The method comprises the following steps: receiving access requests, wherein each of the access requests comprises a plurality of different access addresses, and the access addresses of each access request access the same cache line; simultaneously translating the access addresses in the access requests to obtain translation results of each of the access addresses; determining whether the access requests hit according to the translation results, and if so, performing read or write operations on data in a storage unit group corresponding to the current access request according to the translation result corresponding to the current access request for each of the access requests, wherein the number of storage units in each of the storage unit groups is a plurality, and the receiving end of the access request comprises a plurality of storage unit groups.

2. The method of claim 1, wherein, The method further comprises the following steps: determining a starting access address in each of the access requests as a target access address, and determining a translation result of the target access address as a target translation result, wherein the target access address is the starting address in each of the access requests, and the starting access address is the starting address of the accessed cache line; determining whether the access requests hit by using the target translation result.

3. The method according to claim 1 or 2, characterized in that, After the step of determining whether the access requests hit according to the translation results, the method further comprises the following steps: if not, sending a missing flag to the sending end of the access requests to prompt that the access requests sent by the sending end do not hit.

4. A vector access method applied to a sending end of an access request, characterized in that, The method comprises the following steps: generating an initial access request, wherein the initial access request comprises a plurality of access addresses; processing a first access request and a second access request in the initial access request by using different preset channels to obtain corresponding target access requests, wherein the probability of the second access request crossing the cache line is greater than that of the first access request; sending the target access requests to the receiving end of the access requests, wherein each of the target access requests accesses data in the same cache line, the receiving end is determined by the vector access method in any one of claims 1-3, and the target access request is the access request in the vector access method in any one of claims 1-3.

5. The method of claim 4, wherein, The method further comprises the following steps: processing the first access request in the initial access request by using a standard load channel and a standard storage channel to obtain a first target access request, wherein the first access request comprises a scalar access request and a vector access request in a standard step length addressing mode; splitting the second access request in the initial access request into a plurality of elements by using a vector dedicated load channel, and integrating the elements to obtain a second target access request, wherein the second access request comprises a vector access request in a non-standard step length addressing mode.

6. The method of claim 4, wherein, The initial access request further comprises a blocking flag bit, and the blocking flag bit value of the second access request is a first preset value; wherein the step of sending the target access requests to the receiving end of the access requests comprises the following steps: When the blocking flag value of the second memory access request is a second preset value, a second target memory access request corresponding to the second memory access request is sent to a receiving end of the memory access request, wherein the first preset value and the second preset value are different, and the change of the blocking flag value of the second memory access request is determined according to a memory access process of the first memory access request by a channel.

7. A vector access device, applied to a receiving end of an access request, characterized in that, The method comprises the following steps: The request receiving module is configured to receive memory access requests, wherein each of the memory access requests comprises a plurality of different memory access addresses, and the memory access addresses of each memory access request access a same cache line; The translation module is configured to simultaneously translate the memory access addresses in the memory access requests to obtain a translation result of each of the memory access addresses; The memory access module is configured to determine whether the memory access requests hit according to the translation results, and if so, perform a read or write operation on data in a storage unit group corresponding to a current memory access request according to a translation result corresponding to the current memory access request, wherein the number of storage units in each of the storage unit groups is a plurality, and the receiving end of the memory access request comprises a plurality of storage unit groups.

8. A vector access device, applied to a sending end of an access request, characterized in that, The method comprises the following steps: The request generating module is configured to generate initial memory access requests, wherein the initial memory access requests comprise a plurality of memory access addresses; The processing module is configured to process a first memory access request and a second memory access request in the initial memory access requests by using different preset channels to obtain corresponding target memory access requests, wherein the probability of the second memory access request crossing a cache line is greater than that of the first memory access request; The request sending module is configured to send the target memory access requests to a receiving end of the memory access requests, wherein each of the target memory access requests accesses data in a same cache line, the receiving end is determined by the vector memory access method in any one of claims 1-3, and the target memory access request is a memory access request in the vector memory access method in any one of claims 1-3.

9. An electronic device, comprising: The electronic device comprises: at least one processor; and a memory connected with the at least one processor in communication; wherein The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the vector memory access method in any one of claims 1-3 and / or the vector memory access method in any one of claims 4-6.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling the processor to implement the vector memory access method in any one of claims 1-3 and / or the vector memory access method in any one of claims 4-6 when executed.

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