High-speed DDR wiring structure optimization method and device based on silicon substrate
By optimizing the wiring structure of DDR interconnects, the signal integrity and power integrity issues in wafer-level chips were resolved, enabling high-performance, high-reliability, and low-cost high-speed DDR signal transmission.
Patent Information
- Application Number
- CN202511382302.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-25
- Publication Date
- 2026-01-06
AI Technical Summary
Existing technologies cannot meet the signal integrity and power integrity requirements for high-speed DDR signal transmission in wafer-level chips, especially in three-dimensional packaging structures with dense wiring and complex interconnect structures, where strong inter-line coupling crosstalk effects are severe.
By optimizing the routing structure of DDR interconnects, the initial routing structure is optimized using the characteristics of ground hole arrangement, parallel routing, and ground wire distribution. This includes adjusting DDR interconnects to avoid ground holes, non-parallel routing, segmented isolation of ground wires, and grounding multiple return ground wires. Iterative optimization is then performed using simulation tests and deep learning models.
It improves signal integrity and power integrity, meets the high-speed DDR signal quality and time delay requirements of dense wiring and complex interconnect structures in wafer-level chips, and achieves multiple goals of high performance, high reliability and low cost.
Smart Images
Figure CN121279239A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a method and apparatus for optimizing high-speed DDR wiring structure based on silicon substrate. Background Technology
[0002] In wafer-level chip interconnect architecture, the interposer wiring density is extremely high, and the package structure exhibits complex three-dimensional characteristics. In addition, with the continuous increase in the signal transmission rate of high-speed DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, hereinafter referred to as DDR), the strong inter-line coupling crosstalk effect will lead to serious signal integrity degradation problems. Therefore, it is necessary to optimize the design of DDR wiring structure.
[0003] In existing technologies, design software is generally used to automatically generate wiring structures, and then deep learning models are used to iteratively optimize the wiring structures.
[0004] However, current wiring structure optimization methods cannot meet signal integrity and power integrity requirements at the wafer-level chip level. Summary of the Invention
[0005] Therefore, it is necessary to provide a method and apparatus for optimizing high-speed DDR wiring structure based on silicon substrate that can meet the requirements of signal integrity and power integrity, in order to address the above-mentioned technical problems.
[0006] In a first aspect, this application provides a method for optimizing high-speed DDR wiring structures based on silicon substrates, including:
[0007] Obtain the initial routing structure corresponding to the target type of DDR interconnect. The target type is one of memory access control interconnect, data transmission interconnect, and coplanar waveguide interconnect.
[0008] The initial wiring structure is simulated and tested to obtain the initial signal integrity test results corresponding to the initial wiring structure.
[0009] If the initial signal integrity test results meet the preset optimization conditions, the initial wiring structure is optimized using preset quality impact features to obtain the target wiring structure corresponding to the DDR interconnect. The quality impact features include ground hole arrangement features, parallel trace features, and ground wire distribution features.
[0010] In one embodiment, the initial wiring structure is optimized using preset quality impact characteristics to obtain the target wiring structure corresponding to the DDR interconnect, including:
[0011] For the ground hole arrangement characteristics, adjust the DDR interconnects in the initial wiring structure so that the projection range of the DDR interconnects in the initial wiring structure avoids the ground holes;
[0012] For parallel routing features, adjust the DDR interconnects and ground lines in the initial routing structure to a non-parallel routing structure or a segmented isolation structure;
[0013] For the grounding distribution characteristics, the DDR interconnects in the initial wiring structure are grounded through multiple return ground wires.
[0014] In one embodiment, the initial wiring structure is subjected to simulation testing to obtain the initial signal integrity test results corresponding to the initial wiring structure, including:
[0015] Obtain the distributed parameters and coupling information corresponding to the initial wiring structure;
[0016] Based on the distributed parameters and coupling information, perform the following operations on the initial wiring structure:
[0017] The initial wiring structure is subjected to time-domain transient simulation using a preset pseudo-random sequence signal to obtain the initial eye diagram corresponding to the initial wiring structure.
[0018] The initial wiring structure was simulated in the frequency domain using a preset sweep frequency signal to obtain the initial insertion loss parameters and the initial return loss parameters.
[0019] Crosstalk analysis is performed on each DDR interconnect in the initial wiring structure to obtain the initial crosstalk information corresponding to each DDR interconnect.
[0020] The initial eye diagram, initial insertion loss parameters, initial return loss parameters, and initial crosstalk information are merged to obtain the initial signal integrity test results.
[0021] In one embodiment, the quality impact characteristics further include power supply layout characteristics, and the method further includes:
[0022] Based on the target routing structure, identify the interconnects of interest from the DDR interconnects of the target routing structure;
[0023] A virtual mesh was added to the interconnect of interest, and simulation testing was performed to obtain the signal integrity test results after adding the virtual mesh.
[0024] If the signal integrity test results after adding the virtual mesh meet the preset optimization conditions, the wiring structure of the interconnects of interest is optimized using power layout characteristics to obtain the updated target wiring structure.
[0025] In one embodiment, the method further includes:
[0026] Update the target type;
[0027] Return to the step of obtaining the initial routing structure corresponding to the target type of DDR interconnect, until the target routing structure corresponding to all types of DDR interconnect is obtained.
[0028] In one embodiment, the method further includes:
[0029] Obtain the distributed parameters and coupling information corresponding to the target wiring structure;
[0030] Based on the distributed parameters and coupling information corresponding to the target wiring structure, a time-domain transient simulation of the target wiring structure is performed to obtain the target eye diagram;
[0031] Frequency domain characteristics of the target wiring structure are simulated to obtain the target insertion loss parameters and the target return loss parameters;
[0032] Crosstalk analysis is performed on each DDR interconnect in the target wiring structure to obtain target crosstalk information;
[0033] The target eye diagram, target insertion loss parameters, target return loss parameters, and target crosstalk information are merged to obtain the target signal integrity test results.
[0034] The target signal integrity test results are compared with the initial signal integrity test results to obtain the optimization verification conclusion.
[0035] Secondly, this application also provides a high-speed DDR wiring structure optimization device based on a silicon substrate, comprising:
[0036] The information acquisition module is used to acquire the initial routing structure corresponding to the target type of DDR interconnect. The target type is one of memory access control interconnect, data transmission interconnect, and coplanar waveguide interconnect.
[0037] The simulation test module is used to perform simulation test processing on the initial wiring structure and obtain the initial signal integrity test results corresponding to the initial wiring structure.
[0038] The structure optimization module is used to optimize the initial wiring structure by using preset quality influence characteristics when the initial signal integrity test results meet the preset optimization conditions, so as to obtain the target wiring structure corresponding to the DDR interconnect. The quality influence characteristics include ground hole arrangement characteristics, parallel trace characteristics, and ground wire distribution characteristics.
[0039] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the high-speed DDR wiring structure optimization method based on a silicon substrate as described in the first aspect.
[0040] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the high-speed DDR wiring structure optimization method based on a silicon substrate as described in the first aspect.
[0041] Fifthly, this application also provides a wafer-level chip, which includes multiple DDRs, and the DDRs are interconnected using the high-speed DDR wiring structure optimization method based on silicon substrate as described in the first aspect.
[0042] The aforementioned method and apparatus for optimizing high-speed DDR wiring structures based on silicon substrates establish a full-process design method for optimizing high-speed interconnect wiring structures in wafer-level high-speed DDR scenarios. The optimization is determined based on integrity test results, and the initial wiring structure is optimized based on three quality-influencing features: ground hole arrangement characteristics, parallel trace characteristics, and ground line distribution characteristics. This yields the target wiring structure corresponding to the DDR interconnect, effectively improving the signal integrity and power integrity of the target wiring structure. This meets the application scenarios of wafer-level chips with dense wiring and complex interconnect structures, where high-speed DDR has strict requirements for signal quality and signal delay. It helps achieve the multiple goals of high performance, high reliability, and low cost for wafer-level chips in the field of high-speed data transmission. Attached Figure Description
[0043] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0044] Figure 1 This is an application environment diagram of a high-speed DDR wiring structure optimization method based on a silicon substrate in one embodiment;
[0045] Figure 2 This is a flowchart illustrating a method for optimizing a high-speed DDR wiring structure based on a silicon substrate in one embodiment.
[0046] Figure 3(a) shows the eye diagram of multiple DDR interconnects in the initial wiring structure of one embodiment;
[0047] Figure 3(b) shows the eye diagram of a single DDR interconnect in the initial wiring structure of one embodiment;
[0048] Figure 4(a) is a schematic diagram showing the projection range of the DDR interconnect coinciding with the ground via in one embodiment;
[0049] Figure 4(b) is the eye diagram corresponding to the wiring structure in Figure 4(a);
[0050] Figure 5(a) is a schematic diagram showing the separation of the projection range of the DDR interconnect from the ground via in one embodiment;
[0051] Figure 5(b) is the eye diagram corresponding to the wiring structure in Figure 5(a);
[0052] Figure 6(a) is a schematic diagram of DDR interconnects sharing the same return ground wire in one embodiment;
[0053] Figure 6(b) is the eye diagram corresponding to the wiring structure in Figure 6(a);
[0054] Figure 7(a) is a schematic diagram of multiple return ground wires in one embodiment;
[0055] Figure 7(b) is the eye diagram corresponding to the wiring structure in Figure 7(a);
[0056] Figure 8 This is a flowchart illustrating a high-speed DDR wiring structure optimization method based on a silicon substrate in another embodiment.
[0057] Figure 9 This is a structural block diagram of a high-speed DDR wiring structure optimization device based on a silicon substrate in one embodiment;
[0058] Figure 10 This is an internal structural diagram of a computer device in one embodiment.
[0059] Explanation of reference numerals in the attached figures:
[0060] 1. DDR interconnect; 2. Ground hole; 3. Return ground. Detailed Implementation
[0061] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0062] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.
[0063] The high-speed DDR wiring structure optimization method based on silicon substrate provided in this application embodiment can be applied to, for example... Figure 1In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104, or it can be located in the cloud or on another network server.
[0064] Terminal 102 can connect to the DDR to collect the distributed parameters and coupling information corresponding to the DDR interconnect and send them to server 104, so that server 104 can obtain the initial routing structure. Server 104 is used to obtain the initial routing structure corresponding to the target type of DDR interconnect, which is one of memory access control interconnect, data transmission interconnect, and coplanar waveguide interconnect; to perform simulation test processing on the initial routing structure to obtain the initial signal integrity test results corresponding to the initial routing structure; if the initial signal integrity test results meet the preset optimization conditions, the initial routing structure is optimized using preset quality influence features to obtain the target routing structure corresponding to the DDR interconnect. The quality influence features include ground hole arrangement features, parallel trace features, and ground wire distribution features.
[0065] Terminal 102 may be, but is not limited to, various oscilloscopes, network analyzers, time domain reflectometers, probes, and bit error rate testers. Server 104 may be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server providing cloud computing services.
[0066] In one exemplary embodiment, such as Figure 2 As shown, a method for optimizing high-speed DDR wiring structures based on silicon substrates is provided, which is then applied to... Figure 1 Taking server 104 as an example, the explanation includes the following steps 202 to 206. Wherein:
[0067] Step 202: Obtain the initial wiring structure corresponding to the DDR interconnect of the target type.
[0068] The target type is one of memory access control interconnects, data transmission interconnects, and coplanar waveguide interconnects.
[0069] Among them, the memory access control bus (CA) is a DDR interconnect used to send various commands to DDR memory, such as read commands, write commands, activation commands, precharge commands, etc.
[0070] Data Queue Bus (DQ) is a channel in DDR memory used for data transfer, primarily responsible for transferring data between memory and external devices, such as the memory controller.
[0071] Coplanar waveguide (CPW) interconnects are planar DDR interconnects used in fields such as high-speed digital circuits.
[0072] In some embodiments, the target type may also include, but is not limited to, clock lines (CK), chip select bus (CS), and clock enable bus (CKE).
[0073] Step 204: Perform simulation testing on the initial wiring structure to obtain the initial signal integrity test results corresponding to the initial wiring structure.
[0074] Among them, simulation test processing refers to constructing a circuit model of the initial wiring structure through simulation software, simulating the signal transmission state based on the initial wiring structure under actual working conditions, and generating signal integrity test results to characterize the voltage change of the signal flowing through the DDR interconnect.
[0075] For example, simulation testing may include performing time-domain reflection simulation, time-domain transient simulation, frequency-domain characteristic simulation, switching noise simulation, and jitter decomposition simulation on the initial wiring structure. The data obtained from each simulation test together constitute the signal integrity test results, providing data support for subsequent wiring structure optimization.
[0076] Step 206: If the initial signal integrity test results meet the preset optimization conditions, optimize the initial wiring structure using preset quality influence characteristics to obtain the target wiring structure corresponding to the DDR interconnect.
[0077] Among them, the quality impact characteristics include the borehole arrangement characteristics, parallel routing characteristics, and ground wire distribution characteristics.
[0078] For example, optimization conditions may include one, several, or specific items in the signal integrity test results exceeding a preset range of available values, indicating that the signal integrity test results of the initial wiring structure cannot meet the signal integrity and power integrity requirements of the wafer-level chip, and the initial wiring structure needs to be optimized.
[0079] For example, as shown in Figures 3(a) and 3(b), the eye diagrams obtained by simultaneously simulating multiple DDR interconnects in the initial wiring structure are compared with the eye diagrams obtained by simulating a single DDR interconnect. If the difference between the eye width in Figure 3(a) and the eye width in Figure 3(b) is greater than the threshold set in the optimization conditions, or if the difference between the eye height in Figure 3(a) and the eye height in Figure 3(b) is greater than the threshold set in the optimization conditions, then the initial signal integrity test result corresponding to the initial wiring structure meets the preset optimization conditions. In Figures 3(a) and 3(b), the horizontal axis represents time, and the unit can be set to ns; the vertical axis represents voltage.
[0080] In some embodiments, iterative simulations can be performed using deep learning to continuously adjust the wiring structure and compare simulation results, thereby obtaining the initial signal integrity test results corresponding to the initial wiring structure and locating the causes of signal integrity and power integrity issues. However, due to the large number of high-speed DDR interconnect traces and the huge design space in the large-size substrate of wafer-level chips, although it may meet the corresponding analysis requirements, it will bring incalculable time costs and may even fail to converge and close the loop.
[0081] The aforementioned high-speed DDR wiring structure optimization method based on silicon substrate establishes a full-process design method for optimizing high-speed interconnect wiring structures in wafer-level high-speed DDR scenarios. The optimization is determined based on integrity test results, and the initial wiring structure is optimized based on three quality influence characteristics: ground hole arrangement characteristics, parallel trace characteristics, and ground line distribution characteristics. This yields the target wiring structure corresponding to the DDR interconnect, effectively improving the signal integrity and power integrity of the high-speed DDR wiring structure. This meets the application scenarios of wafer-level chips with dense wiring and complex interconnect structures, where high-speed DDR has strict requirements for signal quality and signal delay. It helps achieve the multiple goals of high performance, high reliability, and low cost for wafer-level chips in the field of high-speed data transmission.
[0082] In an exemplary embodiment, simulation testing is performed on the initial wiring structure to obtain the initial signal integrity test result corresponding to the initial wiring structure, including: obtaining the distributed parameters and coupling information corresponding to the initial wiring structure; and performing the following operations on the initial wiring structure based on the distributed parameters and coupling information:
[0083] The initial wiring structure is subjected to time-domain transient simulation using a preset pseudo-random sequence signal to obtain the initial eye diagram corresponding to the initial wiring structure; the initial insertion loss parameter and the initial return loss parameter are obtained by using a preset frequency sweep signal to perform frequency-domain characteristic simulation of the initial wiring structure; crosstalk analysis is performed on each DDR interconnect in the initial wiring structure to obtain the initial crosstalk information corresponding to each DDR interconnect; the initial eye diagram, initial insertion loss parameter, initial return loss parameter and initial crosstalk information are merged and processed to obtain the initial signal integrity test results.
[0084] The distributed parameters and coupling information corresponding to the initial wiring structure can include stack-up parameters, dielectric material constants, loss factors, line width and spacing of DDR interconnects, and via size and distribution, which can accurately reflect the transmission path, electromagnetic coupling relationship and impedance characteristics of the initial wiring structure.
[0085] Frequency domain characteristic simulation refers to setting ports at both ends of the initial wiring structure and applying a broadband sweep frequency signal to extract the scattering parameters of the initial wiring structure, obtaining the response curves of the initial insertion loss parameters and the initial return loss parameters as a function of frequency. Based on the initial insertion loss curve, the signal attenuation at different frequencies can be analyzed; from the initial return loss curve, the magnitude of signal reflection can be analyzed, thereby determining the impedance continuity of the initial wiring structure.
[0086] In this context, time-domain transient simulation refers to applying a pseudo-random sequence signal to the initial wiring structure and transiently solving the dynamic transmission characteristics of DDR interconnects under high-speed operating conditions. The initial eye diagram obtained through time-domain transient simulation yields indicators such as eye height, eye width, jitter, and noise margin, thereby quantitatively evaluating the signal integrity of the initial wiring structure under high-speed operating conditions.
[0087] Crosstalk analysis involves designating adjacent traces in the initial wiring structure as excitation lines and victim lines, respectively. A high-speed signal is applied to the excitation line, and the voltage waveforms of the victim line at the near and far ends are monitored. The amplitude and duration of the near-end crosstalk noise and far-end crosstalk noise are obtained as initial crosstalk information. This allows for the determination of the impact of wiring spacing and parallel coupling in the initial wiring structure on signal transmission.
[0088] In some embodiments, the simulation test process may further include applying a step signal to the initial wiring structure, monitoring the signal reflection along the DDR interconnect, and obtaining an impedance distribution curve as a function of transmission distance. This curve can be used to determine whether there are impedance discontinuities in the initial wiring structure at locations such as vias and turning points, thereby locating potential reflection sources.
[0089] In some embodiments, the simulation test process may further include performing simultaneous switching noise simulation on the initial wiring structure. By simultaneously applying switching excitation to multiple DDR interconnects, the voltage fluctuations and eye diagram closure of the received signal waveform are observed to determine the impact of power integrity and ground bounce on signal transmission.
[0090] For example, the optimization condition may be that one, several, or specific items of the initial eye diagram, initial insertion loss parameter, initial return loss parameter, and initial crosstalk information exceed a preset range of available values. This indicates that the signal integrity test results of the initial wiring structure cannot meet the signal integrity and power integrity requirements of the wafer-level chip, and the initial wiring structure needs to be optimized.
[0091] In this embodiment of the application, by performing time-domain simulation, frequency-domain analysis, transient analysis, and crosstalk analysis on the initial wiring structure, the comprehensive test results of the initial wiring structure in terms of signal integrity can be obtained. This can fully reflect the performance of the initial wiring structure in terms of impedance control, insertion loss, return loss, crosstalk noise, and power supply noise, providing a reliable basis for locating problems and optimizing wiring.
[0092] In one exemplary embodiment, based on Figure 2 The illustrated embodiment optimizes the initial routing structure using preset quality impact characteristics to obtain the target routing structure corresponding to the DDR interconnect, including:
[0093] 1. For the ground hole layout characteristics, adjust the DDR interconnects in the initial wiring structure so that the projection range of the DDR interconnects in the initial wiring structure avoids the ground holes.
[0094] In this context, a ground via is a structure that connects different layers of ground wires or enables the connection of ground wires to other circuit components. In the embodiments of this application, no ground vias are drilled between adjacent layers of ground wires within the projection range of the high-speed interconnect; instead, the ground wires are aggregated through planar continuity or external transitions.
[0095] For example, in Figure 4(a), the projection range of the DDR interconnects in the initial routing structure coincides with the ground vias; Figure 4(b) is the eye diagram corresponding to the initial routing structure in Figure 4(a). Figure 5(a) shows the routing structure after optimizing the routing structure in Figure 4(a), where the projection range of the DDR interconnects avoids the ground vias; Figure 5(b) is the eye diagram corresponding to the routing structure in Figure 5(a). Comparing Figure 4(b) and Figure 5(b), it can be seen that compared to the initial routing structure, the optimized eye diagram is clearer overall and the lines are denser. The optimization process can effectively reduce signal jitter and signal crosstalk.
[0096] 2. For parallel routing features, adjust the DDR interconnects and ground lines in the initial routing structure to a non-parallel routing structure or a segmented isolation structure.
[0097] In high-speed DDR at the wafer level, the metal layer thickness is 2µm, while the dielectric thickness is only 1.6µm. The spacing between DDR interconnects and ground lines is smaller than the conductor's own size. Even with extremely short parallel traces, the electromagnetic fields between the DDR interconnects and ground lines will interact, generating significant crosstalk. To optimize the routing structure, parallel routing of DDR interconnects and ground lines should be avoided by employing non-parallel routing structures or segmented isolation.
[0098] 3. Regarding the grounding characteristics, the DDR interconnects in the initial wiring structure are grounded through multiple return ground wires.
[0099] When multiple DDR interconnects share the same return ground wire to the grounding port, multi-directional crosstalk will occur due to the superposition interference of return current and ground bounce noise.
[0100] For example, in Figure 6(a), the DDR interconnects in the initial routing structure share the same return ground wire to the ground port; Figure 6(b) is the eye diagram corresponding to the initial routing structure in Figure 6(a). In the process of optimizing the routing structure, multiple return ground wires are used to return to the ground port, as shown in Figure 7(a), and Figure 7(b) is the eye diagram corresponding to the routing structure in Figure 7(a). Comparing Figure 6(b) and Figure 7(b), it can be seen that compared to the initial routing structure, the optimized structure effectively reduces signal jitter and crosstalk.
[0101] In one possible implementation, the method may further include: acquiring the distributed parameters and coupling information corresponding to the target wiring structure; performing time-domain transient simulation on the target wiring structure based on the distributed parameters and coupling information to obtain the target eye diagram; performing frequency-domain characteristic simulation on the target wiring structure to obtain the target insertion loss parameters and target return loss parameters; performing crosstalk analysis on each DDR interconnect in the target wiring structure to obtain the target crosstalk information; merging the target eye diagram, target insertion loss parameters, target return loss parameters, and target crosstalk information to obtain the target signal integrity test results; and comparing the target signal integrity test results with the initial signal integrity test results to obtain the optimization verification conclusion.
[0102] The simulation test process of performing time-domain transient simulation, frequency-domain characteristic simulation, and crosstalk analysis on the target wiring structure is consistent with the simulation test process of the initial wiring structure in the aforementioned embodiment, so as to obtain corresponding and comparable signal integrity test results.
[0103] The optimization verification conclusion is obtained by comparing the target signal integrity test results with the initial signal integrity test results. Specifically, the optimization verification conclusion can be obtained by comparing the initial eye diagram and target eye diagram aperture size, the initial return loss parameter and target return loss parameter, the initial insertion loss parameter and target insertion loss parameter, and the initial crosstalk information and target crosstalk information.
[0104] For example, simulation tests were performed on the target cabling structure. The target return loss parameter of the target cabling structure was less than -15dB at 0.6GHz, the target insertion loss parameter was approximately -6dB at 0.6GHz, and the magnitude of the target crosstalk information was below -40dB. Compared with the initial crosstalk information of approximately -25dB before optimization, the target cabling structure showed a significant improvement in signal integrity. The timing still had a large margin under the 48% template. It can be concluded that the target cabling structure has a significant improvement in signal quality compared with the initial cabling structure, verifying the effectiveness of the optimization strategy based on quality impact characteristics.
[0105] In one possible implementation, the method may further include: updating the target type; returning to the step of obtaining the initial routing structure corresponding to the DDR interconnect of the target type, until the target routing structure corresponding to all types of DDR interconnects is obtained.
[0106] For example, this method can first select memory access control interconnects (CA lines) as the target type for optimization to obtain the target routing structure corresponding to the CA lines. Then, the target type is updated to DDR interconnects (DQ lines) as data transmission interconnects, and the DQ lines are optimized to obtain the target routing structure corresponding to the DQ lines. Simulation verification of the target routing structure corresponding to the DQ lines shows that its return loss is approximately -13dB at 1.2GHz, its insertion loss is less than -3dB at 1.2GHz, and its crosstalk is on the order of -37dB. This can also effectively improve the signal integrity of the high-speed DDR routing structure, further illustrating the scalability of the silicon substrate-based high-speed DDR routing structure optimization method in the embodiments of this application.
[0107] In this embodiment, the initial wiring structure is optimized based on quality influence characteristics such as ground hole arrangement, parallel trace characteristics, and ground wire distribution characteristics. This effectively improves return loss, crosstalk level, and timing and voltage margin. Furthermore, by performing simulation testing on the optimized target wiring structure, the target signal integrity test results are obtained. These results are then compared with the initial signal integrity test results to obtain optimization verification conclusions. This verifies the optimization effect of the optimization method provided in this embodiment, thereby obtaining a wiring structure that effectively improves the signal integrity of DDR interconnects and enhances the reliability of the high-speed DDR wiring structure optimization method based on silicon substrates.
[0108] In an exemplary embodiment, the quality impact features further include power routing features. The method may also include: determining the interconnects of interest from the DDR interconnects of the target routing structure based on the target routing structure; adding a virtual mesh to the interconnects of interest and performing simulation testing to obtain the signal integrity test results after adding the virtual mesh; and optimizing the routing structure of the interconnects of interest using the power routing features if the signal integrity test results after adding the virtual mesh meet the preset optimization conditions to obtain the updated target routing structure.
[0109] The interconnects of interest can be selected from several important DDR interconnects. For example, the interconnects of interest may include one DDR interconnect for writing, one for reading, and one for control. Simulation tests are performed on the interconnects of interest with the added virtual mesh to obtain signal integrity test results. The initial routing structure is then optimized based on multiple quality impact features, including power supply layout characteristics, to obtain the updated target routing structure.
[0110] In some embodiments, the method further includes performing simulation testing on the updated target wiring structure and comparing the simulation test results before and after optimization to verify the signal integrity and power integrity of the updated target wiring structure.
[0111] For example, adding a virtual mesh may significantly worsen crosstalk levels in critical frequency bands, manifesting as increased coupling noise. When the crosstalk level or other test parameters meet preset optimization conditions, the power solder ball arrangement in the initial wiring structure can be optimized using quality impact features to avoid focusing on dense power meshes beneath interconnects. In the simulation test results corresponding to the updated target wiring structure, the crosstalk level decreased from -25dB to below -40dB, demonstrating a significant improvement.
[0112] In this embodiment, by adding a virtual mesh to the interconnects of interest, the updated target wiring structure is obtained through optimization. This effectively improves the power integrity of the wiring structure. Furthermore, the optimization process is based on the power arrangement characteristics for targeted optimization and adjustment, which effectively reduces the electromagnetic coupling effect caused by the virtual mesh and effectively suppresses signal crosstalk caused by the dense distribution of the power mesh. This further enhances the overall signal integrity of the target wiring structure and improves the reliability of the high-speed DDR wiring structure optimization method based on silicon substrate.
[0113] In one exemplary embodiment, such as Figure 8 As shown, a method for optimizing a high-speed DDR wiring structure based on a silicon substrate is provided, including steps 801 to 809. Wherein:
[0114] Step 801: Obtain the initial wiring structure corresponding to the DDR interconnect of the target type.
[0115] The target type is one of memory access control interconnects, data transmission interconnects, and coplanar waveguide interconnects.
[0116] Step 802: Perform simulation testing on the initial wiring structure to obtain the initial signal integrity test results corresponding to the initial wiring structure.
[0117] Step 802 may further include obtaining the distributed parameters and coupling information corresponding to the initial wiring structure; based on the distributed parameters and coupling information, performing the following operations on the initial wiring structure: performing time-domain transient simulation on the initial wiring structure using a preset pseudo-random sequence signal to obtain the initial eye diagram corresponding to the initial wiring structure; performing frequency-domain characteristic simulation on the initial wiring structure using a preset frequency sweep signal to obtain the initial insertion loss parameters and initial return loss parameters; performing crosstalk analysis on each DDR interconnect in the initial wiring structure to obtain the initial crosstalk information corresponding to each DDR interconnect; and merging the initial eye diagram, initial insertion loss parameters, initial return loss parameters, and initial crosstalk information to obtain the initial signal integrity test results.
[0118] Step 803: If the initial signal integrity test results meet the preset optimization conditions, optimize the initial wiring structure using preset quality influence characteristics to obtain the target wiring structure corresponding to the DDR interconnect.
[0119] The quality impact characteristics include via layout, parallel routing, ground wire distribution, and power supply layout. The optimization process may include: for via layout characteristics, adjusting the DDR interconnects in the initial routing structure so that the projection range of the DDR interconnects avoids the vias; for parallel routing characteristics, adjusting the DDR interconnects and ground wires in the initial routing structure to a non-parallel routing structure or a segmented isolation structure; for ground wire distribution characteristics, grounding the DDR interconnects in the initial routing structure through multiple return ground wires.
[0120] Step 804: Update the target type; return to the step of obtaining the initial routing structure corresponding to the DDR interconnect of the target type, until the target routing structure corresponding to all types of DDR interconnects is obtained.
[0121] Step 805: Perform simulation testing on the target wiring structure to obtain the signal integrity test results corresponding to the target wiring structure.
[0122] The process of simulating and testing the target wiring structure may include: obtaining the distributed parameters and coupling information corresponding to the target wiring structure; performing time-domain transient simulation on the target wiring structure based on the distributed parameters and coupling information to obtain the target eye diagram; performing frequency-domain characteristic simulation on the target wiring structure to obtain the target insertion loss parameters and target return loss parameters; performing crosstalk analysis on each DDR interconnect in the target wiring structure to obtain the target crosstalk information; and merging the target eye diagram, target insertion loss parameters, target return loss parameters, and target crosstalk information to obtain the target signal integrity test results.
[0123] Step 806: Compare the target signal integrity test results with the initial signal integrity test results to obtain the optimization verification conclusion.
[0124] Step 807: Based on the target routing structure, identify the interconnects of interest from the DDR interconnects of the target routing structure.
[0125] Step 808: Add a virtual mesh to the interconnect of interest and perform simulation testing to obtain the signal integrity test results after adding the virtual mesh.
[0126] Step 809: If the signal integrity test results after adding the virtual mesh meet the preset optimization conditions, optimize the wiring structure of the interconnects of interest using power layout features to obtain the updated target wiring structure.
[0127] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.
[0128] Based on the same inventive concept, this application also provides a silicon substrate-based high-speed DDR wiring structure optimization apparatus for implementing the aforementioned silicon substrate-based high-speed DDR wiring structure optimization method. The solution provided by this apparatus is similar to the implementation described in the above method. Therefore, the specific limitations in one or more embodiments of the silicon substrate-based high-speed DDR wiring structure optimization apparatus provided below can be found in the limitations of the silicon substrate-based high-speed DDR wiring structure optimization method described above, and will not be repeated here.
[0129] In one exemplary embodiment, such as Figure 9 As shown, a high-speed DDR wiring structure optimization device based on a silicon substrate is provided, including: an information acquisition module 902, a simulation testing module 904, and a structure optimization module 906, wherein:
[0130] The information acquisition module 902 is used to acquire the initial wiring structure corresponding to the target type of DDR interconnect. The target type is one of memory access control interconnect, data transmission interconnect, and coplanar waveguide interconnect.
[0131] The simulation test module 904 is used to perform simulation test processing on the initial wiring structure and obtain the initial signal integrity test results corresponding to the initial wiring structure.
[0132] The structure optimization module 906 is used to optimize the initial wiring structure by using preset quality influence characteristics when the initial signal integrity test results meet the preset optimization conditions, so as to obtain the target wiring structure corresponding to the DDR interconnect. The quality influence characteristics include ground hole arrangement characteristics, parallel trace characteristics and ground wire distribution characteristics.
[0133] In one embodiment, the structure optimization module 906 is further configured to adjust the DDR interconnects in the initial wiring structure to avoid the ground holes for the ground hole arrangement features; adjust the DDR interconnects and ground wires in the initial wiring structure to a non-parallel wiring structure or a segmented isolation structure for the parallel routing features; and ground wire distribution features to ground the DDR interconnects in the initial wiring structure through multiple return ground wires.
[0134] In one embodiment, the simulation test module 904 is further configured to acquire the distributed parameters and coupling information corresponding to the initial wiring structure; based on the distributed parameters and coupling information, perform the following operations on the initial wiring structure: perform time-domain transient simulation on the initial wiring structure using a preset pseudo-random sequence signal to obtain the initial eye diagram corresponding to the initial wiring structure; perform frequency-domain characteristic simulation on the initial wiring structure using a preset frequency sweep signal to obtain the initial insertion loss parameters and initial return loss parameters; perform crosstalk analysis on each DDR interconnect in the initial wiring structure to obtain the initial crosstalk information corresponding to each DDR interconnect; and merge the initial eye diagram, initial insertion loss parameters, initial return loss parameters, and initial crosstalk information to obtain the initial signal integrity test results.
[0135] In one embodiment, the quality impact features also include power routing features. The simulation test module 904 is further used to determine the interconnects of interest from the DDR interconnects of the target wiring structure based on the target wiring structure; add virtual meshes to the interconnects of interest and perform simulation test processing to obtain the signal integrity test results after adding virtual meshes; if the signal integrity test results after adding virtual meshes meet the preset optimization conditions, optimize the wiring structure of the interconnects of interest using power routing features to obtain the updated target wiring structure.
[0136] In one embodiment, the structure optimization module 906 is further configured to update the target type; return to the step of obtaining the initial routing structure corresponding to the DDR interconnect of the target type, until the target routing structure corresponding to all types of DDR interconnects is obtained.
[0137] In one embodiment, the simulation test module 904 is further configured to acquire the distributed parameters and coupling information corresponding to the target wiring structure; perform time-domain transient simulation on the target wiring structure based on the distributed parameters and coupling information corresponding to the target wiring structure to obtain the target eye diagram; perform frequency-domain characteristic simulation on the target wiring structure to obtain the target insertion loss parameters and the target return loss parameters; perform crosstalk analysis on each DDR interconnect in the target wiring structure to obtain the target crosstalk information; merge the target eye diagram, target insertion loss parameters, target return loss parameters, and target crosstalk information to obtain the target signal integrity test results; and compare the target signal integrity test results with the initial signal integrity test results to obtain the optimization verification conclusion.
[0138] Each module in the aforementioned high-speed DDR wiring structure optimization device based on a silicon substrate can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0139] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores the initial wiring structure. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a high-speed DDR wiring structure optimization method based on a silicon substrate.
[0140] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0141] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.
[0142] In one exemplary embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above-described method embodiments.
[0143] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0144] In one exemplary embodiment, a wafer-level chip is provided, including a plurality of DDRs, wherein the DDRs are interconnected using the method described in the above embodiment.
[0145] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.
[0146] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0147] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0148] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A method for high-speed DDR routing structure optimization based on silicon substrate, characterized in that, The method comprises: acquiring an initial wiring structure corresponding to a target type of DDR interconnection line, the target type being one of a memory access control type interconnection line, a data transmission type interconnection line, and a coplanar waveguide type interconnection line; performing simulation test processing on the initial wiring structure to obtain an initial signal integrity test result corresponding to the initial wiring structure; in a case where the initial signal integrity test result meets preset optimization conditions, optimizing the initial wiring structure by using preset quality influence characteristics to obtain a target wiring structure corresponding to the DDR interconnection line, the quality influence characteristics including a ground hole arrangement characteristic, a parallel wire characteristic, and a ground wire distribution characteristic.
2. The method of claim 1, wherein, The optimization of the initial wiring structure by using the preset quality influence characteristics to obtain the target wiring structure corresponding to the DDR interconnection line comprises: for the ground hole arrangement characteristic, adjusting the DDR interconnection line in the initial wiring structure so that the projection range of the DDR interconnection line in the initial wiring structure avoids the ground hole; for the parallel wire characteristic, adjusting the DDR interconnection line and the ground wire in the initial wiring structure into a non-parallel wiring structure or a segmented isolation structure; for the ground wire distribution characteristic, connecting the DDR interconnection line in the initial wiring structure to ground through multiple reflow ground wires.
3. The method of claim 1, wherein, The simulation test processing on the initial wiring structure to obtain the initial signal integrity test result corresponding to the initial wiring structure comprises: acquiring distribution parameters and coupling information corresponding to the initial wiring structure; based on the distribution parameters and the coupling information, performing the following operations on the initial wiring structure: performing time-domain transient simulation on the initial wiring structure by using a preset pseudo-random sequence signal to obtain an initial eye diagram corresponding to the initial wiring structure; performing frequency-domain characteristic simulation on the initial wiring structure by using a preset sweep signal to obtain an initial insertion loss parameter and an initial return loss parameter; performing crosstalk analysis on each DDR interconnection line in the initial wiring structure to obtain initial crosstalk information corresponding to each DDR interconnection line; performing merging processing on the initial eye diagram, the initial insertion loss parameter, the initial return loss parameter, and the initial crosstalk information to obtain the initial signal integrity test result.
4. The method of claim 1, wherein, The quality influence characteristics further include a power supply arrangement characteristic, and the method further comprises: based on the target wiring structure, determining a concerned interconnection line from the DDR interconnection line of the target wiring structure; adding a virtual grid to the concerned interconnection line and performing simulation test processing to obtain a signal integrity test result after the virtual grid is added; in a case where the signal integrity test result after the virtual grid is added meets preset optimization conditions, optimizing the wiring structure of the concerned interconnection line by using the power supply arrangement characteristic to obtain an updated target wiring structure.
5. The method of claim 1, wherein, The method further comprises: updating the target type; returning to performing the step of acquiring the initial wiring structure corresponding to the target type of DDR interconnection line until target wiring structures corresponding to all types of DDR interconnection lines are obtained.
6. The method of claim 3, wherein, The method further comprises: obtain distribution parameters and coupling information corresponding to the target wiring structure; perform time-domain transient simulation on the target wiring structure based on the distribution parameters and the coupling information, to obtain a target eye diagram; perform frequency-domain characteristic simulation on the target wiring structure, to obtain target insertion loss parameters and target return loss parameters; perform crosstalk analysis on each DDR interconnection line in the target wiring structure, to obtain target crosstalk information; merge the target eye diagram, the target insertion loss parameters, the target return loss parameters, and the target crosstalk information, to obtain a target signal integrity test result; perform corresponding comparison processing on the target signal integrity test result and the initial signal integrity test result, to obtain an optimization verification conclusion.
7. A high speed DDR routing structure optimization apparatus based on silicon substrate, characterized by, The device comprises: an information acquisition module configured to acquire an initial wiring structure corresponding to a target type of DDR interconnection line, the target type being one of a memory control type interconnection line, a data transmission type interconnection line, and a coplanar waveguide type interconnection line; a simulation test module configured to perform simulation test processing on the initial wiring structure, to obtain an initial signal integrity test result corresponding to the initial wiring structure; a structure optimization module configured to, if the initial signal integrity test result meets a preset optimization condition, optimize the initial wiring structure by using a preset quality influence feature, to obtain a target wiring structure corresponding to the DDR interconnection line, the quality influence feature including a ground hole arrangement feature, a parallel wire feature, and a ground wire distribution feature.
8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to implement the steps of the method of any one of claims 1 to 6.
9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.
10. A wafer level chip, characterized by, The wafer-level chip comprises a plurality of DDRs, and the DDRs are wired by using the method of any one of claims 1 to 6.