Drive circuit, transmitter circuit, semiconductor memory and data transmission method

Abstract

The application relates to a driving circuit, a transmitter circuit, a semiconductor memory and a data transmission method. The driving circuit comprises a pull-up circuit connected between a power supply and an output terminal, and a pull-down circuit connected between the output terminal and the ground; the pull-up circuit and the pull-down circuit each comprise, in sequence, a first transistor for adjusting an output impedance, a second transistor for transmitting data, and a third transistor for voltage division according to a protection voltage to protect the first transistor and the second transistor. The application enables the driving circuit to work safely and effectively under different voltages, and realizes compatibility of high and low voltages.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a driving circuit, a transmitter circuit, a semiconductor memory and a data transmission method. BACKGROUND

[0002] With the development of semiconductor technology, people have higher and higher requirements for data transmission when using electronic devices; for example, in a memory system, the performance of a transmitter circuit (such as a sending end TX circuit) has a great influence on the reliability of transmitted data, signal quality and power consumption and the like. However, the compatibility of the conventional transmitter circuit is poor, which affects data transmission. SUMMARY

[0003] Therefore, it is necessary to provide a driving circuit, a transmitter circuit, a semiconductor memory and a data transmission method capable of improving compatibility in view of the above technical problems.

[0004] In a first aspect, the present application provides a driving circuit, comprising a pull-up circuit connected between a power supply and an output terminal, and a pull-down circuit connected between the output terminal and a ground; the pull-up circuit and the pull-down circuit each comprise, in sequence: a first transistor for adjusting an output impedance; a second transistor for transmitting data; and a third transistor for dividing a protection voltage to protect the first transistor and the second transistor.

[0005] In one of the embodiments, the protection voltage comprises a clamping voltage; and the third transistor is configured to: when the voltage of the power supply is a low voltage, take the voltage of the power supply as the clamping voltage; and when the voltage of the power supply is a high voltage, determine the clamping voltage according to a threshold voltage of the third transistor.

[0006] In one of the embodiments, the type of the transistor in the pull-up circuit is a PMOS tube, and the type of the transistor in the pull-down circuit is an NMOS tube.

[0007] In one of the embodiments, in the pull-up circuit, the first transistor, the second transistor and the third transistor are connected in series along a direction from the power supply to the output terminal; and in the pull-down circuit, the third transistor, the second transistor and the first transistor are connected in series along a direction from the output terminal to the ground.

[0008] In one of the embodiments, the driving circuit further comprises a control module configured to detect the voltage of the power supply and generate the protection voltage based on the detection result.

[0009] In one of the embodiments, the control module comprises an analog circuit.

[0010] In a second aspect, the present application further provides a transmitter circuit, which at least comprises the driving circuit as described above.

[0011] In a third aspect, the application further provides a semiconductor memory, which comprises at least a transmitter circuit, and the transmitter circuit comprises the driving circuit as described above.

[0012] In a fourth aspect, the application further provides a data transmission method, which comprises: controlling a first transistor in a pull-up circuit and a pull-down circuit according to a calibration code, so as to adjust an output impedance of a transmitter circuit; the pull-up circuit is connected between a power supply and an output terminal, and the pull-down circuit is connected between the output terminal and a ground; controlling a second transistor in the pull-up circuit and the pull-down circuit according to a data signal, so as to transmit data through the output terminal; controlling a third transistor in the pull-up circuit and the pull-down circuit according to a protection voltage, so as to protect the first transistor and the second transistor; wherein the first transistor, the second transistor and the third transistor are connected in sequence.

[0013] In one embodiment, the protection voltage comprises a clamping voltage; and the controlling the third transistor in the pull-up circuit and the pull-down circuit according to the protection voltage comprises: when the voltage of the power supply is a low voltage, taking the voltage of the power supply as the clamping voltage; and when the voltage of the power supply is a high voltage, determining the clamping voltage according to a threshold voltage of the third transistor.

[0014] The driving circuit, the transmitter circuit, the semiconductor memory and the data transmission method, the pull-up circuit and the pull-down circuit in the driving circuit each comprise a first transistor, a second transistor and a third transistor connected in sequence, and the third transistor is used for voltage division according to a protection voltage, so as to protect the first transistor and the second transistor. Through the third transistor controlled by the protection voltage, the driving circuit can work safely and effectively under different voltages, and the compatibility of high and low voltages is realized. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other related drawings can be obtained by those skilled in the art without any creative effort.

[0016] Figure 1 It is a structural diagram of a traditional transmitter circuit.

[0017] Figure 2 It is a structural schematic diagram of the driving circuit in one embodiment.

[0018] Figure 3 It is a structural schematic diagram of the driving circuit in another embodiment.

[0019] Figure 4 It is a structural schematic diagram of the transmitter circuit in one embodiment.

[0020] Figure 5 Figure 1 is a flowchart of a data transmission method according to an embodiment. DETAILED DESCRIPTION

[0021] For the purpose of the present application, the technical solutions and advantages will be more clearly apparent, the following will be further described in detail with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not intended to limit the present application.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0023] It should be noted that the terms "first", "second", and the like used herein can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. As used herein, the singular forms "a", "an" and "the" can also include the plural forms unless the context clearly indicates otherwise. The terms "include" and "have" and any variations thereof used herein are intended to cover non-exclusive inclusion. The term "a plurality of" used herein means two or more, "at least one" means one or more, and "at least part of the element" means part or all of the element. In addition, the character " / " generally indicates that the associated objects before and after are in an "or" relationship. The term "and / or" used herein means one of the options or any combination of multiple options.

[0024] It can be understood that "connection" in the following embodiments means "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have electrical signal or data transmission between each other.

[0025] Taking DDR (Double Data Rate) as an example, the TX (Transmitter) circuit (transmitter circuit) in the DDR memory system is located inside the memory controller (such as CPU (Central Processing Unit) or special chip), which is mainly responsible for sending data to DRAM (Dynamic Random Access Memory) particles (write operation). Its core function is to ensure the reliability of high-speed data writing through precise timing control, signal shaping and data synchronization.

[0026] As Figure 1As shown, the conventional technology is to select MOS and resistance corresponding to threshold value according to the size of IO (Input / Output) power voltage (VDDQ), which can be adjusted to the target value by, for example, Trim code, and transmit data by the second level MOS. It should be noted that, Figure 1 The PU (Pull Up) Trim code refers to the PU Trim code, i.e. the pull-up calibration code; the PD (Pull Down) Trim code refers to the PD Trim code, i.e. the pull-down calibration code; the PU data refers to the PU data, i.e. the pull-up data; the PD data refers to the PD data, i.e. the pull-down data; and the PAD (Passivation opening) refers to the pad.

[0027] However, since the MOS cannot withstand high voltage or cannot be turned on at low voltage, the conventional technology is only applicable to a single power voltage or a similar power voltage application scenario, which has low versatility and poor compatibility.

[0028] Based on the above conventional technology, the three-level transistor of the embodiments of the present application is proposed, wherein the first level is Trim code control, the second level is data transmission, and the third level is designed as a bias clamping voltage to protect the low-voltage transistor from stable operation at high voltage. Since it can work at different voltages, the present application can be compatible with multiple protocols, which can be optionally but not limited to DDR4, LPDDR4(X), DDR5, and LPDDR5(X). It can be understood that the encoding structure of the Trim code in the present application is not limited.

[0029] It should be noted that the beneficial effects or technical problems solved by the embodiments of the present application are not limited to this, but also other implicit or related problems, which can be seen from the description of the following embodiments. The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in detail in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0030] In one exemplary embodiment, as Figure 2As shown, a driving circuit 10 is provided, for example, applied to a transmitter circuit, which can include a pull-up circuit 102 connected between a power supply VDDQ and an output terminal, and a pull-down circuit 104 connected between the output terminal and ground; the pull-up circuit 102 and the pull-down circuit 104 each include first, second and third transistors connected in sequence: the first transistor is used for adjusting output impedance; the second transistor is used for transmitting data; and the third transistor is used for voltage division according to a protection voltage to protect the first and second transistors.

[0031] Specifically, the pull-up circuit 102 is connected between the power supply VDDQ and the output terminal, and the pull-down circuit 104 is connected between the power supply VDDQ and the output terminal. Exemplarily, the transistors included in the pull-up circuit 102 can be referred to as pull-up transistors, and the transistors included in the pull-down circuit 104 can be referred to as pull-down transistors. Optionally, the pull-up transistors can be PMOS transistors, and the pull-down transistors can be NMOS transistors.

[0032] In the driving circuit of the embodiments of the present application, the pull-up circuit and the pull-down circuit each adopt a three-stage transistor structure (the three-stage transistor structure in the present application can be referred to as Cascode), in which one stage is used for adjusting output impedance, one stage is used for transmitting data, and one stage is used for voltage division according to a protection voltage. For example, the first stage is an input for calibration code, the second stage is a data input, and the third stage is a safe voltage input, so that the third transistor can protect the first and second transistors, for example, a low-voltage MOS transistor can work stably at high voltage. In the pull-up circuit 102, the protection voltage for controlling the third transistor can be referred to as a PU protection voltage (PU protect); in the pull-down circuit 104, the protection voltage for controlling the third transistor can be referred to as a PD protection voltage (PD protect).

[0033] It can be understood that the first, second and third transistors are independently controlled by different control signals. In the pull-up circuit, the control end of the first transistor receives a pull-up calibration code (PU Trim code) for impedance adjustment of the pull-up circuit, the control end of the second transistor receives pull-up data (PU data), i.e. data to be transmitted, to determine the on and off of the pull-up circuit, and the control end of the third transistor receives a pull-up protection voltage (PU protect) to control the working state of the transistor, thereby realizing voltage protection for the other two series-connected transistors.

[0034] Correspondingly, in the pull-down circuit, the control end of the first transistor receives a pull-down trim code (PD Trim code) for adjusting the on-resistance of the pull-down circuit to achieve impedance matching, the control end of the second transistor receives a pull-down data (PD data), i.e., the data to be sent, and the control end of the third transistor receives a pull-down protection voltage (PD protect) for controlling the working state of the transistor, thereby achieving voltage protection for the other two series-connected transistors.

[0035] Based on the present application, dynamic control of the third transistor in the pull-up circuit 102 and the third transistor in the pull-down circuit 104 is achieved, so that the driving circuit can safely work under high and low voltage power supply voltages without replacing the internal core low-voltage device, and wide-range voltage compatibility is achieved. At the same time, under any voltage mode, the output impedance of the circuit can still be accurately controlled by adjusting the pull-up trim code and the pull-down trim code, thereby ensuring the integrity of the signal.

[0036] The above driving circuit, by introducing the third transistor for voltage division according to the protection voltage, enables the driving circuit to safely and effectively work under a wide range of power supply voltages, achieving compatibility for high and low voltage applications, such as compatibility with different memory protocols such as DDR4 and LPDDR5, significantly enhancing the application range and reusability. Moreover, the present application integrates voltage protection, data driving, and impedance calibration in the same three-level series structure, which is compact in structure, improves the flexibility of chip design, avoids repeated design for different voltage standards, reduces costs, and ensures better performance under the condition of using small-size devices, such as ensuring the driving performance of the circuit under low voltage and effectively protecting the low-voltage device of the core under high voltage, successfully expanding the high-voltage working capability of the circuit without sacrificing low-voltage performance, while maintaining accurate impedance calibration function.

[0037] Regarding the control of the third transistor in the embodiment of the present application, in one embodiment, the protection voltage can include a clamping voltage; the third transistor is configured to: when the voltage of the power supply is a low voltage, take the voltage of the power supply as the clamping voltage; and when the voltage of the power supply is a high voltage, determine the clamping voltage according to the threshold voltage of the third transistor.

[0038] Specifically, as the third level in the three-level transistor structure, the third transistor is a clamping voltage input, and by changing the clamping voltage, the low-voltage tube can be effectively protected. Illustratively, different voltages can be set according to the threshold voltage vth. Alternatively, the clamping voltage can be set to the power supply voltage under low-voltage working; when working under high voltage, different clamping protection voltage values are set according to the different threshold voltages vth.

[0039] In this embodiment, low voltage and high voltage are relative. When the power supply voltage is low, such as 1.1V (refer to the memory interface standard), the clamping voltage applied to the gate of the third transistor can be the power supply voltage, ensuring excellent driving performance of the circuit when operating at low voltage. When the power supply voltage is high, such as 1.8V, directly applying 1.8V to the first and second transistors, which have a withstand voltage of only 1.2V, will cause device damage. This embodiment solves the above problem through the third transistor. In this mode, the clamping voltage is set to a precisely calculated preset protection voltage value.

[0040] By dynamically controlling the third transistor in the pull-up and pull-down circuits, the drive circuit can safely operate under two drastically different power supply voltages without replacing the internal core low-voltage components, achieving wide-range voltage compatibility. Simultaneously, in any voltage mode, the circuit's output impedance can still be precisely controlled by adjusting the pull-up and pull-down calibration codes, thus ensuring signal integrity.

[0041] Regarding the device sequence of the three transistors, in some embodiments, in a pull-up circuit, the first transistor, the second transistor, and the third transistor are connected in series in the direction from the power supply to the output terminal; and in a pull-down circuit, the third transistor, the second transistor, and the first transistor are connected in series in the direction from the output terminal to ground.

[0042] Specifically, both the pull-up and pull-down circuits employ a cascaded structure consisting of three metal-oxide-semiconductor transistors connected in series. Optionally, the pull-up transistor is a PMOS transistor, and the pull-down transistor is an NMOS transistor.

[0043] like Figure 3 As shown, in the drive circuit 10, pull-up transistors A, B, and C are connected in series along the direction from the power supply VDDQ to the output terminal PAD. The sources and drains of these three PMOS transistors are connected in series, forming a path from the power supply VDDQ to the output terminal PAD. Specifically, the source of pull-up transistor A is connected to the power supply VDDQ, and its drain is connected to the source of pull-up transistor B; the drain of pull-up transistor B is connected to the source of pull-up transistor C; and the drain of pull-up transistor C is connected to the output terminal PAD.

[0044] It should be noted that the gates of the pull-up transistor A, the pull-up transistor B and the pull-up transistor C are independently controlled by different control signals. The gate of the pull-up transistor A receives a PU calibration code, which is used to adjust the on-resistance of the transistor, so as to participate in impedance adjustment of the entire pull-up path. The gate of the pull-up transistor B receives PU data. The gate of the pull-up transistor C receives a PU protection voltage (for example, a pull-up clamping voltage), which is used to control the working state of the protection transistor, so as to realize voltage protection of the other two series-connected transistors.

[0045] Corresponding to the pull-up circuit, the pull-down circuit comprises three series-connected N-channel metal oxide semiconductor transistors. In the direction from the output terminal PAD to the ground GND, the pull-down transistor D, the pull-down transistor E and the pull-down transistor F are connected in series. The drain and the source of the three NMOS transistors are connected in series, and a path from the output terminal PAD to the ground GND is formed. Among them, the drain of the pull-down transistor D is connected to the output terminal PAD, and the source thereof is connected to the drain of the pull-down transistor E; the source of the pull-down transistor E is connected to the drain of the pull-down transistor F; and the source of the pull-down transistor F is connected to the ground GND.

[0046] Similarly, the gates of the three NMOS transistors are independently controlled by different control signals. The gate of the pull-down transistor D receives a PD protection voltage (for example, a pull-down clamping voltage), so as to realize voltage protection of other transistors in the pull-down circuit. The gate of the pull-down transistor E receives PD data. The gate of the pull-down transistor F receives a PD calibration code, so as to realize impedance matching.

[0047] In actual application, the pull-up transistor B, the pull-down transistor E, and the pull-up transistor A and the pull-down transistor F usually adopt low-voltage devices of a core process, so as to obtain higher switching speed and smaller size. However, this also means that their voltage withstand capability is low, for example, the gate oxide breakdown voltage and the drain-source breakdown voltage thereof can be only 0.8 V. In this case, the pull-up transistor C and the pull-down transistor D can be selected according to requirements.

[0048] Further, the cascade order of the three transistors in the embodiment of the application, that is, the physical arrangement order of the three transistors in the pull-up circuit and the pull-down circuit, is fixed, wherein the first stage is an input for a calibration code, the second stage is a data input, and the third stage is a clamping voltage input; in the embodiment of the application, the transistor of the first stage (the pull-up transistor A / the pull-down transistor F) is used to access the calibration code, so that the calibration code can be used as a static signal, and when the first stage is connected to a power supply or the ground, it is equivalent to a current source; if the second stage or another stage is used to access the calibration code, additional capacitor charging and discharging will be generated, which will affect the overall electrical signal and further affect the performance.

[0049] Secondly, the transistors of the second stage (pull-up transistor B / pull-down transistor E) are used to access data (PD data / PU data), because the second stage is used to control the opening and closing of the entire circuit, and the opening and closing needs to be continuously performed in practical applications. Further, the transistors of the third stage (pull-up transistor C / pull-down transistor D) can be used as protection devices, which are equivalent to resistors. When the entire circuit is used to transmit signals, the influence of the transistors of the third stage on the electrical signals at the output end PAD is limited, and the influence of the transistors of the third stage on the charging and discharging is not great.

[0050] The above driving circuit improves the operability of low-voltage devices in different voltage domains (including high-voltage domains), and can be compatible with memory protocols with a very large voltage domain span, such as DDR4 and LPDDR5. Because low-voltage devices can be used, the parasitic capacitance generated by the device itself can be greatly reduced, thereby improving the data transmission quality and optimizing the power consumption.

[0051] In one embodiment, the driving circuit further includes a control module configured to detect a voltage of the power supply and generate a protection voltage based on a detection result. Specifically, the driving circuit can automatically generate the clamping voltage required by the third transistor. The driving circuit can further include a control module configured to detect a voltage of the power supply and generate a protection voltage based on a detection result.

[0052] For example, the control module can be a comparator configured to compare the voltage of the power supply VDDQ with a fixed reference voltage (for example, 1.2V), where the reference voltage can represent a preset threshold for determining a high voltage and a low voltage. If the comparison result is that VDDQ is lower than the preset threshold (for example, VDDQ < 1.5V), it is determined that the current working mode is a low-voltage working mode, and the control module can set the clamping voltage to the voltage of the power supply. If the comparison result is that VDDQ is higher than or equal to the preset threshold (for example, VDDQ >= 1.5V), it is determined that the current working mode is a high-voltage working mode, and the control module can set different clamping voltages according to different threshold voltages vth. The above functions can be realized by an analog switch or a logic gate circuit controlled by the comparator. It should be noted that the specific circuit structure of the control module is not limited in the embodiments of the present application, as long as the control module can generate a corresponding protection voltage based on the detected voltage of the power supply.

[0053] The embodiments of the present application realize automatic configuration of the clamping voltage through the control module, so that the entire driving circuit can be "plug and play" to adapt to different power supply environments without external software or firmware intervention, thereby simplifying the design complexity of the system level and reducing the risk of chip damage caused by configuration errors, thereby improving the robustness and reliability of the entire system.

[0054] In one embodiment, the control module comprises an analog circuit. Specifically, the control module can be an analog or mixed-signal circuit capable of automatically detecting the supply voltage VDDQ and outputting appropriate pull-up and pull-down clamp voltages to the driver circuit according to the detection result. The input of the module can be connected to the power supply VDDQ of the system, and the output can be connected to the gate of the third transistor in all driver circuits in the transmitter circuit.

[0055] The third transistor in the above-mentioned driver circuit, whose gate voltage is controlled by the clamp voltage, can generate a certain voltage drop across itself, thus sharing a portion of the total voltage, so as to ensure that the voltage borne by the first transistor and the second transistor in series in the same path is within the safe working range thereof, preventing them from being broken down by high voltage. By introducing and dynamically controlling the third transistor, the driver circuit of the embodiment of the present application can safely and reliably work under a plurality of different high and low supply voltages without sacrificing the impedance calibration function, thus realizing wide-range voltage compatibility. Among them, the data driving, impedance calibration and voltage protection functions are integrated in the same current path by using a three-stage cascode MOS tube structure, and the working state of the transistor is controlled by an independent clamp voltage, thus realizing adaptive switching of high and low supply voltages.

[0056] In one exemplary embodiment, as shown in Figure 4 The present application also provides a transmitter circuit, which at least comprises the above-mentioned driver circuit.

[0057] Specifically, in order to realize adjustable driving capability and accurate output impedance matching, the entire transmitter circuit can comprise a plurality of parallel driver circuits, Figure 4 which are schematically shown as driver circuits X1 to XN and XN to X2N, where N is a positive integer. By selectively turning on or off these parallel driver circuits, the total driving strength and output impedance of the transmitter can be programmed and controlled.

[0058] Among them, each driver circuit adopts a three-stage transistor structure. Exemplarily, in one driver circuit, the pull-up circuit and the pull-down circuit both adopt a cascode structure formed by three metal oxide semiconductor transistors in series.

[0059] In one exemplary embodiment, a semiconductor memory is provided, which at least comprises a transmitter circuit comprising the above-mentioned driver circuit.

[0060] Specifically, the semiconductor memory can further include a receiver circuit. Exemplarily, the semiconductor memory can be a dynamic random access memory (DRAM). For the DRAM, not only can the memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, etc. be met, but also the memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc. can be met, which are not limited in the present application.

[0061] In one exemplary embodiment, as shown in Figure 5 A data transmission method is provided, which is applied to the above-mentioned driving circuit or the transmitter circuit, and the following steps S202 to S206 are described by way of example.

[0062] In step S202, a first transistor in a pull-up circuit and a pull-down circuit is controlled according to a trim code to adjust an output impedance of the transmitter circuit; the pull-up circuit is connected between a power supply and an output terminal, and the pull-down circuit is connected between the output terminal and a ground.

[0063] Specifically, the adjustment of the impedance is realized by the trim code. Exemplarily, the pull-up trim code and the pull-down trim code can be two independent signals, such as binary signals. It should be noted that the encoding method of the trim code is not limited in the present application.

[0064] Based on the pull-up circuit and the pull-down circuit with the three-stage transistor structure, the impedance of the transmitter circuit (TX) can be adjusted to a target value by the trim code.

[0065] In step S204, a second transistor in the pull-up circuit and the pull-down circuit is controlled according to a data signal to transmit data through the output terminal.

[0066] Specifically, the data signal can refer to pull-up data (PU data) and pull-down data (PD data); the embodiment of the present application can control the conduction or turn-off of the second transistor in the pull-up circuit and the pull-down circuit according to the data signal, and then transmit data through the output terminal.

[0067] In step S206, a third transistor in the pull-up circuit and the pull-down circuit is controlled according to a protection voltage to protect the first transistor and the second transistor; wherein the first transistor, the second transistor and the third transistor are connected in sequence.

[0068] Specifically, the first transistor and the second transistor can be protected by the third transistor controlled by the protection voltage, and then high-quality signal transmission can be ensured under various working conditions.

[0069] In one of the embodiments, the protection voltage includes a clamping voltage; and the controlling the third transistor in the pull-up circuit and the pull-down circuit according to the protection voltage includes: when the voltage of the power supply is a low voltage, taking the voltage of the power supply as the clamping voltage; and when the voltage of the power supply is a high voltage, determining the clamping voltage according to a threshold voltage of the third transistor.

[0070] For the specific implementation of the data transmission method, reference can be made to the description of the driving circuit above, which will not be repeated here.

[0071] It should be understood that, although each step in the flowchart involved in each embodiment as described above is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and any non-contradictory combination formed by the combination shall be considered within the scope of the present application.

[0072] Each technical feature of the above embodiments can be combined arbitrarily, and in order to make the description concise, not all possible combinations of each technical feature in the above embodiments are described, however, as long as the combination of these technical features does not exist contradictions, it should be considered as the scope of the present application.

[0073] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that, for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A driving circuit, characterized in that, It includes a pull-up circuit connected between the power supply and the output terminal, and a pull-down circuit connected between the output terminal and ground; both the pull-up circuit and the pull-down circuit include the following components connected in sequence: The first transistor is used to adjust the output impedance; The second transistor is used to transmit data; as well as The third transistor is used to divide the voltage according to the protection voltage to protect the first transistor and the second transistor; The protection voltage includes a clamping voltage; the third transistor is configured to: When the voltage of the power supply is low, the voltage of the power supply is used as the clamping voltage; and When the voltage of the power supply is high, the clamping voltage is determined based on the threshold voltage of the third transistor.

2. The driving circuit according to claim 1, characterized in that, The transistor in the pull-up circuit is a PMOS transistor, and the transistor in the pull-down circuit is an NMOS transistor.

3. The driving circuit according to claim 2, characterized in that, In the pull-up circuit, the first transistor, the second transistor, and the third transistor are connected in series along the direction from the power supply to the output terminal; and In the pull-down circuit, the third transistor, the second transistor, and the first transistor are connected in series in the direction from the output terminal to the ground.

4. The driving circuit according to claim 1, characterized in that, Also includes: The control module is used to detect the voltage of the power supply and generate the protection voltage based on the detection result.

5. The driving circuit according to claim 4, characterized in that, The control module includes analog circuitry.

6. A transmitter circuit, characterized in that, The transmitter circuit includes at least the drive circuit as described in any one of claims 1 to 5.

7. A semiconductor memory, characterized in that, The semiconductor memory includes at least a transmitter circuit, which includes a driving circuit as described in any one of claims 1 to 5.

8. A data transmission method, characterized in that, The method includes: The first transistor in the pull-up and pull-down circuits is controlled according to the calibration code to adjust the output impedance of the transmitter circuit; the pull-up circuit is connected between the power supply and the output terminal, and the pull-down circuit is connected between the output terminal and ground. The second transistor in the pull-up circuit and the pull-down circuit is controlled according to the data signal to transmit data through the output terminal; The third transistor in the pull-up circuit and the pull-down circuit is controlled according to the protection voltage to protect the first transistor and the second transistor; wherein the first transistor, the second transistor and the third transistor are connected in sequence; The protection voltage includes a clamping voltage; controlling the third transistor in the pull-up circuit and the pull-down circuit according to the protection voltage includes: When the voltage of the power supply is low, the voltage of the power supply is used as the clamping voltage; When the voltage of the power supply is high, the clamping voltage is determined based on the threshold voltage of the third transistor.

9. The method according to claim 8, characterized in that, The method further includes: The voltage of the power supply is detected, and the protection voltage is generated based on the detection result.

10. The method according to claim 8, characterized in that, Detecting the voltage of the power supply includes: The voltage of the power supply is compared with the reference voltage to obtain the comparison result.

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