Magnetoresistive weight storage circuit, architecture, spiking neural network magnetic computing acceleration chip system and electronic device

Abstract

The application provides a magnetoresistance weight storage circuit, architecture, pulse neural network magnetic computing acceleration chip system and electronic equipment. The magnetoresistance weight storage circuit is used for storing weight values of a magnetoresistance weight storage architecture. The magnetoresistance weight storage circuit comprises a plurality of weight units which are fully connected in a matrix form. Each weight unit comprises a plurality of groups of complementary voltage-controlled magnetic anisotropy magnetic tunnel junction devices. Each group of complementary voltage-controlled magnetic anisotropy magnetic tunnel junction devices comprises two magnetic tunnel junction elements with opposite magnetoresistance states. The plurality of groups of complementary voltage-controlled magnetic anisotropy magnetic tunnel junction devices are connected in series. The magnetoresistance weight storage circuit of the application adopts a series voltage division topology, generates a linear reference voltage by using the resistance state difference of a pair of complementary voltage-controlled magnetic anisotropy magnetic tunnel junction devices, significantly improves the signal sampling margin, and reduces the process sensitivity.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a magnetoresistive weighted storage circuit, architecture, spiking neural network magnetic computing acceleration chip system, and electronic device. Background Technology

[0002] Neuromorphic computing is a computing paradigm inspired by biological nervous systems. Its core lies in simulating the dynamic information processing mechanisms of neurons and synapses, overcoming the bottlenecks of traditional computing architectures through asynchronous event-driven approaches, spatiotemporal coding, and energy efficiency optimization. Compared to the traditional von Neumann architecture, neuromorphic computing systems can significantly reduce power consumption and improve computational efficiency, making them particularly suitable for energy-intensive applications such as edge computing, the Internet of Things (IoT), and real-time signal processing.

[0003] In the field of deep learning, traditional Artificial Neural Networks (ANNs) rely on continuous real-number operations, employ activation functions (such as ReLU and ELU) for nonlinear transformations, and are trained using backpropagation algorithms. However, the computational methods of ANNs differ significantly from those of biological neural systems, leading to challenges in energy efficiency and real-time performance. In contrast, the Spiking Neural Network (SNN), as a third-generation neural network model, is closer to the operating mechanism of biological neurons, offering higher biological interpretability and computational efficiency.

[0004] The core features of SNNs lie in their neuron model and information encoding method. Specifically, SNNs employ a Leaky Integrate-and-Fire (LIF) model to simulate the dynamic behavior of biological neurons, where neurons generate discrete pulse signals through the accumulation of membrane potential and threshold triggering mechanisms. This event-based spatiotemporal encoding method enables SNNs to transmit information with sparse pulse sequences, thereby significantly reducing computational and communication overhead.

[0005] Despite the advantages of SNNs in terms of energy efficiency and biological rationality, their hardware implementation still faces several challenges, including:

[0006] High computational complexity: The impulsive dynamics of SNNs make their computation process more complex than that of ANNs, which traditional computing architectures struggle to support efficiently.

[0007] Training difficulty: Due to the discreteness of pulse signals, the training algorithm of SNN is difficult to directly apply backpropagation, which limits its performance in complex tasks.

[0008] High hardware resource consumption: Existing neuromorphic chips usually require dedicated circuit design, making it difficult to flexibly adapt to SNN models of different sizes.

[0009] Therefore, there is an urgent need for an efficient and scalable neuromorphic computing architecture that can improve the computational performance and training efficiency of SNNs while ensuring low power consumption, so as to meet the needs of edge intelligence and real-time signal processing. Summary of the Invention

[0010] In view of this, firstly, embodiments of this application provide a magnetoresistive weight storage circuit, which is used to store the weight values ​​of a magnetoresistive weight storage architecture;

[0011] The magnetoresistive weighted storage circuit includes multiple weight units, which are fully connected in matrix form.

[0012] Each weighting unit includes multiple sets of complementary voltage-controlled magnetic anisotropic magnetic tunnel junction devices, wherein each set of complementary voltage-controlled magnetic anisotropic magnetic tunnel junction devices contains two magnetic tunnel junction elements with opposite magnetoresistance states.

[0013] The multiple sets of complementary voltage-controlled magnetic anisotropic magnetic tunnel junction devices are connected in series.

[0014] Optionally, the weighting unit achieves N different weight values ​​through 2*(N-1) different resistance states of the voltage-controlled magnetic anisotropic magnetic tunnel junction device;

[0015] When the coded value corresponding to the voltage-controlled magnetic anisotropic magnetic tunnel junction device is 0, it indicates a low-resistance state;

[0016] When the coding value corresponding to the voltage-controlled magnetic anisotropic magnetic tunnel junction device is 1, it indicates a high-resistivity state.

[0017] Optionally, the mapping relationship between the weight value of the weighting unit and the magnetoresistance state of the voltage-controlled magnetic anisotropic tunnel junction device is as follows:

[0018] Different weight values ​​can be achieved by combining the low-resistivity and high-resistivity configurations of the magnetic anisotropic tunnel junction with different voltages.

[0019] When all voltage-controlled magnetic anisotropic tunnel junction devices in the pull-up network of the weighting unit are in a low-resistance state, the weighting unit corresponds to the maximum weight value.

[0020] When all voltage-controlled magnetic anisotropic tunnel junction devices in the pull-down network of the weighting unit are in a high-resistivity state, the weighting unit corresponds to the minimum weight value.

[0021] In a second aspect, embodiments of this application provide a magnetoresistive weighted storage architecture, which includes a magnetoresistive weighted storage circuit as described in any of the first aspects, an integral-leakage-ignition neuron module, and a voltage-controlled current source array;

[0022] The output of each column of weighted units is connected to an integral-leak-ignition neuron;

[0023] The input pulse triggers the corresponding weighting unit to output a reference voltage;

[0024] The voltage-controlled current source array converts the reference voltage into a charging current, driving the membrane potential integration of the integral-leakage-ignition neuron.

[0025] When the membrane potential exceeds the threshold, the magnetoresistive weighted storage architecture outputs a pulse and resets the integral-leakage-ignition neuron.

[0026] Optionally, the magnetoresistive weighted storage architecture asynchronously responds to input pulse signals;

[0027] The weighting unit is activated only when triggered by an input pulse;

[0028] The magnetoresistive weighted storage architecture has no global clock signal.

[0029] Optionally, the integral-leakage-ignition neuron includes:

[0030] Integrating capacitors are used to accumulate input current and form a film potential;

[0031] The leakage resistor is connected in parallel with the integrating capacitor to achieve membrane potential decay.

[0032] The comparator circuit triggers an output pulse when the membrane potential exceeds a threshold.

[0033] The reset circuit resets the membrane potential after the output pulse.

[0034] Thirdly, embodiments of this application provide a multi-layer magnetoresistive weighted storage architecture, which includes: an input layer, a hidden layer, and an output layer;

[0035] The input layer is used to receive the preprocessed pulse signal;

[0036] Each of the hidden layers includes multiple integral-leak-ignition neurons, the number of which is determined based on the volume of the multi-layer magnetoresistive weighted storage architecture and the recognition accuracy of the multi-layer magnetoresistive weighted storage architecture.

[0037] The output layer is used to output the recognition results of the multi-layer magnetoresistive weighted storage architecture;

[0038] Each layer of integral-leakage-ignition neurons corresponds to a magnetoresistive weight storage circuit as described in any of the first aspects.

[0039] Optionally, the input layer, the hidden layer, and the output layer are triggered by a pulse signal, without the need for clock synchronization.

[0040] Fourthly, embodiments of this application provide a spiking neural network magnetic computing acceleration chip system, including the multi-layer magnetoresistive weighted storage architecture as described in any of the third aspects. The spiking neural network magnetic computing acceleration chip system is used to realize bionic neural network bionics or recognition based on the multi-layer magnetoresistive weighted storage architecture.

[0041] Fifthly, embodiments of this application provide an electronic device including a multilayer magnetoresistive weighted storage architecture as described in any of the third aspects, the electronic device being used to realize bionic neural bionics or recognition based on the multilayer magnetoresistive weighted storage architecture.

[0042] The magnetoresistive weighted storage circuit provided in this application adopts a series voltage divider topology and uses complementary voltage to control the resistance difference of the magnetic anisotropic magnetic tunnel junction device pair to generate a linear reference voltage, which significantly improves the signal sampling margin and reduces process sensitivity. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the LIF neuron model provided in the embodiments of this application;

[0044] Figure 2(a) is a schematic diagram of the SNN network architecture provided in an embodiment of this application;

[0045] Figure 2(b) is a schematic diagram of the working principle of the magnetoresistive weighted storage architecture provided in the embodiment of this application;

[0046] Figure 3(a) is a schematic diagram of the memory bit structure of the VCMA-MTJ device provided in the embodiment of this application; Figure 3(b) is a schematic diagram of the barrier change of the VCMA-MTJ provided in the embodiment of this application;

[0047] Figure 3(c) is a schematic diagram of the write waveform of the VCMA-MTJ device provided in the embodiment of this application;

[0048] Figure 4(a) is a schematic diagram of the implementation of multidimensional convolution operation in a conventional ANN accelerator provided in this application through a standard digital application-specific integrated circuit;

[0049] Figure 4(b) is a schematic diagram of the hardware implementation of the SNN digital domain provided in the embodiment of this application;

[0050] Figure 4(c) is a schematic diagram of the hardware implementation of the SNN simulation domain provided in the embodiments of this application;

[0051] Figure 4(d) is a schematic diagram of the implementation of the traditional ANN in-memory computing architecture provided in the embodiments of this application;

[0052] Figure 4(e) is a schematic diagram of the in-memory computing SNN architecture for weight reading and computation provided in the embodiments of this application;

[0053] Figure 4(f) is a schematic diagram of the in-memory computing SNN architecture for in-memory logic operations provided in an embodiment of this application;

[0054] Figure 5 This is a schematic diagram of the magnetoresistive weight storage circuit and magnetoresistive weight storage architecture provided in the embodiments of this application;

[0055] Figure 6(a) is a schematic diagram of the changes in membrane potential when different densities of input current are applied to a single biological neuron according to an embodiment of this application;

[0056] Figure 6(b) is a schematic diagram of the working waveform of the magnetoresistive weighted storage architecture provided in the embodiments of this application when pulses are input to synapses with different connection strengths;

[0057] Figure 7 A schematic diagram of the multi-layer magnetoresistive weighted storage architecture provided in this application embodiment;

[0058] Figure 8 This is a weighted array layout for implementing handwritten digit recognition provided in an embodiment of this application;

[0059] Figure 9 A schematic diagram illustrating the peak power consumption and percentage of different weighted magnetoresistive weighted storage architectures provided in the embodiments of this application. Detailed Implementation

[0060] SNNs employ a leak-integration-fire model to simulate the dynamic behavior of biological neurons, where neurons generate discrete pulse signals through the accumulation of membrane potential and a threshold triggering mechanism. See details... Figure 1 , Figure 1 This is a schematic diagram of the LIF neuron model provided in the embodiments of this application, as shown below. Figure 1 As shown, SNN neurons include: membrane capacitance (C m The following components are used to simulate the cell membrane capacitance of biological neurons, responsible for accumulating input charge; the leakage resistor (R) is used to simulate the leakage characteristics of ion channels, allowing the membrane potential to decay naturally over time; the input pulse interface (I(t)) is used to receive pulse signals from presynaptic neurons; and the threshold comparator (V) is used to simulate the leakage characteristics of ion channels. m When the membrane voltage exceeds the threshold, an output pulse (Spike Out) is triggered.

[0061] When there is no external input, the voltage on the membrane capacitor decays naturally through the leakage resistance channel, exhibiting an exponentially decreasing curve, simulating the resting potential maintenance mechanism of biological neurons. When a pulse is input, the input pulse is converted into current through synaptic weights, charging the membrane capacitor and causing the membrane voltage to rise linearly (integration process). The integration rate depends on the frequency of the input pulse and the weight strength. When the membrane voltage exceeds a preset threshold, the neuron generates an output pulse and sets the membrane voltage of this neuron to the reset voltage. The reset neuron enters a brief refractory period.

[0062] The following describes the topology and working principle of the SNN, specifically referring to Figures 2(a) and 2(b). Figure 2(a) is a schematic diagram of the SNN network architecture provided in an embodiment of this application, and Figure 2(b) is a schematic diagram of the working principle of the magnetoresistive weighted storage architecture provided in an embodiment of this application. As shown in Figure 2(a), the SNN network architecture consists of multiple neuron layers, including: an input layer, used to receive external triggers (such as sensor data) and convert them into pulse sequences; hidden layers (which can be multiple), used for information processing and feature extraction, typically composed of LIF neurons; and an output layer, used to generate the final pulse output, which can be used for tasks such as classification and decision-making.

[0063] Figure 2(b) illustrates the working principle of the magnetoresistive weighted storage architecture. As shown in Figure 2(b), the input neuron receives external pulse signals (such as spikes from neurons in the previous layer); the weight array stores synaptic connection strengths, determining the degree of influence of the input pulse on the target neuron; and the LIF neuron integrates the weighted input and outputs a pulse when a threshold is reached. The synaptic mapping of the LIF neuron is the weight array, where the input signal is weighted and summed before being fed into the LIF neuron for leakage, integration, and firing operations. When a pulse is sent because the membrane voltage exceeds the threshold, the LIF neuron is set and enters a refractory period during which it does not respond to any input signals. Compared to traditional ANNs, SNNs are network models that are fired at the threshold crossing moment. They do not transmit information at the end of each propagation cycle, but only send signals to neighboring neurons when the membrane potential reaches the threshold. Information from external inputs is transmitted between multiple layers of the network in the form of pulses, eventually accumulating in a neuron in the output layer as the result of the SNN's operation.

[0064] It should be noted that the weighted array can be implemented using a voltage-controlled magnetic anisotropy magnetic tunnel junction (VCMA-MTJ) device. See Figures 3(a)-3(c) for details. Figure 3(a) is a schematic diagram of the storage bit structure of the VCMA-MTJ device provided in this embodiment; Figure 3(b) is a schematic diagram of the barrier change of the VCMA-MTJ device provided in this embodiment; Figure 3(c) is a schematic diagram of the write waveform of the VCMA-MTJ device provided in this embodiment.

[0065] As shown in Figure 3(a), the VCMA-MTJ is composed of a sandwich structure, in which the magnetization direction of the free layer is the same as that of the fixed layer, and has low impedance when the magnetization direction of the free layer is opposite to that of the fixed layer, and has high impedance when the magnetization direction of the free layer is opposite to that of the fixed layer.

[0066] Specifically, the top electrode material of the VCMA-MTJ can be a metal (such as Ta / Pt), which provides the electrical contact interface and applies the write voltage. The free layer material of the VCMA-MTJ can be a ferromagnetic material (such as CoFeB), and the magnetization direction of the free layer can be controlled by an electric field. The oxide layer material of the VCMA-MTJ can be an oxide (such as MgO), which is a quantum tunneling dielectric layer, and its resistance varies with the magnetization direction of the free layer. The fixed layer material of the VCMA-MTJ can be a pinned ferromagnet (such as a Co / Pd multilayer film), and its magnetization direction is fixed, serving as a reference for the magnetization state. The bottom electrode material of the VCMA-MTJ can be a metal (such as Ru), which is grounded and forms a perpendicular electric field with the top electrode.

[0067] Figure 3(b) illustrates the barrier modulation mechanism of VCMA-MTJ under an electric field. Initially, the magnetization direction of the free layer is fixed, resulting in an initial magnetic anisotropy barrier. Electron orbital hybridization at the interface forms a stable magnetic moment orientation. Applying a vertical electric field (V) induces charge accumulation at the interface, altering the electronic density of states distribution. The orbital hybridization intensity is modulated, and the magnetic anisotropy decreases (as shown in Figure 3(b)). Once the barrier is lowered to a level that thermal perturbation can overcome, the free layer magnetic moment flips, and the system enters a new steady state. Applying a reverse voltage raises the barrier again, stabilizing the magnetic moment and achieving non-volatile storage.

[0068] Figure 3(c) shows the timing of the write operation of VCMA-MTJ. The reversible switching of the magnetization direction is achieved by voltage pulse control, showing the regulation of the free layer magnetization direction by positive / negative voltage pulses, reflecting the dynamic transition from the high-resistivity state (AP) to the low-resistivity state (P).

[0069] In the initial state (0V), the free layer maintains its current magnetization direction (e.g., AP state). Applying a positive voltage (V) electric field lowers the magnetic anisotropy barrier, causing the free layer magnetic moment to flip to the P state. The magnetic moment locks in the new state (P state), and the resistance suddenly drops to a low level. A reverse electric field induces the magnetic moment to flip back to the AP state. This completes a full P→AP→P write cycle. It should be noted that picosecond-level pulses can switch the magnetoresistive state, and due to its large resistance, the write power consumption can be as low as 1fJ / bit.

[0070] It should also be noted that the hardware implementation of neural networks can be divided according to different processes and network deployments. See Figures 4(a)-4(f) for details. Figure 4(a) is a schematic diagram of the implementation of multidimensional convolution operations in a conventional ANN accelerator provided in this application through a standard digital application-specific integrated circuit (ASIC). Figure 4(a) shows a typical digital circuit architecture of a conventional artificial neural network (ANN) accelerator based on CMOS (Complementary Metal-Oxide-Semiconductor) technology. Its core is to implement parallel computation of multilayer neural networks through application-specific integrated circuits (ASICs). As shown in Figure 4(a), the weight matrix is ​​first read from memory into a register file, and the weight matrix is ​​distributed to each MAC (Multiply-Accumulate) unit through a cross-switching network. The input data is broadcast to all MAC units, and the matrix multiplication and accumulation operations are performed in parallel.

[0071] In the architecture shown in Figure 4(a), the presynaptic real activation values ​​and synaptic weights are stored in memory, while the postsynaptic activation values ​​are calculated through logic unit operations. Since multiply-accumulate and activation operations (such as ReLU) require a global clock to drive the associated timing circuitry, and the number of multiply-accumulate operations per convolutional layer is fixed, balancing resource consumption and performance presents a significant challenge.

[0072] Figure 4(b) is a schematic diagram of the SNN digital domain hardware implementation provided in this application embodiment. As shown in Figure 4(b), the digital domain SNN significantly reduces the number of multipliers in the logic unit by adopting a pulse sequence propagation mechanism, requiring only synaptic weight accumulation operations. This architecture typically requires an address decoder to locate the pulse signal and relies on a global clock for synchronization. It should be noted that most existing digital domain SNNs abandon the leakage design to reduce resource overhead, thus limiting their biomimeticity.

[0073] The analog domain SNN uses analog circuits to implement the functions of spiking neurons and synapses, as shown in Figure 4(c). Figure 4(c) is a schematic diagram of the hardware implementation of the SNN analog domain provided in this application embodiment. As shown in Figure 4(c), the typical hardware implementation structure of the SNN analog domain uses a capacitor to maintain the synaptic membrane potential V. mem The membrane voltage threshold comparison and reset operations are implemented using transistors. This analog circuit employs an event-driven mechanism, eliminating the need for a global clock and thus reducing power consumption, but it faces the challenge of static current leakage. Due to the significant impact of voltage drop on the metal lines and process variations on the analog domain SNN, large-scale deployment of synaptic arrays is difficult. It is worth noting that under CMOS process architecture, the energy consumption of a single synaptic operation remains in the tens of picojoules range in both digital and analog domain hardware implementations.

[0074] Figure 4(d) is a schematic diagram of the traditional ANN in-memory computing architecture provided in this application embodiment. As shown in Figure 4(d), the input real number is first converted from digital to analog signal. The converted analog signal is then directly used for multiplication and accumulation operations in the storage bits. Fast matrix operations are achieved by utilizing the superposition characteristics of current or voltage. The operation result is converted into a digital quantity through an analog-to-digital converter and output to the next processing stage. This in-memory computing method effectively eliminates the energy consumption overhead of data transfer in the traditional architecture and improves the efficiency of multiplication and accumulation operations by utilizing the superposition characteristics of analog signals. However, the peripheral circuits have high energy consumption and area overhead, especially the use of high-precision digital-to-analog and analog-to-digital conversion circuits, which leads to a significant increase in area and delay.

[0075] Figure 4(e) is a schematic diagram of the in-memory computing SNN architecture with weight readout and computation provided in an embodiment of this application. As shown in Figure 4(e), the weight data stored in the storage bits are read out sequentially. Each weight unit corresponds to a synaptic connection strength. The weight value is converted into an analog signal (such as voltage or current) by the readout circuit, reflecting its magnetoresistive state. The read weight signal is input to the weighted current source array. By controlling the output intensity of the current source, a charging current proportional to the weight value is generated. For example, a high weight value corresponds to a larger charging current, and a low weight value corresponds to a smaller current. The weighted current source charges the membrane capacitance of the target LIF neuron, and the membrane voltage gradually accumulates over time. When the membrane voltage exceeds a preset threshold voltage, the comparator triggers a pulse output, and the neuron transmits a binary pulse signal to the lower layer. At the same time, the membrane voltage is reset to the initial state. This SNN event-driven approach triggers computation only when there is a valid event input, thereby effectively minimizing the readout overhead. At the same time, the binary pulse eliminates the digital-to-analog conversion process, reducing circuit complexity.

[0076] Figure 4(f) is a schematic diagram of the in-memory computing SNN architecture for in-memory logic operations provided in an embodiment of this application. As shown in Figure 4(f), logic operations are performed directly in the memory array without needing to read the weight data to an external circuit. For example, the resistance states (low resistance state "0" or high resistance state "1") of the magnetic tunnel junction (MTJ) are used to directly participate in Boolean operations or pulse signal integration. Through the series or parallel combination of MTJs, the current / voltage superposition of multiple input signals is realized, completing synaptic weighting and integration operations. Input pulses trigger local circuit responses without the need for global clock synchronization. When an input pulse arrives, the corresponding MTJ array is activated, generating a reference voltage or current related to the weights. The membrane capacitor performs dynamic integration based on the weighted sum of the input signals. When the membrane voltage exceeds the threshold, the neuron immediately triggers the output pulse and resets. The digital-to-analog conversion and analog-to-digital conversion links are completely eliminated, and the computation is driven directly by the switching characteristics of binary pulses, significantly reducing power consumption and latency. For example, the input pulse directly controls the gating of the MTJ array, and the current path is naturally shunted through the magnetoresistive state to realize multiplication and accumulation operations. It can achieve asynchronous operation, offering higher energy efficiency and biomimetic performance. However, nonlinear changes in resistance and device fluctuations can affect system stability, and the current inability of MTJs to achieve multi-value storage leads to lower computational accuracy. One approach is to connect multiple MTJs in parallel to form a weighting unit for current distribution, but parallel connection reduces the total resistance change caused by individual magnetoresistive switching, resulting in a significant decrease in margin for multi-value weighting. Furthermore, the parallel array also leads to substantial power consumption. These challenges necessitate innovative circuit design.

[0077] In summary, the core advantage of SNNs lies in reducing computational complexity by sparsifying pulse sequences. Compared to CMOS architectures, in-memory computing architectures can achieve higher computational parallelism and energy efficiency, but they also present challenges such as deploying multi-valued weights.

[0078] To address the issue of multi-weight deployment in the aforementioned SNN networks, this application provides a magnetoresistive weight storage circuit, as detailed below. Figure 5 . Figure 5 This is a schematic diagram of the magnetoresistive weight storage circuit and magnetoresistive weight storage architecture provided in the embodiments of this application. Figure 5 As shown, the magnetoresistive weighted storage circuit includes multiple weight units, which are fully connected in a matrix. Each weight unit includes multiple sets of complementary voltage-controlled magnetic anisotropic magnetic tunnel junction devices. Each set of complementary voltage-controlled magnetic anisotropic magnetic tunnel junction devices contains two magnetic tunnel junction elements with opposite magnetoresistive states. The multiple sets of complementary voltage-controlled magnetic anisotropic magnetic tunnel junction devices are connected in series.

[0079] For example, Figure 5The weighting unit shown includes state-complementary MTJ pairs. Each weighting unit achieves N different weight values ​​through 2*(N-1) voltage-controlled magnetic anisotropic tunnel junction devices. Figure 5 As shown, 14 voltage-controlled magnetic anisotropic tunnel junction devices are used to achieve different resistance states, resulting in 8 different weight values. A code value of 0 for the voltage-controlled magnetic anisotropic tunnel junction device represents a low resistance state; a code value of 1 for the voltage-controlled magnetic anisotropic tunnel junction device represents a high resistance state. Figure 5 The example given is 3 bits, but this application does not impose any specific limitations on this.

[0080] Different weighting values ​​can be achieved by controlling the combination of low-resistivity and high-resistivity configurations of magnetically anisotropic tunnel junction devices with different voltages; for example... Figure 5 As shown, the weight unit includes a pull-up network and a pull-down network. The pull-up network consists of MTJ1-MTJ7 ( Figure 5 The drop-down network consists of MTJ8-MTJ14 (1-7). Figure 5 Composed of (8-14) in the weighted unit. When all voltage-controlled anisotropic magnetic tunnel junction devices in the pull-up network of the weighted unit are in a low-resistance state, the weighted unit corresponds to the maximum weight value; when all voltage-controlled anisotropic magnetic tunnel junction devices in the pull-down network of the weighted unit are in a high-resistance state, the weighted unit corresponds to the minimum weight value. For example... Figure 5 As shown, MTJ1 and MTJ8 form a reference pair with complementary magnetoresistive configuration (MTJ1's low-resistivity state corresponds to MTJ8's high-resistivity state, and vice versa), achieving state mutual exclusion through physical symmetry. The MTJ2-MTJ9, MTJ3-MTJ10, and other unit groups follow the same pattern, constructing a structurally symmetrical complementary unit array. By controlling the combination of magnetoresistive states from MTJ1 to MTJ14 (covering eight different weighted states from all low-resistivity to all high-resistivity), multi-valued weight representation with 3-bit precision can be achieved at the synaptic level, as detailed in Table 1, which shows the weight-magnetoresistive state mapping relationship provided in this application.

[0081] Table 1

[0082]

[0083] like Figure 5 The magnetoresistive weighted storage circuit shown adopts a series voltage divider topology and uses the resistance difference of complementary MTJ pairs to generate a linear reference voltage. Combined with a dynamic threshold calibration module, it significantly improves the signal sampling margin while reducing process sensitivity.

[0084] It should be noted that, Figure 5The MTJ device is used as an example for illustration, but other non-volatile memories, such as SOT-MTJ / STT-MTJ / RRAM / PCRAM / FeRAM, can also be used to implement the magnetoresistive weighted storage circuit in this architecture. This application does not impose specific restrictions on the voltage-controlled magnetic anisotropic magnetic tunnel junction device used.

[0085] Figure 5 A schematic diagram of the magnetoresistive weighted storage architecture is also provided. For example... Figure 5 The illustrated magnetoresistive weighted storage circuit adopts a row-column topology, consisting of j columns of channels. Each column integrates i voltage-controlled magnetic anisotropic tunnel junctions, and the output of each column's weight unit is connected to a LIF neuron. The number of array rows (i) is dynamically configured based on the input neuron size, and the number of columns (j) can be pruned as needed to adapt to the deployment requirements of different levels of magnetoresistive weighted storage architectures (SNNs). All weight units within the same column achieve parallel weight updates through shared word lines / bit lines, ensuring timing consistency. Weight values ​​are encoded using complementary magnetoresistive states, and common-mode noise is suppressed through differential signal paths, improving storage reliability. Figure 5 In the magnetoresistive weighted storage architecture shown, the input pulse triggers the row address decoder, activating the weight unit of the corresponding row. This converts the magnetoresistive state into an analog reference voltage, which is then output to the voltage-controlled current source array. The voltage-controlled current source generates a proportional current based on the reference voltage, integrally charging the membrane capacitance of the target LIF neuron. When the membrane potential exceeds the threshold voltage, the comparator outputs a pulse signal and triggers a reset of the integral-leakage-ignition neuron, simultaneously generating a descending pulse event to output a pulse to the next layer of neurons.

[0086] Furthermore, Figure 5 The integral-leakage-ignition neuron in the magnetoresistive weighted storage architecture shown includes: an integral capacitor for accumulating input current and forming a membrane potential; a leakage resistor connected in parallel with the integral capacitor to achieve membrane potential decay; a comparator circuit that triggers an output pulse when the membrane potential exceeds a threshold; and a reset circuit that resets the membrane potential after the output pulse.

[0087] In summary, the magnetoresistive weighted storage architecture provided in this application can support dynamic reconstruction of the number of columns (j) and rows (i), adapting to variable-scale SNN topologies (such as dynamic pruning and inter-layer heterogeneity). It achieves direct magnetoresistive-voltage conversion without any digital-to-analog conversion step.

[0088] The following comparison of the membrane voltage changes with input pulses in biological neurons and the magnetoresistive weighted storage architecture provided in this application is shown in Figures 6(a) and 6(b). Figure 6(a) is a schematic diagram of the membrane potential changes when different densities of input current are applied to a single biological neuron according to the embodiments of this application. As shown in Figure 6(a), under the condition of no external stimulation, the neuronal membrane potential is stable at the resting value, and the electrochemical equilibrium is maintained by the ion concentration gradient (high K⁺ intracellularly, high Na⁺ extracellularly) established by the active transport of Na⁺ / K⁺-ATPase ion pump and the membrane leakage channel (K⁺ leak channel). The input pulse triggers the opening of the inward Na ion channel, and the membrane potential depolarizes to the threshold potential. The voltage-gated Na⁺ channel opens instantaneously, triggering a rapid influx of Na⁺, and the membrane potential rises rapidly to the peak value. When the membrane potential reaches the peak value, the K⁺ channel activation dominates the repolarization process, and the membrane potential recovers to the resting level in an exponential decay manner. When the synaptic connection strength of the neuron is low, the membrane potential perturbation amplitude is insufficient to trigger an action potential, which manifests as a localized hierarchical potential. High-intensity synaptic input can cause the membrane potential to exceed the threshold potential.

[0089] Figure 6(b) is a schematic diagram of the working waveforms of the magnetoresistive weighted storage architecture provided in this application when pulses are input to synapses with different connection strengths. Figure 6(b) uses a threshold parameter of 600mV as the test benchmark. Experimental data shows that when the input pulse signal is injected through the weight unit, the weighted input current integrally charges the membrane capacitance, causing the membrane potential to exhibit an exponential increase characteristic, and its increase rate is positively correlated with the weight value; when the membrane potential exceeds the preset threshold, the magnetoresistive weighted storage architecture generates a pulse signal output, and at the same time triggers the reset switch to clear the charge of the neuron; during the pulse interval, the discharge circuit formed by the membrane resistor realizes the membrane potential decay, effectively simulating the leakage integral characteristics of biological neurons. This application realizes the circuit-level simulation of the behavior of biological neurons through time-scale compression technology, compressing the millisecond-level pulse response of biological neurons to the nanosecond level (1ns pulse width), while maintaining key biological characteristics such as the discharge threshold mechanism and refractory period characteristics.

[0090] Furthermore, on Figure 5 By extending the provided magnetoresistive weighted storage architecture, a multi-layer magnetoresistive weighted storage architecture can be obtained; see details below. Figure 7 . Figure 7 This application provides a schematic diagram of a multi-layer magnetoresistive weighted storage architecture. (See the attached diagram.) Figure 7The multilayer spiking neural network shown includes: an input layer for receiving preprocessed spiking signals; hidden layers, each containing multiple integral-leak-fire neurons, the number of which is determined by the volume and recognition accuracy of the multilayer magnetoresistive weighted storage architecture; and an output layer for outputting the recognition results of the multilayer magnetoresistive weighted storage architecture. It should be noted that each integral-leak-fire neuron corresponds to one... Figure 5 The magnetoresistive weighted storage circuit shown is shown.

[0091] Specifically, the image is preprocessed in the host computer, and an input layer is deployed. Hidden layers and an output layer are deployed in the chip. By adjusting the number of neurons in the two hidden layers and conducting multiple training and testing experiments, a balance between accuracy and model size can be explored. Specifically, too many neurons in the hidden layers lead to a large model size and increased hardware resource consumption, while too few neurons reduce accuracy. Therefore, a suitable trade-off needs to be found. For example, this application selects 40 and 20 LIF neurons in the two hidden layers, respectively, and introduces quantization error analysis, achieving a recognition accuracy of 91%. Figure 7 It can be seen that the input layer, hidden layer and output layer of the multilayer spiking neural network provided in this application are triggered by pulse signals, without the need for clock synchronization.

[0092] This application also provides a layout design for a magnetoresistive weighted storage circuit, see details below. Figure 8 . Figure 8 This is a weighted array layout for implementing handwritten digit recognition provided in an embodiment of this application. Figure 8 Based on a 28nm process, this system is used for neuromorphic computing simulations. The storage array supports 3-bit weight deployment. The weight array has 16 rows of input pulses and can output 16 reference voltages. One array corresponds to one neuron. The reference voltage is subsequently input into a current source array to charge the neuron. The effective storage capacity of the array is 224 bits, with a total area of ​​16.31 * 7.31 = 119.2261 μm. 2 .

[0093] In some embodiments, the multi-layer magnetoresistive weighted storage architecture provided in this application can be used in a spiking neural network magnetic computing acceleration chip system, which is used to realize bionic neural network bionics or recognition based on the above-described multi-layer magnetoresistive weighted storage architecture.

[0094] In other embodiments, the multilayer magnetoresistive weighted storage architecture provided in this application can be used in electronic devices, which can then be used to realize bionic neural bionics or recognition based on the multilayer magnetoresistive weighted storage architecture.

[0095] In summary, compared to existing magnetoresistive weighted memory architecture inference chip technology based on magnetic storage, the magnetoresistive weighted memory architecture provided in this application has significant power consumption advantages and biomimetic characteristics. Existing magnetoresistive weighted memory architectures employ a scheme where the weights of the read array are fed into a weighted current source for calculation, resulting in significant power consumption during weight reads. Furthermore, the weighted current source itself incurs substantial power overhead. Due to the latency of read operations, the operating speed is slow, making it difficult for existing magnetoresistive weighted memory architectures to achieve true real-time processing.

[0096] Figure 9 By comparing and analyzing the energy efficiency performance of magnetoresistive weighted storage hardware architectures with different weighting structures, the significant advantages of the proposed magnetoresistive weighted storage circuit scheme compared with the traditional parallel architecture are quantitatively demonstrated. Figure 9 A schematic diagram illustrating the peak power consumption and percentage of different weighted magnetoresistive weighted storage architectures provided in the embodiments of this application.

[0097] like Figure 9 As shown, the chart includes a peak power consumption comparison histogram and an energy consumption ratio ring chart. In the peak power consumption comparison chart, existing technologies use multiple MTJ devices connected in parallel to achieve multi-value weighted storage, and complete multiplication and accumulation operations through current superposition. This application uses complementary MTJ pairs to generate a reference voltage through series voltage division, driving a voltage-controlled current source to charge neurons. Under the same input pulse density, the peak power consumption of the series architecture is reduced by 5.32 times. In the parallel scheme, the parallel connection of multiple MTJs limits the variation of the total resistance, requiring a large current drive to maintain signal margin, resulting in high dynamic power consumption. The series scheme utilizes the linear voltage division characteristics of complementary MTJ pairs to generate a stable reference voltage at low current, combined with an event-driven voltage-controlled current source (activated only during valid input pulses), significantly reducing switching losses.

[0098] In the energy consumption distribution diagram, the weight array operation of the traditional parallel architecture (including MTJ reading and current source drive) accounts for 40% of the total energy consumption; neuron charging and discharging accounts for 56%; and peripheral circuits (such as clock synchronization and analog-to-digital conversion) account for 4%.

[0099] This application directly generates the weighted voltage through MTJ series voltage division, eliminating the weight reading and digital-to-analog conversion stages in traditional architectures and reducing data transfer energy consumption. The corresponding weighted unit is activated only when the input pulse arrives, avoiding static power consumption caused by global clock synchronization.

[0100] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable storage medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0102] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0103] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0104] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0105] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0106] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0107] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0108] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A magnetoresistive weighted storage circuit, characterized in that, The magnetoresistive weight storage circuit is used to store the weight values ​​of the magnetoresistive weight storage architecture; The magnetoresistive weighted storage circuit includes multiple weight units, which are fully connected in matrix form. Each weighting unit includes multiple sets of complementary voltage-controlled magnetic anisotropic magnetic tunnel junction devices, wherein each set of complementary voltage-controlled magnetic anisotropic magnetic tunnel junction devices contains two magnetic tunnel junction elements with opposite magnetoresistance states. After the magnetic tunnel junction elements with the same magnetic reluctance state in each group of voltage-controlled magnetic anisotropic magnetic tunnel junction devices are connected in series, magnetic tunnel junction elements with opposite magnetic reluctance states are then connected in series.

2. The magnetoresistive weighted storage circuit according to claim 1, characterized in that, The weighting unit achieves N different weight values ​​through 2*(N-1) different resistance states of the voltage-controlled magnetic anisotropic magnetic tunnel junction device, where N is an integer greater than 1; When the coded value corresponding to the voltage-controlled magnetic anisotropic magnetic tunnel junction device is 0, it indicates a low-resistance state; When the coding value corresponding to the voltage-controlled magnetic anisotropic magnetic tunnel junction device is 1, it indicates a high-resistivity state.

3. The magnetoresistive weighted storage circuit according to claim 1, characterized in that, The mapping relationship between the weight value of the weighting unit and the magnetoresistance state of the voltage-controlled magnetic anisotropic magnetic tunnel junction device is as follows: Different weight values ​​can be achieved by combining the low-resistivity and high-resistivity configurations of the magnetic anisotropic tunnel junction with different voltages. When all voltage-controlled magnetic anisotropic tunnel junction devices in the pull-up network of the weighting unit are in a low-resistance state, the weighting unit corresponds to the maximum weight value. When all voltage-controlled magnetic anisotropic tunnel junction devices in the pull-up network of the weighting unit are in a high-resistance state, and all voltage-controlled magnetic anisotropic tunnel junction devices in the pull-down network of the weighting unit are in a low-resistance state, the weighting unit corresponds to the minimum weight value.

4. A magnetoresistive weighted storage architecture, characterized in that, The magnetoresistive weighted storage architecture includes the magnetoresistive weighted storage circuit, the integral-leakage-ignition neuron module, and the voltage-controlled current source array as described in any one of claims 1-3; The output of each column of weighted units is connected to an integral-leak-ignition neuron; The input pulse triggers the corresponding weighting unit to output a reference voltage; The voltage-controlled current source array converts the reference voltage into a charging current, driving the membrane potential integration of the integral-leakage-ignition neuron. When the membrane potential exceeds the threshold, the magnetoresistive weighted storage architecture outputs a pulse and resets the integral-leakage-ignition neuron.

5. The magnetoresistive weighted storage architecture according to claim 4, characterized in that, The magnetoresistive weighted storage architecture responds asynchronously to input pulse signals; The weighting unit is activated only when triggered by an input pulse; The magnetoresistive weighted storage architecture has no global clock signal.

6. The magnetoresistive weighted storage architecture according to claim 4, characterized in that, The integral-leakage-ignition neuron includes: Integrating capacitors are used to accumulate input current and form a film potential; The leakage resistor is connected in parallel with the integrating capacitor to achieve membrane potential decay. The comparator circuit triggers an output pulse when the membrane potential exceeds a threshold. The reset circuit resets the membrane potential after the output pulse.

7. A multi-layer magnetoresistive weighted storage architecture, characterized in that, The multi-layer magnetoresistive weighted storage architecture includes: an input layer, a hidden layer, and an output layer; The input layer is used to receive the preprocessed pulse signal; Each of the hidden layers includes multiple integral-leak-ignition neurons, the number of which is determined based on the volume of the multi-layer magnetoresistive weighted storage architecture and the recognition accuracy of the multi-layer magnetoresistive weighted storage architecture. The output layer is used to output the recognition results of the multi-layer magnetoresistive weighted storage architecture; Each layer of integral-leakage-ignition neurons corresponds to a magnetoresistive weight storage circuit as described in any one of claims 1-3.

8. The multilayer magnetoresistive weighted storage architecture according to claim 7, characterized in that, The input layer, the hidden layer, and the output layer are triggered by pulse signals, eliminating the need for clock synchronization.

9. A magnetic computing acceleration chip system for spiking neural networks, characterized in that, Including the multi-layer magnetoresistive weighted storage architecture as described in any one of claims 7-8, the spiking neural network magnetic computing acceleration chip system is used to realize bionic neural bionics or recognition based on the multi-layer magnetoresistive weighted storage architecture.

10. An electronic device, characterized in that, Including the multi-layer magnetoresistive weighted storage architecture as described in any one of claims 7-8, the electronic device is used to realize bionic neural bionics or recognition based on the multi-layer magnetoresistive weighted storage architecture.

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