Dram testing method, apparatus, and storage medium

Abstract

The application discloses a DRAM test method, device and storage medium, relates to the technical field of memory test, and discloses a DRAM test method, which comprises the following steps: determining a target bank in each bank of DRAM, and acquiring a DRAM address; generating a system address corresponding to the target bank based on a column address and a row address in the DRAM address, and storing the system address to a DRAM address table; performing a write-read operation on the target bank based on the system address in the DRAM address table; and returning to the step of sequentially determining the target bank in each bank of DRAM when the write-read operation on the target bank is completed. The application generates the system address of the target bank which needs to be tested, performs the write-read operation on each system address of the target bank according to the DRAM address table of the system address, so that the continuous write-read test on the same bank is realized, the test time consumption of the same bank in the DRAM is reduced, the test pressure of the same bank in the DRAM is increased at a faster write-read efficiency, and the test efficiency of the SLT test on the DRAM is improved.

Description

Technical Field

[0001] This application relates to the field of memory testing technology, and in particular to a DRAM testing method, apparatus and storage medium. Background Technology

[0002] System-level testing (SLT) refers to testing the chip under test (DUT), such as DRAM (Dynamic Random Access Memory), in simulated end-user scenarios. During SLT testing, the controller distributes consecutive system addresses across different banks within the DRAM. Systematic tests, such as write / read tests, access these consecutive system addresses via software logic. However, since these consecutive system addresses correspond to different banks, the actual banks accessed through these consecutive system addresses vary. When testing or repeatedly testing the same bank within the DRAM, the dispersed system addresses across all DRAM addresses in that bank necessitate accessing most or all system addresses, resulting in non-contiguous write / read operations (non-contiguous read / write). Non-contiguous read / write operations have longer time intervals than contiguous read / write operations, leading to longer testing times for the same bank.

[0003] Therefore, how to reduce the testing time of the same bank in DRAM and improve testing efficiency is an urgent problem to be solved.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a DRAM testing method, apparatus, and storage medium, aiming to solve the technical problem of how to reduce the testing time of the same bank in DRAM and improve testing efficiency.

[0006] To achieve the above objectives, this application proposes a DRAM testing method, which includes:

[0007] The target bank is determined in each bank of the DRAM based on write and read instructions, and the DRAM address corresponding to the target bank is obtained;

[0008] Based on the column address and row address in the DRAM address corresponding to the target bank, the system address corresponding to the target bank is generated, and the system address is stored in the DRAM address table;

[0009] Based on the system address in the DRAM address table, perform write and read operations on the target Bank;

[0010] When the write / read operation of the target Bank is completed, the process returns to the step of sequentially determining the target Bank in each Bank of the DRAM until the write / read operation of each Bank in the DRAM is completed.

[0011] In one embodiment, the step of generating the system address corresponding to the target bank based on the column address and row address in the DRAM address corresponding to the target bank includes:

[0012] Sequentially obtain the target address from the DRAM address corresponding to the target bank;

[0013] Obtain the bank information corresponding to the target bank and the bank group information to which it belongs, and obtain the chip select information corresponding to the target address;

[0014] Input the Bank parameter into the system address generator to generate the system address corresponding to the target address. The Bank parameter includes Bank information, Bank group information, chip select information, column address of the target address, and row address.

[0015] In one embodiment, after the step of inputting the Bank parameter into the system address generator to generate the system address corresponding to the target address, the DRAM testing method further includes:

[0016] Determine whether the target address is the last DRAM address in the DRAM address corresponding to the target Bank;

[0017] If the target address is not the last DRAM address, then return to the step of sequentially obtaining the target address in the DRAM address corresponding to the target bank, until the system address corresponding to each DRAM address is obtained.

[0018] In one embodiment, the step of storing the system address into the DRAM address table includes:

[0019] Obtain the writable and readable system address range corresponding to the DRAM, and determine whether the system address matches the writable and readable system address range;

[0020] If the system address matches the writable / readable system address range, then the system address is stored in the DRAM address table.

[0021] In one embodiment, after the step of determining whether the system address matches the writable / readable system address range, the DRAM testing method further includes:

[0022] If the system address does not match the writable / readable system address range, then update the Bank parameter, use the updated Bank parameter as the Bank parameter, and return to execute the input of the Bank parameter into the system address generator to generate the system address corresponding to the target address.

[0023] In one embodiment, the step of performing write / read operations on the target Bank based on the system address in the DRAM address table includes:

[0024] The target system address is obtained sequentially from the DRAM address table;

[0025] Based on the target system address, perform write and read operations on the target bank of the DRAM;

[0026] When the write / read operation is completed, it is determined whether the target system address is the last system address in the DRAM address table;

[0027] If the target system address is not the last system address in the DRAM address table, then return to the step of sequentially obtaining the target system address from the DRAM address table.

[0028] In one embodiment, after the step of determining whether the target system address is the last system address in the DRAM address table, the DRAM testing method further includes:

[0029] If the target system address is the last system address in the DRAM address table, then determine whether the write / read instruction corresponding to the target Bank is a loop write / read instruction;

[0030] If the write / read instruction corresponding to the target Bank is a loop write / read instruction, then update the loop write / read count corresponding to the target Bank;

[0031] If the number of loop write / read operations does not reach the preset number of loop write / read operations, then return to the step of sequentially obtaining the target system address from the DRAM address table.

[0032] In one embodiment, after the write / read operation of the target Bank is completed, the step of returning to the step of sequentially determining the target Bank in each Bank of the DRAM is performed until the write / read operation of each Bank in the DRAM is completed, the DRAM testing method further includes:

[0033] If the write / read operation corresponding to the write / read instruction is completed, the memory space corresponding to the DRAM address table is released;

[0034] Release the memory space corresponding to the data structure that manages the DRAM address table state.

[0035] In addition, to achieve the above objectives, this application also proposes a DRAM testing apparatus, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the computer program is configured to implement the steps of the aforementioned DRAM testing method.

[0036] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the aforementioned DRAM testing method.

[0037] One or more technical solutions proposed in this application have at least the following technical effects:

[0038] By generating the system address of the target bank to be tested, and performing write and read operations on each system address of the target bank according to the DRAM address table of the system address, continuous write and read tests are performed on the same bank, reducing the test time of the same bank in DRAM, increasing the test pressure of the same bank in DRAM with faster write and read efficiency, and thus improving the test efficiency of SLT test on DRAM. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart illustrating an embodiment of the DRAM testing method of this application.

[0042] Figure 2 This is a schematic diagram of the device structure of the hardware operating environment involved in the DRAM testing method in this application embodiment.

[0043] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0044] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0045] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0046] The main solution of this application embodiment is as follows: Based on write and read instructions, determine the target bank in each bank of DRAM and obtain the DRAM address corresponding to the target bank; Based on the column address and row address in the DRAM address corresponding to the target bank, generate the system address corresponding to the target bank and store the system address in the DRAM address table; Based on the system address in the DRAM address table, perform write and read operations on the target bank; When the write and read operations on the target bank are completed, return to the step of sequentially determining the target bank in each bank of DRAM until the write and read operations of each bank in DRAM are completed.

[0047] In this embodiment, for ease of description, the following description will focus on the DRAM testing system as the execution subject.

[0048] Currently, SLT (System-level testing) refers to testing the chip under test, such as DRAM, in a simulated end-user scenario. During SLT testing, the controller distributes consecutive system addresses across different banks within the DRAM. For example, during system-level tests like write / read tests, software logic accesses these consecutive system addresses. However, since these consecutive system addresses correspond to different banks, the actual banks accessed through these consecutive system addresses vary. When testing or repeatedly testing the same bank within the DRAM, because the system addresses corresponding to all DRAM addresses in that bank are distributed, most or even all system addresses need to be accessed once during the process. This results in non-contiguous write / read operations on that bank, and non-contiguous write / read operations have longer time intervals than contiguous ones, leading to longer testing times for the same bank.

[0049] In other words, while SLT continuously writes to and reads from the same DRAM bank, effectively writing to and reading from the DRAM continuously, the write and read operations are not concentrated within the same DRAM bank. Furthermore, dividing the test interval by system address results in lower write and read pressure on the same memory address, failing to create data pressure within a short unit of time. This means the time spent writing to and reading from the same memory address is far beyond the limits of DRAM. When encountering DRAM ECC errors, the insufficient pressure reduces the likelihood and degree of reproducibility of the problem.

[0050] Therefore, how to reduce the testing time of the same bank in DRAM and improve testing efficiency is an urgent problem to be solved.

[0051] This application provides a solution that generates the system address of the target bank to be tested, and performs write and read operations on each system address of the target bank according to the DRAM address table of the system address. This enables continuous write and read tests to be performed on the same bank, reduces the test time of the same bank in DRAM, increases the test pressure of the same bank in DRAM with faster write and read efficiency, and thus improves the test efficiency of SLT test on DRAM.

[0052] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or DRAM testing system capable of performing the above functions. The following description uses a DRAM testing system as an example to illustrate this embodiment and the subsequent embodiments.

[0053] Based on this, embodiments of this application provide a DRAM testing method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the DRAM testing method of this application.

[0054] In this embodiment, the DRAM testing method includes steps S110~S140:

[0055] Step S110: Determine the target bank in each bank of the DRAM based on the write and read instructions, and obtain the DRAM address corresponding to the target bank;

[0056] In this embodiment of the application, the write / read instruction can be an instruction to perform a write / read test or a continuous write / read test on a specific Bank in the DRAM, or it can be an instruction to perform a write / read test or a continuous write / read test on multiple Banks (e.g., all Banks) in the DRAM.

[0057] The target bank is determined in each bank of the DRAM based on the write / read instruction. For example, if the write / read instruction is a test instruction for a single bank, the target bank is the bank corresponding to the write / read instruction in each bank. If the write / read instruction is a test instruction for multiple banks in each bank, the multiple banks corresponding to the write / read instruction are first determined in each bank, and then the target bank is determined among the multiple banks corresponding to the write / read instruction. For example, the target bank is selected sequentially from the multiple banks corresponding to the write / read instruction according to the bank number.

[0058] After identifying the target bank, obtain all DRAM addresses for that DRAM, and then obtain the DRAM address corresponding to the target bank from all DRAM addresses. For example, obtain the DRAM address corresponding to the target bank from all DRAM addresses based on the target bank's number.

[0059] Step S120: Based on the column address and row address in the DRAM address corresponding to the target Bank, generate the system address corresponding to the target Bank, and store the system address in the DRAM address table;

[0060] In this embodiment, the system address corresponding to the target bank is generated based on the column address and row address in the DRAM address corresponding to the target bank. Specifically, the column address and row address of each DRAM address are sequentially input into the system address generator, which generates the system address for each DRAM address. The DRAM address corresponds to the physical signal layer, and the system address corresponds to the software logic layer. The two correspond under agreed-upon rules, and changes in the software logic will alter the corresponding physical signals. In a feasible implementation, step S120 may include steps A110~A130:

[0061] Step A110: Sequentially obtain the target address from the DRAM address corresponding to the target Bank;

[0062] Step A120: Obtain the Bank information corresponding to the target Bank and the Bank group information to which it belongs, and obtain the chip select information corresponding to the target address;

[0063] Step A130: Input the Bank parameters into the system address generator to generate the system address corresponding to the target address. The Bank parameters include Bank information, Bank group information, chip select information, the column address of the target address, and the row address. The chip select information includes Rank information, DIMM information, and memory controller information, etc.

[0064] In this embodiment of the application, when generating the system address corresponding to the target bank, the target address is sequentially obtained from the DRAM address corresponding to the target bank. The column address of the target address selected for generating the system address is related to the Burst Length. Different target addresses can be selected according to different DRAMs. For example, for DDR5, its trigger output is 16 times, the number of DQs is 4, the number of chip chips is 8, the sub-channel width is 32 bits, and the data transmitted in one trigger is 512 bits, or 64 bytes. In the column address of DRAM, the prefetched column addresses are 0, 1, 2, and 3. That is to say, the DRAM column addresses 0, 1, 2, and 3 do not need to generate system addresses, and the system address can be generated starting from the 4th column.

[0065] After obtaining the column address, obtain the Bank information corresponding to the target Bank and the Bank group information to which it belongs. That is, the Bank group information is the Bank Group to which the target Bank belongs. At the same time, obtain the ChipSelect information corresponding to the target address.

[0066] After obtaining the chip select information, the Bank information, Bank group information, chip select information, column address of the target address, and row address are input into the system address generator. The system address generator generates the system address corresponding to the target address, so that the system address generated for each DRAM address is different, which further improves the testing efficiency of DRAM.

[0067] Furthermore, in one feasible implementation, after step A130, the DRAM testing method may further include steps A140-A150:

[0068] Step A140: Determine whether the target address is the last DRAM address in the DRAM address corresponding to the target Bank;

[0069] Step A150: If the target address is not the last DRAM address, then return to the step of sequentially obtaining the target address from the DRAM addresses corresponding to the target Bank, until the system address corresponding to each DRAM address is obtained.

[0070] In this embodiment, after obtaining the system address corresponding to the target address, it is determined whether the target address is the last DRAM address in the DRAM address corresponding to the target Bank, that is, whether the system address corresponding to the DRAM address corresponding to the target Bank has been generated.

[0071] If the target address is not the last DRAM address in the DRAM address corresponding to the target bank, then return to the step of obtaining the target address in the DRAM address corresponding to the target bank in turn, until the system address corresponding to each DRAM address is obtained.

[0072] If the target address is the last DRAM address in the DRAM address corresponding to the target bank, determine the system address of each DRAM address corresponding to the target bank that has been generated. At this time, the test operation of the target bank can be performed.

[0073] Furthermore, in a feasible implementation, step S120 may further include steps A160-A170:

[0074] Step A160: Obtain the writable and readable system address range corresponding to the DRAM, and determine whether the system address matches the writable and readable system address range;

[0075] Step A170: If the system address matches the writable / readable system address range, then store the system address in the DRAM address table.

[0076] In this embodiment of the application, when storing each system address into the DRAM address table, the range of writable and readable system addresses corresponding to the DRAM is obtained, and it is determined whether the system address matches the range of writable and readable system addresses, that is, whether the system address is within the range of writable and readable system addresses. The range of writable and readable system addresses can be reasonably set according to the DRAM.

[0077] If the system address matches the writable and readable system address range, the system address is stored in the DRAM address table. Specifically, the system address is stored in the DRAM address table according to the order of each address in the DRAM address corresponding to the target bank.

[0078] Furthermore, in one feasible implementation, after step A160, the DRAM testing method may further include step A180:

[0079] Step A180: If the system address does not match the writable / readable system address range, update the Bank parameter, use the updated Bank parameter as the Bank parameter, and return to execute the input of the Bank parameter into the system address generator to generate the system address corresponding to the target address.

[0080] In this embodiment, if the system address does not match the writable / readable system address range (i.e., the system address is outside the writable / readable system address range), the Bank parameters are updated. This update can simultaneously update all parameters in the Bank parameters or only some parameters within the Bank parameters. For example, consider a 64GB 2Rx4 DDR5 RDIMM memory module with 0x10000 row addresses, 0x400 column addresses, 4 Banks, 8 Bank Groups, and 4 Chip Selects. The order in which the Bank parameters are changed can be "column address - row address - Bank information - Bank group information - chip select information." For instance, the column address increments by 1 from C4 to the maximum value (i.e., if incrementing from 0, each increment is 64 bytes), the row address increments by 1 from 0 to the maximum value, and so on.

[0081] After obtaining the updated Bank parameter, the updated Bank parameter is used as the Bank parameter, and the process returns to step A130 to continue the process of generating the system address corresponding to the target address until a system address within the writable and readable system address range is generated.

[0082] After obtaining the system address of the target bank, the system address is stored in the DRAM address table. Specifically, the system address can be stored in the DRAM address table in the order of the DRAM addresses. If other system addresses exist in the DRAM address table, the system address can be used to overwrite the other system addresses in the DRAM address table. Alternatively, when storing the first system address corresponding to the target bank in the DRAM address table, if other system addresses exist in the DRAM address table, the DRAM address table is cleared first, and then the system address is stored in the DRAM address table.

[0083] Step S130: Perform write / read operations on the target Bank based on the system address in the DRAM address table;

[0084] In this embodiment, when the DRAM address table corresponding to the system address of the target Bank is obtained, a write-read operation is performed on the target Bank based on the system address in the DRAM address table. Specifically, a write-read operation is performed sequentially on each system address in the DRAM address table, that is, a write-read operation is performed on the target Bank of the DRAM at the physical signal level to realize the write-read test of the target Bank. Further, in a feasible implementation, step S130 may include steps B110~B140:

[0085] Step B110: Obtain the target system address from the DRAM address table sequentially;

[0086] Step B120: Based on the target system address, perform write and read operations on the target bank of the DRAM;

[0087] Step B130: When the write / read operation is completed, determine whether the target system address is the last system address in the DRAM address table;

[0088] Step B140: If the target system address is not the last system address in the DRAM address table, then return to the step of sequentially obtaining the target system address from the DRAM address table.

[0089] In this embodiment, when performing write or read operations on each system address in the DRAM address table, the target system address can be obtained sequentially from the DRAM address table. For example, the target system address can be obtained sequentially according to the storage order of each system address in the DRAM address table.

[0090] After obtaining the target system address, write and read operations are performed on the target bank of the DRAM based on the target system address, that is, write and read operations are performed on the storage area corresponding to the target system address in the target bank of the DRAM.

[0091] When a write / read operation is completed, it is determined whether the target system address is the last system address in the DRAM address table. This is to determine whether all system addresses in the current DRAM address table have undergone write / read operations, and thus whether the target bank has been completely written / read.

[0092] If the target system address is not the last system address in the DRAM address table, that is, the current target bank has not completed all write and read tests, then return to the step of sequentially obtaining the target system address in the DRAM address table to test the system addresses that have not been written and read.

[0093] It should be noted that if the target system address is the last system address in the DRAM address table, it is determined that all writes to the target bank are complete. Then, the process returns to the step of determining the target bank in each bank of the DRAM based on the write and read instructions. At this time, if the write and read instruction is a write and read test instruction for a certain bank, or if the target bank is the last bank in each bank corresponding to the write and read instruction, the DRAM test ends. If the target bank is not the last bank in each bank corresponding to the write and read instruction, the target bank is re-determined in each bank of the DRAM to perform write and read tests on the new target bank.

[0094] Furthermore, in one feasible implementation, after step B130, the DRAM testing method may further include steps B150 to B170:

[0095] Step B150: If the target system address is the last system address in the DRAM address table, then determine whether the write / read instruction corresponding to the target Bank is a loop write / read instruction;

[0096] Step B160: If the write / read instruction corresponding to the target Bank is a loop write / read instruction, then update the loop write / read count corresponding to the target Bank;

[0097] Step B170: If the number of loop write-read cycles has not reached the preset number of loop write-read cycles, then return to the step of sequentially obtaining the target system address from the DRAM address table.

[0098] In this embodiment of the application, if the target system address is the last system address in the DRAM address table, it is determined whether the write / read instruction corresponding to the target Bank is a loop write / read instruction. If the write / read instruction corresponding to the target Bank is a loop write / read instruction, the loop write / read count corresponding to the target Bank is updated, that is, the loop write / read count is increased by 1 to obtain the updated loop write / read count. The initial value of the loop write / read count can be 0.

[0099] After the loop write / read count is updated, if the loop write / read count has not reached the preset loop write / read count, the process returns to the step of sequentially obtaining the target system address from the DRAM address table in order to complete the write / read operations for all system addresses corresponding to the target Bank.

[0100] It should be noted that if the number of loop write / read tests reaches the preset number of loop write / read tests, the process will return to the step of sequentially determining the target bank in each bank of the DRAM. That is, after completing the loop write / read test of the target bank, if it is necessary to perform write / read tests on other banks, the target bank will be determined sequentially in each bank of the DRAM again.

[0101] Step S140: When the write / read operation of the target Bank is completed, return to the step of sequentially determining the target Bank in each Bank of the DRAM until the write / read operation of each Bank in the DRAM is completed.

[0102] In this embodiment of the application, when the write-read operation of the target Bank is completed, for example, when the number of loop write-reads reaches the preset number of loop write-reads, or when the write-read instruction is a write-read test instruction for a certain Bank and the target Bank is not the last Bank among the various Banks corresponding to the write-read instruction, the target system address is the last system address in the DRAM address table, then it is determined that the write-read operation of the target Bank is completed. At this time, the process returns to the step of sequentially determining the target Bank in each Bank of the DRAM. That is, after completing the loop write-read test of the target Bank, if it is necessary to perform write-read tests on other Banks, the target Bank is determined again in each Bank of the DRAM to perform write-read tests on the new target Bank.

[0103] Furthermore, in one feasible implementation, after step S140, the DRAM testing method may further include steps S150-S160:

[0104] Step S150: If the write / read operation corresponding to the write / read instruction is completed, then the memory space corresponding to the DRAM address table is released.

[0105] Step S160: Release the memory space corresponding to the data structure that manages the DRAM address table status.

[0106] In this embodiment of the application, after completing the write / read operation corresponding to the write / read instruction, the memory space corresponding to the DRAM address table is released, and the memory space corresponding to the data structure that manages the state of the DRAM address table is also released, so as to release the data written in the DRAM when the write / read instruction is executed.

[0107] This embodiment provides a DRAM testing method. It involves determining a target bank within each DRAM bank based on write / read instructions and obtaining the corresponding DRAM address. Then, based on the column and row addresses of the DRAM address corresponding to the target bank, a system address is generated and stored in a DRAM address table. Next, write / read operations are performed on the target bank based on the system address in the DRAM address table. After the write / read operations on the target bank are completed, the process returns to the previous steps of sequentially determining the target bank within each DRAM bank until all write / read operations in each DRAM bank are completed. By generating the system address of the target bank to be tested and performing write / read operations on each system address of the target bank according to the DRAM address table, continuous write / read tests on the same bank are achieved, reducing the testing time for the same DRAM bank and increasing the testing pressure on the same DRAM bank with faster write / read efficiency, thereby improving the testing efficiency of SLT testing on DRAM.

[0108] Meanwhile, by conducting continuous write and read tests on the same bank, the write and read pressure on the same storage address was increased, thereby increasing the probability and degree of recurrence of DRAM ECC error problems.

[0109] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the DRAM testing method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0110] This application also provides a DRAM testing apparatus, the DRAM testing apparatus comprising:

[0111] The determination module is used to determine the target bank in each bank of DRAM based on write and read instructions, and to obtain the DRAM address corresponding to the target bank;

[0112] The generation module is used to generate the system address corresponding to the target bank based on the column address and row address in the DRAM address corresponding to the target bank, and store the system address in the DRAM address table;

[0113] The write / read module is used to perform write / read operations on the target Bank based on the system address in the DRAM address table;

[0114] The execution module is used to return to the steps of sequentially determining the target bank in each bank of the DRAM when the write and read operations of the target bank are completed, until the write and read operations of each bank in the DRAM are completed.

[0115] The DRAM testing apparatus provided in this application, employing the DRAM testing method described in the above embodiments, can solve the technical problem of how to reduce the testing time of the same bank in DRAM and improve testing efficiency. Compared with the prior art, the beneficial effects of the DRAM testing apparatus provided in this application are the same as those of the DRAM testing method provided in the above embodiments, and other technical features in the DRAM testing apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0116] This application provides a DRAM testing apparatus, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the DRAM testing method in the above embodiment 1.

[0117] The following is for reference. Figure 2 The diagram illustrates a structural schematic of a DRAM testing apparatus suitable for implementing embodiments of this application. The DRAM testing apparatus in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 2 The DRAM testing apparatus shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0118] like Figure 2As shown, the DRAM testing apparatus may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the DRAM testing apparatus. The processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the DRAM test apparatus to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a DRAM test apparatus with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented alternatively.

[0119] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0120] The DRAM testing apparatus provided in this application, employing the DRAM testing method described in the above embodiments, can solve the technical problem of how to reduce the testing time of the same bank in DRAM and improve testing efficiency. Compared with the prior art, the beneficial effects of the DRAM testing apparatus provided in this application are the same as those of the DRAM testing method provided in the above embodiments, and other technical features of this DRAM testing apparatus are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0121] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0122] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0123] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the DRAM testing method in the above embodiments.

[0124] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0125] The aforementioned computer-readable storage medium may be included in the DRAM testing apparatus; or it may exist independently and not be assembled into the DRAM testing apparatus.

[0126] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by a DRAM testing device, the DRAM testing device: determines a target bank in each bank of the DRAM based on write / read instructions and obtains the DRAM address corresponding to the target bank; generates a system address corresponding to the target bank based on the column address and row address in the DRAM address corresponding to the target bank, and stores the system address in a DRAM address table; performs write / read operations on the target bank based on the system address in the DRAM address table; and when the write / read operations on the target bank are completed, returns to the step of sequentially determining the target bank in each bank of the DRAM until the write / read operations on each bank in the DRAM are completed.

[0127] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0128] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0129] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0130] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described DRAM testing method. This solves the technical problem of how to reduce testing time for the same bank in DRAM and improve testing efficiency. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the DRAM testing method provided in the above embodiments, and will not be repeated here.

[0131] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the DRAM testing method described above.

[0132] The computer program product provided in this application can solve the technical problem of how to reduce the testing time of the same bank in DRAM and improve testing efficiency. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the DRAM testing method provided in the above embodiments, and will not be repeated here.

[0133] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A DRAM testing method, characterized in that, The DRAM testing method includes: The target bank is determined in each bank of the DRAM based on write and read instructions, and the DRAM address corresponding to the target bank is obtained; Based on the column address and row address in the DRAM address corresponding to the target bank, the system address corresponding to the target bank is generated, and the system address is stored in the DRAM address table; Based on the system address in the DRAM address table, perform write and read operations on the target Bank; When the write / read operation of the target Bank is completed, return to the step of sequentially determining the target Bank in each Bank of the DRAM until the write / read operation of each Bank in the DRAM is completed; The step of generating the system address corresponding to the target bank based on the column address and row address in the DRAM address corresponding to the target bank includes: Sequentially obtain the target address from the DRAM address corresponding to the target bank; Obtain the bank information corresponding to the target bank and the bank group information to which it belongs, and obtain the chip select information corresponding to the target address; Input the Bank parameter into the system address generator to generate the system address corresponding to the target address. The Bank parameter includes Bank information, Bank group information, chip select information, column address of the target address, and row address.

2. The DRAM testing method as described in claim 1, characterized in that, After the step of inputting the Bank parameter into the system address generator to generate the system address corresponding to the target address, the DRAM testing method further includes: Determine whether the target address is the last DRAM address in the DRAM address corresponding to the target Bank; If the target address is not the last DRAM address, then return to the step of sequentially obtaining the target address in the DRAM address corresponding to the target bank, until the system address corresponding to each DRAM address is obtained.

3. The DRAM testing method as described in claim 2, characterized in that, The step of storing the system address into the DRAM address table includes: Obtain the writable and readable system address range corresponding to the DRAM, and determine whether the system address matches the writable and readable system address range; If the system address matches the writable / readable system address range, then the system address is stored in the DRAM address table.

4. The DRAM testing method as described in claim 3, characterized in that, After the step of determining whether the system address matches the writable / readable system address range, the DRAM testing method further includes: If the system address does not match the writable / readable system address range, then update the Bank parameter, use the updated Bank parameter as the Bank parameter, and return to execute the input of the Bank parameter into the system address generator to generate the system address corresponding to the target address.

5. The DRAM testing method as described in claim 1, characterized in that, The steps of performing write / read operations on the target Bank based on the system address in the DRAM address table include: The target system address is obtained sequentially from the DRAM address table; Based on the target system address, perform write and read operations on the target bank of the DRAM; When the write / read operation is completed, it is determined whether the target system address is the last system address in the DRAM address table; If the target system address is not the last system address in the DRAM address table, then return to the step of sequentially obtaining the target system address from the DRAM address table.

6. The DRAM testing method as described in claim 5, characterized in that, After the step of determining whether the target system address is the last system address in the DRAM address table, the DRAM testing method further includes: If the target system address is the last system address in the DRAM address table, then determine whether the write / read instruction corresponding to the target Bank is a loop write / read instruction; If the write / read instruction corresponding to the target Bank is a loop write / read instruction, then update the loop write / read count corresponding to the target Bank; If the number of loop write / read operations does not reach the preset number of loop write / read operations, then return to the step of sequentially obtaining the target system address from the DRAM address table.

7. The DRAM testing method according to any one of claims 1 to 6, characterized in that, When the write / read operation of the target Bank is completed, the process returns to the step of sequentially determining the target Bank in each Bank of the DRAM until the write / read operation of each Bank in the DRAM is completed. The DRAM testing method further includes: If the write / read operation corresponding to the write / read instruction is completed, the memory space corresponding to the DRAM address table is released; Release the memory space corresponding to the data structure that manages the DRAM address table state.

8. A DRAM testing apparatus, characterized in that, The DRAM testing apparatus includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the DRAM testing method as described in any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the DRAM testing method as described in any one of claims 1 to 7.

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