Ethernet port controller and system on chip
By introducing the CPR internal clock generation module and clock phase offset module into the Ethernet port controller, an internal target clock that meets timing requirements is generated, solving the problem of data sampling errors in the MAC-to-MAC direct connection method and achieving both data sampling accuracy and clock flexibility.
Patent Information
- Application Number
- CN202511441610.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-10
- Publication Date
- 2026-01-06
AI Technical Summary
In a direct MAC-to-MAC connection, the routing path affects the quality of digital signals, especially high-frequency clock signals, making it difficult for the timing of chip port signals to meet timing requirements, resulting in data sampling errors.
The system employs an internal clock generation module, a clock phase offset module, and an internal clock selector to generate an internal target clock that meets timing requirements through phase modulation and selection, which is then used for data sampling.
It improves data sampling accuracy, meets data timing requirements, and enhances the clock flexibility of the Ethernet port controller.
Smart Images
Figure CN121283552A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to an Ethernet port controller and system-on-a-chip. Background Technology
[0002] Currently, in SOC (System on Chip) systems, network port modules typically only support a single MAC (Media Access Control) + PHY (Physical Layer Transceiver) architecture. However, in some application scenarios, it is necessary to support MAC-to-MAC applications, that is, data transmission is required without a PHY.
[0003] In this direct MAC-to-MAC connection method, the routing path will affect the quality of digital signals, especially high-frequency clock signals in network transmission. The routing delay will make it difficult for the timing of the chip port signals to meet the timing requirements, resulting in data sampling errors.
[0004] In conclusion, how to accurately sample data is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this application is to provide an Ethernet port controller that can, to some extent, solve the technical problem of how to accurately sample data. This application also provides a system-on-a-chip.
[0006] To achieve the above objectives, this application provides the following technical solution:
[0007] An Ethernet port controller, comprising:
[0008] The CPR internal clock generation module is used to generate the internal clock of the Ethernet port controller.
[0009] A clock phase offset module connected to the CPR internal clock generation module is used to perform phase modulation on the internal clock to obtain an internal offset clock.
[0010] An internal clock selector connected to the clock phase offset module is used to select the internal offset clock and the received clock to obtain the internal target clock;
[0011] The gigabit media access control top-level module, connected to the internal clock selector, is used to sample data according to the internal target clock.
[0012] Preferably, the clock phase offset module is further used to perform phase offset on the internal clock to obtain a transmission offset clock;
[0013] The gigabit media access control top-level module is also used to generate a transmission clock;
[0014] The Ethernet port controller also includes:
[0015] An external clock selector connected to the clock phase offset module and the gigabit media access control top-level module is used to select the transmission offset clock and the transmission clock to obtain the transmission target clock.
[0016] Preferably, the transmit clock interface of the Ethernet port controller is connected to the receive clock interface of another Ethernet port controller; the receive clock interface of the Ethernet port controller is connected to the transmit clock interface of another Ethernet port controller.
[0017] Preferably, the clock phase offset module includes a high-frequency sampling offset module.
[0018] Preferably, the high-frequency sampling offset module includes a first register, a second register, a third register, and a fourth register;
[0019] The falling edge of the first register is connected to a set high-frequency clock, and the data input terminal of the first register is connected to the first data output terminal of the first register.
[0020] The data input terminal of the second register is connected to the second data output terminal of the first register, and the falling sampling edge of the second register is connected to the high-frequency clock.
[0021] The data input terminal of the third register is connected to the first data output terminal of the second register, and the rising sampling edge of the third register is connected to the high-frequency clock.
[0022] The data input terminal of the fourth register is connected to the first data output terminal of the third register, and the falling sampling edge of the fourth register is connected to a high-frequency clock.
[0023] Preferably, the clock phase offset module includes a delay cell level offset module.
[0024] Preferably, the delay cell level offset module includes N delay cell offset sub-modules and an offset register, where N is a positive integer;
[0025] The delay cell offset submodule includes a clock offset unit and an offset selector. The clock offset unit is connected to the input terminal of the delay cell offset submodule. The input terminal of the offset selector is connected to both the input terminal of the delay cell offset submodule and the output terminal of the clock offset unit. The offset register is connected to the output terminal of the offset selector.
[0026] Preferably, the clock phase offset module includes a high-frequency sampling offset module and a delay cell level offset module.
[0027] Preferred options also include:
[0028] The clock control module, which is connected to both the internal clock selector and the external clock selector, is used to set the operating mode of the selector.
[0029] A system-on-a-chip includes an Ethernet port controller as described in any of the above.
[0030] This application provides an Ethernet port controller, including a CPR internal clock generation module for generating the internal clock of the Ethernet port controller; a clock phase offset module connected to the CPR internal clock generation module for phase modulation of the internal clock to obtain an internal offset clock; an internal clock selector connected to the clock phase offset module for selecting between the internal offset clock and the received clock to obtain an internal target clock; and a Gigabit Media Access Control (GMAC) top-level module connected to the internal clock selector for data sampling based on the internal target clock. In this application, after the CPR internal clock generation module of the Ethernet port controller generates the internal clock, the clock phase offset module can perform phase modulation on the internal clock to obtain an internal offset clock different from the internal clock. Therefore, the internal clock selector can select the internal target clock required by the Ethernet port controller from the internal clock and the internal offset clock, allowing the GMAC top-level module to sample data according to the internal target clock. This realizes the function of clock adjustment for the Ethernet port controller by setting the clock phase offset module, making the clock of the Ethernet port controller no longer limited to the internal clock, enhancing the clock flexibility of the Ethernet port controller, ensuring that the timing of the Ethernet port controller meets the data timing requirements, and improving the accuracy of data sampling. The system-on-a-chip provided in this application also solves the corresponding technical problems. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of the structure of an Ethernet port controller provided in an embodiment of this application;
[0033] Figure 2 This is a schematic diagram showing the connection between Ethernet port controllers;
[0034] Figure 3 The simulation waveform diagram is shown for the high-frequency sampling offset module.
[0035] Figure 4 This is a schematic diagram of the high-frequency sampling offset module;
[0036] Figure 5 This is a schematic diagram of the delay cell series offset module;
[0037] Figure 6 The simulation waveform diagram is for the delay cell series offset module. Detailed Implementation
[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0039] Currently, the structure of network port modules integrated in a System-on-Chip (SoC) is generally an on-chip MAC controller + an off-chip PHY chip, or an on-chip MAC controller + an on-chip PCS (Physical Coding Sublayer) + an off-chip PMA. This part constitutes the physical layer and link layer in network transmission, storing the network data to be sent and received in the on-chip storage module. The functions of other layers of the OSI (Seven-Layer Networking System) model are achieved by the CPU executing software programs based on various transmission protocols to realize high-speed and stable network data transmission. Although the PHY chip in the traditional structure can better realize signal transmission and link management, it increases the implementation and maintenance costs and makes the structure relatively complex. In MAC-to-MAC communication scenarios, data may not need to pass through the PHY, but to ensure the reliability of transmission, phase modulation of the clock signals of both sides of the transmission at the same frequency is required to meet timing requirements and ensure that the data can be correctly sampled.
[0040] In MAC-to-MAC direct connection, the routing path affects the quality of digital signals, especially high-frequency clock signals in network transmission. Routing delays can cause timing issues with chip port signals. Specifically, signals are directly connected via IO pads (input / output pads). Without PHY modulation, there is a certain delay and loss in the signal, particularly with high-frequency clock signals. Sending a delayed clock directly to the Ethernet port controller as the sampling clock often fails to meet sampling timing requirements, leading to data sampling errors. The Ethernet port controller and on-chip system provided in this application can accurately sample data.
[0041] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an Ethernet port controller provided in an embodiment of this application.
[0042] An Ethernet port controller provided in this application embodiment may include:
[0043] The CPR (Clock and Reset Generator) internal clock generation module 101 is used to generate the internal clock of the Ethernet port controller.
[0044] The clock phase shift module 102, which is connected to the CPR internal clock generation module, is used to perform phase modulation on the internal clock to obtain an internal shift clock (rx_clk_phase_shift).
[0045] The internal clock selector 103, which is connected to the clock phase offset module, is used to select the internal offset clock and the received clock to obtain the internal target clock (rx_clk_i).
[0046] The Gigabit Media Access Control top-level (gmac_top) module 104, connected to the internal clock selector, is used to sample data according to the internal target clock.
[0047] Understandably, the internal clock can be generated by the PLL (Phase-Locked Loop) of the CPR internal clock generation module; the received clock referenced by the internal clock selector can be an external clock received by the Ethernet port controller through the RX_CLK (Receive Clock) PAD, such as a clock signal sent by another Ethernet port controller communicating with the Ethernet port controller, etc. The received clock is used by the Ethernet port controller to sample the data sent by the other Ethernet port controller; the clock phase offset module adjusts the offset amount to meet the timing requirements by configuring an appropriate offset amplitude, so that the modulated clock can meet the sampling timing requirements of the protocol, and the magnitude of the phase adjustment of the internal clock by the clock phase offset module can be flexibly determined according to the application scenario. For example, the clock phase offset module can use the received clock as the target to adjust the phase of the internal clock to obtain the internal target clock, etc., where the internal target clock is used by the Ethernet port controller to sample data.
[0048] In an exemplary embodiment, considering that when the Ethernet port controller interacts with other devices, such as when sending data to another Ethernet port controller, it needs to send a clock signal to that other Ethernet port controller. That is, the Ethernet port controller needs to synchronously send a clock to the other Ethernet port controller through the TX_CLK (transmit clock) PAD. In this process, in order to facilitate clock synchronization with the other Ethernet port controller, the clock phase shift module can also be used to shift the phase of the internal clock to obtain the transmit offset clock (tx_clk_phase_shift); the Gigabit Media Access Control top-level module can also be used to generate the transmit clock (tx_clk_i); correspondingly, the Ethernet port controller can also include: an external clock selector 105 connected to the clock phase shift module and the Gigabit Media Access Control top-level module, used to select the transmit offset clock and the transmit clock to obtain the transmit target clock (TX_CLK).
[0049] In an exemplary embodiment, the Ethernet port controller can interact with an off-chip PHY chip or with another Ethernet port controller, such as... Figure 2As shown, when interacting with another Ethernet port controller, the transmit clock interface of the Ethernet port controller is connected to the receive clock interface of the other Ethernet port controller; conversely, the receive clock interface of the Ethernet port controller is connected to the transmit clock interface of the other Ethernet port controller. In this way, when the transmit clock TX CLK and receive clock RX CLK are output or input to the MAC, the clock phase offset module can adjust the phase offset of the clock to match the data signal, satisfying the input / output timing and ensuring that both interconnected Ethernet port controllers can correctly sample valid data.
[0050] In an exemplary embodiment, the clock phase offset module may include a high-frequency sampling offset module. The high-frequency sampling offset module works by using a high-frequency clock signal as the sampling clock. The rising and falling edges of this high-frequency clock are used to sample the target clock signal requiring phase offset as the output signal. Thus, the Q-terminal of the upper-level register becomes the D-terminal of the lower-level register. This achieves a delay of half a cycle (45°) of the high-frequency sampling clock cycle for the target clock signal after each register stage. The effective offset using this method can delay the high-frequency sampling clock by 315°, and the specific delay value is determined by the half-cycle time of the high-frequency sampling clock. Assuming the simulation waveform of this structure is as follows... Figure 3 The high-frequency clock is sd_clk, cclk_in is the target offset clock, and clk_200m_pahse_x_pre is the offset clock after high-frequency sampling. The offset after offsetting 315° is T0.
[0051] For specific application scenarios, please refer to Figure 4 The high-frequency sampling offset module includes a first register 201, a second register 202, a third register 203, and a fourth register 204. The falling edge of the first register is connected to a set high-frequency clock, and the data input terminal of the first register is connected to the first data output terminal of the first register. The data input terminal of the second register is connected to the second data output terminal of the first register, and the falling edge of the second register is connected to the high-frequency clock. The data input terminal of the third register is connected to the first data output terminal of the second register, and the rising edge of the third register is connected to the high-frequency clock. The data input terminal of the fourth register is connected to the first data output terminal of the third register, and the falling edge of the fourth register is connected to the high-frequency clock.
[0052] In specific application scenarios, the external clock selector may include a first selector 301 and a second selector 302. The input of the first selector is connected to the second data output of the first register, the first data output of the second register, the first data output of the third register, and the first data output of the fourth register, respectively. The input of the second selector is connected to the output of the first selector and a reference clock (TCLK), respectively. The output of the second selector is used to output the target clock for transmission. Similarly, the internal clock selector may include a third selector 401 and a fourth selector 402. The input of the third selector is connected to the second data output of the first register, the first data output of the second register, and the first data output of the fourth register, respectively. The input of the fourth selector is connected to the output of the third selector and a reference clock, respectively. The output of the fourth selector is used to output the internal target clock.
[0053] It should be noted that when it is necessary to transmit the target offset clock for the Gigabit Media Access Control top-level module, a fifth selector 501 can also be set in the Ethernet port controller. The input of the fifth selector is connected to the second data output of the first register and the reference clock, respectively, and the output of the fifth selector is used to output the target offset clock.
[0054] In an exemplary embodiment, the clock phase offset module may include a delay cell stage offset module. The working principle of the delay cell stage offset module is to insert N stages of delay cells on the clock output path, using the physical delay of the delay cells themselves to achieve the effect of clock phase delay.
[0055] In specific application scenarios, such as Figure 5 As shown, the delay cell series offset module can include N delay cell offset sub-modules and an offset register (configuration register), where N is a positive integer. The delay cell offset sub-module includes a clock offset unit and an offset selector. The clock offset unit is connected to the input of the delay cell offset sub-module. The input of the offset selector is connected to both the input of the delay cell offset sub-module and the output of the clock offset unit. The offset register is connected to the output of the offset selector.
[0056] In an exemplary embodiment, the clock phase offset module may include a high-frequency sampling offset module and a delay cell series offset module. This allows for simultaneous application of high-frequency sampling offset and delay cell series offset to modulate the signal phase of the MAC's TXCLK and RXCLK, enabling a wider range of offsets and better addressing the timing mismatch between data and clock signals encountered when transmitting data between MACs via the GMII / RGMII interface and interconnecting the TX / RX signals in the absence of a PHY chip. To facilitate understanding of the combination of the two methods, assume the simulation waveform is as follows... Figure 6 As shown, clk_200m_pahse_315_pre is the clock signal implemented using a high-frequency sampling clock, with an offset of T0 relative to the target offset clock. Inserting a delay cell on this signal can further increase the offset by T1, resulting in a final signal cclk_phase_deive with a total offset of T0+T1 relative to the original clock source signal cclk_in after the two offset methods are superimposed.
[0057] It should be noted that the offset parameter can be configured via the bus. For example, when using the high-frequency sampling offset method, it is necessary to select the frequency of the input high-frequency clock and use half a cycle of this frequency as the offset of each step, and then configure the offset degree. When using the delay cell method, the number of delay cell stages N can be configured directly.
[0058] In an exemplary embodiment, to facilitate clock management of the Ethernet port controller, the Ethernet port controller provided in this application may further include a clock control module (CCM) 106 connected to both an internal clock selector and an external clock selector, for setting the operating mode of the selectors. For example, the external clock selector can be controlled to reference a transmission offset clock to obtain the transmission target clock by sending a clock selection signal tx_clk_phase_shift_sel; similarly, the internal clock selector can be controlled to reference an internal offset clock to obtain the internal target clock by receiving a clock selection signal rx_clk_phase_shift_sel. In this way, the clock control module can be used to determine whether to apply the clock phase offset module for phase adjustment, thereby flexibly adjusting the connection method of the Ethernet port controller. For example, if the clock control module is set so that neither the external clock selector nor the internal clock selector references the clock phase offset module, the Ethernet port controller can be connected to an external PHY chip. If the clock control module is set so that both the external clock selector and the internal clock selector reference the clock phase offset module, the Ethernet port controller can be connected to another Ethernet port controller. In other words, by simply configuring the clock control module and selecting whether the clock signal needs to pass through the clock phase offset module, it is possible to adapt to clock designs with and without external PHY, further expanding the application scenarios of the network port module in the SOC system.
[0059] This application provides an Ethernet port controller, including a CPR internal clock generation module for generating the internal clock of the Ethernet port controller; a clock phase offset module connected to the CPR internal clock generation module for phase modulation of the internal clock to obtain an internal offset clock; an internal clock selector connected to the clock phase offset module for selecting between the internal offset clock and the received clock to obtain an internal target clock; and a Gigabit Media Access Control (GMAC) top-level module connected to the internal clock selector for data sampling based on the internal target clock. In this application, after the CPR internal clock generation module of the Ethernet port controller generates the internal clock, the clock phase offset module can perform phase modulation on the internal clock to obtain an internal offset clock different from the internal clock. Therefore, the internal clock selector can select the internal target clock required by the Ethernet port controller from the internal clock and the internal offset clock, allowing the GMAC top-level module to sample data according to the internal target clock. This realizes the function of clock adjustment for the Ethernet port controller by setting the clock phase offset module, making the clock of the Ethernet port controller no longer limited to the internal clock, enhancing the clock flexibility of the Ethernet port controller, ensuring that the timing of the Ethernet port controller meets the data timing requirements, and improving the accuracy of data sampling.
[0060] Based on the above embodiments, this application also provides a system-on-a-chip, including an Ethernet port controller as described in any of the above embodiments.
[0061] For descriptions of relevant parts of the on-chip system provided in this application's embodiments, please refer to the detailed description of the corresponding parts in the Ethernet port controller provided in this application's embodiments; they will not be repeated here. Furthermore, parts of the technical solutions provided in this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.
[0062] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0063] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An Ethernet port controller, characterized by The application relates to an Ethernet port controller, which comprises the following parts: a CPR internal clock generation module for generating an internal clock of the Ethernet port controller; a clock phase offset module connected with the CPR internal clock generation module, which is used for phase modulation of the internal clock to obtain an internal offset clock; an internal clock selector connected with the clock phase offset module, which is used for selection of the internal offset clock and a received clock to obtain an internal target clock; a gigabit media access control top module connected with the internal clock selector, which is used for data sampling according to the internal target clock.
2. The Ethernet port controller of claim 1, wherein, The clock phase offset module is also used for phase offset of the internal clock to obtain a sending offset clock. The gigabit media access control top module is also used for generation of a sending clock. The Ethernet port controller further comprises: an external clock selector connected with the clock phase offset module and the gigabit media access control top module, which is used for selection of the sending offset clock and the sending clock to obtain a sending target clock.
3. The Ethernet port controller of claim 2, wherein, A sending clock interface of the Ethernet port controller is connected with a received clock interface of another Ethernet port controller; and a received clock interface of the Ethernet port controller is connected with a sending clock interface of another Ethernet port controller.
4. The Ethernet port controller of claim 2, wherein, The clock phase offset module comprises a high-frequency sampling offset module.
5. The Ethernet port controller of claim 4, wherein, The high-frequency sampling offset module comprises a first register, a second register, a third register and a fourth register. A falling sampling edge of the first register is connected with a set high-frequency clock; a data input end of the first register is connected with a first data output end of the first register. A data input end of the second register is connected with a second data output end of the first register; and a falling sampling edge of the second register is connected with the high-frequency clock. A data input end of the third register is connected with a first data output end of the second register; and a rising sampling edge of the third register is connected with the high-frequency clock. A data input end of the fourth register is connected with a first data output end of the third register; and a falling sampling edge of the fourth register is connected with the high-frequency clock.
6. The Ethernet port controller of claim 2, wherein, The clock phase offset module comprises a delay cell series offset module.
7. The Ethernet port controller of claim 2, wherein, The delay cell series offset module comprises N delay cell offset submodules and an offset register, wherein N is a positive integer. The delay cell offset submodule comprises a clock offset unit and an offset selector; an input end of the clock offset unit is connected with an input end of the delay cell offset submodule; input ends of the offset selector are respectively connected with the input end of the delay cell offset submodule and an output end of the clock offset unit; and the offset register is connected with an output end of the offset selector.
8. The Ethernet port controller of claim 2, wherein, The clock phase offset module comprises a high-frequency sampling offset module and a delay cell series offset module.
9. The Ethernet port controller of claim 2, wherein, The application further comprises: clock control modules connected with the internal clock selector and the external clock selector respectively, which are used for setting of working modes of the selectors.
10. A system on chip, characterized by An Ethernet port controller comprising the Ethernet port controller of any one of claims 1 to 9.