Silicon substrate network physical topological structure and silicon substrate chip architecture

Abstract

The invention relates to a silicon substrate network physical topological structure and a silicon substrate chip architecture, the silicon substrate network physical topological structure comprises a central switch and a plurality of calculation core particle groups, each calculation core particle group is connected with the central switch, the central switch is arranged at the center of a wafer, and each calculation core particle group is arranged in a preset area around the central switch on the wafer; the central switch is used as a data routing node and provides a signal path for any two computing core particle groups; the calculation core particle group comprises a plurality of calculation core particles, all the calculation core particles are arranged in a two-dimensional grid form, all the calculation core particles are mutually connected through an on-chip network, and the calculation core particles are used for calculating data. By adopting the silicon substrate network physical topological structure, the balance between communication resources and computing resources can be ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a silicon substrate network physical topology and silicon substrate chip architecture. Background Technology

[0002] Silicon substrate network refers to the on-chip network of a silicon substrate chip, that is, the interconnection network between various components connected on the wafer through an interposer layer.

[0003] Considering factors such as interconnect robustness and transmission delay, the interconnect length on a wafer must be less than 50mm. Furthermore, due to limitations on the number of metal layers, only a maximum of three metal layers can be used for wiring, thus imposing strict requirements on interconnect density. Currently, commonly used flat two-dimensional planar topologies in computing clusters, such as Flattened Butterfly, Torus, and Dragonfly, are difficult to apply to silicon substrate networks due to layout and wiring constraints. Moreover, existing silicon substrate network physical topologies struggle to ensure a balance between communication and computing resources. Summary of the Invention

[0004] Therefore, it is necessary to provide a silicon substrate network physical topology that can guarantee a balance between communication resources and computing resources to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a silicon substrate network physical topology, including a central switch and multiple computing chip groups, each computing chip group being connected to the central switch. The central switch is located at the center of the wafer, and each computing chip group is located on the wafer within a predetermined area surrounding the central switch. The central switch serves as a data routing node, providing a signal path for any two computing chip groups. Each computing chip group includes multiple computing chips, which are arranged in a two-dimensional grid and interconnected through an on-chip network. The computing chips are used to compute data.

[0006] In one embodiment, the central switch includes at least one switching core, and a port core in the computing core group is connected to a switching core in the central switch via a high-speed link, the port core being a computing core in the computing core group.

[0007] In one embodiment, the number of computed chip groups, the size of computed chip groups, the shape of computed chip groups, and the location of port chips are determined based on wafer physical design constraints and silicon substrate network performance.

[0008] Among them, the size of the computational core group is used to characterize the number of computational cores in the computational core group, and the shape of the computational core group is used to characterize the positional arrangement of each computational core in the computational core group.

[0009] In one embodiment, data transmission between computing chips in the computing chip group is based on the XY routing algorithm.

[0010] In one embodiment, the central switch includes multiple switching cores interconnected via an on-chip network and performs data transmission based on an XY routing algorithm; the switching cores are used to transmit multiple data based on a polling mechanism.

[0011] In one embodiment, the number of switching cores in the central switch is the same as the number of computing core groups.

[0012] Secondly, this application also provides a silicon substrate chip architecture, including the silicon substrate network physical topology as described in any of the first aspects above.

[0013] Thirdly, this application also provides a method for generating a silicon substrate network physical topology, including:

[0014] The wafer area, computed chip area, and exchanged chip area are obtained. Based on the spatial exploration algorithm, the design parameters of the physical topology of the silicon substrate network are determined under the conditions of meeting the wafer physical design constraints and silicon substrate network performance requirements. The design parameters include the number of computed chip groups, the size of computed chip groups, the shape of computed chip groups, and the position of port chips. Among them, the size of computed chip groups is used to characterize the number of computed chips in the computed chip group, and the shape of computed chip groups is used to characterize the positional arrangement of each computed chip in the computed chip group.

[0015] In one embodiment, based on a spatial exploration algorithm, the design parameters of the physical topology of the silicon substrate network are determined while satisfying wafer physical design constraints and silicon substrate network performance requirements. This includes: obtaining multiple candidate computational chip group sizes, where each candidate computational chip group size is any value within a preset range; for each candidate computational chip group size, at least one set of candidate design parameters is determined based on the candidate computational chip group size while satisfying wafer physical design constraints; and performing simulation evaluation on each candidate design parameter, and using the candidate design parameter corresponding to the maximum silicon substrate network performance as the design parameter of the physical topology of the silicon substrate network.

[0016] In one embodiment, the number of candidate compute chip groups is determined based on the wafer area, compute chip area, exchange chip area, and candidate compute chip group size; at least one candidate compute chip group shape is determined based on the candidate compute chip group size; for each candidate compute chip group shape, at least one candidate position of a port chip is determined, and at least one set of candidate design parameters is determined, including the number of candidate compute chip groups, the size of the candidate compute chip group, the shape of the candidate compute chip group, and the candidate position of the port chip.

[0017] The aforementioned silicon substrate network physical topology and silicon substrate chip architecture include a central switch and multiple computing chip groups. Each computing chip group is connected to the central switch, which is located at the center of the wafer. Each computing chip group is located on the wafer within a predetermined area surrounding the central switch. The central switch acts as a data routing node, providing a signal path for any two computing chip groups. Each computing chip group comprises multiple computing chips arranged in a two-dimensional mesh and interconnected via on-chip networks. The computing chips are used to compute data. The physical topology of the silicon substrate network is a heterogeneous structure with multiple computing chip groups connected to the central switch. Locally, it consists of mesh groups scattered across the wafer, with computing chips within each group interconnected via on-chip networks. This allows for the deployment of as many computing chips as possible on the wafer to improve computing resources. Globally, each computing chip group forms a fully connected structure through the central switch, reducing communication latency. Thus, this multi-layered physical topology ensures a balance between communication and computing resources. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the physical topology of a silicon substrate network in one embodiment;

[0020] Figure 2 This is a schematic diagram of the physical topology of a silicon substrate network in one embodiment;

[0021] Figure 3 This is a schematic diagram of the 2D Mesh physical topology;

[0022] Figure 4 A schematic diagram of the physical constraints of a silicon substrate chip;

[0023] Figure 5 This is a flowchart of a method for generating the physical topology of a silicon substrate network in one embodiment;

[0024] Figure 6 This is a flowchart illustrating the steps for determining the design parameters of the physical topology of a silicon substrate network in one embodiment.

[0025] Figure 7 This is a structural block diagram of a silicon substrate network physical topology generation device in one embodiment;

[0026] Figure 8This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "a plurality of" used in this application refers to two or more. In the description of this invention, "at least one" means at least one, such as one, three, etc., unless otherwise explicitly specified. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0029] Silicon-on-a-chip (SiC) networks refer to the interconnect networks between components on a silicon-on-a-chip (SiC) wafer, specifically the interconnect networks between various components connected by interposers on the wafer. Due to numerous physical design constraints, SiC network design differs significantly from other cluster architectures. Specifically, the design constraints lie in the trade-offs of on-chip resources and the interconnect topology constraints resulting from placement and routing constraints. Firstly, the total area occupied by computing, storage, and interconnect resources must be less than the wafer area. This leads to a trade-off design space where increasing interconnect resource area means reducing the area of ​​other resources. However, computing, storage, and communication all significantly impact training throughput under large model training loads, requiring meticulous experimental allocation of on-chip resources. Current GPU and TPU cluster designs do not address this trade-off design space; their interconnect networks are independent of the computing cluster and not constrained by total area, allowing for optimization solely based on communication dimensions. For SiC networks, however, there is currently no complete design scheme that fully considers physical constraints.

[0030] Considering factors such as interconnect robustness and transmission delay, the interconnect length on a wafer must be less than 50mm. Furthermore, due to limitations on the number of metal layers, only a maximum of three metal layers can be used for wiring, thus imposing strict requirements on interconnect density. Currently, commonly used flat two-dimensional planar topologies in computing clusters, such as Flattened Butterfly, Torus, and Dragonfly, are difficult to apply to silicon substrate networks due to layout and wiring constraints.

[0031] Currently, both academia and industry are actively researching how to design silicon substrate network topologies to achieve higher throughput for training large AI models. Although these technologies have expanded the design options for network topologies, existing designs do not take into account various physical design constraints, making them difficult to apply to silicon substrate networks. Furthermore, current solutions do not consider the multi-dimensional trade-offs in design space brought about by physical constraints, but only optimize the design in one dimension. Existing silicon substrate network physical topologies are unable to guarantee a balance between communication and computing resources.

[0032] In view of this, this application provides a silicon substrate network physical topology and silicon substrate chip architecture that can ensure a balance between communication resources and computing resources.

[0033] In one exemplary embodiment, such as Figure 1 As shown, a silicon substrate network physical topology is provided. This topology includes a central switch 10 and multiple computing chip groups 20. Each computing chip group 20 is connected to the central switch 10. The central switch 10 is located at the center of the wafer, and each computing chip group 20 is located on the wafer within a predetermined area surrounding the central switch. The central switch 10 serves as a data routing node, providing a signal path for any two computing chip groups 20. Each computing chip group 20 includes multiple computing chips 201 arranged in a two-dimensional grid. The computing chips 201 are interconnected through an on-chip network and are used for data computation.

[0034] Optionally, the wafer is the basic material in the semiconductor manufacturing process. The wafer area is limited, and the central switch 10 and each computing chip group 20 are all set on the wafer.

[0035] Optionally, each computing chip group 20 is connected to the central switch 10 via a network on chip (NoC), where NoC is an on-chip interconnect network used to connect each computing chip 102 in the computing chip group 20, enabling high-speed data transmission and collaborative work between the computing chips.

[0036] For example, the distance between computing chips in the computing chip group is as small as possible. It is understood that due to the limited interconnect length of the chips, the bit error rate will increase significantly when the data transmission distance exceeds 50 mm. To reduce the bit error rate, forward error correction coding needs to be introduced, which will lead to a significant increase in transmission delay. Therefore, the distance between computing chips in the computing chip group is as small as possible, much less than 50 mm, and data transmission and collaborative work can be achieved through short-distance NoCs, where short-distance NoCs are used for internal short-range communication.

[0037] Optionally, the on-chip network architecture in the computing chip group 20 is a two-dimensional mesh topology. The computing chips 201 are arranged in a two-dimensional mesh, and each computing chip 201 is connected to other adjacent computing chips 201 via horizontal and vertical links, forming a regular mesh structure. Simultaneously, the position of each computing chip can be represented by two-dimensional coordinates, and each computing chip 201 is typically only connected to its four adjacent computing chips 201 (excluding boundary computing chips in the computing chip group 20). This local connection method reduces communication latency and power consumption, while also resulting in shorter interconnect lengths and lower interconnect density, enabling the deployment of computing chips at the highest density, achieving the theoretically highest computing power within a limited area.

[0038] Optionally, data transmission between computing cores 201 in computing core group 20 is based on the XY routing algorithm.

[0039] In 2D Mesh, when data is transmitted based on the XY routing algorithm, the data is first transmitted horizontally until it reaches the same column as the target computing core, and then transmitted vertically until it reaches the target computing core.

[0040] During data transmission based on the XY routing algorithm, if some paths are overloaded and resource contention occurs, a round-robin mechanism can be used to transmit each data. Specifically, during data transmission, the overloaded computing core can transmit each data in the order of arrival time, based on the available arrival time, and transmit the data with the earliest arrival time first.

[0041] It is understandable that the individual computing chips 201 in a computing chip group 20 are interconnected through an on-chip network to achieve data transmission. When two computing chip groups 20 transmit data, they can be connected through a central switch 10. By placing the central switch 10 at the center of the wafer and arranging each computing chip group 20 around the central switch 10, the data transmission distance can be kept as short as possible, thus meeting the chip interconnect length limit.

[0042] like Figure 2 The diagram shown is a layout of the Mesh-Switch physical topology in an embodiment of this application. Compared to the 2D Mesh physical topology in the prior art, referencing... Figure 3In current 2D Mesh physical topologies, each computing chip is only interconnected with chips in its four cardinal directions (up, down, left, and right). However, as the number of computing chips increases, on-chip communication performance becomes a bottleneck. Because the communication radius is positively correlated with chip size, communication latency and time overhead are significantly higher than in other physical topologies. Furthermore, the central network has a high communication load while the edge network has a low load, resulting in a severe communication imbalance. This application's embodiment, through a heterogeneous structure connecting multiple computing chip groups and a central switch, ensures a balance between communication and computing resources.

[0043] The aforementioned silicon substrate network physical topology includes a central switch and multiple computing chip groups. Each computing chip group is connected to the central switch, which is located at the center of the wafer. Each computing chip group is located on the wafer within a predetermined area surrounding the central switch. The central switch acts as a data routing node, providing a signal path for any two computing chip groups. Each computing chip group comprises multiple computing chips arranged in a two-dimensional mesh and interconnected via on-chip networks. The computing chips are used to compute data. The physical topology of the silicon substrate network is a heterogeneous structure with multiple computing chip groups connected to the central switch. Locally, it consists of mesh groups scattered across the wafer, with computing chips within each group interconnected via on-chip networks. This allows for the deployment of as many computing chips as possible on the wafer to improve computing resources. Globally, the computing chip groups form a fully connected structure through the central switch, reducing communication latency. Thus, this multi-layered physical topology ensures a balance between communication and computing resources.

[0044] In an exemplary embodiment, the central switch 10 includes at least one switching core, and a port core in the computing core group 20 is connected to one of the switching cores in the central switch 10 via a high-speed link. The port core is a computing core 201 in the computing core group 20.

[0045] Optionally, the central switch 10 may include one or more switching cores. In this embodiment, the number of switching cores is not limited.

[0046] When the central switch 10 includes multiple switching cores, there are no restrictions on the layout of each switching core.

[0047] Optionally, the port particle can be any one of the computing particles 201 located at the boundary position in the computing particle group 20. For example, if a computing particle group 20 includes 6 computing particles 201 and each computing particle 201 is arranged in a 2-row, 3-column format, then the port particle can be any one of the computing particles 201 in the computing particle group 20. Alternatively, each computing particle 201 can be simulated as a candidate port particle, and the candidate port particle with the best network performance (e.g., throughput) can be selected as the port particle.

[0048] The port cores in the aforementioned computing core groups are connected to a switching core in the central switch via a high-speed link, enabling data transmission between the various computing core groups and avoiding communication delays as the number of computing cores increases. Simultaneously, the high-speed link connection between the port cores and the switching core in the central switch supports high data transmission rates and low data transmission latency.

[0049] In an exemplary embodiment, the central switch 10 includes multiple switching cores interconnected via an on-chip network and performs data transmission based on an XY routing algorithm; the switching cores are used to transmit multiple data based on a polling mechanism.

[0050] Optionally, the central switch 10 may include multiple switching cores, one of which may be connected to a port core in at least one computing core group 20 and transmit data from one computing core group 20 to another computing core group by connecting to other switching cores.

[0051] Optionally, the on-chip network architecture of the central switch 10 is also a two-dimensional mesh topology, with each switching core arranged in a two-dimensional mesh. Data transmission between the switching cores is based on the XY routing algorithm, which will not be elaborated here.

[0052] For example, the number of switching cores in the central switch 10 is the same as the number of computing core groups 20, and one switching core is connected to a port core in one computing core group 20.

[0053] For example, taking a silicon substrate network physical topology that includes 10 computing core groups, the 10 computing core groups are arranged around a central switch. The central switch includes 10 switching cores. When a computing core in one computing core group communicates with a target computing core in another computing core group, the data can first be transmitted to a port core in the computing core group based on the XY routing algorithm. The port core then transmits the data to the corresponding switching core through a high-speed link. Then, the switching core transmits the data to the target switching core through the XY routing algorithm. The target switching core is a switching core connected to a port core in another computing core group. The target switching core then transmits the data to a port core in another computing core group, and finally to the target computing core.

[0054] In an exemplary embodiment, the number of compute chip groups, the size of compute chip groups, the shape of compute chip groups, and the position of port chips are determined based on wafer physical design constraints and silicon substrate network performance; wherein, the size of compute chip groups is used to characterize the number of compute chips in the compute chip group, and the shape of compute chip groups is used to characterize the positional arrangement of each compute chip in the compute chip group.

[0055] Wafer physical design constraints can include wafer area constraints, wafer wiring length constraints, and wafer wiring layer number constraints. In silicon-based chip design, physical constraints profoundly affect chip size, performance, and final yield, stemming from the inherent physical limitations of semiconductor manufacturing processes and the characteristics of the wafer itself. For example... Figure 4 As shown, firstly, the wafer area is limited. Within a wafer area of ​​70,000 square millimeters, the computing die and memory cells need to be rationally allocated. Figure 4 Taking high-bandwidth memory (HBM) as an example, the area of ​​interconnect networks and other functional circuits is limited. Secondly, the interconnect length is limited; when the data transmission distance exceeds 50 mm, the bit error rate increases significantly, requiring the introduction of forward error correction coding, which leads to a substantial increase in transmission delay. Furthermore, wiring density is also limited, typically restricted to three metal layers, and long-distance, high-density wiring is not permitted.

[0056] Optionally, a simulator can be used to simulate the loading of a large language model load to obtain the throughput corresponding to the design parameters of different silicon substrate network physical topologies, and the corresponding silicon substrate network performance can be determined based on the throughput. The design parameters may include the number of computational cores, the size of the computational cores, the shape of the computational cores, and the position of the port cores.

[0057] In one exemplary embodiment, a silicon substrate chip architecture is provided, including the silicon substrate network physical topology as described in any of the above embodiments.

[0058] The following is an exemplary description of the process for determining the design parameters in the physical topology of the silicon substrate network in the above embodiments. In one exemplary embodiment, such as Figure 5 As shown, a method for generating the physical topology of a silicon substrate network is provided, the method comprising:

[0059] Step 501: Obtain wafer area, calculate chip area, and exchange chip area.

[0060] Optionally, the wafer area, calculated chip area, and exchanged chip area can be preset or input by the user before simulation.

[0061] In obtaining the area of ​​the computed core, the computing power corresponding to the computed core can also be obtained. For example, the area of ​​the computed core can be 876 mm².2 The computing power of the switching core can be calculated to be 362 TFLOPs. Similarly, when obtaining the switching core area, the data transmission rate of the switching core can be obtained. For example, if the switching core area is 658 mm², the data transmission rate of the switching core can be obtained. 2 The data transmission rate is 51.2Tb / s.

[0062] Step 502: Based on the spatial exploration algorithm, determine the design parameters of the physical topology of the silicon substrate network while meeting the wafer physical design constraints and silicon substrate network performance requirements.

[0063] The design parameters include the number of computational core groups, the size of the computational core groups, the shape of the computational core groups, and the position of the port cores. The size of the computational core group characterizes the number of computational cores in the group, and the shape of the computational core group characterizes the positional arrangement of the computational cores within the group.

[0064] Optionally, spatial exploration algorithms are a class of algorithms used to search for optimal solutions or solutions that satisfy specific conditions in complex spaces. They may include biologically inspired algorithms (such as genetic algorithms or ant colony algorithms) or brute-force search algorithms.

[0065] For example, different computing chip group sizes can be traversed from the outer loop, and different computing chip group shapes can be traversed under each computing chip group size. Under each computing chip group shape, different port chip positions can be traversed. In this way, through nested loops, simulations can be performed based on different design parameters while satisfying wafer physical design constraints. The performance of silicon substrate network under different design parameters can be obtained, and the design parameters with the best silicon substrate network performance (maximum throughput) can be used as the design parameters of the silicon substrate network physical topology.

[0066] In the above method, the wafer area, the calculated chip area, and the exchanged chip area are obtained. Based on the spatial exploration algorithm, the design parameters of the physical topology of the silicon substrate network are determined under the condition of meeting the wafer physical design constraints and silicon substrate network performance requirements. The wafer physical design constraints and silicon substrate network performance requirements can be used as conditions. The number of computing chip groups, the size of computing chip groups, the shape of computing chip groups, and the position of port chips in the physical topology of the silicon substrate network are determined by the spatial exploration algorithm, thereby determining the optimal physical topology of the silicon substrate network that balances computing resources and communication resources.

[0067] In one embodiment, such as Figure 6 As shown, based on the spatial exploration algorithm, the design parameters of the physical topology of the silicon substrate network are determined while satisfying the wafer physical design constraints and silicon substrate network performance requirements. These parameters include:

[0068] Step 601: Obtain multiple candidate computational core group sizes. The candidate computational core group size is any value within a preset range.

[0069] Optionally, each integer value within a preset range can be used as a candidate computational core group size to obtain multiple candidate computational core group sizes.

[0070] Step 602: For each candidate computational chip group size, under the premise of satisfying the wafer physical design constraints, determine at least one set of candidate design parameters based on the candidate computational chip group size.

[0071] Optionally, for each candidate computational core group size, different candidate computational core group shapes can be determined based on the computational core group size. For example, when the computational core group size is 4, the candidate computational core group shape can be a 2×2 mesh group or a 1×4 mesh group. Then, for each candidate computational core group shape, the positions of different port cores are determined. For a 2×2 mesh group, there are 4 possible candidate positions for the port cores. For a 1×4 mesh group, there are also 4 possible candidate positions for the port cores. Thus, when the computational core group size is 4, 2×4=8 sets of candidate design parameters can be obtained.

[0072] Optionally, while satisfying wafer physical design constraints, at least one set of candidate design parameters is determined based on the candidate computed chip group size, including:

[0073] The number of candidate compute grain groups is determined based on the wafer area, compute grain area, exchange grain area, and candidate compute grain group size; at least one candidate compute grain group shape is determined based on the candidate compute grain group size; for each candidate compute grain group shape, at least one candidate position of port grain is determined, and at least one set of candidate design parameters is determined, including the number of candidate compute grain groups, the size of candidate compute grain groups, the shape of candidate compute grain groups, and the candidate position of port grains.

[0074] Optionally, since the number of switching cores in the central switch is the same as the number of computing core groups, the maximum number of candidate computing core groups can be set based on the wafer area, computing core area, switching core area, and candidate computing core group size, provided that the wafer area does not exceed 50mm and the interconnect length does not exceed 50mm.

[0075] With the number and size of the calculated core groups fixed, different candidate calculated core group shapes are determined based on the candidate calculated core group size. Then, for different candidate calculated core group shapes, multiple sets of candidate design parameters are determined based on the candidate positions of the core particles at different ports, with the number, size, and shape of the calculated core groups fixed.

[0076] Step 603: Perform simulation evaluation on each candidate design parameter, and take the candidate design parameter corresponding to the maximum performance of the silicon substrate network as the design parameter of the physical topology of the silicon substrate network.

[0077] Optionally, when each set of candidate design parameters is determined, the throughput corresponding to the physical topology of the silicon substrate network based on the candidate design parameters can be simulated by a simulator when a large language model load is applied, and the throughput and the corresponding candidate design parameters can be stored.

[0078] For example, multiple sets of throughput and corresponding candidate design parameters can be stored, and then the throughput can be sorted. The candidate design parameters corresponding to the maximum throughput can be used as the design parameters for the physical topology of the silicon substrate network. Alternatively, only the maximum throughput and the corresponding candidate design parameters can be stored. That is, after each simulation evaluation, the throughput obtained from the current simulation can be compared with the throughput determined based on the previous candidate design parameters, and the maximum throughput and the corresponding candidate design parameters can be stored.

[0079] For example, in a wafer area of ​​5000 mm² 2 The calculated core area is 876 mm². 2 The computing power of the core is 362 TFLOPs, and the exchange core area is 658 mm². 2 When the data transmission rate is 51.2 Tb / s and the interconnect length does not exceed 50 mm, and the number of computing chip groups is determined to be 10, the size of each computing chip group is 4, and the shape of each computing chip group is 2×2 Mesh, the silicon substrate network exhibits excellent performance in terms of computing density, communication efficiency, and wiring compliance through the above generation method. In this case, the physical topology of the silicon substrate network includes a central switch and 10 computing chip groups. Each computing chip group is connected to the central switch, which is located at the center of the wafer. Each computing chip group is located on the wafer within a predetermined area surrounding the central switch. One computing chip group includes 4 computing chips, arranged in a 2×2 Mesh configuration.

[0080] Based on the same inventive concept, this application also provides a silicon substrate network physical topology generation apparatus for implementing the silicon substrate network physical topology generation method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the silicon substrate network physical topology generation apparatus provided below can be found in the limitations of the silicon substrate network physical topology generation method described above, and will not be repeated here.

[0081] In one exemplary embodiment, such as Figure 7As shown, a silicon substrate network physical topology generation apparatus 700 is provided, comprising: an acquisition module 701 and a determination module 702, wherein:

[0082] The acquisition module 701 is used to acquire the wafer area, calculate the chip area, and exchange the chip area;

[0083] The determination module 702 is used to determine the design parameters of the physical topology of the silicon substrate network based on a spatial exploration algorithm, while meeting the wafer physical design constraints and silicon substrate network performance requirements. The design parameters include the number of computing core groups, the size of the computing core groups, the shape of the computing core groups, and the position of the port cores. The size of the computing core groups is used to characterize the number of computing cores in the computing core groups, and the shape of the computing core groups is used to characterize the positional arrangement of the computing cores in the computing core groups.

[0084] Each module in the aforementioned silicon substrate network physical topology generation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0085] In one exemplary embodiment, a computer device is provided, which may be a server or a computer, and its internal structure diagram may be as follows: Figure 8 As shown, the computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for generating a silicon substrate network physical topology.

[0086] Those skilled in the art will understand that Figure 8The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0088] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A silicon substrate network physical topology, characterized by, The silicon substrate network physical topology structure comprises a central switch and a plurality of computing chip groups, each of the computing chip groups is connected with the central switch, the central switch is arranged at the center of a wafer, and each of the computing chip groups is arranged in a preset area around the central switch on the wafer; The central switch is configured to serve as a data routing node and provide a signal path for any two computing chip groups. Each of the computing chip groups comprises a plurality of computing chips arranged in a two-dimensional grid form, and the computing chips are interconnected through an on-chip network.

2. The silicon substrate cyber physical topology of claim 1, wherein, The central switch comprises at least one switching chip, and a port chip in the computing chip group is connected with one switching chip in the central switch through a high-speed link, and the port chip is one computing chip in the computing chip group.

3. The silicon substrate cyber physical topology of claim 2, wherein, The number of the computing chip groups, the size of the computing chip groups, the shape of the computing chip groups and the position of the port chip are determined based on wafer physical design constraints and silicon substrate network performance. The size of the computing chip group is used to represent the number of the computing chips in the computing chip group, and the shape of the computing chip group is used to represent the position arrangement of the computing chips in the computing chip group.

4. The silicon substrate cyber physical topology of claim 1, wherein, The data transmission between each of the computing chips in the computing chip group is based on an XY routing algorithm.

5. The silicon substrate cyber physical topology of claim 2, wherein, The central switch comprises a plurality of switching chips, each of the switching chips is interconnected through an on-chip network, and the data transmission between each of the switching chips is based on an XY routing algorithm. The switching chip is configured to transmit each of the data based on a polling mechanism when transmitting a plurality of data.

6. The silicon substrate cyber physical topology of claim 5, wherein, The number of the switching chips in the central switch is the same as the number of the computing chip groups.

7. A silicon substrate chip architecture, characterized by, The silicon substrate network physical topology structure comprises any one of claims 1-6.

8. A method for generating a network physical topology of a silicon substrate, the method comprising: receiving a plurality of network physical topology data; and generating a network physical topology of the silicon substrate based on the plurality of network physical topology data. The method comprises: obtaining the wafer area, the computing chip area and the switching chip area; determining the design parameters of the silicon substrate network physical topology structure based on a space exploration algorithm under the condition that the wafer physical design constraints and the silicon substrate network performance requirements are met, the design parameters comprising the number of the computing chip groups, the size of the computing chip groups, the shape of the computing chip groups and the position of the port chip; The size of the computing chip group is used to represent the number of the computing chips in the computing chip group, and the shape of the computing chip group is used to represent the position arrangement of the computing chips in the computing chip group.

9. The method of claim 8, wherein, The method comprises: obtaining a plurality of candidate computing chip group sizes, the candidate computing chip group size being any value in a preset value range; for each of the candidate computing chip group sizes, determining at least one set of candidate design parameters according to the candidate computing chip group size under the condition that the wafer physical design constraints are met; for each of the candidate design parameters, performing simulation evaluation, and taking the candidate design parameter corresponding to the maximum silicon substrate network performance as the design parameter of the silicon substrate network physical topology structure.

10. The method of claim 9, wherein, The method comprises the following steps: determining at least one set of candidate design parameters according to the candidate compute core group size under the condition of satisfying the wafer physical design constraint, wherein the candidate design parameters comprise the candidate number of compute core groups, the candidate compute core group size, the candidate compute core group shape and the candidate position of the port core; determining the candidate number of compute core groups according to the wafer area, the compute core area, the exchange core area and the candidate compute core group size; determining at least one candidate compute core group shape according to the candidate compute core group size; for each candidate compute core group shape, determining at least one candidate position of the port core and determining at least one set of candidate design parameters, wherein the candidate design parameters comprise the candidate number of compute core groups, the candidate compute core group size, the candidate compute core group shape and the candidate position of the port core.

Images