PCB differential line wiring method, design method and PCB
By using differential line routing and vertical coupling, the problems of high routing difficulty and cost in the BGA area are solved, achieving more efficient routing and improved signal quality, which is suitable for high-density integrated circuit design.
Patent Information
- Application Number
- CN202410897581.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-05
- Publication Date
- 2026-01-06
AI Technical Summary
When routing high-speed lines in the BGA area, the existing parallel differential line routing method on the same layer results in high routing difficulty, high processing cost, and easily affected signal quality, making it difficult to meet the needs of high-density integrated circuit design.
The heterogeneous differential routing method is adopted, which involves fanning out curved traces around the trace pads in the middle layer of the PCB and adding copper areas on the curved traces. Combined with vertical coupling, the impedance is reduced and the coupling effect is enhanced.
It saves cabling space, reduces cabling pressure, improves signal quality, reduces crosstalk, lowers production costs, and achieves more efficient cabling capabilities.
Smart Images
Figure CN121284833A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of printed circuit board (PCB) technology, and particularly relates to a PCB differential line routing method, design method, and PCB. Background Technology
[0002] High-speed, high-performance chips are used in most electronic devices. In the process of high-density integrated circuit layout design, high-speed signals must be routed in the ball grid array (BGA) area of the chip. However, the BGA area has a high density of different signal vias and return ground vias. High-speed routing in the BGA area places high demands on PCB layout and routing, and unreasonable design can easily affect the signal quality of high-speed routing.
[0003] To address the challenges of layout and routing in the BGA area, the signal lines connecting various chips can be designed as differential lines to increase crosstalk immunity, such as... Figure 1 The image shows a top view of a PCB with differential line routing in the prior art. Parallel differential lines on the same layer are used in the BGA area. Specifically, two parallel signal lines (i.e., differential lines) on the same layer are routed in area 1. However, due to the limited space between the two pads, the line width and spacing between the two parallel signal lines on the same layer are small, resulting in excessively high trace impedance. For example... Figure 1 In region 1, the two signal lines have very small line widths and spacings. The impedance of each signal line increases compared to when there is only one trace between the two pads (with ample routing space). Furthermore, the spacing between most chip pads is only about 1mm. Using two parallel signal lines on the same layer for differential lines increases routing difficulty, etching difficulty for the PCB manufacturer, and makes it impossible to guarantee finished product tolerances. This reaches the limit of differential line routing capabilities, making it impossible to manufacture traces with smaller line widths and spacings. This method of using parallel differential lines on the same layer places high demands on the PCB manufacturer's capabilities, significantly increasing the manufacturing cost of PCBs using this method.
[0004] Therefore, conflicts between differential line routing methods, PCB manufacturing capabilities, and BGA area routing requirements are inevitable problems faced by every PCB layout and routing that contains chips. Effectively solving this problem can make the interconnection between chips and PCBs smoother and realize various high-density integrated circuit design functions. Summary of the Invention
[0005] To address the aforementioned technical problems, this application provides a PCB differential line routing method, design method, and PCB. By routing differential lines across different layers, routing space is saved, routing pressure in the BGA area is reduced, and a vertical coupling method is used for rapid coupling of differential lines, resulting in stronger differential line coupling. This application employs flexible curved traces and area copper filling for differential lines: curved traces provide copper space, and area copper filling increases the trace capacitance of differential lines and reduces differential line impedance.
[0006] The objective of this application is achieved through the following technical solution:
[0007] In a first aspect, embodiments of this application provide a PCB differential line routing method, wherein the PCB includes at least a first differential line, and the method includes:
[0008] On the middle layer of the PCB, the first differential line is fanned out with a curved trace around the trace pad within the spherical grid array area, based on the principle of not entering the pad keepout region. The pad keepout region is a circular area, the center of which coincides with the center of the trace pad, and the radius of the pad keepout region is greater than or equal to the radius of the trace pad + 3 μm.
[0009] In one possible implementation, before fanning out curved traces around the trace pads within the spherical grid array region for the first differential line, the method further includes:
[0010] The curvature and radius of the fan-out curved trace of the first differential line are determined based on the simulation results.
[0011] In one possible implementation, the method further includes:
[0012] A copper-filled area is added to the curved trace of the first differential line. The copper-filled area is the area enclosed by two troughs and one peak of the curved trace. The two troughs are connected by a straight line, and the trough and the peak are connected by an arc.
[0013] In one possible implementation, the first differential line includes a first line and a second line. The first differential line is fanned out on the intermediate layer of the PCB. Specifically, the first line and the second line are fanned out on different layers of the intermediate layer of the PCB. The projections of the first line and the second line completely overlap. The first line and the second line are coupled through the shortest connection path. The differential line coupling method is vertical coupling.
[0014] Secondly, embodiments of this application provide a PCB differential line routing method, wherein the PCB further includes at least a second differential line, and the second differential line is routed according to the routing method of the first differential line in the PCB differential line routing method described in the first aspect above, wherein the spacing between the first differential line and the second differential line is greater than or equal to the minimum processing distance of the PCB.
[0015] In one possible implementation, the curvature and radius of the fan-out curved traces of the first differential line and the second differential line are the same.
[0016] In one possible implementation, the vertical distance between the first differential line and the nearest reference layer is less than the horizontal distance between the first differential line and the second differential line; the vertical distance between the second differential line and the nearest reference layer is less than the horizontal distance between the first differential line and the second differential line.
[0017] Thirdly, embodiments of this application provide a PCB differential line design method, the method comprising:
[0018] Design layer-change vias around the chip pads according to the number of wiring layers of the PCB. Differential lines are led out from the chip pads through the layer-change vias to the middle layer of the PCB.
[0019] In the middle layer of the PCB, the differential lines are coupled along the shortest connection path between the trace pads, and the differential line coupling method is vertical coupling.
[0020] Based on the principle of not entering the pad ban area, curved traces are fanned out around the trace pads within the spherical grid array area for the differential lines. The curvature and radius of the curved traces are determined based on simulation results.
[0021] A copper-filled area is added to the curved trace of the differential line. The copper-filled area is the area enclosed by two troughs and one peak of the curved trace. The two troughs are connected by a straight line, and the trough and the peak are connected by an arc.
[0022] Fourthly, embodiments of this application provide a PCB, the PCB including a first differential line routed according to the PCB differential line routing method described in the first aspect above.
[0023] In one possible implementation, the PCB further includes at least a second differential line, which is routed according to the routing method of the first differential line in the PCB differential line routing method described in the first aspect above, and the spacing between the first differential line and the second differential line is greater than or equal to the minimum processing distance of the PCB.
[0024] This application provides a PCB differential line routing method, design method, and PCB. By routing differential lines across different layers, it saves routing space, reduces routing pressure in the BGA area, and employs vertical coupling for rapid differential line coupling, resulting in stronger differential line coupling. This application utilizes flexible curved traces and area copper filling for the differential lines: curved traces provide copper space, and area copper filling increases the trace capacitance and reduces differential line impedance. In this application, the two differential lines fan out curved traces with the same curvature and radius, thereby achieving symmetrical routing in adjacent areas of the two differential lines, fully utilizing routing space, and significantly reducing crosstalk between differential lines. Attached Figure Description
[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 A top view of a PCB with existing differential line routing technology;
[0027] Figure 2 A flowchart of a PCB differential line design method provided in this application embodiment;
[0028] Figure 3 A PCB side view provided for an embodiment of this application;
[0029] Figure 4 A top view of a PCB provided for an embodiment of this application.
[0030] Icons: 1-Upper ground plane, 2-Lower ground plane, 3-Intermediate layer, 4-Intermediate layer, 5-PCB resin material and glass fiber, 6-Via, 7-Via, 8-Pack keepout area, 9-Spacing between two differential lines, 01-First line of the first differential line, 02-Second line of the first differential line, 03-First line of the second differential line, 04-Second line of the second differential line, 11-Trace pad, 12-Trace pad, 13-Trace pad, 14-Trace pad. Detailed Implementation
[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0032] The terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.
[0033] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design that is described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0034] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.
[0035] First, let me explain some basic concepts involved in this application:
[0036] BGA (Ball Grid Array) area: In this embodiment, it refers to the densely via area within the board covered by the chip.
[0037] Differential lines: These are a pair (two) copper traces that are coupled to each other (also referred to as signal lines in this embodiment). The mutual coupling can improve the anti-crosstalk capability and is often used for high-speed traces.
[0038] Line width: The trace width of one signal line in a differential line.
[0039] Line spacing: The distance between the two signal lines of a differential line.
[0040] Fan-out routing: The behavior of routing within a BGA area to the outside of the BGA area.
[0041] PCB: Printed circuit board, which supports various electronic components and enables electrical connections between them.
[0042] PCB Layout: Printed board circuit layout and wiring, refers to the general term for the placement and electrical connection of electronic components (chips).
[0043] Consistency: refers to the fact that the appearance and performance parameters of each piece of equipment produced in batches are consistent and there are basically no differences.
[0044] Reliability: refers to the stability of a single device operating within the permissible environmental range (temperature, humidity, pressure, etc.).
[0045] Coupling: refers to the situation where electromagnetic fields intersect between traces on a PCB, and one trace can affect another adjacent trace.
[0046] The above method will be described in detail below with reference to specific embodiments.
[0047] High-speed, high-performance chips are used in most electronic devices. In the process of high-density integrated circuit layout design, high-speed signals must be routed in the BGA area of the chip. However, the BGA area has a high density of different signal vias and return ground vias. High-speed routing in the BGA area places high demands on PCB layout and routing, and unreasonable design can easily affect the signal quality of high-speed routing.
[0048] To address the challenges of BGA area layout and routing, signal lines connecting various chips can be designed as differential lines to increase crosstalk immunity. Currently, existing technology uses parallel differential line routing on the same layer; however, this approach still presents the following technical problems:
[0049] Because the distance between the two chip pads is limited, typically only about 1mm, when the differential lines are routed in parallel on the same layer, the trace width and spacing of the two signal lines are very small. This results in high impedance or impedance discontinuity in the differential lines, which in turn causes signal reflection and loss. Furthermore, the small trace width and spacing of the two signal lines lead to a fixed routing method, placing them near the no-access areas of vias. This poses a risk of the drill breaking the traces during via fabrication, increasing PCB fabrication difficulty and production costs. In parallel differential line routing on the same layer, the spacing between pads is limited. If multiple differential lines are needed, the spacing between them is very small. This small spacing increases the electromagnetic coupling area between different differential signals, increasing the total coupling energy. This leads to increased crosstalk between differential lines, and the coupling energy of one signal line is considered noise relative to another. The ratio of noise signal to useful signal is crosstalk.
[0050] This application provides targeted technical solutions to address the above-mentioned technical problems. The complete technical solution and thought process are explained in detail here.
[0051] In the embodiments of this application, the trace impedance can be equivalently represented as the ratio of inductive to capacitive impedance, which can be expressed by the following formula: Impedance and capacitance are inversely proportional, while impedance and inductance are directly proportional. Based on this principle, in this embodiment, the trace width can be increased to increase trace capacitance, thus solving the problem of small trace width and high trace impedance. Simultaneously, increased trace capacitance improves the trace's anti-crosstalk capability, i.e., capacitive filtering. However, increasing the trace width must also ensure a certain safe distance from other differential lines; that is, the coupling strength between different differential lines should not be too strong to avoid excessive crosstalk. In the BGA area, the spacing between pads is very small, making it difficult to route differential lines on the same plane. Existing technologies using parallel differential line routing on the same layer lead to problems such as high impedance, excessive crosstalk, and increased production costs. Therefore, in this embodiment, we consider using heterogeneous differential line routing and switching the differential lines from horizontal coupling to vertical coupling. Vertical coupling results in a larger relative area between the two signal lines of the differential line, leading to stronger coupling. This also solves the problem of high routing difficulty.
[0052] To achieve the above objectives, this application provides a PCB differential line routing method, wherein the PCB includes at least one differential line, and the method includes:
[0053] Fan out the differential line on the middle layer of the PCB. Based on the principle of not entering the pad ban area, fan out the differential line in a curved shape around the trace pad within the spherical grid array area.
[0054] In this embodiment, the differential lines are routed on the middle layer of the PCB, avoiding the routing of differential lines in densely padded areas such as the top and bottom layers of the PCB, thus greatly reducing the difficulty of differential line routing. The middle layer of the PCB refers to any layer on the PCB other than the top and bottom layers.
[0055] For example, all pads within the BGA area are circular. These pads include trace pads or chip pads, etc. The chip pads and trace pads are located on different layers of the PCB. The method of increasing trace tolerance by routing between pads is also considered here, using circular shapes. One possible implementation is that the trace pads and differential lines are located on the same layer of the PCB, using curves around the trace pads. This not only fits the existing feature shape but also makes more efficient use of space to increase trace tolerance.
[0056] In this embodiment, based on the principle of not entering the pad-free (i.e., no-routing) area, curved traces are fanned out around the trace pads within the BGA area for differential lines. For example, the pad-free area is a circular region, with its center coinciding with the center of the trace pad, and its radius being greater than or equal to the radius of the trace pad + 3 μm.
[0057] In one possible implementation, before fanning out curved traces around the trace pads within the BGA region, the PCB differential line routing method provided in this application embodiment further includes:
[0058] The curvature and radius of the fan-out curved trace of the differential line are determined based on the simulation results.
[0059] Preferably, the curvature and radius of each peak or trough of the differential line fan-out curved trace are the same to reduce the difficulty of PCB manufacturing. Obviously, the curvature and radius of each peak or trough of the differential line fan-out curved trace can also be different, as long as the curved trace does not enter the pad keep-out area.
[0060] In one possible implementation, to increase trace capacitance, the total area of the trace can be increased to increase the equivalent capacitance. An embodiment of this application provides a PCB differential line routing method that further includes adding a copper-filled area to the curved trace of the differential line to increase the total volume of the trace, thereby increasing the equivalent capacitance. The copper-filled area is the region enclosed by two troughs and one peak of the curved trace, with a straight line connecting the two troughs and an arc connecting the trough and the peak. For example, after the differential line is fanned out into a curved trace, periodic copper-filling is performed in a certain manner to increase the total volume of the curved trace, thereby improving the trace capacitance and reducing the trace impedance. In this embodiment, the copper pour area is a region enclosed by two troughs and one crest of a curved trace. The two troughs are connected by a straight line, and the troughs and crests are connected by an arc. In this copper pour area structure, one side of the curved trace is arc-shaped to fit the shape of the pad and avoid entering the pad's no-go area. The other side of the curved trace is always straight to avoid shortening the spacing between it and other differential lines (or other signal traces), thus avoiding increased crosstalk and signal incompleteness.
[0061] In this embodiment, the solder balls of the chip are attached to the corresponding number of pre-made chip pads on the PCB board. The differential lines start from two adjacent chip pads and reach the internal routing layer of the PCB through layer-changing vias. The two signal lines of the differential lines reach different layers to achieve heterogeneous differential line routing.
[0062] In one possible implementation, a differential line includes two signal lines. The differential line is fanned out in the middle layer of the PCB, specifically including: two signal lines are fanned out in different layers of the middle layer of the PCB, and the projection areas of the two signal lines completely overlap.
[0063] In one possible implementation, to minimize uncoupled traces, the two signal lines are coupled differentially via the shortest connection path (the straight-line distance between the two pads), and the differential coupling method is perpendicular coupling. This rapid coupling via the shortest connection path avoids haphazard routing of the two signal lines, which could lead to different coupling lengths and affect the coupling effect.
[0064] This application provides a PCB differential line routing method that saves routing space and reduces routing pressure in the BGA area by routing differential lines across different layers. Furthermore, it employs vertical coupling for rapid differential line coupling, resulting in stronger coupling performance. This application utilizes flexible curved traces and copper filling in specific areas for the differential lines: curved traces provide copper space, and copper filling increases the capacitance of the differential lines and reduces their impedance.
[0065] For example, this application embodiment provides a PCB differential line routing method, wherein the PCB includes at least a first differential line, the method comprising:
[0066] Fan-out routing is performed on the first differential line in the middle layer of the PCB. Based on the principle of not entering the pad keep-out area, curved routing is fanned out around the trace pad within the spherical grid array area. The pad keep-out area is a circular area, the center of which coincides with the center of the trace pad, and the radius of the pad keep-out area is greater than or equal to the radius of the trace pad + 3 μm.
[0067] In one possible implementation, before fanning out a curved trace around the trace pad in the BGA region for the first differential line, the PCB differential line routing method provided in this application embodiment further includes:
[0068] The curvature and radius of the fan-out curved trace of the first differential line are determined based on the simulation results.
[0069] In one possible implementation, the PCB differential line routing method provided in this application further includes: adding a copper-filled area to the curved trace of the first differential line to increase the total volume of the trace, thereby increasing the equivalent capacitance of the trace. The copper-filled area is the region enclosed by two troughs and one peak of the curved trace, with a straight line connecting the two troughs and an arc connecting the trough and the peak. In this application embodiment, after fanning out a curved trace for the first differential line, the total volume of the curved trace is increased by adding a copper-filled area, thereby improving the trace capacitance and reducing the trace impedance.
[0070] In one possible implementation, the first differential line includes a first line and a second line. The first differential line is fanned out on the intermediate layer of the PCB, specifically by fanning out the first line and the second line on different layers of the intermediate layer of the PCB, with the projections of the first line and the second line completely overlapping. The PCB differential line routing method provided in this application theoretically frees up half of the routing space through cross-layer differential line routing, providing ample routing space for the differential lines, reducing routing difficulty and stability, and resulting in higher routing quality.
[0071] In one possible implementation, to minimize uncoupled traces, the first and second traces are coupled differentially via the shortest connection path (the straight-line distance between the two pads), and the differential coupling method is perpendicular coupling. This rapid coupling via the shortest connection path avoids arbitrary routing of the first and second traces, which could lead to different coupling lengths and affect the coupling effect.
[0072] This application provides a PCB differential line routing method that saves routing space and reduces routing pressure in the BGA area by routing differential lines across different layers. Furthermore, it employs vertical coupling for rapid differential line coupling, resulting in stronger coupling performance. This application utilizes flexible curved traces and copper filling in specific areas for the differential lines: curved traces provide copper space, and copper filling increases the capacitance of the differential lines and reduces their impedance.
[0073] To further clarify how to solve the problem of excessive crosstalk between differential lines, this application uses an example of two differential lines on a PCB board:
[0074] For example, this application embodiment provides a PCB differential line routing method, wherein the PCB further includes at least a second differential line, that is, in this example, the PCB includes a first differential line and a second differential line, and the method includes:
[0075] The second differential line is routed according to the routing method of the first differential line in the PCB differential line routing method provided in the above embodiment. The spacing between the first differential line and the second differential line is greater than or equal to the minimum processing distance of the PCB, thereby reducing the processing difficulty of the PCB and lowering the production cost of the PCB. The minimum processing distance of the PCB is generally 4 mm.
[0076] In one possible implementation, the curvature and radius of the fan-out curved traces of the first differential line and the second differential line are the same.
[0077] In one possible implementation, the vertical distance between the first differential line and the nearest reference layer is less than the horizontal distance between the first differential line and the second differential line, to ensure that the coupling energy strength between the first differential line and the nearest reference layer is greater than the coupling strength between the first differential line and the second differential line. Correspondingly, the vertical distance between the second differential line and the nearest reference layer is less than the horizontal distance between the first differential line and the second differential line, to ensure that the coupling energy strength between the second differential line and the nearest reference layer is greater than the coupling strength between the first differential line and the second differential line.
[0078] In one possible implementation, the first differential line and the second differential line fan out curved routing with the same curvature and radius, thereby achieving symmetrical routing in the adjacent area of the first differential line and the second differential line, making full use of the routing space, and at the same time greatly reducing crosstalk between differential lines.
[0079] In practical applications, the above-mentioned PCB differential line routing method can be implemented in the following ways. Specifically, this application provides a PCB differential line design method, such as... Figure 2 As shown, the method includes:
[0080] Step 101: Design layer-change vias around the chip pads according to the number of routing layers on the PCB. Differential lines are led out from the chip pads through the layer-change vias to the PCB middle layer, so that the differential lines reach the target routing layer through the layer-change vias. In this step, the PCB layout personnel can design layer-change vias in the pad area according to the actual routing layers. The differential lines are led out to the PCB middle layer through the layer-change vias for routing. Here, the PCB middle layer is any layer on the PCB board other than the top and bottom layers.
[0081] Step 102: On the PCB middle layer, the differential lines are coupled along the shortest connection path between the trace pads. The differential line coupling method is vertical coupling. In this step, because the pad spacing is larger than the spacing of a regular differential line, after completing the layer-change via design, the two signal lines of the differential line are coupled along the shortest connection path between the two trace pads. The coupling method is: vertical coupling, and the projection areas of the two signal lines on different layers completely overlap.
[0082] Step 103: Based on the principle of not entering the pad keepout area, fan out curved traces for the differential lines around the trace pads within the spherical grid array area. The curvature and radius of the curved traces can be determined based on the simulation results from the simulation software. In this step, flexible curved traces can be used for the differential lines as long as they do not enter the pad keepout area. The curvature and radius of the curved traces can be determined based on the actual simulation results from the simulation software. The purpose of the curved traces is to provide space for subsequent copper pouring.
[0083] Step 104: Add a copper pour area to the curved trace of the differential line. The copper pour area is the region enclosed by the two troughs and one crest of the curved trace. The two troughs are connected by a straight line, and the troughs and crests are connected by an arc. In this step, after completing the fan-out curved trace of the differential line, adding a copper pour area to the curved trace increases the overall volume of the curved trace, thereby improving the trace capacitance and reducing the trace impedance.
[0084] This application provides a PCB differential line design method that saves routing space and reduces routing pressure in the BGA area by using differential line routing on different layers. Furthermore, it employs vertical coupling for rapid differential line coupling, resulting in stronger coupling performance. This application utilizes flexible curved traces and area copper filling for the differential lines: curved traces provide copper space, and area copper filling increases the trace capacitance and reduces differential line impedance.
[0085] In this embodiment, when two differential lines are required, the via layer switching method and fast coupling method for the two differential lines are the same. The fan-out curved traces of the two differential lines use the same curvature and radius to ensure symmetrical routing in adjacent areas. The spacing between the two differential lines is ensured to be greater than the minimum PCB fabrication distance. Symmetrical routing in adjacent areas of the two differential lines not only satisfies design advantages but also makes full use of space, standardizes the design, and maximizes the spacing between the traces of the two differential lines to reduce crosstalk between them.
[0086] In one possible implementation, this application provides a PCB including a first differential line routed according to the PCB differential line routing method provided in the above embodiments.
[0087] In one possible implementation, the PCB further includes at least a second differential line, which is routed according to the routing method of the first differential line in the PCB differential line routing method provided in the above embodiments, and the spacing between the first differential line and the second differential line is greater than or equal to the minimum processing distance of the PCB.
[0088] For example, such as Figure 3 The image shown is a side view of a PCB provided in an embodiment of this application. The PCB includes an upper ground plane layer 1, a lower ground plane layer 2, an intermediate layer 3, an intermediate layer 4, PCB resin material and included fiberglass, etc., 5, vias 6 and 7. In this example, there are two differential lines in the intermediate layer: a first differential line O1 and a second differential line O3 in intermediate layer 3, and a second differential line O2 and a second differential line O4 in intermediate layer 4. O1 and O2 are a pair of different-layer differential lines (first differential lines), and O3 and O4 are another pair of different-layer differential lines (second differential lines). Figure 3The diagram schematically shows two adjacent trace pads 11 and 13 on intermediate layer 3, and two adjacent trace pads 12 and 14 on intermediate layer 4. The surface chip pads and solder balls (not shown in the diagram) of the PCB board are connected to trace pads 11 and 13 through vias 6, and to trace pads 12 and 14 through vias 7. The chip pad and the trace pad are located in the same via, and the chip pad and the trace pad are located in different layers of the PCB. The vertical distance between the first line 01 of the first differential line (or the first line 03 of the second differential line) and the nearest reference layer (upper ground plane layer 1) is less than the horizontal distance between the first line 01 of the first differential line and the first line 03 of the second differential line. The vertical distance between the second line 02 of the first differential line (or the second line 04 of the second differential line) and the nearest reference layer (lower ground plane layer 2) is less than the horizontal distance between the second line 02 of the first differential line and the second line 04 of the second differential line, so as to ensure that the coupling energy intensity between the first differential line and the nearest reference layer (or the second differential line and the nearest reference layer) is greater than the coupling strength between the first differential line and the second differential line.
[0089] For example, such as Figure 4 The diagram shows a top view of a PCB provided in an embodiment of this application. In order to minimize uncoupled traces, differential lines are quickly coupled through the shortest connection path, as shown in structure 1. Under the premise of not entering the pad ban area, curved traces are fanned out along the edge of the pad area, as shown in structure 2. Figure 4 In the diagram, the radius of the pad keepout region 8 is equal to the radius of the trace pad + 3 mil. Obviously, in practical applications, the radius of the pad keepout region can also be greater than the radius of the trace pad + 3 mil. The diagram only illustrates the case where the radius of the pad keepout region 8 differs from the radius of the trace pad by 3 mil. A copper pour area is added to the curved trace of the first line 01 (or the second line 02) of the first differential line. The copper pour area is the area enclosed by two troughs and one crest of the curved trace. The two troughs are connected by a straight line, and the troughs and crests are connected by an arc. Figure 4 The example shows multiple copper-clad areas, with a single copper-clad area as shown in structure 3. Figure 4In this design, multiple copper areas of the curved trace of the first differential line are periodically copper-poured. To avoid introducing other problems, the curvature and radius of the fan-out curved traces of the first and second differential lines are the same. Adjacent areas of the first and second differential lines are symmetrically routed, as in structure 4, where the adjacent areas of the first line 01 of the first differential line and the first line 03 of the second differential line are symmetrically routed, as are the adjacent areas of the second line 02 of the first differential line and the second line 04 of the second differential line. Specifically, the first line 01 and the second line 02 of the first differential line overlap, and the first line 03 and the second line 04 of the second differential line overlap. The spacing 9 between the first and second differential lines must at least meet the minimum PCB processing distance requirement, which is generally 4 μm. That is, the spacing between the first and second differential lines is not less than the minimum PCB processing distance.
[0090] This application provides a PCB differential line routing method applicable to high-density integrated circuit designs for all application chips. It alleviates the problem of insufficient routing space for chip solder balls and routing areas, and the use of heterogeneous differential line routing can save approximately 50% of routing space. In practical applications, it alleviates conflicts between PCB layout design capabilities and PCB material size, density, and PCB manufacturer processing capabilities; it also alleviates signal integrity issues sensitive to high-speed signals, such as high impedance discontinuity in high-speed signal BGA areas and crosstalk between signal lines. Simultaneously, compared to existing differential line fan-out structures, impedance can be optimized by approximately 15%, and crosstalk between different differential lines can be optimized by approximately 10%. This improves the design margin for high-speed differential signals, solves the reliability and consistency issues of mass production equipment, and reduces the risk of mass use. Compared to existing parallel differential line designs on the same layer, it can significantly reduce PCB size while achieving the same function. For example, the heterogeneous differential line routing method provided in this application can complete the routing of two differential lines within the routing space where existing technologies can only lay one differential line. This allows for miniaturization of supporting equipment and saves on corresponding material costs.
[0091] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0092] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for routing differential lines on a PCB, characterized in that, The PCB at least comprises a first differential line, and the method comprises: fan-out routing the first differential line in the PCB middle layer, and based on the principle of not entering the pad forbidden routing area, fan-out curved routing the first differential line around the routing pad in the ball grid array area.
2. The PCB differential line routing method of claim 1, wherein, Before the fan-out curved routing the first differential line in the ball grid array area around the routing pad, the method further comprises: determining the curvature and radius of the fan-out curved routing of the first differential line according to the simulation result.
3. The PCB differential line routing method of claim 2, wherein, The method further comprises: adding a copper coating area on the curved routing of the first differential line, the copper coating area being an area enclosed by two troughs and one peak of the curved routing, the two troughs being connected by a straight line, and the troughs and the peak being connected by an arc line.
4. The PCB differential line routing method of claim 3, wherein, The first differential line comprises a first line and a second line, and the fan-out routing of the first differential line in the PCB middle layer specifically comprises: fan-out routing the first line and the second line in different layers of the PCB middle layer, the projections of the first line and the second line completely overlap, the first line and the second line are coupled by the shortest connection path, and the differential line coupling mode is vertical coupling.
5. A method of routing differential lines of a PCB, characterized by, The PCB at least further comprises a second differential line, and the second differential line is routed according to the routing method of the first differential line in the PCB differential line routing method according to any one of claims 1-6, and the distance between the first differential line and the second differential line is greater than or equal to the minimum processing distance of the PCB.
6. The PCB differential line routing method of claim 5, wherein, The curvature and radius of the fan-out curved routing of the first differential line and the second differential line are the same.
7. The PCB differential line routing method of claim 6, wherein, The vertical distance between the first differential line and the nearest reference layer is less than the horizontal distance between the first differential line and the second differential line, and the vertical distance between the second differential line and the nearest reference layer is less than the horizontal distance between the first differential line and the second differential line.
8. A method of designing a differential line on a PCB, the method comprising: The method comprises: designing a layer change via hole around the chip pad according to the number of routing layers of the PCB, and leading out the differential line from the chip pad to the PCB middle layer through the layer change via hole; coupling the differential line along the shortest connection path between the routing pads in the PCB middle layer, and the differential line coupling mode is vertical coupling; based on the principle of not entering the pad forbidden routing area, fan-out curved routing the differential line around the routing pad in the ball grid array area, and the curvature and radius of the curved routing are determined according to the simulation result; adding a copper coating area on the curved routing of the differential line, the copper coating area being an area enclosed by two troughs and one peak of the curved routing, the two troughs being connected by a straight line, and the troughs and the peak being connected by an arc line.
9. A PCB characterized by, The PCB comprises a first differential line routed according to the PCB differential line routing method of any one of claims 1-6.
10. The PCB of claim 9, wherein, The PCB at least further comprises a second differential line, and the second differential line is routed according to the routing method of the first differential line in the PCB differential line routing method according to any one of claims 1-6, and the distance between the first differential line and the second differential line is greater than or equal to the minimum processing distance of the PCB.