Vertical non-volatile memory device

Abstract

The vertical non-volatile memory device may include: a gate stack including gate electrodes and interlayer insulating layers alternately stacked; a gate spacer; and gate contact plugs spaced apart from each other in the gate stack. The gate contact plugs may include a first gate contact plug vertically contacting a first one of the gate electrodes and a second gate contact plug vertically contacting a second one of the gate electrodes. The gate contact plug may include a vertical plug portion extending in a vertical direction and protruding plug portions horizontally protruding from both sides of the vertical plug portion. A gate spacer may be between the protruding plug portion and the gate electrode. The gate spacer may insulate the gate contact plug from a portion of the gate electrodes.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0087045, filed with the Korean Intellectual Property Office on July 2, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to non-volatile memory devices, and more specifically, to vertical non-volatile memory devices. Background Technology

[0004] In electronic systems requiring data storage, non-volatile memory devices capable of storing large amounts of data may be necessary. Accordingly, vertical non-volatile memory devices with three-dimensionally arranged memory cells (instead of two-dimensionally arranged memory cells) have been proposed. However, vertical non-volatile memory devices with three-dimensionally arranged memory cells may have low connection reliability due to gate contact plugs connected to the gate electrode. Summary of the Invention

[0005] The present invention provides a vertical non-volatile memory device that can improve the connection reliability of the gate contact plugs connected to the gate electrodes of a three-dimensionally arranged memory cell.

[0006] According to embodiments of the present invention, a vertical non-volatile memory device may include: a gate stack including a plurality of alternately stacked gate electrodes and a plurality of interlayer insulating layers; a gate spacer; and a plurality of gate contact plugs spaced apart from each other in the gate stack. The plurality of gate contact plugs may include a first gate contact plug vertically contacting a first gate electrode among the plurality of gate electrodes and a second gate contact plug vertically contacting a second gate electrode among the plurality of gate electrodes. The gate contact plugs may include a plurality of vertical plug portions extending in a vertical direction and a plurality of protruding plug portions horizontally protruding from both sides of the plurality of vertical plug portions. The gate spacer may be located between the plurality of protruding plug portions and the plurality of gate electrodes. The gate spacer may insulate the plurality of gate contact plugs from a portion of the plurality of gate electrodes.

[0007] According to embodiments of the present invention, a vertical non-volatile memory device may include: a gate stack including a plurality of gate electrodes and a plurality of interlayer insulating layers stacked alternately; gate spacers; and a plurality of gate contact plugs spaced apart from each other in the gate stack. The gate stack may define a first vertical via exposing a first gate electrode among the plurality of gate electrodes, a first horizontal recess extending horizontally from the first vertical via, a second vertical via exposing a second gate electrode among the plurality of gate electrodes, and a second horizontal recess extending horizontally from the second vertical via. The plurality of gate contact plugs may include first gate contact plugs and second gate contact plugs. The first gate contact plug may be in the first vertical via and may vertically contact the first gate electrode among the gate electrodes. The first gate contact plug may be disposed on one side of the first horizontal recess. The second gate contact plug may be in the second vertical via and may vertically contact the second gate electrode. The second gate contact plug may be disposed on one side of the second horizontal recess. A plurality of first gate spacers may be in the first horizontal recess, and a plurality of second gate spacers may be in the second horizontal recess. A plurality of first gate spacers can insulate the first gate contact plug from the gate electrodes other than the first gate electrode among the plurality of gate electrodes. A plurality of second gate spacers can insulate the second gate contact plug from the gate electrodes other than the second gate electrode among the plurality of gate electrodes.

[0008] According to embodiments of the present invention, a vertical non-volatile memory device may include: a memory cell array structure including a memory cell array; gate spacers; and an extension structure extending from one side of the memory cell array structure and connected to a plurality of gate electrodes of the memory cell array structure. The memory cell array structure and the extension structure may include a gate stack. The gate stack may include a plurality of alternately stacked gate electrodes and a plurality of interlayer insulating layers, and the extension structure may include a plurality of gate contact plugs spaced apart from each other in the gate stack. The plurality of gate contact plugs may include a first gate contact plug vertically contacting a first gate electrode among the plurality of gate electrodes and a second gate contact plug vertically contacting a second gate electrode among the plurality of gate electrodes. The plurality of gate contact plugs may include a plurality of vertical plug portions extending in a vertical direction and a plurality of protruding plug portions horizontally protruding from both sides of the plurality of vertical plug portions. The gate spacers may be located between the plurality of protruding plug portions and the plurality of gate electrodes. The gate spacers may insulate the plurality of gate contact plugs from a portion of the plurality of gate electrodes. Attached Figure Description

[0009] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram of a vertical non-volatile storage device according to an embodiment;

[0011] Figure 2 This is a schematic perspective view of a vertical non-volatile storage device according to an embodiment;

[0012] Figure 3 This is an equivalent circuit diagram of a memory cell array (MCA) of a vertical non-volatile memory device according to an embodiment;

[0013] Figure 4 This is a schematic plan view of a vertical non-volatile storage device according to an embodiment;

[0014] Figure 5 This is a cross-sectional view detailing the key components of a vertical non-volatile storage device according to an embodiment;

[0015] Figure 6 yes Figure 5 Enlarged cross-sectional view of the central region EN1;

[0016] Figure 7 yes Figure 5 Enlarged cross-sectional view of the middle region EN2;

[0017] Figure 8 yes Figure 7 Enlarged cross-sectional view of the central region EN3;

[0018] Figure 9 It is used for explanation Figure 7 and Figure 8 An enlarged view of the gate contact structure; and

[0019] Figures 10 to 17 This is a cross-sectional view illustrating a method of manufacturing a vertical non-volatile storage device according to one embodiment. Detailed Implementation

[0020] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0021] Figure 1 This is a block diagram of a vertical non-volatile storage device 100 according to an embodiment.

[0022] The vertical non-volatile storage device 100 can have the characteristic of continuously retaining stored data even without power. The vertical non-volatile storage device 100 can be a vertical NAND flash memory device.

[0023] The vertical non-volatile storage device 100 may include a memory cell array (MCA) and peripheral circuitry (PC). The memory cell array (MCA) may include multiple memory cell blocks BLK1, BLK2, ..., BLKn (where n is a positive integer). The memory cell blocks BLK1, BLK2, ..., BLKn (where n is a positive integer) may be collectively referred to as memory cell block BLK.

[0024] Each memory cell block (BLK1, BLK2, ..., BLKn, where n is a positive integer) can contain multiple memory cells. Memory cell blocks BLK1, BLK2, ..., BLKn (where n is a positive integer) can be connected to the peripheral circuit PC via bit line BL, word line WL, serial select line SSL, and ground select line GSL.

[0025] The peripheral circuitry PC may include a line decoder 232, a page buffer 234, data input / output circuitry 236, control logic 238, and a common source line (CSL) driver 239. Although Figure 1 Not shown, but the peripheral circuit PC may also include various circuits, such as voltage generating circuits that generate various voltages for the operation of the vertical non-volatile storage element 100, error correction circuits for correcting errors in the data read from the storage cell array MCA, and / or input / output interfaces.

[0026] The memory cell array (MCA) can be connected to the page buffer 234 via the bit line BL. The memory cell array (MCA) can be connected to the row decoder 232 via the word line WL, the serial select line SSL, and the ground select line GSL. In the memory cell array (MCA), each of the multiple memory cell blocks BLK1, BLK2, ..., BLKn (where n is a positive integer) includes multiple memory cells that can be flash memory cells.

[0027] A memory cell array (MCA) may include a three-dimensional memory cell array. A three-dimensional memory cell array may include multiple NAND strings. Multiple NAND strings may include multiple memory cells, each connected to a vertically stacked word line (WL).

[0028] The peripheral circuit PC can receive address ADDR, command CMD and control signal CTRL from the outside of the vertical non-volatile memory device 100, and can send data DATA to and receive data DATA from devices located outside the vertical non-volatile memory device 100.

[0029] The row decoder 232 can select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., BLKn (where n is a positive integer) in response to an external address ADDR, and can select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 232 can transmit the voltage used to perform the memory operation to the word line WL of the selected memory cell block.

[0030] Page buffer 234 can be connected to the memory cell array MCA via bit line BL. Page buffer 234 can act as a write driver during programming operations, applying voltage to bit line BL according to the data DATA to be stored in the memory cell array MCA, and can act as a sense amplifier during read operations, detecting the data DATA stored in the memory cell array MCA. Page buffer 234 can operate according to the control signal PCTL provided by control logic 238.

[0031] Data input / output circuit 236 can be connected to page buffer 234 via multiple data lines DL. During programming operations, data input / output circuit 236 can receive data DATA from memory controller (not shown) and provide programming data DATA to page buffer 234 based on the column address C_ADDR provided from control logic 238. During read operations, data input / output circuit 236 can provide read data DATA stored in page buffer 234 to memory controller based on the column address C_ADDR provided from control logic 238.

[0032] The data input / output circuit 236 can send input addresses or commands to the control logic 238 and / or the line decoder 232. The peripheral circuit PC may also include electrostatic discharge (ESD) circuitry and / or pull-up / pull-down drivers.

[0033] Control logic 238 can receive commands CMD and control signals CTRL from the memory controller. Control logic 238 can provide the row address R_ADDR to the row decoder 232 and the column address C_ADDR to the data input / output circuitry 236. Control logic 238 can generate various internal control signals used in the vertical non-volatile memory device 100 in response to the control signal CTRL. For example, control logic 238 can control the voltage levels supplied to the word line WL and bit line BL when performing memory operations (such as programming or erasing operations).

[0034] CSL driver 239 can be connected to the memory cell array MCA via a common source line CSL. CSL driver 239 can apply a common source voltage (e.g., power supply voltage) or ground voltage to the common source line CSL based on the control signal CTRL of control logic 238. In an example embodiment, CSL driver 239 may be arranged below the memory cell array MCA. CSL driver 239 may be arranged to vertically overlap at least a portion of the memory cell array MCA.

[0035] Figure 2 This is a schematic perspective view of a vertical non-volatile storage device according to an embodiment.

[0036] The vertical non-volatile storage device 100 may include a memory cell array structure (MCAS) and a peripheral circuit structure (PCS) that overlap each other in the vertical direction (Z direction). The X direction or -X direction may be referred to as the first horizontal direction. The Y direction or -Y direction may be referred to as the second horizontal direction.

[0037] exist Figure 2 In the MCAS (Memory Cell Array Structure), the memory cell array structure is stacked vertically (in the Z direction) on the peripheral circuit structure PCS (Peripheral Circuit Structure), but the peripheral circuit structure PCS can be arranged horizontally (in the X direction) on one side of the memory cell array structure MCAS as needed.

[0038] MCAS (Memory Cell Array) architecture can include Figure 1 The memory cell array (MCA). The peripheral circuitry (PCS) may include... Figure 1 The peripheral circuit PC. Figure 2 The MCAS (Multi-access Array of Memory) storage cell array structure can include multiple TILs. Each TIL can include multiple storage cell blocks BLK1, BLK2, ..., BLKn (where n is a positive integer). Storage cell blocks BLK1, BLK2, ..., BLKn (where n is a positive integer) can be collectively referred to as storage cell block BLK. Storage cell blocks BLK1, BLK2, ..., BLKn (where n is a positive integer) can include multiple storage cells arranged in three dimensions.

[0039] Figure 3 This is an equivalent circuit diagram of a memory cell array (MCA) of a vertical non-volatile memory device according to an embodiment.

[0040] Figure 3 The above can be used as a reference. Figure 1 Equivalent circuit diagram of the memory cell array MCA of the described vertical non-volatile memory device 100 (e.g., vertical NAND flash memory device). Figure 2 The storage unit blocks BLK1, BLK2, ..., BLKn (where n is a positive integer) can each contain a set of storage units. Figure 3The circuit shown is configured as a memory cell array (MCA).

[0041] A memory cell array (MCA) may include multiple memory cell strings (MS). The memory cell array (MCA) may include multiple bit lines BL1, BL2, ..., BLm (where m is a positive integer), multiple word lines WL1, WL2, ..., WLn-1, WLn (where n is a positive integer), at least one string select line (SSL), at least one ground select line (GSL), and a common source line (CSL).

[0042] Multiple memory cell strings (MS) can be formed between multiple bit lines (BL) and a common source line (CSL). Figure 3 The example illustrates a scenario where each of a plurality of memory cell strings (MS) includes two string select lines (SSLs), but this embodiment is not limited to this. For example, each of the plurality of memory cell strings (MS) may include one string select line (SSL).

[0043] Each of the multiple memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and multiple memory cell transistors MC1, MC2, ..., MCn-1, MCn (where n is a positive integer). The memory cell transistors MC1, MC2, ..., MCn-1, MCn (where n is a positive integer) may each be a memory cell.

[0044] The drain region of the string select transistor (SST) can be connected to the bit line BL, and the source region of the ground select transistor (GST) can be connected to the common source line CSL. The common source line CSL can be the region where the source regions of multiple ground select transistors (GST) are connected together.

[0045] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1, MCn (where n is a positive integer) can be connected to multiple word lines WL respectively.

[0046] Figure 4 This is a schematic plan view of a vertical non-volatile storage device according to an embodiment.

[0047] Vertical non-volatile storage device 100 may include multiple memory cell blocks BLK, as referenced above. Figure 1 and Figure 2 As stated above. Figure 4 It shows Figure 1 and Figure 2 A schematic plan view of the first storage cell block BK1 of one of the storage cell blocks BLK of the vertical non-volatile storage device 100.

[0048] Figure 4The plan view of the vertical non-volatile storage device 100 can be Figure 3 A plan view at the horizontal height of the SSL selection line. Figure 4 The plan view of the first storage cell block BK1 shown is used to illustrate the inventive concept, and the inventive concept is not limited to... Figure 4 .

[0049] Each memory cell block (BLK) may include a memory cell array region (MCAR) and an extended region (EXTR) disposed on at least one side of the MCAR. The extended region (EXTR) may be a region extending from the memory cell array region (MCAR) in a first horizontal direction (X direction). The extended region (EXTR) may be referred to as a gate connection region. Each memory cell block (BLK) may have a linear or strip-shaped extension in the first horizontal direction (X direction).

[0050] The vertical non-volatile storage device 100 may include block separation structures (BSS) spaced apart from each other. The block separation structure (BSS) may include a closed-loop shape surrounding each side of the memory cell block (BLK).

[0051] The vertical non-volatile memory device 100 may include a stacked structure ST. The stacked structure ST may include a gate stacked region GS and a dummy stacked region DS. Each memory cell block BLK may include a gate stacked region GS. The dummy stacked region DS may be disposed outside each memory cell block BLK. The dummy stacked region DS may include a through contact region THVR.

[0052] Each memory cell block (BLK) may include vertical structures VSc, VSd1, and VSd2. The vertical structures VSc, VSd1, and VSd2 may include a vertical memory structure VSc arranged in the memory cell array region MCAR, a first vertical virtual structure VSd1 arranged in the memory cell array region MACR, and a second vertical virtual structure VSd2 arranged in the extended region EXTR.

[0053] Here, the vertical non-volatile storage device 100 will be described in more detail, with a focus on the first storage cell block BLK1 in the storage cell block BLK.

[0054] The first memory cell block BLK1 can be completely surrounded by a block separation structure BSS. The block separation structure BSS surrounding the first memory cell block BLK1 may include a first line portion BSS_1 and a second line portion BSS_2 extending parallel to each other along a first horizontal direction (X direction), and a third line portion BSS_3 and a fourth line portion BSS_4 extending parallel to each other along a second horizontal direction (Y direction). The block separation structure BSS surrounding the first memory cell block BLK1 may have a rectangular closed loop shape. The first memory cell block BLK1 may include string select lines SSL1, SSL2, SSL3, and SSL4.

[0055] The serial select lines SSL1, SSL2, SSL3, and SSL4 of the memory cell array region (MCAR) may include a first upper gate electrode 27U1. In the extended region (EXTR), the first dummy upper gate electrode 27U1' may be arranged to correspond to the first upper gate electrode 27U1 of the memory cell array region (MCAR).

[0056] The vertical non-volatile storage device 100 may include an auxiliary separation structure DSS. The auxiliary separation structure DSS may be arranged within a closed ring block separation structure BSS. The auxiliary separation structure DSS may include line portions spaced apart from each other and arranged in a first horizontal direction (X direction).

[0057] The auxiliary separation structure DSS may include: a first line portion extending through the memory cell array region MCAR and into the extended region EXTR; and a second line portion spaced apart from the first line portion within the extended region EXTR and arranged sequentially in a first horizontal direction (X direction). The auxiliary separation structure DSS can separate the second select line SSL2 and the third select line SSL3.

[0058] The vertical non-volatile storage device 100 may include an upper separation pattern 51. The upper separation pattern 51 may be arranged between the first select line SSL1 and the second select line SSL2, and between the third select line SSL3 and the fourth select line SSL4. The upper separation pattern 51 may include a line portion extending along a first horizontal direction (X direction).

[0059] The vertical non-volatile memory device 100 may include a plurality of gate contact structures GC disposed within a first memory cell block BLK1. The gate contact structure GC may include gate contact plugs GCc and insulating gate spacers GCs.

[0060] Gate contact structures GC can be arranged to be spaced apart from each other within the gate stack region GS. Vertical nonvolatile memory device 100 may include a plurality of through contact structures TC1 arranged within the through contact region THVR.

[0061] Each gate contact structure GC may include a gate contact plug GCc and gate spacers GCs surrounding the gate contact plug GCc. The gate spacers GCs may include an insulating layer. Each of the multiple through contact structures TC1 may include a through contact plug TC1c and insulating spacers TC1s surrounding the through contact plug TC1c.

[0062] At least one gate contact structure GC may have an elongated strip or ellipse shape in one direction (e.g., a first horizontal direction (X direction)). The width of each gate contact structure GC and through contact structure TC1 may be greater than the width of each vertical memory structure VSC.

[0063] Figure 5 This is a cross-sectional view detailing the key components of a vertical non-volatile storage device according to an embodiment.

[0064] Specifically, Figure 5 It can be along Figure 4 A cross-sectional view taken from line II. The vertical non-volatile memory device 100 may include a peripheral circuit structure PCS and a superstructure MS on the peripheral circuit structure PCS.

[0065] The peripheral circuit structure PCS may include a semiconductor substrate 3, a device isolation region 6s defining an active region 6a on the semiconductor substrate 3, peripheral circuitry 8 on the active region 6a, circuit wiring 12 on and electrically connected to the peripheral circuitry 8, and an insulating structure 14 covering the peripheral circuitry 8 and the circuit wiring 12. Each peripheral circuitry 8 may include a transistor, which includes a peripheral gate 10a and a peripheral source / drain 10b.

[0066] The peripheral circuit 8 may include a first peripheral circuit 8a and a second peripheral circuit 8b. The vertical non-volatile storage device 100 may include a board pattern 16 and a dummy region 18 arranged on the peripheral circuit structure PCS. The dummy region 18 may be arranged on one side of the board pattern 16. The dummy region 18 may include an insulating material layer and / or a dummy pattern whose side surface is covered by an insulating material layer.

[0067] The board pattern 16 may include a lower layer 16a, an intermediate layer 16b on the lower layer 16a, and an upper layer 16c on the intermediate layer 16b. The board pattern 16 may include at least one silicon layer. For example, the lower layer 16a, the intermediate layer 16b, and the upper layer 16c may include polysilicon layers with N-type conductivity.

[0068] The upper structure MS can be arranged on the board pattern 16 and the dummy area 18. The upper structure MS may include a memory cell array structure MCAS, an extension structure EXTS, and a through structure THVS. The memory cell array structure MCAS, the extension structure EXTS, and the through structure THVS can respectively correspond to Figure 4 The storage cell array area MCAR, the extended area EXTR, and the through contact area THVR.

[0069] The upper structure MS may include a stacked structure ST, a separation structure including a block separation structure BSS and an auxiliary separation structure DSS, vertical structures VSc, VSd1 and VSd2, a gate contact structure GC and a through contact structure TC1, as shown in the reference. Figure 4 The upper structure MS may include a first upper insulating layer 55, a second upper insulating layer 68 and a third upper insulating layer 77, a bit line 80a and a gate connection wiring 80b.

[0070] The stacked structure ST may include a gate stacked region GS and a dummy stacked region DS, as shown in the reference. Figure 4 The stacked structure ST may include alternating and repeated stacking of first layers 24a and 24b and second layers 27a and 27b. The second layers 27a and 27b may be stacked spaced apart from each other in a vertical direction (Z) perpendicular to the upper surface of the plate pattern 16.

[0071] The first layers 24a and 24b may include an insulating material, such as silicon oxide. The second layers 27a and 27b may include at least one of doped polycrystalline silicon, W, Ru, Mo, Ni, NiSi, Co, CoSi, Ti, TiN, and WN.

[0072] In the first layers 24a and 24b, the first layer located within the gate stack region GS can be referred to as the first interlayer insulating layer 24a, and the first layer located within the dummy stack region DS can be referred to as the second interlayer insulating layer 24b. In the second layers 27a and 27b, the second layer located within the gate stack region GS can be referred to as the gate electrode 27a, and the second layer located within the dummy stack region DS can be referred to as the dummy gate electrode 27b.

[0073] Accordingly, the gate stack region GS may include an alternately and repeatedly stacked first interlayer insulating layer 24a and gate electrode 27a. The gate stack region GS may have a structure in which the gate electrode 27a and the first interlayer insulating layer 24a are stacked alternately.

[0074] The dummy stacked region DS may include an alternately and repeatedly stacked second interlayer insulating layer 24b and a dummy gate electrode 27b. The dummy stacked region DS may have a structure in which the dummy gate electrode 27b and the second interlayer insulating layer 24b are stacked alternately.

[0075] The separate structures BSS and DSS can penetrate the stacked structure ST. The upper surfaces of the separate structures BSS and DSS can be disposed at a lower height than the upper surface of the gate contact structure GC. The separate structures BSS and DSS can each include a core pattern 49 and insulating spacers 48 disposed on the side of the core pattern 49. In one example, the core pattern 49 may include a conductive material and may be in contact with the lower layer 16a of the board pattern 16. In another example, the core pattern 49 may include an insulating material.

[0076] The vertical structures VSc, VSd1, and VSd2 can penetrate the gate stack region GS. The first upper insulating layer 55, the second upper insulating layer 68, and the third upper insulating layer 77 are sequentially stacked on the stack structure ST.

[0077] The gate contact structure GC may extend downward through the first upper insulating layer 55. As described above, the gate contact structure GC may include a gate contact plug GCc and gate spacers GCs. The gate spacers GCs may include an insulating material. For example, the gate spacers GCs may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric.

[0078] The gate contact plug GCc can have a bottom surface at different heights and a top surface at the same height. The gate contact plug GCc can contact the gate electrode 27a in the vertical direction (Z direction).

[0079] The gate contact plug GCc may include a first gate contact plug that is vertically in contact with one of the first gate electrodes (27L1, 27L2, 27M, 27U1 and 27U2) in the gate electrode 27a, and a second gate contact plug that is vertically in contact with one of the second gate electrodes (27L1, 27L2, 27M, 27U1 and 27U2) in the gate electrode 27a.

[0080] Within the gate stack region GS, the second gate electrode (one of 27L1, 27L2, 27M, 27U1, and 27U2) (e.g., the intermediate gate electrode 27M) can be at a higher height than the first gate electrode (one of 27L1, 27L2, 27M, 27U1, and 27U2) (e.g., the second lower gate electrode 27L2). The gate contact plug GCc can be electrically connected to the gate electrode 27a.

[0081] The gate electrode 27a may include a first intermediate gate electrode 27M1 and a second intermediate gate electrode 27M2 at a lower height than the first intermediate gate electrode 27M1. The gate electrode 27a may include a first lower gate electrode 27L1, a second lower gate electrode 27L2, a plurality of intermediate gate electrodes 27M, a first upper gate electrode 27U1 and a second upper gate electrode 27U2, which are stacked sequentially in the vertical direction (Z direction).

[0082] In the extended region EXTR, the first dummy upper gate electrode 27U1' and the second dummy upper gate electrode 27U2' can be arranged to correspond to the first upper gate electrode 27U1 and the second upper gate electrode 27U2 of the memory cell array region MCAR, respectively.

[0083] The gate contact plug GCc may include a first intermediate gate contact plug GCc_1 that contacts the first intermediate gate electrode 27M1 and a second intermediate gate contact plug GCc_2 that contacts the second intermediate gate electrode 27M2 at a height lower than the first intermediate gate electrode 27M1. The first intermediate gate electrode 27M1 and the second intermediate gate electrode 27M2 may be a first word line and a second word line.

[0084] In one example, if the first intermediate gate contact plug GCc_1 and the second intermediate gate contact plug GCc_2 are arranged adjacent to each other and sequentially in the first horizontal direction (X direction), then one or more gate electrodes may be located between the first intermediate gate electrode 27M1 and the second intermediate gate electrode 27M2.

[0085] The through-contact structure TC1 penetrates the first upper insulating layer 55 and the second upper insulating layer 68, the dummy stacked region DS, and the dummy region 18. The through-contact structure TC1 may extend downwards and be electrically connected to the first peripheral circuit 8a in the peripheral circuit 8. For example, the through-contact structure TC1 may include a through-contact plug TC1c and an insulating spacer TC1s surrounding the through-contact plug TC1c. The through-contact plug TC1c may be electrically connected to and in contact with the first peripheral pad 12p1 of the circuit wiring 12, which is electrically connected to the first peripheral circuit 8a.

[0086] Bit line 80a can be electrically connected to the vertical memory structure VSC. For example, bit line 80a may include a line portion on the third upper insulating layer 77 and a through-hole portion that penetrates the first upper insulating layer to the third upper insulating layers 55, 68 and 77 below the line portion and contacts the vertical memory structure VSC.

[0087] The gate connection wiring 80b can electrically connect the gate contact plug GCc and the through contact plug TC1c. For example, the gate connection wiring 80b may include a line portion on the third upper insulating layer 77 and a via portion below the second upper insulating layer 68 and the third upper insulating layer 77 that contacts the through contact plug TC1c and the gate contact plug GCc.

[0088] Figure 6 yes Figure 5 Enlarged cross-sectional view of the central region EN1.

[0089] Specifically, the gate electrode 27a may include a first lower gate electrode 27L1, a second lower gate electrode 27L2, a plurality of intermediate gate electrodes 27M, a first upper gate electrode 27U1 and a second upper gate electrode 27U2, which are stacked sequentially in the vertical direction (Z direction) as described above.

[0090] In one example, the first lower gate electrode 27L1 and the second lower gate electrode 27L2 can be lower select gate lines. The first lower select gate line and the second lower select gate line can also be ground select gate lines. The intermediate gate electrode 27M can be a word line WL. The first upper gate electrode 27U1 and the second upper gate electrode 27U2 can be upper select gate lines. The upper select gate line can also be a string select gate line.

[0091] Figure 6 The vertical storage structure VSC is exemplary, and this embodiment is not limited to... Figure 6 The structure of the vertical storage structure VSC may each include a channel hole 30, an insulating core region 42, a pad pattern 45 on the insulating core region 42, an information storage structure 36 on the side of the insulating core region 42 and the side of the pad pattern 45, and a channel layer 39 between the insulating core region 42 and the information storage structure 36 and between the pad pattern 45 and the information storage structure 36.

[0092] The vertical memory structure VSC may include a barrier dielectric layer 33 covering the outer and bottom surfaces of the information storage structure 36. The pad pattern 45 may include doped silicon, such as polysilicon with N-type conductivity. The channel layer 39 may contact the pad pattern 45. The channel layer 39 may include a silicon layer.

[0093] The information storage structure 36 may include a first dielectric layer 36a, an information storage layer 36d, and a second dielectric layer 36b. The information storage layer 36d may be located between the first dielectric layer 36a and the second dielectric layer 36b. The first dielectric layer 36a may include silicon oxide and / or a high-k dielectric.

[0094] The information storage layer 36d may include a material capable of storing information in a NAND flash memory device, such as silicon nitride capable of trapping charge. The second dielectric layer 36b may be a tunnel dielectric layer in contact with the channel layer 39.

[0095] The second dielectric layer 36b may include silicon oxide or silicon oxide doped with impurities. The barrier dielectric layer 33 may include silicon oxide and / or a high-k dielectric. In the board pattern 16, the intermediate layer 16b may penetrate the barrier dielectric layer 33 and the information storage structure 36 and contact the channel layer 39. The intermediate layer 16b may include a silicon layer with N-type conductivity, and the portion of the channel layer 39 that contacts the intermediate layer 16b may have N-type conductivity.

[0096] Figure 7 yes Figure 5 Enlarged cross-sectional view of region EN2 in the middle area. Figure 8 yes Figure 7 An enlarged cross-sectional view of the central region EN3, and Figure 9 It is shown Figure 7 and Figure 8 An enlarged view of the gate contact structure.

[0097] Specifically, the gate contact structure GC may include the gate contact plug GCc and gate spacers GCs as described above. The gate contact plug GCc may include tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or any combination thereof.

[0098] like Figure 8 and Figure 9 As shown, the gate contact plug GCc may include a vertical plug portion 162 extending in the vertical direction (Z direction) and protruding plug portions 164 protruding in a first horizontal direction (X direction and -X direction) on both sides of the vertical plug portion 162. The protruding plug portions 164 may extend in the horizontal direction (X direction) and may be referred to as horizontal plug portions.

[0099] The bottom of the vertical plug portion 162 can contact the upper part of the gate electrode 27a. The protruding plug portion 164 does not contact the gate electrode 27a through the gate spacers GCs.

[0100] The vertical plug portion 162 may have a different width in the first horizontal direction (X direction) than the protruding plug portion 164. The vertical plug portion 162 may have a first width W1 in the first horizontal direction (X direction). The protruding plug portion 164 may have a second width W2 in the first horizontal direction (X direction). The second width W2 in each protruding plug portion 164 may be smaller than the first width W1.

[0101] At the height of the gate electrode 27a and at the height of the first interlayer insulating layer 24a, the gate contact plug GCc may have different widths in the first horizontal direction (X direction). The gate contact plug GCc has a third width W3 at the height of the gate electrode 27a (excluding the first lower gate electrode 27L1).

[0102] The gate contact plug GCc has a first width W1 at the height of the first interlayer insulating layer 24a. A third width W3 may be greater than the first width W1. The gate contact plug GCc may have a surface 166, whose sidewalls are curved in the vertical direction (Z direction) or have a curved surface, such as... Figure 8 As shown.

[0103] Gate spacers GCs may be disposed between the protruding plug portion 164 and the gate electrode 27a to insulate the gate contact plug Gc from the gate electrode 27a. The gate spacers GCs may be partially embedded in horizontal recesses 112 recessed from a sidewall 168 of the first interlayer insulating layer 24a along a first horizontal direction (X direction or -X direction) between the layers of the first interlayer insulating layer 24a. The horizontal recesses 112 may have a fourth width W4 in the first horizontal direction (X direction).

[0104] Gate spacers GCs can be formed by recessing inward from one sidewall 168 of the first interlayer insulating layer 24a. The gate spacers GCs can have a fifth width W5 in the first horizontal direction (X direction). The fifth width W5 can be smaller than the fourth width W4.

[0105] The extended region (or gate connection region) of the vertical non-volatile memory device 100 according to an embodiment includes a gate stack region GS having a structure in which gate electrodes 27a and first interlayer insulating layers 24a are alternately stacked. A gate contact plug GCc is disposed within the gate stack region GS.

[0106] The gate contact plug GCc includes a plurality of vertical plug portions 162 extending in a vertical direction and a plurality of protruding plug portions 164 protruding horizontally from both sides of the vertical plug portions 162. Gate spacers GCs, which insulate the gate contact plug GCc and the gate electrode 27a, are arranged between the protruding plug portions 164 and the gate electrode 27a. The vertical non-volatile memory device 100 with this configuration can improve the connection reliability between the gate electrode 27a and the gate contact plug GCc of the three-dimensionally arranged memory cell.

[0107] Figures 10 to 17 This is a cross-sectional view illustrating a method for manufacturing a vertical non-volatile storage device according to an embodiment.

[0108] Specifically, Figures 10 to 17 It is used to explain the manufacturing process. Figure 7 A cross-sectional view of the manufacturing method of EN2. Figures 10 to 17 In, with Figures 7 to 9 Similar reference numerals in the accompanying drawings indicate similar components. Figures 10 to 17 In, and reference Figures 7 to 9 Descriptions that are identical to the given descriptions are either given briefly or omitted.

[0109] refer to Figure 10 Multiple sacrificial material layers 23 and multiple interlayer insulating material layers 24 are alternately stacked layer by layer on board pattern 16 (reference). Figure 5 The sacrificial material layer 23 may include silicon nitride, silicon carbide, or polycrystalline silicon.

[0110] The sacrificial material layer 23 ensures space for the formation of gate lines (or gate electrodes) in subsequent processes. The interlayer insulating material layer 24 may include silicon oxide.

[0111] refer to Figure 11 For interlayer insulation material layer 24 (reference) Figure 10 ) and sacrificial material layer 23 (reference) Figure 10 The holes are patterned to form the first to third vertical holes 102, 104, and 106. The first to third vertical holes 102, 104, and 106 can be formed by etching the interlayer insulating material layer 24 (see reference) using a photolithography process. Figure 10 ) and sacrificial material layer 23 (reference) Figure 10 For example, the first to third vertical holes 102, 104 and 106 can be formed by etching the interlayer insulating material layer 24 using a wet etching process (see reference). Figure 10 ) and sacrificial material layer 23 (reference) Figure 10 It is formed by )

[0112] The first to third vertical holes 102, 104, and 106 can be formed spaced apart from each other in the first horizontal direction (X direction). The depths of the first to third vertical holes 102, 104, and 106 can be different from each other. Based on the formation of the first to third vertical holes 102, 104, and 106, the interlayer insulating material layer 24 (reference) Figure 10 ) and sacrificial material layer 23 (reference) Figure 10 They can form an interlayer insulating layer 24a and a sacrificial layer 23a, respectively.

[0113] refer to Figure 12 The sacrificial layer 23a is selectively etched along the first horizontal direction (X direction and -X direction) within the first to third vertical holes 102, 104 and 106. Accordingly, first horizontal recesses 108, 110 and 112 recessed along the first horizontal direction (X direction and -X direction) are formed within the first to third vertical holes 102, 104 and 106, respectively.

[0114] For example, the first to third horizontal recesses 108, 110, and 112 can be formed by wet etching of the sacrificial layer 23a. The first to third horizontal recesses 108, 110, and 112 can be formed by selective etching using the sacrificial layer 23a and the interlayer insulating layer 24a. When the sacrificial layer 23a is wet-etched, the first to third bottoms 114, 116, and 118 of the first to third vertical holes 102, 104, and 106 are hardly etched.

[0115] refer to Figure 13A first buried insulating layer to a third buried insulating layer 120, 122 and 124 are formed in the first vertical hole to the third vertical hole 102, 104 and 106, respectively embedded in the first horizontal hole to the third horizontal hole 108, 110 and 112.

[0116] Furthermore, first bottom insulating layers to third bottom insulating layers 126, 128, and 130 are formed on the first bottom to third bottom 114, 116, and 118 of the first to third vertical holes 102, 104, and 106, respectively. When forming the first buried insulating layers to third buried insulating layers 120, 122, and 124 and the first bottom insulating layers to third bottom insulating layers 126, 128, and 130, an insulating layer may also be formed on the sidewall of the interlayer insulating layer 24a within the first to third vertical holes 102, 104, and 106. The first buried insulating layers to third buried insulating layers 120, 122, and 124 and the first bottom insulating layers to third bottom insulating layers 126, 128, and 130 may include alumina.

[0117] refer to Figure 14 Filling first vertical holes to third vertical holes 102, 104 and 106 (reference) are formed on the first buried insulation layer to the third buried insulation layer 120, 122 and 124 and the first bottom insulation layer to the third bottom insulation layer 126, 128 and 130. Figure 13 The first to third buried sacrificial layers 132, 134 and 136 inside the burial sacrificial layer. The first to third buried sacrificial layers 132, 134 and 136 may include silicon nitride, polycrystalline silicon or silicon carbide.

[0118] refer to Figure 15 Sacrificial layer 23a (reference) Figure 14 The gate electrode 27a is replaced. The sacrificial layer 23a is etched and removed (see reference). Figure 14 After that, a gate electrode 27a is formed in the space after removal.

[0119] exist Figure 15 In this process, the gate electrode 27a may include a first lower gate electrode 27L1, a second lower gate electrode 27L2, and an intermediate gate electrode 27M that are stacked sequentially in the vertical direction (Z direction).

[0120] refer to Figure 16 Remove the first to the third buried sacrificial layers 132, 134 and 136 (reference) Figure 15 The first to third buried sacrificial layers 132, 134, and 136 were removed using a wet etching method (see reference). Figure 15 ).

[0121] Therefore, the final result is that a first bottom insulating layer to a third bottom insulating layer 126, 128 and 130 are formed in the first vertical holes to the third vertical holes 102, 104 and 106, respectively, and a first buried insulating layer to a third buried insulating layer 120, 122 and 124 are formed in the first horizontal recessed holes to the third horizontal recessed holes 108, 110 and 112, respectively.

[0122] refer to Figure 17 The first buried insulating layer to the third buried insulating layers 120, 122 and 124 are etched by wet etching (see reference). Figure 16 ), first bottom insulating layer to third bottom insulating layer 126, 128 and 130 (reference) Figure 16 ) and the first bottom insulating layer to the third bottom insulating layer 126, 128 and 130 (reference) Figure 16 The interlayer insulation layer 24a below.

[0123] Thus, the first buried insulating layer to the third buried insulating layer 120, 122 and 124 can be etched within the first to third horizontal recesses 108, 110 and 112 (reference). Figure 16 To form gate spacers (GCs). The first buried insulating layer to the third buried insulating layers 120, 122, and 124 can be recessed and etched on one sidewall of the interlayer insulating layer 24a (see reference). Figure 16 (as shown by reference numerals 150, 152 and 154 in the attached figures) to form gate spacers GCs.

[0124] Furthermore, if a wet etching method is used to etch the first bottom insulating layer to the third bottom insulating layer 126, 128, and 130 (see reference) Figure 16 ) and the first bottom insulating layer to the third bottom insulating layer 126, 128 and 130 (reference) Figure 16 The interlayer insulating layer 24a below the first vertical hole to the third vertical holes 102, 104 and 106 can easily expose the gate electrode 27a. The bottom 156, 158 and 160 of the first vertical hole to the third vertical holes 102, 104 and 106 can be the portions that expose the gate electrode 27a.

[0125] Continue, as Figure 7 As shown, a gate contact plug GCc is formed in the first to third vertical holes 102, 104 and 106 of the exposed gate electrode 27a, thereby forming a gate contact structure GC.

[0126] The gate contact plug GCc formed in the first to third vertical holes 102, 104 and 106 of the exposed gate electrode 27a can be easily connected to the gate electrode 27a. In other words, the connection reliability between the gate contact plug GCc in the first to third vertical holes 102, 104 and 106 of the exposed gate electrode 27a and the gate electrode 27a can be improved.

[0127] Here, for reference Figure 7 Describe the gate contact structure GC.

[0128] like Figure 7 As shown, the gate contact plug GCc may include a first gate contact plug GCc-1 buried in the first vertical hole 102, the first gate contact plug GCc-1 being in vertical contact with the first gate electrode 27M in the gate electrode 27a, and being arranged on one side of the first horizontal recess 108 extending horizontally from the first vertical hole 102.

[0129] The gate contact plug GCc may include a second gate contact plug GCc-2 filled in the second vertical hole 104, the second gate contact plug GCc-2 being in vertical contact with the second gate electrode 272L2 in the gate electrode 27a, and disposed on one side of the second horizontal recess 110 extending horizontally from the second vertical hole 104. Within the gate stack region GS, the first gate electrode 27M may be at a height higher than the second gate electrode 27L2 (see reference). Figure 5 ).

[0130] The gate contact plug GCc may include a third gate contact plug GCc-3 buried in the third vertical hole 106, which vertically contacts the third gate electrode 27L1 in the gate electrode (27a) and is disposed on one side of the third horizontal recess 112 extending horizontally from the third vertical hole 106. Within the gate stack region GS, the second gate electrode 27L2 may be at a higher height than the third gate electrode 27L1 (see reference). Figure 5 ).

[0131] The gate spacers GCs can be partially buried in the first horizontal recess 108, the second horizontal recess 110 and the third horizontal recess 112 to insulate the gate contact plug GCc from the gate electrode 27a.

[0132] One or more of the elements disclosed above may include or be implemented in processing circuitry, which may be, for example, hardware including logic circuitry, a hardware / software combination such as a processor executing software, or a combination of both. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0133] Although the inventive concept has been described in detail with reference to embodiments, the inventive concept is not limited thereto, and those skilled in the art can make various modifications and changes within the technical spirit and scope of the inventive concept.

Claims

1. A vertical nonvolatile memory device, comprising: a gate stack including a plurality of gate electrodes and a plurality of interlayer insulating layers stacked alternately; gate spacers; and a plurality of gate contact plugs spaced apart from each other in the gate stack, wherein the plurality of gate contact plugs includes a first gate contact plug vertically contacting a first gate electrode of the plurality of gate electrodes and a second gate contact plug vertically contacting a second gate electrode of the plurality of gate electrodes, wherein the gate contact plugs include a plurality of vertical plug portions extending in a vertical direction and a plurality of protruding plug portions protruding horizontally from both sides of the plurality of vertical plug portions, and wherein the gate spacers are between the plurality of protruding plug portions and the plurality of gate electrodes, and the gate spacers insulate the plurality of gate contact plugs from a part of the plurality of gate electrodes.

2. The vertical nonvolatile memory device of claim 1, wherein, bottoms of the plurality of vertical plug portions contact upper portions of the plurality of gate electrodes.

3. The vertical nonvolatile memory device of claim 1, wherein, a height of the first gate electrode in the gate stack is higher than a height of the second gate electrode.

4. The vertical nonvolatile memory device of claim 1, wherein, in a horizontal direction, widths of the plurality of vertical plug portions are different from a width of the protruding plug portions.

5. The vertical nonvolatile memory device according to claim 4, wherein the plurality of vertical plug portions have a first width in the horizontal direction, the plurality of protruding plug portions have a second width in the horizontal direction, and the second width in each protruding plug portion is smaller than the first width.

6. The vertical nonvolatile memory device of claim 1, wherein, a respective one of the plurality of gate contact plugs has different widths in a horizontal direction at a height of a respective one of the plurality of gate electrodes and at a height of a respective one of the plurality of interlayer insulating layers.

7. The vertical nonvolatile memory device according to claim 6, wherein a respective one of the plurality of gate contact plugs has a first width in the horizontal direction at a height of a respective one of the plurality of interlayer insulating layers, a respective one of the plurality of gate contact plugs has a second width in the horizontal direction at a height of a respective one of the plurality of gate electrodes, and the second width is larger than the first width.

8. The vertical nonvolatile memory device of claim 1, wherein, sidewalls of the plurality of gate contact plugs have curved surfaces.

9. The vertical nonvolatile memory device according to claim 1, wherein the plurality of gate electrodes include horizontal recesses recessed in a horizontal direction from sidewalls of one side of the plurality of interlayer insulating layers, and the gate spacers are in the horizontal recesses.

10. The vertical nonvolatile memory device according to claim 9, wherein a width of the gate spacers in the horizontal direction is smaller than a width of the horizontal recesses recessed in the horizontal direction from the sidewalls of the one side of the plurality of interlayer insulating layers.

11. A vertical nonvolatile memory device, comprising: a gate stack including a plurality of gate electrodes and a plurality of interlayer insulating layers stacked alternately; gate spacers; and a plurality of gate contact plugs spaced apart from each other in the gate stack, wherein the gate stack defines a first vertical hole over a first gate electrode of the plurality of gate electrodes and exposing the first gate electrode, a first horizontal recess hole horizontally extending from the first vertical hole, a second vertical hole over a second gate electrode of the plurality of gate electrodes and exposing the second gate electrode, and a second horizontal recess hole horizontally extending from the second vertical hole, wherein the plurality of gate contact plugs includes a first gate contact plug and a second gate contact plug, the first gate contact plug is in the first vertical hole and vertically contacts the first gate electrode of the gate electrodes, the first gate contact plug is arranged on one side of the first horizontal recess hole, the second gate contact plug is in the second vertical hole and vertically contacts the second gate electrode, the second gate contact plug is arranged on one side of the second horizontal recess hole, and wherein a plurality of first gate spacers are in the first horizontal recess hole and a plurality of second gate spacers are in the second horizontal recess hole, the plurality of first gate spacers insulate the first gate contact plug from gate electrodes of the plurality of gate electrodes other than the first gate electrode, and the plurality of second gate spacers insulate the second gate contact plug from gate electrodes of the plurality of gate electrodes other than the second gate electrode.

12. The vertical nonvolatile memory device of claim 11, wherein, a height of the first gate electrode in the gate stack is higher than a height of the second gate electrode in the gate stack.

13. The vertical nonvolatile memory device of claim 11, wherein the plurality of gate contact plugs includes a vertical plug portion and a horizontal plug portion, the vertical plug portion of the first gate contact plug is within the first vertical hole, the vertical plug portion of the second gate contact plug is within the second vertical hole, the horizontal plug portion of the first gate contact plug is within the first horizontal recess hole, and the horizontal plug portion of the second gate contact plug is within the second horizontal recess hole.

14. The vertical nonvolatile memory device of claim 13, wherein in a horizontal direction, the vertical plug portion of the plurality of gate contact plugs is wider than the horizontal plug portion of the plurality of gate contact plugs.

15. The vertical nonvolatile memory device of claim 11, wherein in a horizontal direction, a width of the plurality of gate contact plugs at a height of the plurality of gate electrodes is greater than a width of the plurality of gate contact plugs at a height of the plurality of interlayer insulating layers.

16. The vertical nonvolatile memory device of claim 11, wherein, a sidewall of the plurality of gate contact plugs has a curved surface.

17. A vertical nonvolatile memory device, comprising: a memory cell array structure including a memory cell array; a gate spacer; and an extension structure extending from a side of the memory cell array structure and connected with a plurality of gate electrodes of the memory cell array structure, wherein the memory cell array structure and the extension structure include a gate stack, wherein the gate stack includes the plurality of gate electrodes and a plurality of interlayer insulating layers stacked alternately, and the extension structure includes a plurality of gate contact plugs spaced apart from each other in the gate stack, the gate stack defines a first vertical hole over a first gate electrode of the plurality of gate electrodes and exposing the first gate electrode, a first horizontal recess hole horizontally extending from the first vertical hole, a second vertical hole over a second gate electrode of the plurality of gate electrodes and exposing the second gate electrode, and a second horizontal recess hole horizontally extending from the second vertical hole, wherein the plurality of gate contact plugs includes a first gate contact plug and a second gate contact plug, the first gate contact plug is in the first vertical hole and vertically contacts the first gate electrode of the gate electrodes, the first gate contact plug is arranged on one side of the first horizontal recess hole, the second gate contact plug is in the second vertical hole and vertically contacts the second gate electrode, the second gate contact plug is arranged on one side of the second horizontal recess hole, and wherein a plurality of first gate spacers are in the first horizontal recess hole and a plurality of second gate spacers are in the second horizontal recess hole, the plurality of first gate spacers insulate the first gate contact plug from gate electrodes of the plurality of gate electrodes other than the first gate electrode, and the plurality of second gate spacers insulate the second gate contact plug from gate electrodes of the plurality of gate electrodes other than the second gate electrode. a height of the first gate electrode in the gate stack is higher than a height of the second gate electrode in the gate stack. wherein the plurality of gate contact plugs includes a first gate contact plug vertically contacting a first gate electrode of the plurality of gate electrodes and a second gate contact plug vertically contacting a second gate electrode of the plurality of gate electrodes, and wherein the plurality of gate contact plugs includes a plurality of vertical plug portions extending in a vertical direction and a plurality of protruding plug portions protruding horizontally from both sides of the plurality of vertical plug portions, and wherein the gate spacers are between the plurality of protruding plug portions and the plurality of gate electrodes, and the gate spacers insulate the plurality of gate contact plugs from a portion of the plurality of gate electrodes.

18. The vertical nonvolatile memory device of claim 17, wherein bottoms of the plurality of vertical plug portions contact upper portions of the plurality of gate electrodes, and in a horizontal direction, widths of the plurality of vertical plug portions are greater than widths of the plurality of protruding plug portions.

19. The vertical nonvolatile memory device of claim 17, further comprising: a through structure on one side of the extension structure, wherein the through structure includes a dummy stack, the dummy stack includes a plurality of dummy gate electrodes and a plurality of insulating layers alternately stacked.

20. The vertical nonvolatile memory device of claim 19, further comprising: a peripheral circuit structure, wherein the memory cell array structure, the extension structure, and the through structure are on the peripheral circuit structure, and the through structure includes a via contact plug connecting the memory cell array structure to the peripheral circuit structure.

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