Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, and relates to the technical field of semiconductors. The first doping type well region is formed in the substrate along the first side of the substrate, the stress region and the second doping type source region are formed in the first doping type well region, and the second doping type drain region is formed in the stress region; the gate structure is formed on the substrate along the first side of the substrate; wherein the stress region is formed by growing a material which is in lattice mismatch with the substrate material, and along the thickness direction of the substrate, the gate structure covers a part of the stress region and a part of the top of the first doping type well region, and is connected with the second doping type drain region and the second doping type source region. According to the technical scheme, the electron mobility can be improved, and then the current capacity of the nLDMOS is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, chip and electronic device. Background Technology

[0002] LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) is a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). LDMOS achieves high voltage tolerance while maintaining high frequency characteristics through lateral current transport and drift region doping control.

[0003] nLDMOS (N-type lateral double-diffused metal-oxide semiconductor) is a type of LDMOS. Currently, due to the fact that the architectural parameters (such as the length of the lateral drift region and the gate control precision), process conditions (such as silicon doping concentration and photolithography resolution) and process limits (such as the intensification of short-channel effects and the saturation of parasitic parameters) of nLDMOS are approaching the physical limits (including the carrier transport limit and the material breakdown field strength threshold), its performance improvement faces bottlenecks.

[0004] Furthermore, existing bipolar-CMOS-DMOS (BCD) composite processes are constrained by compatibility with traditional CMOS architectures. Optimization of nLDMOS is limited to fine-tuning local parameters such as field oxygen, drift region, and pitch. The intrinsic physical properties of pure silicon solidify the performance within this range, leaving no significant room for optimization within the full safe operating area (Full SOA). Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method, chip and electronic device, which provides a technical solution that can improve electron mobility and thus increase the current capability of nLDMOS.

[0006] In a first aspect, embodiments of this application provide a semiconductor device, the semiconductor device comprising: Substrate; Along a first side of the substrate, a first doped type well region is formed in the substrate, a stress region and a second doped type source region are formed in the first doped type well region, and a second doped type drain region is formed in the stress region; And a gate structure formed on the substrate along a first side of the substrate; The stress region is formed by growing a material that is lattice mismatched with the substrate material. Along the thickness direction of the substrate, the gate structure covers the top of a portion of the stress region and a portion of the first doped type well region, and is connected to the second doped type drain region and the second doped type source region.

[0007] In one alternative embodiment, the semiconductor device further includes: a first doped substrate contact region formed in the stress region; Along a direction perpendicular to the substrate thickness, the first doped substrate contact region is connected to the side of the second doped drain region opposite to the second doped source region.

[0008] In one alternative embodiment, the gate structure includes: a gate, a gate oxide layer, and sidewalls; Along the thickness direction of the substrate, the gate oxide layer and the gate electrode are sequentially formed on the substrate; The sidewalls are formed on both sides of the gate oxide layer and the gate along a direction perpendicular to the thickness of the substrate.

[0009] In one alternative embodiment, the stress region is one of a silicon carbide stress region, a silicon-germanium stress region, and a polycrystalline silicon stress region. The substrate is a silicon substrate.

[0010] In one alternative embodiment, the stress region includes a first doped type body implantation layer and a stress layer; The first doped type body injection layer is located between the stress layer and the first doped type well region.

[0011] In one alternative embodiment, the doping concentration of the first doped type well region, the doping concentration of the first doped type body implantation layer, and the doping concentration of the stress layer gradually increase along the thickness direction of the substrate.

[0012] Secondly, embodiments of this application provide an N-type lateral double-diffused metal-oxide-semiconductor device, the semiconductor device comprising: Substrate; Along a first side of the substrate, a P-type well region is formed in the substrate, a stress region and an N-type source region are formed in the P-well region, and an N-type drain region is formed in the stress region; And a gate structure formed on the substrate along a first side of the substrate; The stress region is formed by growing a material that is lattice mismatched with the substrate material; along the thickness direction of the substrate, the gate structure covers the top of a portion of the stress region and a portion of the N-type well region, and is connected to the P-type drain region and the P-type source region.

[0013] In one alternative embodiment, the semiconductor device further includes a P-type substrate contact region formed in the stress region; Along a direction perpendicular to the thickness of the substrate, the P-type substrate contact area is connected to the side of the N-type drain region that is away from the N-type source region.

[0014] Thirdly, this application provides a method for fabricating a semiconductor device, the method comprising: Provide substrate; Along a first side of the substrate, a stress region and a first doped type well region are formed in the substrate; wherein the stress region is formed in the first doped type well region; A gate structure is formed on the substrate; Along a first side of the substrate, a second doped source region is formed in the first doped type well region, and a second doped drain region is formed in the stress region; The stress region is formed by growing a material that is lattice mismatched with the substrate material; along the thickness direction of the substrate, the gate structure covers the top of a portion of the stress region and a portion of the first doped type well region, and is connected to the second doped type drain region and the second doped type source region.

[0015] In one alternative embodiment, the formation of a stress region and a first-doped type well region on the substrate includes: A stress groove is formed in a first predetermined region of the substrate; Ion implantation of a first doping type is performed on the stress groove along the opening direction of the stress groove to form a first doping type bulk implantation layer; The stress groove is filled with stress material to form a stress layer; Along the first side of the substrate, a second predetermined region of the substrate is subjected to ion doping of a first doping type to form a first doping type well region; wherein, the first side of the substrate is the side where the stress region is located.

[0016] In one optional embodiment, forming the gate structure on the substrate includes: Along a first side of the substrate, a gate oxide material layer and a gate material layer are sequentially formed on the substrate; The gate oxide material layer and the gate material layer are subjected to a first patterning process to obtain the gate oxide layer and the gate; wherein, along the thickness direction of the substrate, the gate oxide layer is connected to a portion of the stress region; Sidewalls are formed on both sides of the gate oxide layer and the gate along a direction perpendicular to the thickness of the substrate.

[0017] In one alternative embodiment, forming a second doped type source region in the first doped type well region along a first side of the substrate, and forming a second doped type drain region in the stress region, includes: Along the first side of the substrate, a second type of ion implantation is performed on a third predetermined region of the stress region to obtain a second type of drain region, and a second type of ion implantation is performed on a fourth predetermined region of the first type of well region to obtain a second type of source region.

[0018] In an optional implementation, the method further includes: Along the first side of the substrate, ion implantation of a first doping type is performed on the fourth predetermined region of the stress region to form a first doping type substrate contact region; Wherein, along a direction perpendicular to the substrate thickness, the first doped substrate contact region is connected to the side of the second doped drain region away from the stress region.

[0019] Fourthly, this application provides a chip including the semiconductor device described in the first aspect, or the vertical gate planar field-effect transistor described in the third aspect, or the current mirror described in the fourth aspect.

[0020] Fifthly, this application provides an electronic device including the chip described in the fifth aspect.

[0021] With the above technical solution adopted, embodiments of this application provide a semiconductor device and its fabrication method, chip and electronic device. The semiconductor device includes: a substrate; a first doped type well region formed in the substrate along a first side, a stress region and a second doped type source region formed in the first doped type well region, and a second doped type drain region formed in the stress region; and a gate structure formed on the substrate along the first side; wherein the stress region is formed by growing a material that is lattice mismatched with the substrate material, and along the thickness direction of the substrate, the gate structure covers the top of a portion of the stress region and a portion of the first doped type well region, and is connected to the second doped type drain region and the second doped type source region.

[0022] In this embodiment, a stress region is formed by growing a material with a lattice mismatch with the substrate material. This stress region, mismatched with the substrate lattice, generates stress to regulate carrier transport in the semiconductor device. Specifically, when the stress material is epitaxially grown on the silicon substrate, the lattice mismatch applies tensile stress to the surrounding drift regions. This tensile stress reduces the effective mass of electrons in the silicon lattice and decreases the probability of valley scattering, thereby improving the electron mobility of the semiconductor device. It should be understood that electron mobility determines the device current. Therefore, under the same gate voltage and size, the stress region can increase the device's saturation current, solving the technical problem of insufficient current capability under high voltage in traditional pure silicon devices. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0024] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 ; Figure 3 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 2 ; Figure 4 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 3 ; Figure 5 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 4 ; Figure 6 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 5 ; Figure 7 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 6 ; Figure 8 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 7 ; Figure 9 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 8 ; Figure 10 A schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 9 .

[0025] Figure Descriptions: Substrate 101 - First side of substrate; 20 - Stress region; 201 - Stress groove; 202 - First doped type body implantation layer; 203 - Stress layer; 30 - Epitaxial layer; 40 - Gate structure; 401 - Gate oxide material layer; 402 - Gate material layer; 403 - Gate oxide layer; 404 - Gate; 405 - Sidewall; 50 - Second doped type source region; 60 - Second doped type drain region; 70 - First doped type substrate contact region. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various information or data, but these elements are not limited by these terms. These terms are only used to distinguish first information from another type of information. For example, without departing from the scope of this application, first action information may be referred to as second action information, and similarly, second action information may be referred to as first action information. Both first action information and second action information are action information, but they are not the same action information.

[0028] In this document, it should be understood that the terminology used is for convenience of understanding only and does not imply any limitation on its meaning. Furthermore, any number of elements in the accompanying drawings is for illustrative purposes only and not for limitation, and any naming is for distinction only and has no limiting meaning.

[0029] LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) is a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). LDMOS achieves high voltage tolerance while maintaining high frequency characteristics through lateral current transport and drift region doping control.

[0030] nLDMOS (N-type lateral double-diffused metal-oxide semiconductor) is a type of LDMOS. Currently, due to the fact that the architectural parameters (such as the length of the lateral drift region and the gate control precision), process conditions (such as silicon doping concentration and photolithography resolution) and process limits (such as the intensification of short-channel effects and the saturation of parasitic parameters) of nLDMOS are approaching the physical limits (including the carrier transport limit and the material breakdown field strength threshold), its performance improvement faces bottlenecks.

[0031] Furthermore, existing bipolar-CMOS-DMOS (BCD) composite processes are constrained by compatibility with traditional CMOS architectures. Optimization of nLDMOS is limited to fine-tuning local parameters such as field oxygen, drift region, and pitch. The intrinsic physical properties of pure silicon solidify the performance within this range, leaving no significant room for optimization within the full safe operating area (Full SOA).

[0032] Based on this, the inventive concept of this application embodiment is: to form a stress region in the LDMOS device so that the tensile stress generated by the stress region acts on the current channel of the device, thereby increasing the current capability of the LDMOS device. While being compatible with the BCD process, it breaks through the physical limits of pure silicon material and provides an optimized path for high performance and easy mass production of LDMOS devices.

[0033] The technical solutions shown in this application will now be described in detail through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; for identical or similar content, the description will not be repeated in different embodiments.

[0034] Reference Figure 1 This application illustrates a semiconductor device provided in an embodiment of the present application. The semiconductor device includes: a substrate 10; a first doped type well region 30 formed in the substrate 10 along a first side 101 of the substrate 10; a stress region 20 and a second doped type source region 50 formed in the first doped type well region 30; a second doped type drain region 60 formed in the stress region; and a gate structure 40 formed on the substrate 10.

[0035] The stress region is formed by growing a material that is lattice mismatched with the substrate 10. Along the thickness direction of the substrate 10, the gate structure covers the top of a portion of the stress region and a portion of the first doped type well region 30, and is connected to the second doped type drain region 60 and the second doped type source region 50.

[0036] In the embodiments of this application, the semiconductor device described above can be a laterally double-diffused metal-oxide-semiconductor device, or any other semiconductor device adapted to the above structure. The embodiments of this application do not impose any special limitations on this.

[0037] The aforementioned substrate 10 is the physical base of the device, used to support all upper structures and provide mechanical / electrical support. It can be a P-type silicon substrate 10, an N-type silicon substrate 10, or other suitable substrates 10. This application embodiment does not make any special limitation on this.

[0038] For example, when the semiconductor device is an N-type lateral double-diffused metal-oxide-semiconductor device, the substrate 10 can be a P-type silicon substrate 10.

[0039] When the semiconductor device is a P-type lateral double-diffused metal-oxide semiconductor device, the substrate 10 can be an N-type silicon substrate 10.

[0040] In this embodiment, a first-doped well region 30 is formed in a substrate 10, which can be understood as the substrate 10 and the epitaxial layer formed on the substrate 10. The first-doped well region 30 can be formed by ion implantation of the epitaxial layer with a first-doped type.

[0041] When the semiconductor device is an N-type lateral double-diffused metal-oxide-semiconductor device, the first doped type well region 30 is a P-type well region, the second doped type source region 50 and the second doped type drain region 60 can be N-type source regions and N-type drain regions. Based on this, the first doped type well region 30 forms a PN junction with the second doped type source region and the second doped type drain region. When reverse biased, a depletion layer is generated to withstand high voltage.

[0042] In this embodiment, the stress region 20 is formed by growing a material that is compatible with the lattice of the substrate 10, and the bottom and sidewalls of the stress region 20 are covered by a first doped type well region 30 to transfer the lattice stress of the stress region 20 to the current channel of the device, while limiting the lateral expansion of the stress region and avoiding interference to other areas.

[0043] In this embodiment, the source region and drain region of the second doping type are heavily doped regions. The drain region 60 of the second doping type is formed in the stress region to withstand high voltage, serving as the voltage-bearing region for the device. The source region 50 of the second doping type is located on the other side of the well region 30 of the first doping type, and the PN junction formed with the well region 30 is grounded via a metal interconnect to fix the potential and suppress parasitic latch-up effects.

[0044] Reference Figure 1Along a direction perpendicular to the thickness of the substrate 10, the second doped drain region 60, the stress region 20, the first doped well region 30, and the second doped source region 50 are sequentially connected to form a complete lateral current path. Electrons start from the second doped source region 50, pass through the channel region on the surface of the first doped well region 30 to the stress region 20, and then pass to the second doped drain region 60.

[0045] Based on the above description, in this embodiment, a stress region is formed by growing a material whose lattice is compatible with that of the substrate 10. Therefore, the stress region can mismatch with the lattice of the substrate 10, generating lateral stress that can then regulate the transport of charge carriers in the semiconductor device. Specifically, when the stress material is epitaxially grown on the silicon substrate 10, tensile stress is applied to the surrounding drift regions due to lattice mismatch. When this tensile stress acts on the drift regions, it reduces the effective mass of electrons in the silicon lattice and decreases the probability of inter-valley scattering, thereby increasing electron mobility. Electron mobility determines the magnitude of the device current. Therefore, under the same gate voltage and device size, the stress region can increase the saturation current of the device, solving the technical problem of insufficient current capability under high voltage in traditional pure silicon devices.

[0046] Optionally, the semiconductor device provided in this application embodiment further includes: the semiconductor device further includes: a first doped substrate contact region 70 formed in the stress region; Along a direction perpendicular to the thickness of the substrate 10, the first doped substrate contact region 70 is connected to the side of the second doped drain region 60 away from the second doped source region 50.

[0047] Reference Figure 1 In this embodiment, the first doped substrate contact region 70 is formed on the upper surface of the stress region, and its bottom and one side wall are covered by the stress region. It can be directly connected to a low potential through metal interconnect. It and the first doped well region 30 are respectively connected to the upper and lower sides of the stress region, anchoring the potential of the stress region to a low potential and avoiding potential drift caused by charge accumulation in the stress region.

[0048] Furthermore, in the embodiments of this application, the contact area of ​​the first conductivity type substrate 10 is only formed on the upper surface of the stress region and has a limited lateral dimension. Therefore, its doping will not significantly destroy the lattice integrity of the stress region, and thus has a minimal impact on the improvement of the device's electron mobility.

[0049] In some examples, the stress region may be one of a silicon carbide stress region, a silicon-germanium stress region, and a polycrystalline silicon stress region; the substrate 10 is a silicon substrate 10.

[0050] The silicon carbide stress region has a large lattice mismatch with the silicon substrate 10, which can generate strong tensile stress, thereby increasing the electron mobility of the LDMOS drift region, reducing the on-resistance, and thus enhancing the current capability of the LDMOS.

[0051] It should be understood that the breakdown field strength of silicon carbide is eight times that of silicon. Therefore, the interface between the silicon carbide stress region and the first-doped type well region 30 can disperse the drain electric field, thereby further increasing the breakdown voltage of the semiconductor device. Furthermore, silicon carbide has a thermal conductivity three times that of silicon, which can quickly dissipate the heat generated during semiconductor device operation, reducing junction temperature drop and improving the thermal stability of the device.

[0052] Based on the above description, semiconductor devices fabricated based on silicon carbide stress regions can be applied to scenarios such as 5G base station RF power amplifiers, new energy vehicle inverters, and industrial-grade switching power supplies.

[0053] Among them, the lattice mismatch between the silicon-germanium stress region and the silicon substrate 10 generates stress, which can also improve the electron mobility of the semiconductor device, thereby enhancing the current capability of the LDMOS.

[0054] It should be understood that the silicon-germanium stress region has a lower lattice mismatch rate with the silicon substrate 10, and the epitaxial growth temperature is lower than that of the silicon carbide stress region. This results in less thermal damage to the silicon substrate 10 and surrounding CMOS devices, making it suitable for the integration of low-voltage modules in the BCD process. Furthermore, the epitaxial growth process of the silicon-germanium stress region has a lower cost.

[0055] Based on the above description, semiconductor devices fabricated based on silicon-germanium stress regions can be applied to low-voltage power management chips (such as LDO regulators) and low-power DC-DC converters in consumer electronics (such as mobile phone charging modules).

[0056] Among them, polycrystalline silicon has a smaller lattice mismatch rate with silicon substrate 10 by controlling the doping concentration and growth temperature, which can generate weak tensile / compressive stress and improve the electron mobility of the device. It is suitable for scenarios with low performance requirements but low cost requirements.

[0057] Polycrystalline silicon growth is a mature step in traditional CMOS processes, allowing for the direct reuse of existing equipment without the need for additional process modules, and achieving 100% compatibility with BCD processes. Furthermore, polycrystalline silicon exhibits a low interface defect density with silicon, and its long-term stability in the stress region is superior to that of silicon carbide and silicon germanium, making it suitable for applications with high lifespan requirements.

[0058] Based on the above description, semiconductor devices fabricated based on silicon carbide stress regions can be applied to scenarios such as white goods power controllers, low-voltage motor drive chips, and automotive body electronics.

[0059] Optionally, the stress region includes a first doped type body implantation layer 202 and a stress layer 203; The first doped type body implantation layer 202 is located between the stress layer 203 and the first doped type well region 30.

[0060] In this embodiment, the doping concentration of the first doped type body implantation layer 202 is greater than that of the first doped type well region 30 and less than that of the stress layer 203, so as to form a doping gradient from the first doped type well region 30, the first doped type body implantation layer 202 to the stress layer 203.

[0061] Based on this, when a high voltage is applied to the second-doped drain region 60, the electric field will smoothly transition along the doping gradient, avoiding the formation of an electric field peak at the direct interface between the stress layer 203 and the first-doped well region 30. Therefore, the peak electric field at the drain end can be monitored, thereby improving the device breakdown voltage.

[0062] It should be understood that the lattice mismatch between the stress layer 203 and the silicon substrate 10 generates stress. If it directly contacts the first-doped well region 30, dislocations (lattice defects) are easily generated at the interface due to abrupt stress changes, leading to increased carrier scattering and decreased mobility. The first-doped bulk injection layer 202 can act as a lattice buffer band. Its crystal structure is close to that of the silicon substrate 10, and it can gradually release some of the stress in the stress layer 203, avoiding lattice relaxation caused by stress concentration. Therefore, the presence of the first-doped bulk injection layer 202 reduces the dislocation density at the interface between the stress layer 203 and the first-doped well region 30, reducing the scattering probability of carriers at the interface, and maintaining a long-term stable effect of the stress layer 203 on improving mobility. Furthermore, the buffering effect of the first-doped bulk injection layer 202 reduces lattice defects in the stress layer 203, allowing stress to be transmitted more uniformly to the main current channel. For example, the tensile stress of the stress layer 203 can be transmitted through the bulk injection layer to the channel region on the surface of the first-doped well region 30 without being absorbed by interface defects.

[0063] Furthermore, the first doped type body implantation layer 202 and the first doped type well region 30 belong to the same doping type, and can be connected by the doping concentration gradient to form a low-resistance ohmic contact, avoiding the increase of parasitic resistance caused by material differences.

[0064] The first-doped bulk implantation layer 202 can isolate impurities in the stress layer 203 and the first-doped well region 30, preventing impurity diffusion from causing lattice structure distortion of the stress layer 203. Furthermore, for different types of stress layers 203 (SiC, SiGe, polycrystalline silicon), the first-doped bulk implantation layer 202 can optimize interface characteristics by adjusting the doping concentration, eliminating the need to adjust the growth parameters of the stress layer 203 to fit the first-doped well region 30, thus improving process flexibility.

[0065] In this embodiment of the application, the gate structure includes: a gate 404, a gate oxide layer 403, and a sidewall 405; Along the thickness direction of the substrate 10, the gate oxide layer 403 and the gate electrode 404 are sequentially formed on the substrate 10; Along a direction perpendicular to the thickness of the substrate 10, the sidewall 405 is formed on both sides of the gate oxide layer 403 and the gate 404.

[0066] Along the thickness direction of the substrate 10, a gate oxide layer 403 is formed on the surface of the substrate 10. It is an extremely thin insulating dielectric layer, typically SiO2 or a high-k material such as HfO2, used to transmit the electric field of the gate 404 and isolate the electrical connection between the gate 404 and the channel. The insulating nature of the gate oxide layer 403 ensures that there is no DC conduction path between the gate 404 and the channel, and the control signal is transmitted only through electric field coupling, avoiding current runaway caused by the gate 404 voltage directly driving the channel.

[0067] When a voltage is applied to the gate 404, an electric field perpendicular to the surface of the substrate 10 is formed on both sides of it. This electric field can penetrate to the surface of the first doped type well region 30 below the gate oxide layer 403, inducing the formation of a conductive channel.

[0068] The gate 404 is located above the gate oxide layer 403 and is usually made of polysilicon (Poly-Si) or metal (such as TiN, Al) to apply control voltage and generate a modulated electric field.

[0069] The gate 404 receives an external drive signal through a metal interconnect. When the drive signal is greater than the turn-on threshold signal, the electric field generated by the gate 404 induces the formation of a channel through the gate oxide layer 403. When the drive signal is less than the turn-on threshold signal, the electric field generated by the gate 404 disappears and the channel is turned off, thereby realizing the switching control function.

[0070] Along the thickness direction (lateral direction) of the substrate 10, sidewalls 405 are formed on both sides of the gate oxide layer 403 and the gate 404. They are made of insulating materials such as Si3N4 and SiO2 and are used to isolate the gate 404 from the source and drain, assist in the self-alignment process, and optimize the electric field distribution.

[0071] It should be understood that the sidewalls 405 are formed on both sides of the gate 404 to prevent heavily doped atoms from the source and drain regions from diffusing into the gate 404 and avoid gate-source / gate-drain short circuits. At the same time, the sidewalls 405, as a low dielectric constant insulating layer, can reduce the parasitic capacitance between the gate 404 and the source and drain regions.

[0072] It should be further understood that in the source / drain region ion implantation process, the sidewall 405 can be used as a mask. When ions are implanted, the sidewall 405 will prevent ions from being directly implanted below the gate 404, so that the source / drain region automatically maintains a fixed distance from the edge of the gate 404. The channel length can be defined without additional photolithography steps, which can improve the control accuracy of the channel length and thus improve the performance of semiconductor devices.

[0073] Secondly, embodiments of this application provide an N-type lateral double-diffused metal-oxide-semiconductor device, the semiconductor device comprising: Substrate; Along a first side of the substrate, a P-type well region is formed in the substrate, a stress region and an N-type source region are formed in the P-well region, and an N-type drain region is formed in the stress region; And a gate structure formed on the substrate along a first side of the substrate; The stress region is formed by growing a material that is lattice mismatched with the substrate material; along the thickness direction of the substrate, the gate structure covers the top of a portion of the stress region and a portion of the N-type well region, and is connected to the P-type drain region and the P-type source region.

[0074] In this embodiment, a P-type well region is formed in a substrate, which can be understood as the substrate and the epitaxial layer formed on the substrate. This P-type well region can be formed by P-type ion implantation into the epitaxial layer.

[0075] In this system, the P-type well region forms a PN junction with the N-type source region and the N-type drain region, and a depletion layer is generated when reverse biased to withstand high voltage.

[0076] In this embodiment, a material adapted to the lattice of the substrate material is grown, and the bottom and sidewalls of the stress region are covered by a P-type well region to transfer the lattice stress of the stress region to the current channel, while limiting the lateral expansion of the stress region and avoiding interference to other areas.

[0077] In the embodiments of this application, the N-type source region and N-type drain region are heavily doped regions. The N-type drain region is located near the stress region and is used to withstand high voltage. The PN junction depletion layer formed with the P-type well region mainly extends into the stress region, serving as the voltage-carrying region for the device. On the other side of the N-type source region near the P-type well region, the PN junction formed with the P-type well region is grounded through a metal interconnect to fix the potential and suppress parasitic latch-up effects.

[0078] Along a direction perpendicular to the substrate thickness, the N-type drain region, the stress region, the P-type well region, and the N-type source region are connected in sequence to form a complete lateral current path. Electrons start from the N-type source region, are transported through the channel region on the surface of the P-type well region to the stress region, and then to the N-type drain region.

[0079] Based on the above description, in this embodiment, a stress region is formed by growing a material whose lattice is compatible with the substrate material. Therefore, the stress region can mismatch with the substrate lattice, generating lateral stress, thereby regulating the carrier transport in the semiconductor device. Specifically, when the stress material is epitaxially grown on the silicon substrate 10, tensile stress is applied to the surrounding drift regions due to lattice mismatch. When this tensile stress acts on the drift regions, it reduces the effective mass of electrons in the silicon lattice and decreases the probability of inter-valley scattering, thereby increasing electron mobility. It should be understood that electron mobility determines the magnitude of the device current. Therefore, under the same gate voltage and device size, the stress region can increase the saturation current of the nLDMOS, solving the technical problem of insufficient current capability under high voltage in traditional pure silicon devices.

[0080] Optionally, the semiconductor device further includes: a P-type substrate contact region; Along the thickness direction of the substrate 10, the substrate, the stress region, and the P-type substrate 10 contact region are sequentially stacked; along the direction perpendicular to the thickness of the substrate, the P-type substrate 10 contact region is formed between the stress region and the side of the N-type drain region away from the N-type source region.

[0081] In this embodiment, the P-type substrate contact region can be P + The heavily doped region forms a low-resistance path with the stress region, P-type well region and substrate below in the vertical direction. When the device is working, the P-type substrate 10 contact area is directly grounded (or connected to a low potential) through metal interconnect, which forces the potential of the substrate and P-type well region to be anchored at a low potential, avoiding the substrate potential rise caused by parasitic current.

[0082] Furthermore, along the direction perpendicular to the substrate thickness, stress regions, P-type substrate 10 contact regions, and N-type drain regions are formed, creating N... - P + To N + The doping gradient allows the electric field generated by the high voltage in the N-type drain region to gradually decrease along this gradient, thus avoiding the N-type drain region stress in semiconductor devices without a stress region. + Leakage area to N - The drift region forms the electric field peak.

[0083] Furthermore, in the embodiments of this application, the contact area of ​​the P-type substrate 10 only covers the upper surface of the stress region and has a limited lateral dimension. Therefore, its doping will not significantly damage the lattice integrity of the stress region, and thus has a minimal impact on the improvement of the device's electron mobility.

[0084] Optionally, the gate structure includes: a gate, a gate oxide layer, and sidewalls; Along the thickness direction of the substrate, the gate oxide layer and the gate electrode are sequentially formed on the substrate; along the direction perpendicular to the thickness of the substrate, the sidewalls are formed on both sides of the gate oxide layer 403 and the gate electrode.

[0085] The description here is the same as that in the first part, and will not be repeated here.

[0086] Optionally, the stress region is one of a silicon carbide stress region, a silicon-germanium stress region, and a polycrystalline silicon stress region. The substrate is a silicon substrate.

[0087] The description here is the same as that in the first part, and will not be repeated here.

[0088] Optionally, the stress zone includes a P-type body injection layer and a stress layer; The P-type body injection layer is located between the stress layer and the P-type well region.

[0089] In one alternative embodiment, the doping concentration of the P-type well region, the doping concentration of the P-type body implantation layer, and the doping concentration of the stress layer gradually increase along the thickness direction of the substrate 10.

[0090] In the embodiments of this application, the doping concentration of the P-type body implantation layer is greater than that of the P-type well region and less than that of the stress layer, so as to form a doping gradient from the P-type body implantation layer to the stress layer in the P-type well region.

[0091] Based on this, when a high voltage is applied to the drain region of the second doping type, the electric field will smoothly transition along the doping gradient, avoiding the formation of an electric field peak at the direct interface between the stress layer and the P-type well region. Therefore, the peak electric field at the drain end can be monitored, thereby improving the breakdown voltage of the device.

[0092] It should be understood that the lattice mismatch between the stress layer and the silicon substrate generates stress. If the stress layer directly contacts the P-type well region, dislocations (lattice defects) are easily generated at the interface due to abrupt stress changes, leading to increased carrier scattering and decreased mobility. The P-type bulk injection layer acts as a lattice buffer band. Its crystal structure is similar to that of the silicon substrate, allowing it to gradually release some of the stress from the stress layer and avoid lattice relaxation caused by stress concentration. Therefore, the P-type bulk injection layer reduces the dislocation density at the interface between the stress layer and the P-type well region, decreasing the probability of carrier scattering at the interface, and maintaining a long-term stable effect of the stress layer on improving mobility. Furthermore, the buffering effect of the P-type bulk injection layer reduces lattice defects in the stress layer, allowing stress to be transmitted more uniformly to the main current channel. For example, the tensile stress of the stress layer can be transferred to the channel region on the surface of the P-type well region through the bulk injection layer without being absorbed by interface defects.

[0093] Furthermore, since the P-type body implantation layer and the P-type well region are of the same doping type, they can be connected by a doping concentration gradient to form a low-resistance ohmic contact, thus avoiding an increase in parasitic resistance due to material differences.

[0094] The P-type body implantation layer can isolate impurities in the stress layer and the P-type well region, preventing impurity diffusion from causing lattice structure distortion in the stress layer. Furthermore, for different types of stress layers (SiC, SiGe, polycrystalline silicon), the interface characteristics of the P-type body implantation layer can be optimized by adjusting the doping concentration, eliminating the need to adjust the growth parameters of the stress layer to fit the P-type well region, thus improving process flexibility.

[0095] Thirdly, embodiments of this application also provide a method for fabricating a semiconductor device, the method comprising: Reference Figure 2 The first step is to provide a substrate 10.

[0096] In this embodiment of the application, the substrate 10 may be a silicon substrate 10, including a substrate 10 body and an epitaxial layer formed on the substrate 10 body.

[0097] The substrate 10 is the physical base of the device, used to support all upper structures and provide mechanical / electrical support. It can be a P-type silicon substrate 10 or an N-type silicon substrate 10.

[0098] For example, when the semiconductor device is an N-type laterally diffused metal-oxide-semiconductor device, the substrate 10 can be a P-type silicon substrate 10. When the semiconductor device is a P-type laterally diffused metal-oxide-semiconductor device, the substrate 10 can be an N-type silicon substrate 10.

[0099] In the embodiments of this application, the substrate 10 body provides physical support for the device, and is usually a doped region, which is used to reduce the substrate 10, ensure the discharge of parasitic current (such as lateral current in the substrate 10), and avoid potential fluctuations caused by excessive resistance of the substrate 10.

[0100] The epitaxial layer has the same conductivity as the substrate 10. It serves as the direct growth and fabrication carrier for all upper structures (such as stress region, well region, source / drain region, and gate 404). Its thickness and doping concentration directly determine the longitudinal breakdown voltage capability of the device and can be set according to actual needs.

[0101] The second step, refer to Figures 3-5 A stress region and a first doped type well region 30 are formed in the substrate 10 along a first side of the substrate. The stress region is located in the first doped type well region.

[0102] In this embodiment, both the stress region and the first doped type well region 30 are formed in the epitaxial layer of the substrate 10. The bottom of the first doped type well region 30 is in direct contact with the epitaxial layer, and the top extends to the surface of the substrate 10, forming a well-like structure that penetrates the epitaxial layer longitudinally. The stress region is embedded inside the first doped type well region 30, with its bottom in contact with the first doped type well region 30 and its top flush with the top of the first doped type well region 30.

[0103] The stress region can be formed by etching and selective epitaxy, and the first doped type well region 30 can be formed by ion doping.

[0104] Third step, refer to Figures 7-9 A gate structure is formed on the substrate 10.

[0105] Fourth step, along the first side 101 of the substrate 10, a second doped source region 50 is formed in the first doped type well region 30, and a second doped drain region 60 is formed in the stress region 20.

[0106] In this embodiment, the gate 404 can be formed by depositing gate 404 material on the substrate 10 and performing an etching process. The second doped source region 50 and the second doped drain region 60 can be formed by ion implantation into the substrate 10.

[0107] The first doped type well region 30 covers the bottom and sidewalls of the stress region, which is formed by growing a material that is lattice mismatched with the substrate 10.

[0108] The second doped type drain region 60 is formed in the stress region, and the first doped type well region 30 is formed in the second doped type source region 50; Along the thickness direction of the substrate 10, the gate structure covers the top of a portion of the stress region and a portion of the first doped type well region 30, and is connected to the second doped type drain region 60 and the second doped type source region 50.

[0109] In the embodiments of this application, the semiconductor device prepared as described above can be a lateral double-diffused metal-oxide semiconductor device, or any other semiconductor device adapted to the above structure. The embodiments of this application do not impose any special limitations on this.

[0110] Optionally, when the semiconductor device is an N-type lateral double-diffused metal-oxide-semiconductor device, the first doped type well region 30 is a P-type well region, the second doped type source region 50 and the second doped type drain region 60 can be N-type source regions and N-type drain regions. Based on this, the first doped type well region 30 forms a PN junction with the second doped type source region and the second doped type drain region, and a depletion layer is generated when reverse biased to withstand high voltage.

[0111] In this embodiment, the stress region is formed by growing a material that is compatible with the lattice of the substrate 10, and the bottom and sidewalls of the stress region are covered by a first doped type well region 30 to transfer the lattice stress of the stress region to the current channel, while limiting the lateral expansion of the stress region and avoiding interference to other regions.

[0112] In this embodiment, the source region and drain region of the second doping type are heavily doped regions. The drain region 60 of the second doping type is formed in the stress region to withstand high voltage, and the PN junction depletion layer formed with the well region 30 of the first doping type serves as the voltage-bearing region for the fabricated semiconductor device. The source region 50 of the second doping type is located on the other side of the well region 30 of the first doping type, and the PN junction formed with the well region 30 of the second doping type is grounded through a metal interconnect to fix the potential and suppress parasitic latch-up effects.

[0113] Along a direction perpendicular to the thickness of the substrate 10, the second doped drain region 60, the stress region, the first doped well region 30, and the second doped source region 50 are sequentially connected to form a complete lateral current path. Electrons start from the second doped source region 50, pass through the channel region on the surface of the first doped well region 30 to the stress region, and then pass to the second doped drain region 60.

[0114] Based on the above description, in this embodiment, a stress region is formed by growing a material whose lattice is compatible with that of the substrate 10. Therefore, the stress region can mismatch with the lattice of the substrate 10, generating lateral stress that can then regulate the transport of charge carriers in the semiconductor device. Specifically, when the stress material is epitaxially grown on the silicon substrate 10, tensile stress is applied to the surrounding drift regions due to lattice mismatch. When this tensile stress acts on the drift regions, it reduces the effective mass of electrons in the silicon lattice and decreases the probability of inter-valley scattering, thereby increasing electron mobility. Electron mobility determines the magnitude of the device current. Therefore, under the same gate voltage and device size, the stress region can increase the saturation current of the device, solving the technical problem of insufficient current capability under high voltage in traditional pure silicon devices.

[0115] In an optional embodiment, a stress region is formed on the substrate 10, and a first doped type well region 30 includes: First, refer to Figure 3 A stress groove 201 is formed in a first predetermined region of the substrate 10.

[0116] In this embodiment, the first predetermined region is laterally located in the first doped type well region 30 and close to the side of the subsequently formed second doped type drain region 60, so that the stress generated by the stress region can be concentrated on the current path between the source and drain regions. The first predetermined region is vertically located in the upper middle part of the epitaxial layer, and the top of the first predetermined region is flush with the top of the epitaxial layer. That is, the top of the first predetermined region does not cover the epitaxial layer, so as to ensure that the subsequently grown stress region can directly act on the main carrier transport path, such as the drift region of nLDMOS.

[0117] Optionally, the matching degree between the position of the stress groove 201 and the current density distribution can be determined first through simulation verification, and then the first predetermined area can be determined to ensure that the stress zone covers the area with the highest current density (usually the drift zone near the leakage area).

[0118] Optionally, the stress groove 201 can be formed through a three-step process of pattern definition, etching, and surface treatment.

[0119] The pattern definition is achieved by coating photoresist onto the surface of the epitaxial layer of substrate 10, exposing and developing it using a photomask, leaving a photoresist window (i.e., the etchable area of ​​the groove) in a first predetermined region, while other areas are protected by photoresist. The groove formation can be achieved using plasma dry etching (such as reactive ion etching), employing a gas that reacts with silicon (the epitaxial layer material), removing the epitaxial layer material within the photoresist window through a combination of ion bombardment and chemical reaction. Surface treatment involves wet cleaning after etching to remove residual etching polymers, followed by short-term thermal oxidation to form a thin oxide layer, repairing lattice damage caused by etching.

[0120] Then, refer to Figure 4 Ion implantation of the first doping type is performed on the stress groove 201 along the opening direction of the stress groove 201 to form a first doping type body implantation layer 202.

[0121] It is worth noting that the first doped type body implantation layer 202 formed must completely cover the inner surface (bottom + two side walls) of the stress groove 201 and extend a short section to the surface of the substrate 10 outside the groove opening to ensure seamless connection with the subsequently formed first doped type well region 30.

[0122] Optionally, when the first doping type is P-type, P-type ions can be used during ion implantation, such as boron (B). + When the first doping type is N-type, N-type ions can be used during ion implantation.

[0123] The ion implantation energy can be selected as low or medium energy to ensure shallow implantation depth, forming only a thin layer of doping on the surface of the groove, and avoiding penetration into the substrate 10 body.

[0124] The dosage of ion implantation needs to ensure that the doping concentration of the first doped type implantation layer is between the subsequent stress layer 203 and the first doped type well region 30, forming a smooth concentration gradient from the first doped type well region 30 to the first doped type body implantation layer 202 and the stress layer 203.

[0125] It should be understood that although the inner surface of the stress groove 201 has undergone surface treatment, it still has slight lattice distortion. The stress layer 203 has a high lattice mismatch rate with the silicon substrate 10, and direct growth easily leads to high-density dislocations at the interface. However, the lattice structure of the first-doped bulk injection layer 202 is consistent with the silicon substrate 10, and the doped atoms can fill the dangling bonds on the groove surface, reducing the dangling bond density at the interface. As a transitional lattice layer, the first-doped bulk injection layer 202 can gradually adapt to the lattice differences between the stress layer 203 and silicon, reducing the dislocation density during the growth of the stress layer 203 and ensuring that stress can be efficiently transferred to the current channel. Furthermore, the first-doped bulk injection layer 202 and the first-doped well region 30 both belong to the first-doped silicon type, and can form a low-resistance ohmic contact through a concentration gradient, thereby reducing leakage current.

[0126] Secondly, refer to Figure 5 The stress groove 201 is filled with stress material to form a stress layer 203.

[0127] Optionally, a material layer with specific lattice stress, such as SiC, SiGe, or polycrystalline silicon, can be formed within the stress groove 201 using techniques such as selective epitaxial growth. The selective epitaxial growth process ensures that the stress layer 203 grows only within the stress groove 201, preventing the stress layer 203 from covering the surface of the substrate 10 outside the groove.

[0128] For example, SiC can be chosen as the stress material for n-type devices (such as nLDMOS). The difference in lattice constant between SiC and silicon generates tensile stress, which can reduce the effective mass of electrons, decrease the scattering probability, and increase electron mobility.

[0129] For p-type devices (such as pLDMOS), SiGe can be selected as the stress material. Ge has a higher lattice constant than Si, and introducing compressive stress can improve hole mobility and optimize the conductivity of the p-type channel.

[0130] Finally, refer to Figure 6 Along the first side 101 of the substrate 10, the second predetermined region of the substrate 10 is subjected to ion doping of the first doping type to form a first doping type well region 30; wherein, the first side of the substrate 10 is the side where the stress region 20 is located.

[0131] The second predetermined region can be the region on the first side of the substrate 10 other than the second predetermined region.

[0132] In this embodiment, the first doped type well region 30 formed needs to cover the region in the epitaxial layer other than the stress region.

[0133] Specifically, the formation of the first doped type well region 30 in the second predetermined region includes selective doping through processes such as mask definition, directional doping, and annealing diffusion to ensure that doping only occurs in the target region.

[0134] The mask definition is used to coat photoresist on the first side surface of the substrate 10, expose and develop it through the photomask, and open the photoresist window only in the second predetermined area.

[0135] In directional doping, the ion beam implanted by ion implantation is perpendicular to the first side surface of the substrate 10, ensuring that the doped atoms can diffuse into the depth direction of the substrate 10, forming a sufficiently thick well region and covering the bottom of the stress region.

[0136] Annealing diffusion is used to optimize the doping distribution and boundaries within the first doping type well region 30.

[0137] Optionally, forming the gate structure on the substrate 10 includes the following steps: First step, refer to Figure 7 Along the first side of the substrate 10, a gate oxide material layer 401 and a gate material layer 402 are sequentially formed on the substrate 10.

[0138] In this embodiment of the application, a gate oxide material layer 401 and a gate material layer 402 can be sequentially formed on the substrate 10 using a deposition process.

[0139] Among them, the gate oxide material layer 401 needs to have high insulation, good dielectric properties and compatibility with the substrate 10.

[0140] For example, in low-voltage devices, since the interface state density between silicon dioxide and silicon substrate 10 is low, the threshold voltage can be kept stable. Moreover, the oxidation process is mature and low-cost. Therefore, silicon dioxide can be used as the gate oxide material layer 401. In this case, a thermal oxidation method can be used to generate long silicon dioxide on the surface of substrate 10 to form the gate oxide material layer 401.

[0141] In high-voltage devices, a stacked structure of SiO2 and high-k material can be used as the gate oxide material layer 401. Since high-k material can provide a higher equivalent oxide layer thickness at the same physical thickness, it can meet the insulation requirements under high voltage and avoid the gate capacitance reduction caused by simply thickening SiO2. In this case, a high-k material can be generated on the surface of the substrate 10 by using a pattern layer deposition method to form the gate oxide material layer 401.

[0142] The gate material layer 402 needs to form good contact with the gate oxide layer 403, and has low resistance, high temperature stability and compatibility with subsequent processes.

[0143] The gate material layer 402 can be selected from polysilicon or metal gate 404. Polysilicon can be doped to achieve low resistance and good interface compatibility with SiO2, and the pattern can be precisely defined by photolithography. Metal gate 404 (such as TiN, W) is suitable for high-frequency, high-performance devices, has lower resistance, and can suppress the depletion layer effect of polysilicon, thereby avoiding changes in gate capacitance with voltage and reducing the switching loss of the device at high frequencies.

[0144] When polysilicon is selected as the gate material layer 402, a chemical vapor deposition process can be used to form the gate material layer 402 on the gate oxide material layer 401.

[0145] When the gate material layer 402 is selected as the metal gate 404 material, the gate material layer 402 can be formed on the gate oxide material layer 401 using a physical vapor deposition process.

[0146] Based on the above description, a gate oxide material layer 401 and a gate material layer 402 are sequentially formed on the substrate 10.

[0147] The second step, refer to Figure 8 The gate oxide material layer 401 and the gate material layer 402 are subjected to a first patterning process to obtain a gate oxide layer 403 and a gate 404; wherein, along the thickness direction of the substrate 10, the gate oxide layer 403 is connected to a portion of the stress region.

[0148] In this embodiment of the application, performing a first patterning process on the gate oxide material layer 401 and the gate material layer 402 to form the gate oxide layer 403 and the gate 404 is to process a continuous thin film into a functionalized electrode structure.

[0149] The first patterning process may include photolithography, etching, and surface repair.

[0150] Photolithography involves coating the surface of the gate material layer 402 with photoresist, exposing it through a photomask, and then developing it to form a pattern on the photoresist that matches the target gate 404.

[0151] Etching is a step-by-step etching process that uses photoresist as a mask and first etches the gate material layer 402, then etches the gate oxide material layer 401.

[0152] Optionally, for the polysilicon gate material layer 402, CF4 / O2 plasma etching can be used to control the etching depth to the surface of the gate oxide material layer 401 to avoid damaging the gate oxide layer 403; for the metal gate material layer 402, Cl2-based plasma is used to ensure that the top of the gate 404 is flat after etching.

[0153] For etching the gate oxide layer 401, HF-based plasma can be used to etch to the surface of the substrate 10 (the surface of the first doped type well region 30 or the stress region) to form a gate oxide layer 403 that is the same shape as the gate 404.

[0154] Surface repair is used to eliminate etching damage and can be achieved through wet cleaning and low-temperature annealing.

[0155] In the embodiments of this application, the length of the gate 404, i.e. the lateral dimension of the gate 404, determines the channel length of the device and can be designed according to the device speed requirements.

[0156] The source edge of the obtained gate 404 (on the side closer to the second-doped source region 50) is spaced a certain distance from the predetermined position of the source region, which is used to form the sidewall 405 later. The drain edge (on the side farther from the second-doped source region 50) covers part of the stress region. Specifically, the side of the gate 404 closest to the second-doped drain region 60 needs to cover the stress region to ensure that the gate oxide layer 403 can form a connection with the stress region in the longitudinal (thickness direction).

[0157] In this embodiment, the top surface of the stress region is flush with (or slightly lower by 0.1 μm) the surface of the first conductivity type well region. The gate oxide layer 403 covers the surface of the well region and part of the surface of the stress region, so that the stress generated in the stress region can be transmitted through the silicon lattice (channel region) under the gate oxide layer 403, ensuring that the channel carriers can feel the lattice effect of the stress region.

[0158] Third step, refer to Figure 9 Sidewalls 405 are formed on both sides of the gate oxide layer 403 and the gate 404 along a direction perpendicular to the thickness of the substrate 10.

[0159] Among them, the sidewall 405, as an insulating isolation structure, can provide a self-aligned mask for subsequent source and drain region injection by controlling its width and morphology, while optimizing the electric field distribution at the edge of the gate 404.

[0160] The specific steps for forming the sidewall 405 can be any suitable process of the prior art, and the embodiments of this application do not impose any special limitations on this.

[0161] The resulting sidewall 405 needs to be tightly fitted to the sidewall of the gate 404 to prevent impurities from seeping into the gate oxide layer 403 through the gap, thus ensuring the stability of the breakdown voltage of the gate oxide layer 403. Furthermore, the width of the sidewall 405 needs to match the implantation depth of the source / drain regions to prevent short circuits between the source / drain regions and the gate 404 after diffusion.

[0162] Reference Figure 10The formation of a second doped source region in the first doped type well region 30 along the first side 101 of the substrate 10 and the formation of a second doped drain region in the stress region include: performing second doped type ion implantation in a third predetermined region of the stress region along the first side 101 of the substrate 10 to obtain a second doped drain region 60, and performing second doped type ion implantation in a fourth predetermined region of the first doped type well region 30 to obtain a second doped source region 50.

[0163] The third predetermined region is located on the side of the stress region away from the source region and needs to cover the adjacent portion of the stress region and the first doped type substrate contact region 70. This ensures that the subsequently formed second doped type drain region 60 can simultaneously form an electrical connection with both the stress region and the first conductive type substrate 10 contact region, thus collecting charge carriers and withstanding high voltage through the PN junction. It is worth noting that if the depth of the third predetermined region is too shallow, the contact resistance between the drain region and the stress region will be too high; if it is too deep, it may break down the substrate 10. Therefore, the vertical depth of the third predetermined region needs to penetrate the stress layer 203 and extend to the underlying first doped type bulk injection layer 202, but not penetrate to the substrate 10 body.

[0164] The fourth predetermined region (source injection region) is located in the first doped type well region 30 near the source end of the gate 404 and must be enclosed by the first doped type well region 30 to ensure that the formed second conductivity type source region and the first conductivity type well region form a clear PN junction. At the same time, it is close to the channel region of the gate 404 to facilitate carrier injection into the channel. The lateral width of the fourth predetermined region matches the source metal contact area, and the vertical depth is shallower than the second doped type drain region 60. The shallow depth can reduce the parasitic capacitance between the source region and the substrate 10, and at the same time avoid short circuit with the substrate 10 body at the bottom of the first doped type well region 30.

[0165] In this embodiment, both the source and drain regions are heavily doped with the second doping type. However, due to the different material properties of the implanted regions, the implantation parameters can be set differently according to the actual situation, and self-aligned implantation can be achieved using the sidewall 405. For example, the dopant ion in the second doping type source region 50 can be phosphorus (P... + ) or arsenic (As + The injection energy is 10~50keV, and the injection dose is 10. 19 ~10 20 cm -2 The annealing activation conditions are 900~1000℃ for 30 minutes. For example, the dopant ion in the drain region 60 of the second doping type can be phosphorus (P... + ) or antimony (Sb + The injection energy is 50~150keV, and the injection dose is 10¹ 9 ~10² 0 cm -2The annealing activation conditions are 950~1050℃ for 60 minutes.

[0166] In this embodiment, the obtained second doped source region 50 is located on the surface of the first doped well region 30 in the longitudinal direction and does not penetrate the well region (to avoid short-circuiting with the substrate 10 body); in the lateral direction, it is adjacent to the gate sidewall 405 on one side and wrapped by the well region on the other side, and the top is exposed to the surface of the substrate 10 (a metal contact will be made later), forming a PN junction with the first doped well region 30.

[0167] The resulting second-doped drain region 60 is located longitudinally within the stress layer 203 but does not penetrate the bulk implantation layer to avoid short-circuiting with the well region. Laterally, it is adjacent to the contact region of the first conductivity type substrate 10 on one side and connected to the stress region on the other side. Its top is exposed on the surface of the substrate 10, forming an N-type doped region with the stress region. + -N - The ohmic contact (isotype doped, low resistance) forms a reverse PN junction with the first doped type substrate contact region 70.

[0168] Based on the above description, the self-alignment function of the sidewall 405 in this embodiment of the application is used to ensure the spacing between the source / drain region and the gate 404, so as to avoid gate-source / gate-drain short circuit caused by too small a spacing, or channel resistance increase caused by too large a spacing.

[0169] Furthermore, after the second conductivity type drain region is injected into the stress region, N is formed. + To N - Gradient doping allows the electric field in the drain region to extend gradually towards the stress region, avoiding electric field concentration.

[0170] After the source region of the second conductivity type is injected into the well region of the first conductivity type, the well region of the first conductivity type and the source region of the second conductivity type form a PN junction for isolation, ensuring that the source region of the second conductivity type only provides carriers to the channel and does not leak current to the substrate 10, thereby reducing the leakage current between the source and drain.

[0171] In an optional implementation, the method for fabricating the semiconductor device provided in this application further includes: Ion implantation of a first doping type is performed on a fourth predetermined region of the stress region along the first side of the substrate 10 to form a first doping type substrate contact region 70.

[0172] In this context, along a direction perpendicular to the thickness of the substrate 10, the first doped substrate contact region 70 is connected to the side of the second doped drain region 60 that is away from the stress region.

[0173] In this embodiment, the fourth predetermined region is a specific region in the stress region used to form the first doped type substrate contact region 70, and its range must strictly match the electrical connection requirements between the location of the second doped type drain region 60 and the substrate 10.

[0174] Specifically, the fourth predetermined region is located laterally on the side of the second doped type drain region 60 in the stress region away from the stress region, and is directly adjacent to the drain region to ensure the formation of a continuous PN junction interface. The longitudinal direction is located in the stress region and does not penetrate the stress region.

[0175] Based on the above description, the first doped substrate contact region 70 is located on the upper surface of the stress region and is connected to the stress region on one side. It can be directly connected to a low potential through metal interconnection. It and the first doped well region 30 are respectively connected to the upper and lower sides of the stress region, anchoring the potential of the stress region to a low potential and avoiding potential drift caused by charge accumulation in the stress region.

[0176] Furthermore, along the direction perpendicular to the thickness of the substrate 10, stress regions, first conductivity type substrate 10 contact regions, and second conductivity type drain regions are formed, forming N... - P + To N + The doping gradient allows the electric field generated by the high voltage in the drain region to gradually decrease along this gradient, avoiding the N-type doping problem in semiconductor devices without stress regions. + Leakage area to N - The drift region forms the electric field peak.

[0177] Furthermore, in the embodiments of this application, the first conductivity type substrate contact area only covers the upper surface of the stress region and has a limited lateral dimension. Therefore, its doping will not significantly damage the lattice integrity of the stress region, and thus has minimal impact on the improvement of the device's electron mobility.

[0178] Fourthly, this application provides a chip comprising the semiconductor device described in the first aspect, or the N-type lateral double-diffused metal-oxide-semiconductor device described in the second aspect.

[0179] In this embodiment, the chip integrates the aforementioned semiconductor devices, or N-type lateral double-diffused metal-oxide-semiconductor devices, or supporting auxiliary circuits to achieve specific electrical functions according to the application scenario. For example, it can utilize the low-loss switching characteristics of semiconductor devices to construct a high-voltage power path, adapt to new energy and industrial power control scenarios through the high withstand voltage and high-efficiency carrier transport capabilities of N-type lateral double-diffused metal-oxide-semiconductor devices, or ensure the stable operation of power devices by leveraging the driving and protection functions of supporting auxiliary circuits. This not only ensures the applicability of the chip in different power fields, but also improves the overall system reliability and energy conversion efficiency through the synergistic effect of the characteristics of devices and circuits.

[0180] Fifthly, this application provides an electronic device including the chip described in the fourth aspect.

[0181] In this embodiment of the application, the electronic device, by integrating the chip described in the fourth aspect, can realize specific core functions according to its own application scenario: for example, in new energy vehicles, the high-voltage power control capability of the chip enables efficient energy conversion of the on-board charger and precise current regulation of the motor drive; in industrial inverter equipment, the high voltage resistance and low loss characteristics of the chip ensure the stable operation of the servo motor and efficient grid connection of photovoltaic energy; in 5G base station power supply equipment, the high-frequency switching and temperature compensation capability of the chip enables low standby power consumption and reliable output over a wide temperature range for base station power supply. Based on this, the functional adaptability of the electronic device in different fields is ensured, and the high integration and high reliability of the chip can simplify the overall circuit design of the electronic device, reduce its size, and improve long-term operational stability.

[0182] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0183] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a first-doped-type well region formed in the substrate along a first side of the substrate, a stress region and a second-doped-type source region formed in the first-doped-type well region, and a second-doped-type drain region formed in the stress region; and a gate structure formed on the substrate along the first side of the substrate; wherein the stress region is formed by growing a material that is lattice-mismatched with the substrate material, the gate structure covers a top portion of part of the stress region and part of the first-doped-type well region along a thickness direction of the substrate, and is connected with the second-doped-type drain region and the second-doped-type source region.

2. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a first-doped-type substrate contact region formed in the stress region; the first-doped-type substrate contact region is connected with a side of the second-doped-type drain region that is away from the second-doped-type source region along a direction perpendicular to the thickness of the substrate.

3. The semiconductor device of claim 1, wherein The gate structure comprises a gate, a gate oxide layer, and a sidewall; the gate oxide layer and the gate are sequentially formed on the substrate along the thickness direction of the substrate; the sidewall is formed on both sides of the gate oxide layer and the gate along a direction perpendicular to the thickness of the substrate.

4. The semiconductor device according to any one of claims 1 to 3, wherein The stress region comprises one of a silicon carbide stress region, a silicon germanium stress region, and a polysilicon stress region; The substrate is a silicon substrate.

5. The semiconductor device according to any one of claims 1 to 3, wherein The stress region comprises a first-doped-type body implant layer and a stress layer; The first-doped-type body implant layer is between the stress layer and the first-doped-type well region.

6. The semiconductor device according to claim 5, wherein The doping concentration of the first-doped-type well region, the doping concentration of the first-doped-type body implant layer, and the doping concentration of the stress layer gradually increase along the thickness direction of the substrate.

7. An N-type lateral double diffused metal oxide semiconductor device, characterized by, The semiconductor device comprises: a substrate; a P-type well region formed in the substrate along a first side of the substrate, a stress region and an N-type source region formed in the P-type well region, and an N-type drain region formed in the stress region; and a gate structure formed on the substrate along the first side of the substrate; wherein the stress region is formed by growing a material that is lattice-mismatched with the substrate material; the gate structure covers a top portion of part of the stress region and part of the N-type well region along a thickness direction of the substrate, and is connected with the P-type drain region and the P-type source region.

8. The semiconductor device of claim 7, wherein, The semiconductor device further comprises a P-type substrate contact region formed in the stress region; the P-type substrate contact region is connected with a side of the N-type drain region that is away from the N-type source region along a direction perpendicular to the thickness of the substrate.

9. A method of manufacturing a semiconductor device, characterized by, The preparation method comprises: providing a substrate; forming a stress region and a first-doped-type well region in the substrate along a first side of the substrate; wherein the stress region is in the first-doped-type well region; forming a gate structure on the substrate; forming a second-doped-type source region in the first-doped-type well region and a second-doped-type drain region in the stress region along the first side of the substrate; The stress region is formed by growing a material which is lattice mismatched with the substrate material; the gate structure covers part of the stress region and part of the top of the first-doped-type well region along the thickness direction of the substrate, and is connected with the second-doped-type drain region and the second-doped-type source region.

10. The method of producing a semiconductor device according to Claim 9, wherein The stress region is formed in the substrate, and the first-doped-type well region comprises: A stress groove is formed in the first predetermined region of the substrate; The stress groove is subjected to ion implantation of the first-doped-type along the opening direction of the stress groove to form a first-doped-type body implantation layer; The stress groove is filled with a stress material to form a stress layer; The second predetermined region of the substrate is subjected to ion implantation of the first-doped-type along the first side of the substrate to form a first-doped-type well region; wherein the first side of the substrate is the side where the stress region is located.

11. The method of producing a semiconductor device according to Claim 9, wherein The gate structure formed on the substrate comprises: The gate oxide material layer and the gate material layer are formed on the substrate along the first side of the substrate in sequence; The gate oxide material layer and the gate material layer are subjected to first patterning processing to obtain a gate oxide layer and a gate; wherein the gate oxide layer is connected with part of the stress region along the thickness direction of the substrate; The side walls are formed on both sides of the gate oxide layer and the gate along the direction perpendicular to the thickness of the substrate.

12. The method of producing a semiconductor device according to Claim 11, wherein The second-doped-type source region is formed in the first-doped-type well region along the first side of the substrate, and the second-doped-type drain region is formed in the stress region comprises: The third predetermined region of the stress region is subjected to ion implantation of the second-doped-type along the first side of the substrate to obtain a second-doped-type drain region, and the fourth predetermined region of the first-doped-type well region is subjected to ion implantation of the second-doped-type to obtain a second-doped-type source region.

13. The method of claim 11, wherein, The method further comprises: The fourth predetermined region of the stress region is subjected to ion implantation of the first-doped-type along the first side of the substrate to form a first-doped-type substrate contact region; Wherein the first-doped-type substrate contact region is connected with the side of the second-doped-type drain region which is away from the stress region along the direction perpendicular to the thickness of the substrate.

14. A chip, characterized by The semiconductor device of any one of claims 1-6, or the N-type lateral double-diffusion metal-oxide semiconductor device of claim 7 or 8.

15. An electronic device, comprising: The chip of claim 14.

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