Data hierarchy scheduling method and system, storage medium and equipment

Abstract

The invention provides a data hierarchy scheduling method and system, a storage medium and equipment, and relates to the field of data processing, and the method comprises the steps: obtaining a sparse matrix in a row compression storage format; performing matrix segmentation on the sparse matrix to obtain segmented small matrixes; calling a vector access unit to package and access paired indexes in the sparse matrix, storing row data to be updated into an on-chip local memory, and storing a non-zero element column index of the sparse matrix corresponding to each row of the L matrix and a corresponding numerical value into a storage space of each thread in the on-chip local memory; global threads are grouped to obtain a plurality of thread blocks, and thread indexes of the thread blocks are stored in an atomic cache; and in the atomic cache, the segmented small matrixes are correspondingly processed by using the thread blocks. The parallel computing capability of the multi-core processor can be fully utilized, the memory delay is reduced, and the data access efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data processing, in particular to a data level scheduling method and system, a storage medium and an equipment. BACKGROUND

[0002] IC decomposition algorithm is an incomplete Cholesky decomposition, which is a numerical method for approximately solving linear equations, and is suitable for symmetric positive definite matrix. Due to its inherent strong data dependency and irregular computing and memory access mode, it is difficult to achieve good performance optimization on many-core processors based on SIMD (Single Instruction Multiple Data) and SIMT (Single Instruction Multiple Threads) architecture. SUMMARY

[0003] The purpose of the present application is to provide a data level scheduling method, system, computer readable storage medium and electronic equipment, which can accelerate IC numerical decomposition, improve data reuse access efficiency and reduce memory access delay.

[0004] To solve the above technical problems, the present application provides a data level scheduling method, and the specific technical solutions are as follows:

[0005] Obtain a sparse matrix in row compressed storage format;

[0006] Perform matrix partitioning on the sparse matrix to obtain a small partitioned matrix;

[0007] Call the vector memory unit to pack and read the pair of indexes in the sparse matrix, store the to-be-updated row data into the on-chip local memory, and store the non-zero element column index and corresponding value of each row of the L matrix of the sparse matrix into the storage space of each thread in the on-chip local memory;

[0008] Group the global threads to obtain a plurality of thread blocks, and store the thread index of the thread block into an atomic cache;

[0009] In the atomic cache, each thread block corresponding to the thread block processes the small partitioned matrix.

[0010] Optionally, before calling the vector memory unit to pack and read the pair of indexes in the sparse matrix, the method further comprises:

[0011] Perform breadth-first search traversal on the lower triangular matrix in the sparse matrix to obtain a directed acyclic graph;

[0012] Aggregating the matrix rows in the directed acyclic graph that are independent of each other into independent levels.

[0013] Optionally, the calling the vector memory access unit to pack data in the pair of indexes in the sparse matrix comprises:

[0014] Reading row data of an integer type and a starting index of a corresponding row in the directed acyclic graph;

[0015] Packing the row data and the starting index in a data pair in a composite data type.

[0016] Optionally, the packing the row data and the starting index in a data pair in a composite data type comprises:

[0017] Transmitting an index value of the row data packed in a composite data type and obtaining a row pointer of the row data by a vector load pointer of the vector load unit; the row pointer is used to perform a memory access operation on the row data.

[0018] Optionally, the grouping the global threads into a plurality of thread blocks, storing a thread index of the thread block into an atomic cache, and performing dynamic scheduling of the threads by using the atomic cache comprises:

[0019] Enabling a global shared array of the thread block as a global thread;

[0020] Blocking the global threads to obtain a plurality of thread blocks;

[0021] Storing a thread ID of the thread block into an atomic cache;

[0022] In the atomic cache, using an atomic operation function to increment the thread ID corresponding to the thread block to adjust the calling frequency of different load threads.

[0023] Optionally, the matrix partitioning of the sparse matrix to obtain a partitioned small matrix comprises:

[0024] Calling a graph partitioning function to perform graph partitioning on the sparse matrix to obtain a plurality of sub-matrices.

[0025] Optionally, after the calling the graph partitioning function to perform graph partitioning on the sparse matrix to obtain a plurality of sub-matrices, further comprising:

[0026] Allocating each of the sub-matrices to a corresponding processing unit to perform task processing; the process of allocating each of the sub-matrices to a corresponding processing unit to perform task processing comprises:

[0027] Screening a thread block corresponding to the sub-matrix and determining a thread range corresponding to the thread block;

[0028] In the corresponding thread range, a hierarchy of thread blocks and corresponding rows are determined; the hierarchy is used to indicate access to global threads, and the rows are used to locate row information;

[0029] In the thread block, the atomic cache is used to schedule a thread that has completed a current task to perform a task corresponding to a thread that has not completed a previous task.

[0030] The application also provides a data hierarchy scheduling system, comprising:

[0031] A matrix acquisition module is configured to acquire a sparse matrix in a row compressed storage format.

[0032] A matrix segmentation module is configured to perform matrix segmentation on the sparse matrix to obtain a segmented small matrix.

[0033] A data acquisition module is configured to call a vector memory unit to pack and acquire pairs of indexes in the sparse matrix, store to-be-updated row data into an on-chip local memory, and store non-zero element column indexes and corresponding values of each row of the L matrix corresponding to the sparse matrix into a storage space of each thread in the on-chip local memory.

[0034] A thread grouping module is configured to group global threads to obtain a plurality of thread blocks, and store thread indexes of the thread blocks into an atomic cache.

[0035] A task calculation module is configured to group global threads to obtain a plurality of thread blocks, and store thread indexes of the thread blocks into an atomic cache.

[0036] The application also provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the data hierarchy scheduling method described above.

[0037] The application also provides an electronic device comprising a memory and a processor, wherein the memory has a computer program stored therein, and the processor, when calling the computer program in the memory, implements the steps of the data hierarchy scheduling method described above.

[0038] The application provides a data hierarchy scheduling method, comprising: acquiring a sparse matrix in a row compressed storage format; performing matrix segmentation on the sparse matrix to obtain a segmented small matrix; calling a vector memory unit to pack and acquire pairs of indexes in the sparse matrix, store to-be-updated row data into an on-chip local memory, and store non-zero element column indexes and corresponding values of each row of the L matrix corresponding to the sparse matrix into a storage space of each thread in the on-chip local memory; grouping global threads to obtain a plurality of thread blocks, and store thread indexes of the thread blocks into an atomic cache; and using each of the thread blocks to process the segmented small matrix in the atomic cache.

[0039] The application adopts row compressed storage format (CSR) to store the sparse matrix, greatly reducing the occupation of storage space. The sparse matrix is divided into multiple small matrices by matrix partitioning and is allocated to different thread blocks for processing, fully utilizing the parallel computing capability of multi-core processors and significantly improving the computing speed. By calling the vector memory unit to pack the pair of indexes in the sparse matrix, and storing the to-be-updated row data and the column index and value of the non-zero element into the on-chip local memory, the access to the global memory is reduced, the memory delay is reduced, and the data access efficiency is improved. At the same time, by grouping the global threads into thread blocks and storing the thread index into the atomic cache, the thread scheduling and task allocation can be more efficiently managed, the conflicts between threads can be avoided, and the consistency and correctness of data can be ensured. By using the vector memory unit to pack the data and the on-chip local memory, the number of cache invalidations is further reduced, the data access locality is improved, the memory bandwidth pressure is reduced, and the overall performance of the system is improved. The application has good scalability and flexibility, and can dynamically adjust the number and size of thread blocks according to hardware resources, and is suitable for various scenarios that need to process large-scale sparse matrices.

[0040] The application also provides a data level scheduling system, a computer readable storage medium and an electronic device, which have the above beneficial effects, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute the embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0042] Figure 1 A flowchart of a data level scheduling method provided by an embodiment of the application;

[0043] Figure 2 A matrix partitioning schematic diagram provided by an embodiment of the application;

[0044] Figure 3 A node allocation process schematic diagram provided by an embodiment of the application;

[0045] Figure 4 A dynamic scheduling thread index process schematic diagram provided by an embodiment of the application;

[0046] Figure 5 A 16-8 thread grouping schematic diagram provided by an embodiment of the application;

[0047] Figure 6A data level scheduling system structure schematic diagram provided by an embodiment of the present application;

[0048] Figure 7 A structure diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0050] On the MIMD architecture, each processing unit has an independent program counter and control logic, can independently execute different instructions, process different data, realize task parallelism and data parallelism, and exhibits strong flexibility. The MIMD architecture has good applicability to irregular computing, good adaptability to the algorithm implementation of incomplete factor decomposition, and feasibility of performance optimization. The MIMD architecture does not need to frequently restart the kernel program when the parallel granularity changes, thereby effectively avoiding the additional overhead generated thereby. This feature is highly consistent with the dynamic change feature of parallelism in the IC decomposition process, and improves the application potential of related parallel algorithms on the MIMD many-core processor. Hierarchical scheduling is one of the main methods to realize the parallelization of incomplete factor decomposition, but has technical defects such as large memory access overhead and load imbalance.

[0051] To solve the above problems, refer to Figure 1 , Figure 1 A flowchart of a data level scheduling method provided by an embodiment of the present application, the method comprising:

[0052] S101: acquiring a sparse matrix in a row compressed storage format;

[0053] S102: performing matrix partitioning on the sparse matrix to obtain a small partitioned matrix;

[0054] S103: calling a vector memory access unit to pack and fetch paired indexes in the sparse matrix, storing to-be-updated row data into an on-chip local memory, and storing non-zero element column indexes and corresponding values of each row of the L matrix corresponding to the sparse matrix into a storage space of the on-chip local memory of each thread;

[0055] S104: grouping global threads to obtain a plurality of thread blocks, and storing thread indexes of the thread blocks into an atomic cache;

[0056] S105: In the atomic cache, each thread block corresponding to the processing of the segmented small matrix.

[0057] In step S101, a sparse matrix represented in compressed sparse row (CSR) format is obtained. This format stores the information of the sparse matrix through three arrays: one array stores the values of non-zero elements, one array stores the column indices of non-zero elements, and one array stores the starting position of each row. This storage method can effectively reduce the storage space occupation, and facilitate the row operation of the sparse matrix.

[0058] In step S102, the sparse matrix is segmented and divided into multiple small matrices. The segmentation method can be adjusted according to actual needs and hardware resources, for example, it can be segmented by row or column, or the matrix can be divided into multiple sub-blocks. Each small matrix after segmentation can be processed independently, thereby providing a basis for parallel computing.

[0059] In step S103, the vector memory unit is called to pack the pair of indexes in the sparse matrix. The pair of indexes refers to the row index and column index of the non-zero element in the sparse matrix. Through the way of packed data access, the efficiency of data access can be improved, and the number of memory access can be reduced. At the same time, the data of the row to be updated is stored in the on-chip local memory, which can reduce the access to the global memory and improve the data access speed. In addition, the non-zero element column index and corresponding value of each row of the L matrix (assuming it is the lower triangular matrix in LU decomposition) corresponding to the sparse matrix are also stored in the storage space of each thread in the on-chip local memory. The purpose of this is to enable each thread to quickly access the required data in subsequent calculations, reducing the overhead of data transmission.

[0060] In step S104, the global threads are grouped to obtain several thread blocks. The thread block is a basic unit in parallel computing, and each thread block contains a certain number of threads. The thread index of the thread block is stored in the atomic cache. The atomic cache can ensure the correctness and consistency of the thread index, avoiding the problem of data race and conflict in a multi-threaded environment.

[0061] In step S105, in the atomic cache, each thread block corresponding to the processing of the segmented small matrix. Each thread block independently processes a small matrix, which can fully utilize the parallel computing capability of the hardware and improve the speed of the entire sparse matrix processing. During the processing, the threads in the thread block can efficiently access the data in the on-chip local memory, thereby reducing the dependence on the global memory and further improving the computing efficiency.

[0062] This application aims to package and retrieve paired indices in a sparse matrix with compressed sparse row (CSR) storage format using vector memory access units, and store the data of the row to be updated in on-chip local memory; group global threads, store the relevant thread indices in atomic cache, and use the high performance of atomic cache for dynamic thread scheduling; and divide the matrix appropriately according to the number of different processing units used, and then form new small matrices to be distributed to different processing units for calculation.

[0063] This application utilizes a multi-core processor based on the MIMD architecture, such as the PEZY-SC3s many-core processor. The PEZY-SC3s processor employs a three-tier architecture design, integrating 512 Processing Elements (PEs) and supporting 4096 threads running concurrently. Its structure is as follows: it consists of two Prefectures, each Prefecture comprising 16 City nodes, each City containing four Village sub-units, and each Village integrating four PE processing units. Furthermore, each City integrates a Special Function Unit (SFU) for accelerating high-latency operations (such as division / modulo / square root). The PEZY-SC3s is equipped with a 32KB shared atomic operation cache, supporting full-thread spatial atomic instruction synchronization. Each PE has a dedicated 6KB L1 cache (4KB instruction cache + 2KB data cache) and 24KB of on-chip shared local memory (IPM), enabling fast data access and supporting rapid data exchange between the eight threads within the same PE. The amount of data in the shared local memory can be dynamically adjusted by the user through thread stack configuration. PEZY-SC3s supports a fully asynchronous MIMD execution mode, where each thread can independently access heterogeneous memory layers and execute differentiated instruction streams.

[0064] like Figure 2 As shown, Figure 2 This is a schematic diagram of matrix segmentation provided in an embodiment of this application. Since the lower triangular matrix of the original sparse matrix contains the dependencies between rows during incomplete decomposition, the hierarchical scheduling method achieves dependency hierarchical classification through the symbolic analysis stage: First, a breadth-first search (BFS) traversal is performed on the lower triangular matrix to obtain a directed acyclic graph (DAG) representing the data dependencies between rows. Then, the independent matrix rows in the DAG are aggregated into independent levels. Figure 2As shown, the edge k→i in the figure represents the calculation dependence of the ith row on the kth row, row 0 has dependence on row 4 and row 5, row 4 has dependence on row 7, row 5 has dependence on row 8, and so on to obtain the dependence relationship between the matrix rows. The directed arrow of each node in Level1-Level4 represents the dependence relationship between the matrix rows, and the row nodes in the same level have no dependence and can be calculated independently, such as rows 0, 1, 3, and 6 in Level1, which can be calculated in parallel because there are no interconnection edges. The entire calculation needs to be traversed layer by layer in order, and the row nodes in the same level have no data dependence and can be calculated in parallel.

[0065] First, the row-compressed sparse matrix is packed using vectorized memory access. IC decomposition row update often needs to access two elements, such as int type rowptr[i] and rowptr[i+1], where i represents a row, and rowptr[i] represents the starting index of a row. The packed transmission of index values is realized by a composite data type (int2). The 128-bit vector load instruction of the vector load unit is used to obtain the row pointer (int), so that the efficiency of single memory access operation is improved to twice that of the traditional scalar mode.

[0066] Then, a row of elements is stored in the on-chip local memory, and when the row elements are used, they are loaded from the on-chip local memory to the register. IC decomposition repeatedly uses the data of the row to be updated when updating, and the non-zero element column index and value of each row of the L matrix are stored in the on-chip local memory allocated to each thread in advance. Subsequent access and update of these non-zero elements only need to be performed in the on-chip local memory, improving the efficiency of data acquisition by a single thread.

[0067] A global shared array of thread blocks can be opened in advance, and the threads are blocked to obtain thread blocks. After thread blocking, the thread ID in the linear block is stored in the atomic cache, and the atomic operation function is used to increment the thread ID in the block, so that the threads with high calculation load are called less frequently, and the threads with low calculation load are called more frequently.

[0068] The application adopts row compression storage format to store the sparse matrix, greatly reducing the occupation of storage space. The sparse matrix is divided into multiple small matrices by matrix partitioning and is allocated to different thread blocks for processing, fully utilizing the parallel computing capability of multi-core processors and significantly improving the computing speed. By calling the vector memory unit, the pair of indexes in the sparse matrix is packed and read, and the to-be-updated row data and the column index and value of the non-zero element are stored in the on-chip local memory, reducing the access to the global memory, reducing the memory delay, and improving the data access efficiency. At the same time, by grouping the global threads into thread blocks and storing the thread index in the atomic cache, the thread scheduling and task allocation can be more efficiently managed, conflicts between threads can be avoided, and the consistency and correctness of data can be ensured. By using the vector memory unit to pack and read data and the on-chip local memory, the number of cache invalidations is further reduced, the data access locality is improved, the memory bandwidth pressure is reduced, and the overall performance of the system is improved. The application has good scalability and flexibility, and can dynamically adjust the number and size of thread blocks according to hardware resources, and is suitable for various scenarios that need to process large-scale sparse matrices

[0069] The partitioning process of the sparse matrix is further described below:

[0070] The update operation of each row in the IC decomposition process is abstracted as a task node, and the algorithm uses edge-based partitioning as the initial partitioning strategy in the partitioning stage, calls a graph partitioning function to perform graph partitioning on the sparse matrix, and obtains a plurality of sub-matrices. At this time, no limitation is made on which graph partitioning function is used, for example, the METIS_PartGraphKway function of the METIS library can be used to perform k-way graph partitioning to divide the matrix into nparts sub-matrices, that is, the rows of the sparse matrix are divided into nparts blocks according to the level, and are allocated to different processing cores.

[0071] Specifically, a complete implementation process of the application can include the following steps:

[0072] Step 1. After obtaining the sparse matrix, the sparse matrix is partitioned to obtain a partitioned small matrix. This embodiment takes the example of dividing the matrix into nparts=16 regions to obtain a level boundary pointer array p_levelptr, a row ID mapping array p_rowpid, a level pointer partition offset array levelptr_off, and a row ID partition offset array rowpid_off.

[0073] Taking nparts=2 and nparts=3 as examples, Figure 3 shows the use of graph partitioning to allocate different computing nodes to 2 or 3 processing units. As Figure 3As shown, the task load required for each processing unit before using graph partitioning is not the same, and after using graph partitioning, the number of task loads of the processing units is relatively small. When nparts = 2, the original matrix is divided into 2 parts, each part contains the same number of row nodes, when nparts = 3, the original matrix is divided into 3 parts, each part contains approximately equal row nodes, thereby ensuring that the workloads of the processing units are substantially equivalent.

[0074] Step 2. Get process ID (pid) and thread ID (tid), calculate global ID (gid) and total work thread size (GLOBAL_WORK_SIZE).

[0075] Step 3. Control the number of threads to 128, and the number of groups to nparts.

[0076] Step 4. Initialize the array:

[0077] Lpointer: Row pointer array (similar to row compression format row_ptr), recording the start and end positions of each row of non-zero elements.

[0078] Lindices: Column index array (similar to row compression format col_ind), recording the column number of non-zero elements.

[0079] Ldata: Non-zero element value array.

[0080] currow: The current processed row number.

[0081] Ldata_up: Updated non-zero element value array, storing the calculated L matrix.

[0082] Step 5. Filter the partition, for different partitions p, each partition corresponds to a dedicated thread range.

[0083] Step 6. Get the level and corresponding row of different partitions, levelptr_off represents the level pointer offset array of each partition, used to access the global level index; rowpid_off represents the row ID offset array of each partition, used to locate the specific row ID.

[0084] Step 7. Calculate the index within the thread block, divide the threads within the partition into blocks of 8 threads, so that each group of blockIdx starts from 0, and each group of threadINblock ranges from 0-8.

[0085] Step 8. Traverse the level of the current partition. p_levelptr represents the global level boundary pointer array, and the level size p_lev_size of different partitions is calculated.

[0086] Step 9. Use atomic operation to dynamically schedule thread index. See Figure 4 , Figure 4 The dynamic scheduling thread index process provided by the embodiments of the present application is shown in Figure 4 (a), which is an unoptimized thread scheduling. Assuming that the number of threads is 5, after the first round of 0-4 thread calculation, the next round of 0-4 thread calculation is performed, and the calculation amount of thread 2 is the largest in the whole process, followed by thread 0, but threads 1, 3, and 4 finish the calculation early and are in an idle state, and the calculation time is determined by the thread 2 time. Figure 4 (b) is an atomic scheduling optimized thread scheduling diagram, which shows the effect of using atomic cache to optimize thread load imbalance. In the original first round of 0-4 thread calculation, the calculation amount of thread 1 is the smallest, which will be finished first, at this time, through dynamic scheduling, thread 1 is made to do the work of thread 0 in the original static scheduling, instead of being in an idle state. After thread 3 is finished, dynamic scheduling makes it do the work of thread 2 in the original static scheduling, and so on. After all the tasks are calculated, the entire calculation time is determined by the time of thread 4, and the time difference after the calculation of threads 0-4 is reduced. Therefore, through the dynamic scheduling method, the idle time of threads caused by different calculation amounts can be reduced, and the load balance among threads can be better achieved, as shown in the comparison of Figure 4 (a) and (b).

[0087] See Figure 5 , Figure 5 The 16-8 thread grouping diagram provided by the embodiments of the present application is shown in Figure 5 Taking the 16-8 thread grouping scheme as an example, when using 128 threads, the threads are divided into 16 blocks, and 8 threads are dynamically scheduled in each thread block. First, the blockIdx array is passed into the atomic cache, and the pz_atomic_inc atomic operation is used in a single grouping to dynamically obtain the next thread index, achieving the purpose of dynamic scheduling.

[0088] Each thread starts processing from , and ends when . The size of the two-dimensional array 16_8 is atomically operated by pz_atomic_inc to dynamically obtain the next thread index.

[0089] Step 10. Get the current row id, currow = p_rowpid[pidoff+i], p_rowpid represents a global row ID mapping array, which stores the actual row number to be processed.

[0090] Step 11. Define a structure local_storage, which contains a two-dimensional array currowdata (storing data pointers) and currowindices (storing column indices). Allocate local storage for each thread block through shared memory (get_local_mem_addr()).

[0091] Step 12. Derive the row start data Lpointer[currow], Lpointer[currow+1] according to the current row number, and pack them into lp. Use the vector unit to access memory, where lp.x represents Lpointer[currow] and lp.y represents Lpointer[currow+1].

[0092] Step 13. Obtain the column index j = Lindices[k] and data value A_ij = Ldata[k], and set the result variable result = 0.0

[0093] Step 14. At this time, set the current row start to Lp1_begin = lp.x and the end to Lp1_end = lp.y - 1. Refer to the row represented by column j, set the start to Lp2_begin = Lpointer[j] and the end to Lp2_end = Lpointer[j+1] - 1.

[0094] Step 15. Store the updated row in advance in the local memory.

[0095] Before using on-chip local memory, the data that needs to be reused needs to be stored in advance in the on-chip local memory. When these data are needed in the calculation process, they can be directly taken from the on-chip local memory, thereby reducing the time overhead caused by memory access, as shown in the following figure. Figure 5 The ILU decomposition first calculates the row update factor when updating the row. The non-zero elements of the current row are reused in the update process of the current row. This feature is consistent with the requirement of using on-chip local memory to improve data locality. Store the non-zero elements of the current row to be updated in the on-chip local memory. When these non-zero elements are used in the subsequent row update, they only need to be taken from the on-chip local memory, which can improve the efficiency of data access.

[0096] Step 16. For each non-zero element k, obtain its column number j and original value A_ij. The prefetch instruction prefetches Ldata_up[k] to reduce memory access delay.

[0097] prefetch<1>(&Ldata_up[k],0);

[0098] Step 17. Initialize double pointers Lpl (current row) and Lp2 (row corresponding to column j), find matches in the ordered sequence indices.

[0099] Step 18. Calculate indices of the two rows as follows:

[0100] int Lp2_index = Lindices[Lp2_begin];

[0101] double Ld_up2 = Ldata_up[Lp2_begin];

[0102] int Lp1_index = ls.currowindices[l1][tid];

[0103] double Ld_up1 = *ls.currowdata[l1][tid];

[0104] Step 19. Accumulate the product result += Ld_up1 * Ld_up2 for matching column indices (Lpl_index == Lp2_index), and let l1 = l1 + 1, Lp2_begin = Lp2_begin + 1.

[0105] Step 20. If Lpl_index < Lp2_index, let l1 = l1 + 1;

[0106] Step 21. If Lpl_index > Lp2_index, let Lp2_begin = Lp2_begin + 1;

[0107] Step 22. Calculate temp2 = A_ij - result.

[0108] Step 23. Non-diagonal elements (j < currow): update to temp2 / L[j][j] (divide by diagonal element of column j).

[0109] Step 24. Diagonal elements (j == currow): update to sqrt(temp2).

[0110] Step 25. Flush the updated array back to memory using the global flush function flush().

[0111] See Figure 6 , Figure 6 A data level scheduling system structure provided by an embodiment of the present application, the system comprises:

[0112] The matrix obtaining module is configured to obtain a sparse matrix in a row compressed storage format.

[0113] The matrix dividing module is configured to divide the sparse matrix to obtain a divided small matrix.

[0114] The data obtaining module is configured to call the vector memory unit to pack and obtain pairs of indexes in the sparse matrix, store the to-be-updated row data into the on-chip local memory, and store the non-zero element column indexes and corresponding values of each row of the L matrix of the sparse matrix into the storage space of the on-chip local memory of each thread.

[0115] The thread grouping module is configured to group the global threads to obtain a plurality of thread blocks, and store thread indexes of the thread blocks into the atomic cache.

[0116] The task calculating module is configured to group the global threads to obtain a plurality of thread blocks, and store thread indexes of the thread blocks into the atomic cache.

[0117] The present application also provides a computer readable storage medium corresponding embodiment. The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the method described in the above method embodiment.

[0118] It can be understood that if the method in the above embodiment is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and executes all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0119] The computer readable storage medium provided in the embodiment includes the method mentioned above, and the effects are the same as above.

[0120] The present application also provides an electronic device, referring to Figure 7 , the structural diagram of the electronic device provided by the embodiment of the present application, as Figure 7 shown, can include a processor 1410 and a memory 1420.

[0121] The processor 1410 can include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 1410 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array). The processor 1410 can also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also known as a CPU (Central Processing Unit), and the coprocessor being a low-power processor for processing data in a standby state. In some embodiments, the processor 1410 can be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing the content to be displayed by the display screen. In some embodiments, the processor 1410 can also include an AI (Artificial Intelligence) processor for processing machine learning-related computing operations.

[0122] The memory 1420 can include one or more computer-readable storage media that can be non-transitory. The memory 1420 can also include a high-speed random access memory, and a non-volatile memory such as one or more disk storage devices, flash storage devices. In this embodiment, the memory 1420 is at least used to store the following computer program 1421, wherein the computer program is loaded and executed by the processor 1410, and can implement the related steps in the method executed by the electronic device side disclosed in any of the preceding embodiments. In addition, the resources stored by the memory 1420 can also include an operating system 1422 and data 1423, and the storage mode can be temporary storage or permanent storage. The operating system 1422 can include Windows, Linux, Android, and the like.

[0123] In some embodiments, the electronic device can also include a display screen 1430, an input / output interface 1440, a communication interface 1450, a sensor 1460, a power supply 1470, and a communication bus 1480.

[0124] Of course, Figure 7 The structure of the electronic device shown does not constitute a limitation on the electronic device in the embodiments of the present application. In actual applications, the electronic device can include more or fewer components than those shown, or some components can be combined. Figure 7 ​

[0125] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. As the system provided in the embodiments corresponds to the method provided in the embodiments, the description is relatively simple; relevant parts can be found in the method section.

[0126] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

[0127] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A data hierarchical scheduling method, characterized in that, include: Obtain a sparse matrix in row-compressed storage format; The sparse matrix is ​​partitioned to obtain smaller partitioned matrices; The vector memory access unit is called to pack and retrieve the paired indices in the sparse matrix, the row data to be updated is stored in the on-chip local memory, and the column indexes of the non-zero elements of each row of the L matrix corresponding to the sparse matrix and the corresponding values ​​are stored in the storage space of the on-chip local memory of each thread. The global threads are grouped into several thread blocks, and the thread index of the thread blocks is stored in the atomic cache. In the atomic cache, the segmented small matrix is ​​processed using each of the thread blocks.

2. The data hierarchical scheduling method according to claim 1, characterized in that, Before calling the vector memory access unit to pack and retrieve the pairwise indices in the sparse matrix, the process also includes: A breadth-first search is used to traverse the lower triangular matrix in the sparse matrix to obtain a directed acyclic graph; The independent matrix rows in the directed acyclic graph are aggregated into independent levels.

3. The data hierarchical scheduling method according to claim 2, characterized in that, Calling the vector memory access unit to pack data using pairwise indices in the sparse matrix includes: Read the row data of type integer and the starting index of the corresponding row in the directed acyclic graph; The row data and the starting index are packaged into data pairs using a composite data type.

4. The data hierarchical scheduling method according to claim 3, characterized in that, Packing the row data and the starting index into data pairs using a composite data type includes: The index value of the row data is packaged and transmitted according to the data type, and the row pointer of the row data is obtained by using the vector loading pointer of the vector loading unit; the row pointer is used to perform memory access operations on the row data.

5. The data hierarchical scheduling method according to claim 1, characterized in that, The global threads are grouped into several thread blocks, and the thread indexes of the thread blocks are stored in an atomic cache. Dynamic thread scheduling is performed using the atomic cache, including: Enable the global shared array of thread blocks as a global thread; The global thread is divided into blocks to obtain several thread blocks; Store the thread ID of the thread block into the atomic cache; Within the atomic cache, atomic operation functions are used to increment the thread ID corresponding to the thread block to adjust the call frequency of threads with different workloads.

6. The data hierarchical scheduling method according to claim 1, characterized in that, The sparse matrix is ​​partitioned to obtain smaller partitioned matrices, including: The sparse matrix is ​​partitioned by calling the graph partitioning function to obtain several sub-matrices.

7. The data hierarchical scheduling method according to claim 6, characterized in that, After performing graph partitioning on the sparse matrix using the graph partitioning function to obtain several sub-matrices, the process also includes: Each of the sub-matrices is assigned to a corresponding processing unit for task processing; the process of assigning each of the sub-matrices to a corresponding processing unit for task processing includes: Filter the thread blocks corresponding to the submatrix and determine the thread range corresponding to the thread blocks; Within the corresponding thread scope, determine the thread block's level and corresponding line; the level is used to indicate access to the global thread, and the line is used to locate line information; Within the thread block, the atomic cache is used to schedule the thread that has completed its current task to process the task corresponding to the thread that has not yet completed its previous task.

8. A data hierarchical scheduling system, characterized in that, include: The matrix acquisition module is used to acquire sparse matrices in row-compressed storage format; A matrix segmentation module is used to perform matrix segmentation on the sparse matrix to obtain smaller segmented matrices. The data retrieval module is used to call the vector memory access unit to pack and retrieve the paired indices in the sparse matrix, store the row data to be updated into the on-chip local memory, and store the column index of the non-zero element of each row of the L matrix corresponding to the sparse matrix and the corresponding value into the storage space of the on-chip local memory of each thread. The thread grouping module is used to group global threads into several thread blocks and store the thread index of the thread blocks into an atomic cache. The task calculation module is used to group global threads into several thread blocks and store the thread index of the thread blocks into an atomic cache.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the steps of the method as described in any one of claims 1 to 7.

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