Memory optimization method and device for multi-core system, equipment and medium

Abstract

The invention discloses a memory optimization method and device for a multi-core system, equipment and a medium, and relates to the field of computers, and the method comprises the following steps: constructing a target resource model based on a structure parameter and a performance parameter of a dynamic random access memory; the target resource model is used for defining storage resource information of each structural unit; generating a memory access feature tag of the thread; according to the memory access feature tags of the threads and the number of the active threads meeting the preset active degree in the multi-core system, dividing all the structural units into structural unit groups matched with the number of the active threads; and determining a target structure unit group matched with the target thread, preferentially selecting an idle memory block belonging to the same structure unit as an existing physical page of the target thread in the target structure unit group based on the storage resource information, and mapping a target virtual page of the target thread to a continuous physical address of the idle memory block. Therefore, the restriction of the memory wall on the system performance is relieved, and the system performance and fairness are ensured.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and medium for optimizing memory in a multi-core system. Background Technology

[0002] With the development of semiconductor technology and computer architecture, multi-core processors have become the mainstream architecture of modern computing systems. Since the performance of single-core processors is limited by bottlenecks such as power consumption and heat dissipation, increasing the number of cores to improve the parallel computing capability of the system has become the core path to meet the needs of high-performance computing and other scenarios.

[0003] However, the performance improvement of multi-core systems does not rely on simply increasing the number of cores, but is limited by the performance imbalance between the processor and memory subsystems. The "memory wall" thus becomes the core obstacle restricting the overall performance release. It should be noted that the "memory wall" refers to the performance bottleneck formed in a multi-core system due to the performance imbalance between the processor and memory subsystems. In recent years, processor performance has increased exponentially; however, the imbalance of "fast computation, slow storage" has become prominent. This directly leads to the processor frequently waiting for memory data transfers in most scenarios, leaving a large amount of computing resources idle, and making it difficult to fully utilize the advantages of multi-core parallelism. At the same time, modern multi-core systems generally adopt a storage architecture of "shared last-level cache + shared DRAM (Dynamic Random Access Memory) main memory." As the number of concurrent threads increases, the memory access requests from different threads exhibit highly intensive and randomized characteristics, leading to increasingly fierce competition for memory resources between threads, and consequently, the problem of "memory interference." This memory interference stems from the "row buffer" mechanism of DRAM: in multi-core concurrent scenarios, if memory access requests from different threads frequently hit different rows of the same DRAM bank, it will cause frequent "swap-in and swap-out" of the row buffer. This not only significantly increases the overall memory access latency and further exacerbates the "memory wall" problem, but also causes two major derivative problems: first, the system fairness decreases, for example, memory-intensive threads will occupy more resources, causing computationally intensive threads to run slowly, and even causing "priority inversion" phenomenon; second, resource utilization is low. The above problems urgently need to be solved by people in the field. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a memory optimization method, apparatus, device, and medium for multi-core systems, which reduces the constraints of the "memory wall" on system performance and ensures system performance and fairness. The specific solution is as follows:

[0005] In a first aspect, this application discloses a memory optimization method for multi-core systems, including:

[0006] Based on the structural and performance parameters of the dynamic random access memory, a target resource model is constructed; wherein, the target resource model is used to clarify the storage resource information of each structural unit, and the structural unit is the structural unit in the dynamic random access memory used to process memory access requests individually;

[0007] Memory access feature labels for the threads are generated based on the memory access feature data of the threads in a multi-core system.

[0008] Based on the memory access characteristic tags of the threads and the number of active threads in the multi-core system that meet the preset activity level, all the structural units are divided into structural unit groups that are adapted to the number of active threads.

[0009] When a target memory access request corresponding to the target thread is obtained, a target structural unit group that is compatible with the target thread is determined. Based on the storage resource information, a free memory block belonging to the same structural unit as the existing physical page of the target thread is preferentially selected within the target structural unit group. Then, the target virtual page of the target thread is mapped to the contiguous physical address of the free memory block.

[0010] Optionally, the structural parameters include the total number of storage levels of the dynamic random access memory, the total number of structural units, and the number of structural units contained in each storage level; the performance parameters include row cycle and row buffer capacity; and the storage resource information includes the correspondence between structural units and storage levels and the physical address range of structural units.

[0011] Optionally, generating the memory access feature label of the thread based on the memory access feature data of the thread in the multi-core system includes:

[0012] The memory access characteristics of threads in a multi-core system are collected using the performance counters of the central processing unit; wherein, the memory access characteristics include thread memory access frequency, memory access address patterns, and data duplication rate.

[0013] Based on the collected memory access characteristic data, the threads are classified into two types: a first type of memory-intensive threads and a second type of computation-intensive threads.

[0014] Based on the memory access characteristic data and the divided thread types, the required number of structural units and the cohesion requirement of the structural units for the thread are determined to obtain the memory access characteristic label of the thread; the cohesion requirement of the structural units refers to whether the high-frequency access data of the thread needs to be clustered in consecutive structural units within the same storage level; the access frequency of the high-frequency access data of the thread is greater than a preset threshold.

[0015] Optionally, the step of dividing all the structural units into structural unit groups adapted to the number of active threads based on the memory access characteristic tags of the threads and the number of active threads in the multi-core system that meet a preset activity level includes:

[0016] Determine the number of active threads in a multi-core system that meet the preset activity level;

[0017] Based on the memory access feature tags of each active thread, the allocation quantity requirement of the structural unit, the cohesion requirement of the structural unit, and the thread type corresponding to each active thread are extracted: wherein, the preset activity level indicates that the thread is in a non-blocking state and continuously occupies the target resource within a preset time.

[0018] Based on the thread type and cohesion requirements of each active thread, a corresponding structural unit group is assigned to each active thread; wherein the number of structural units contained in each structural unit group is consistent with the structural unit allocation requirements of the corresponding active thread.

[0019] The number of structural unit groups obtained by the control partitioning is matched with the number of active threads.

[0020] Optionally, the step of assigning a corresponding structural unit group to each active thread based on the thread type and the cohesion requirement of the structural unit includes:

[0021] If any active thread is a memory-intensive first thread type, and the cohesion requirement of the structure unit indicates that the thread's high-frequency access to data does not need to be clustered in consecutive structure units within the same storage level, then the active thread is allocated a structure unit group spanning multiple storage levels.

[0022] Optionally, the step of assigning a corresponding structural unit group to each active thread based on the thread type and the cohesion requirement of the structural unit includes:

[0023] If any active thread is a computationally intensive second thread type, and the cohesion requirement of the structural unit indicates that the thread's frequently accessed data needs to be clustered in a continuous structural unit within the same storage level, then a continuous structural unit group within the same storage level is allocated to the active thread.

[0024] Optionally, the memory optimization method for the multi-core system further includes:

[0025] The physical address bits of each structural unit in the dynamic random access memory are colored to make each group of structural units correspond to a unique color identifier.

[0026] Secondly, this application discloses a memory optimization device for a multi-core system, comprising:

[0027] The resource model construction module is used to construct a target resource model based on the structural parameters and performance parameters of the dynamic random access memory; wherein, the target resource model is used to specify the storage resource information of each structural unit, and the structural unit is the structural unit in the dynamic random access memory used to process memory access requests individually;

[0028] The memory access tag generation module is used to generate memory access feature tags for the threads based on the memory access feature data of the threads in a multi-core system.

[0029] The structural unit grouping module is used to divide all the structural units into structural unit groups that match the number of active threads, based on the memory access characteristic tags of the threads and the number of active threads in the multi-core system that meet the preset activity level.

[0030] The memory page mapping module is used to, when a target memory access request corresponding to a target thread is obtained, determine the target structural unit group that is compatible with the target thread, and based on the storage resource information, preferentially select a free memory block in the target structural unit group that belongs to the same structural unit as the existing physical page of the target thread, and then map the target virtual page of the target thread to the contiguous physical address of the free memory block.

[0031] Thirdly, this application discloses an electronic device, comprising:

[0032] Memory, used to store computer programs;

[0033] A processor for executing the computer program to implement the aforementioned memory optimization method for multi-core systems.

[0034] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned memory optimization method for multi-core systems.

[0035] As can be seen, this application proposes a memory optimization method for multi-core systems, including: constructing a target resource model based on the structural parameters and performance parameters of dynamic random access memory; wherein, the target resource model is used to clarify the storage resource information of each structural unit, and the structural unit is a structural unit in the dynamic random access memory used to handle memory access requests individually; generating memory access feature tags for the threads based on the memory access feature data of the threads in the multi-core system; dividing all the structural units into structural unit groups adapted to the number of active threads according to the memory access feature tags of the threads and the number of active threads in the multi-core system that meet a preset activity level; when a target memory access request corresponding to the target thread is obtained, determining the target structural unit group adapted to the target thread, and based on the storage resource information, preferentially selecting a free memory block in the target structural unit group that belongs to the same structural unit as the existing physical page of the target thread, and then mapping the target virtual page of the target thread to the contiguous physical address of the free memory block. As can be seen, this application generates memory access feature tags based on thread-based memory access feature data, and divides the appropriate structural unit groups according to the number of active threads that meet the preset activity level. This allows different active threads to correspond to dedicated structural unit groups, effectively isolating memory access requests from different threads to dynamic random access memory, reducing "memory interference" caused by memory resource contention between concurrent threads, alleviating the problem of frequent "swap-in and swap-out" of row buffers, thereby reducing memory access latency, narrowing the performance gap between the processor and memory, and reducing the constraint of the "memory wall" on system performance. When processing the memory access request of the target thread, free memory blocks belonging to the same structural unit as the target thread's existing physical pages are preferentially selected within the target structural unit group, and the target virtual page is mapped to a contiguous physical address. This ensures the clustering of high-frequency access data of the same thread within the structural unit, and avoids excessive resource occupation by memory-intensive threads through the allocation of dedicated structural unit groups, thus ensuring system performance and fairness. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0037] Figure 1 This application discloses a flowchart of a memory optimization method for a multi-core system.

[0038] Figure 2 This is a schematic diagram of a physical page memory organization structure disclosed in this application;

[0039] Figure 3This is a schematic diagram of the memory optimization device for a multi-core system disclosed in this application;

[0040] Figure 4 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] The performance improvement of multi-core systems does not rely on simply increasing the number of cores, but is limited by the performance imbalance between the processor and memory subsystems. The "memory wall" thus becomes the core obstacle restricting the overall performance release. While processor performance grows exponentially, the imbalance of "fast computation, slow storage" is prominent: this causes the processor to frequently wait for memory data transfers in most scenarios, leaving a large amount of computing resources idle, making it difficult to fully utilize the advantages of multi-core parallelism. At the same time, modern multi-core systems generally adopt a storage architecture of "shared last-level cache + shared DRAM main memory." As the number of concurrent threads increases, the memory access requests from different threads become highly intensive and randomized, leading to increasingly fierce competition for memory resources among threads, resulting in "memory interference" problems. This also causes two major derivative problems: first, a decrease in system fairness, for example, memory-intensive threads will occupy more resources, causing computationally intensive threads to run slowly, and even causing "priority inversion"; second, low resource utilization.

[0043] Therefore, this application proposes a memory optimization scheme for multi-core systems, which can alleviate the constraints of the "memory wall" on system performance and ensure system performance and fairness.

[0044] This application discloses a memory optimization method for multi-core systems. (See also...) Figure 1 As shown, the method includes:

[0045] Step S11: Based on the structural parameters and performance parameters of the dynamic random access memory, construct a target resource model; wherein, the target resource model is used to clarify the storage resource information of each structural unit, and the structural unit is the structural unit in the dynamic random access memory used to process memory access requests individually.

[0046] In this embodiment, a target resource model is constructed based on the structural and performance parameters of the Dynamic Random Access Memory (DRAM). The structural parameters include the total number of DRAM storage levels, the total number of structural units, and the number of structural units contained in each storage level. The performance parameters include row cycle time (tRC) and row buffer capacity. The storage resource information includes the correspondence between structural units and storage levels, and the physical address range of the structural units. Specifically, DRAM is referred to as DRAM, and structural units are referred to as banks (memory blocks) in DRAM. The total number of DRAM storage levels (ranks), the total number of structural units, and the number of structural units contained in each rank are identified through the memory controller interface. Simultaneously, performance parameters such as row cycle time (tRC) and row buffer capacity are collected and recorded. Finally, the target resource model is constructed in the form of a data structure. The storage resource information defined in this model covers both the correspondence between structural units and storage levels, as well as the physical address range of each structural unit, accurately reflecting the distribution of DRAM hardware resources.

[0047] Step S12: Generate thread memory access feature labels based on the memory access feature data of threads in a multi-core system.

[0048] In this embodiment, memory access characteristic data of threads in a multi-core system is collected through the performance counter of the central processing unit. The memory access characteristic data includes thread memory access frequency, memory address patterns, and data duplication rate. Based on the collected memory access characteristic data, the threads are classified into two types: a memory-intensive first thread type and a computationally intensive second thread type. According to the memory access characteristic data and the classified thread types, the required number of structural units and the structural unit cohesion requirements for each thread are determined to obtain the thread's memory access characteristic label. The structural unit cohesion requirement refers to whether high-frequency access data of the thread needs to be clustered in consecutive structural units within the same storage level. The access frequency of the high-frequency access data of the thread is greater than a preset threshold.

[0049] Specifically, firstly, the memory access characteristic data of threads within a multi-core system is collected in real time using the performance counters of the Central Processing Unit (CPU). This memory access characteristic data includes thread memory access frequency (indicating the frequency of DRAM access by a thread), memory address patterns (indicating the distribution pattern of thread memory access addresses), and data duplication rate (indicating the repeated access of the same data by a thread). Then, based on the collected memory access characteristic data, the threads are classified into thread types: if a thread has a high memory access frequency and a low data duplication rate, it is identified as a memory-intensive first thread type (this type of thread has higher requirements for DRAM bandwidth and bank resources); if a thread has a low memory access frequency and a high data duplication rate, it is identified as a compute-intensive second thread type (this type of thread relies more on computing resources and has relatively lower requirements for memory resources). Finally, based on the memory access characteristic data and the divided thread types, the required number of structural units and the cohesion requirements of the structural units are further determined. The required number of structural units is determined based on the thread's memory access frequency and parallel processing requirements (e.g., memory-intensive threads require more banks to improve parallelism). The cohesion requirements of the structural units clarify whether high-frequency access data (data accessed more than a preset threshold) needs to be clustered in consecutive structural units within the same storage level (e.g., computationally intensive threads, due to high data duplication rates, usually need data clustering to improve row buffer hit rate). Finally, the above information is integrated to generate thread memory access characteristic tags containing thread type, required number of structural units, and cohesion requirements of structural units, so as to provide a basis for the subsequent division and allocation of structural unit groups.

[0050] Step S13: Based on the memory access characteristic tags of the threads and the number of active threads in the multi-core system that meet the preset activity level, divide all structural units into structural unit groups that match the number of active threads.

[0051] In this embodiment, the number of active threads in the multi-core system that meet a preset activity level is determined. Based on the memory access characteristic tags of each active thread, the required number of structural units, the cohesion requirement of the structural units, and the thread type corresponding to each active thread are extracted. The preset activity level indicates that the thread is in a non-blocking state and continuously occupies the target resource within a preset time. According to the thread type and structural unit cohesion requirement of each active thread, a corresponding structural unit group is allocated to each active thread. The number of structural units contained in each structural unit group is consistent with the required number of structural units allocated to the corresponding active thread. The number of structural unit groups obtained from the partitioning is controlled to match the number of active threads. The specific allocation logic varies depending on the differences in thread type and cohesion requirement: if any active thread is a memory-intensive first thread type, and the structural unit cohesion requirement indicates that the thread's high-frequency data access does not need to be clustered in consecutive structural units within the same storage level, then a structural unit group spanning multiple storage levels is allocated to the active thread. If any active thread is a computationally intensive second thread type, and the structural unit cohesion requirement indicates that the thread's frequently accessed data needs to be clustered in a contiguous structural unit within the same storage level, then a contiguous structural unit group within the same storage level will be allocated to the active thread.

[0052] For example, firstly, the number of active threads in a multi-core system that meet a preset activity level is determined. The preset activity level indicates that the thread is in a non-blocking state and continuously occupies CPU computing resources or memory access resources within a preset time, thus avoiding including inactive threads that are only temporarily woken up or run for a short time in the allocation scope. Next, based on the memory access characteristic tags of each active thread, the required number of structural units, the cohesion requirement of structural units, and the thread type corresponding to each active thread are extracted to clarify the differentiated memory resource requirements of different threads. Subsequently, according to the thread type and structural unit cohesion requirement of each active thread, combined with the aforementioned target resource model, corresponding structural unit groups are allocated to each active thread. The number of structural units contained in each structural unit group is consistent with the structural unit allocation requirement of the corresponding active thread, while ensuring that the number of structural unit groups obtained is compatible with the number of active threads. Furthermore, a thread-bank group mapping table is established during the allocation process to record the range of structural units accessible to each thread. When allocating structural unit groups to active threads, the specific allocation logic varies depending on the thread type and cohesion requirements: If any active thread is a memory-intensive first-type thread, and the structural unit cohesion requirement indicates that the thread's frequently accessed data does not need to be clustered in consecutive structural units within the same storage level, then the active thread is allocated a structural unit group spanning multiple ranks. This allows for improved memory access throughput through multi-rank parallel processing, adapting to its high bandwidth requirements. If any active thread is a computationally intensive second-type thread, and the structural unit cohesion requirement indicates that the thread's frequently accessed data needs to be clustered in consecutive structural units within the same storage level, then the active thread is allocated a consecutive structural unit group within the same rank. This facilitates the clustering of frequently accessed data from the same thread in adjacent banks, thereby fully utilizing the caching effect of the row buffer to reduce row buffer conflicts and lower memory access latency.

[0053] Step S14: When a target memory access request corresponding to the target thread is obtained, the target structural unit group that is compatible with the target thread is determined, and based on the storage resource information, a free memory block that belongs to the same structural unit as the existing physical page of the target thread is preferentially selected in the target structural unit group. Then, the target virtual page of the target thread is mapped to the continuous physical address of the free memory block.

[0054] When a target memory access request corresponding to the target thread is obtained (e.g., the target thread triggers a page fault, meaning the virtual page accessed by the thread is not mapped to a physical page and physical memory needs to be requested), the thread-Bank group mapping table obtained in the previous steps is queried to determine the target structural unit group corresponding to the target thread. It should be noted that by determining the target structural unit group corresponding to the target thread, the target thread is prevented from accessing the structural unit group corresponding to other threads, thus achieving physical isolation of memory access requests at the hardware level.

[0055] To further improve the efficiency of structural unit group identification and location, this embodiment colors the physical address bits of each structural unit in the dynamic random access memory, so that each divided structural unit group corresponds to a unique color identifier. (For example, 64 banks are divided into 4 structural unit groups of 16 each, corresponding to different color identifiers). This coloring is synchronously recorded in the target resource model and thread-bank group mapping table. When the target structural unit group is determined, the corresponding physical address range can be quickly matched through the color identifier, without having to traverse all structural units one by one, which greatly shortens the location time. Especially in multi-threaded high-frequency page fault exception scenarios, it can significantly reduce the time overhead of mapping table lookup.

[0056] After determining the target structural unit group, the operating system, based on the storage resource information in the target resource model, prioritizes selecting free memory blocks within the target structural unit group that belong to the same structural unit as the target thread's existing physical pages. This is because frequently accessed data by the same thread often exhibits locality of reference. Grouping these data within the same bank ensures that the data is continuously stored in the row buffer of that bank, reducing the "swap-in / swap-out" operations of the row buffer caused by different threads accessing different rows of the same bank, thereby reducing memory access latency. For example, if the target thread's existing physical pages are located in Bank0 within the structural unit group, when a page fault is triggered and a new physical page is requested, the operating system will prioritize searching for free memory blocks in Bank0, rather than randomly selecting resources from other banks within the group, ensuring the clustering of data from the same thread within the bank.

[0057] In addition, when allocating free memory blocks, the memory management logic of the buddy algorithm is followed: each structural unit group contains a free_area array, which links 11 free block linked lists divided into different sizes. The operating system will match the free block linked lists of the corresponding size in the free_area array of the target structural unit group according to the memory capacity requirements corresponding to the page fault of the target thread, and select the most suitable free memory block from them. Figure 2This diagram illustrates the correspondence between Bank Groups and memory page allocation in Dynamic Random Access Memory (DRAM). Multiple Bank Groups are shown, from BankGroup0 to BankGroupn. Taking BankGroup0 as an example, it contains structural units (Banks) with different numbers (e.g., 0, 10, etc.). Each structural unit corresponds to a linked list of memory pages of different sizes; for example, some linked lists connect to memory blocks of 1 page size, while others connect to memory blocks of 1024 pages. Other Bank Groups (such as BankGroupn) exhibit similar structures, with each structural unit also linked to linked lists of memory pages of different sizes. The `free_area` array within each Bank Group links to linked lists of free blocks divided into different sizes. The operating system can select appropriate free memory blocks from the free block lists of the corresponding Bank Group and structural units based on the memory capacity requirements of the target thread, achieving efficient memory allocation that meets data aggregation requirements. This allocation method, combining memory awareness and the buddy system algorithm, ensures efficient memory allocation while strengthening data aggregation, achieving efficient resource utilization and performance optimization.

[0058] Finally, after identifying a free memory block, the operating system maps the target thread's target virtual page to a contiguous physical address within that free memory block and establishes a virtual page-physical page-Bank mapping in the memory page table. This achieves the translation from virtual address to physical address. Furthermore, when the target thread accesses the virtual page again, the memory controller can directly send a memory access request based on the Bank information in the memory page table without resolving the address. Simultaneously, the contiguous physical address mapping design reduces the number of DRAM row activations and precharges (contiguous address data is usually located in the same or adjacent rows), fully utilizing the row buffer's caching function and reducing the processor's waiting time for memory data transfers. It should be noted that if there is no suitable free memory block in the same Bank as the target thread's existing physical page within the target structural unit group, the operating system will select a free memory block from other Banks within the target structural unit group, but will still prioritize Bank resources adjacent to the existing physical page Bank. This ensures timely response to the target thread's memory requests, avoiding increased memory access latency due to waiting for free blocks in the same Bank, while also minimizing the dispersion of data within the same thread and reducing the impact of cross-Bank allocation on the row buffer hit rate.

[0059] As can be seen, this application proposes a memory optimization method for multi-core systems, including: constructing a target resource model based on the structural parameters and performance parameters of dynamic random access memory; wherein, the target resource model is used to clarify the storage resource information of each structural unit, and the structural unit is a structural unit in the dynamic random access memory used to handle memory access requests individually; generating memory access feature tags for the threads based on the memory access feature data of the threads in the multi-core system; dividing all the structural units into structural unit groups adapted to the number of active threads according to the memory access feature tags of the threads and the number of active threads in the multi-core system that meet a preset activity level; when a target memory access request corresponding to the target thread is obtained, determining the target structural unit group adapted to the target thread, and based on the storage resource information, preferentially selecting a free memory block in the target structural unit group that belongs to the same structural unit as the existing physical page of the target thread, and then mapping the target virtual page of the target thread to the contiguous physical address of the free memory block. As can be seen, this application generates memory access feature tags based on thread-based memory access feature data, and divides the appropriate structural unit groups according to the number of active threads that meet the preset activity level. This allows different active threads to correspond to dedicated structural unit groups, effectively isolating memory access requests from different threads to dynamic random access memory, reducing "memory interference" caused by memory resource contention between concurrent threads, alleviating the problem of frequent "swap-in and swap-out" of row buffers, thereby reducing memory access latency, narrowing the performance gap between the processor and memory, and reducing the constraint of the "memory wall" on system performance. When processing the memory access request of the target thread, free memory blocks belonging to the same structural unit as the target thread's existing physical pages are preferentially selected within the target structural unit group, and the target virtual page is mapped to a contiguous physical address. This ensures the clustering of high-frequency access data of the same thread within the structural unit, and avoids excessive resource occupation by memory-intensive threads through the allocation of dedicated structural unit groups, thus ensuring system performance and fairness.

[0060] Accordingly, this application also discloses a memory optimization device for multi-core systems, see [link to relevant documentation]. Figure 3 As shown, the device includes:

[0061] Resource model construction module 11 is used to construct a target resource model based on the structural parameters and performance parameters of the dynamic random access memory; wherein, the target resource model is used to clarify the storage resource information of each structural unit, and the structural unit is the structural unit in the dynamic random access memory used to process memory access requests individually;

[0062] The memory access tag generation module 12 is used to generate memory access feature tags for the threads based on the memory access feature data of the threads in a multi-core system.

[0063] The structural unit grouping module 13 is used to divide all the structural units into structural unit groups that are adapted to the number of active threads, based on the memory access feature tags of the threads and the number of active threads in the multi-core system that meet the preset activity level.

[0064] The memory page mapping module 14 is used to, when a target memory access request corresponding to the target thread is obtained, determine the target structural unit group that is compatible with the target thread, and based on the storage resource information, preferentially select a free memory block in the target structural unit group that belongs to the same structural unit as the existing physical page of the target thread, and then map the target virtual page of the target thread to the contiguous physical address of the free memory block.

[0065] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0066] Furthermore, embodiments of this application also provide an electronic device. Figure 4 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0067] Figure 4 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the memory optimization method for multi-core systems disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0068] In this embodiment, the power supply 26 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 24 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0069] Furthermore, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored thereon may include computer programs 221, and the storage method may be temporary storage or permanent storage. The computer programs 221 may include, in addition to computer programs capable of performing the memory optimization method for a multi-core system executed by the electronic device 20 as disclosed in any of the foregoing embodiments, computer programs capable of performing other specific tasks.

[0070] Furthermore, embodiments of this application also disclose a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned memory optimization method for multi-core systems.

[0071] For the specific steps of this method, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0072] The various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. For the same or similar parts between the various embodiments, refer to each other. As for the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and relevant parts can be referred to in the method section.

[0073] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0074] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0075] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0076] The foregoing has provided a detailed description of a memory optimization method, apparatus, device, and storage medium for a multi-core system. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A memory optimization method for a multi-core system, characterized in that, include: Based on the structural and performance parameters of the dynamic random access memory, a target resource model is constructed; wherein, the target resource model is used to clarify the storage resource information of each structural unit, and the structural unit is the structural unit in the dynamic random access memory used to process memory access requests individually; Memory access feature labels for the threads are generated based on the memory access feature data of the threads in a multi-core system. Based on the memory access characteristic tags of the threads and the number of active threads in the multi-core system that meet the preset activity level, all the structural units are divided into structural unit groups that are adapted to the number of active threads. When a target memory access request corresponding to the target thread is obtained, a target structural unit group that is compatible with the target thread is determined. Based on the storage resource information, a free memory block belonging to the same structural unit as the existing physical page of the target thread is preferentially selected within the target structural unit group. Then, the target virtual page of the target thread is mapped to the contiguous physical address of the free memory block.

2. The memory optimization method for a multi-core system according to claim 1, characterized in that, The structural parameters include the total number of storage levels of the dynamic random access memory, the total number of structural units, and the number of structural units contained in each storage level. The performance parameters include row cycle and row buffer capacity. The storage resource information includes the correspondence between structural units and storage levels, as well as the physical address range of the structural units.

3. The memory optimization method for a multi-core system according to claim 2, characterized in that, The generation of the memory access feature label for the thread based on the memory access feature data of the thread in the multi-core system includes: The memory access characteristics of threads in a multi-core system are collected using the performance counters of the central processing unit; wherein, the memory access characteristics include thread memory access frequency, memory access address patterns, and data duplication rate. Based on the collected memory access characteristic data, the threads are classified into two types: a memory-intensive first thread type and a computationally intensive second thread type. Based on the memory access characteristic data and the divided thread types, the required number of structural units and the cohesion requirement of the structural units for the thread are determined to obtain the memory access characteristic label of the thread; the cohesion requirement of the structural units refers to whether the high-frequency access data of the thread needs to be clustered in consecutive structural units within the same storage level; the access frequency of the high-frequency access data of the thread is greater than a preset threshold.

4. The memory optimization method for a multi-core system according to claim 3, characterized in that, The step of dividing all the structural units into structural unit groups adapted to the number of active threads based on the memory access characteristic tags of the threads and the number of active threads in the multi-core system that meet the preset activity level includes: Determine the number of active threads in a multi-core system that meet the preset activity level; Based on the memory access feature tags of each active thread, the allocation quantity requirement of the structural unit, the cohesion requirement of the structural unit, and the thread type corresponding to each active thread are extracted: wherein, the preset activity level indicates that the thread is in a non-blocking state and continuously occupies the target resource within a preset time. Based on the thread type and cohesion requirements of each active thread, a corresponding structural unit group is assigned to each active thread; wherein the number of structural units contained in each structural unit group is consistent with the structural unit allocation requirements of the corresponding active thread. The number of structural unit groups obtained by the control partitioning is matched with the number of active threads.

5. The memory optimization method for a multi-core system according to claim 4, characterized in that, The step of assigning a corresponding structural unit group to each active thread based on the thread type and the cohesion requirement of the structural unit includes: If any active thread is a memory-intensive first thread type, and the cohesion requirement of the structure unit indicates that the thread's high-frequency access to data does not need to be clustered in consecutive structure units within the same storage level, then the active thread is allocated a structure unit group spanning multiple storage levels.

6. The memory optimization method for a multi-core system according to claim 4, characterized in that, The step of assigning a corresponding structural unit group to each active thread based on the thread type and the cohesion requirement of the structural unit includes: If any active thread is a computationally intensive second thread type, and the cohesion requirement of the structural unit indicates that the thread's frequently accessed data needs to be clustered in a continuous structural unit within the same storage level, then a continuous structural unit group within the same storage level is allocated to the active thread.

7. The memory optimization method for a multi-core system according to any one of claims 1 to 6, characterized in that, Also includes: The physical address bits of each structural unit in the dynamic random access memory are colored to make each group of structural units correspond to a unique color identifier.

8. A memory optimization device for a multi-core system, characterized in that, include: The resource model construction module is used to construct a target resource model based on the structural parameters and performance parameters of the dynamic random access memory; wherein, the target resource model is used to specify the storage resource information of each structural unit, and the structural unit is the structural unit in the dynamic random access memory used to process memory access requests individually; The memory access tag generation module is used to generate memory access feature tags for the threads based on the memory access feature data of the threads in a multi-core system. The structural unit grouping module is used to divide all the structural units into structural unit groups that match the number of active threads, based on the memory access characteristic tags of the threads and the number of active threads in the multi-core system that meet the preset activity level. The memory page mapping module is used to, when a target memory access request corresponding to a target thread is obtained, determine the target structural unit group that is compatible with the target thread, and based on the storage resource information, preferentially select a free memory block in the target structural unit group that belongs to the same structural unit as the existing physical page of the target thread, and then map the target virtual page of the target thread to the contiguous physical address of the free memory block.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the memory optimization method for a multi-core system as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein, when the computer programs are executed by a processor, they implement the memory optimization method for a multi-core system as described in any one of claims 1 to 7.

Images