Data processing systems, methods, apparatus, electronic devices, and storage media

Abstract

This invention relates to the field of computer architecture technology and provides a data processing system, method, apparatus, electronic device, and storage medium. The system includes: an interface control unit for reading firmware data from external memory and generating write transfer requests for the firmware data; and a target storage unit connected to the interface control unit via a bus for receiving write transfer requests transmitted by the interface control unit via the bus and writing firmware data based on the write transfer requests for chip startup or operation. This fundamentally changes the data transfer mode, enabling direct and proactive writing of external firmware data to the on-chip target storage unit without requiring the chip's main control unit to participate in data polling or frequent DMA handshake signal configuration. This significantly reduces the load on the main control unit and reduces data interaction latency on the transmission path, thereby greatly improving the efficiency of firmware data transfer and accelerating chip startup or operation.

Description

Technical Field

[0001] This invention relates to the field of computer architecture technology, and in particular to a data processing system, method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the rapid development of integrated circuits, graphics processing units (GPUs) and artificial intelligence chips are increasingly used in high-performance computing scenarios. The startup phase is crucial in the chip's lifecycle. This phase requires loading a large amount of firmware data from external memory to complete hardware configuration and software environment setup. The efficiency of the on-chip main control unit in acquiring data during this phase directly affects startup time; therefore, improving this efficiency is of great significance for accelerating chip startup.

[0003] Currently, on-chip memory typically communicates with off-chip memory via a serial peripheral interface to obtain data. Data transfer is achieved through direct memory access in conjunction with the serial peripheral interface, or through polling by the main control unit. However, both of these methods have significant drawbacks, namely, they result in substantial delays when transferring large amounts of firmware data, severely slowing down the boot process. Summary of the Invention

[0004] This invention provides a data processing system, method, apparatus, electronic device, and storage medium to solve the problems of long interaction paths and low single transmission efficiency in the firmware data transfer process in the prior art.

[0005] This invention provides a data processing system applied to a chip, comprising:

[0006] An interface control unit is used to read firmware data from an external memory and generate a write transfer request for the firmware data.

[0007] The target storage unit is connected to the interface control unit via a bus, and is used to receive the write transfer request transmitted by the interface control unit via the bus, and write the firmware data based on the write transfer request for the chip to start or run.

[0008] According to a data processing system provided by the present invention, the interface control unit includes:

[0009] The data buffer unit is configured as a multi-row storage structure, with each row of storage structure associated with a valid bit identifier, for temporarily storing the firmware data read from the external memory;

[0010] The buffer management unit is used to write the read firmware data line by line into the data buffer unit and set the associated valid bit identifier, and to clear the associated valid bit identifier after the write transfer request is transmitted to the target storage unit through the bus.

[0011] According to a data processing system provided by the present invention, the interface control unit is further configured with a write pointer and a read pointer; the write pointer points to the row address of the currently temporarily stored data in the data buffer unit, and the read pointer points to the row address of the currently pending data in the data buffer unit;

[0012] The buffer management unit is configured to write the firmware data to the data buffer unit based on the write pointer and update the write pointer, and read the firmware data from the data buffer unit based on the read pointer to generate the write transfer request and update the read pointer.

[0013] According to a data processing system provided by the present invention, the interface control unit further includes:

[0014] A transmission control unit, connected to the buffer management unit, is used to determine the effective amount of data in the data buffer unit based on the write pointer and the read pointer when the total amount of data sent has not reached the target total amount of data.

[0015] The total amount of data sent is the total amount of firmware data corresponding to the write transmission requests that the interface control unit has initiated to the target storage unit, and the total amount of target data is the preset total amount of firmware data to be transmitted.

[0016] The transmission control unit is further configured to generate a transmission instruction based on the effective data volume, the transmission instruction including the starting read address and data transmission length of the firmware data corresponding to the effective data volume being transmitted in the data buffer unit;

[0017] The data transmission unit is used to receive the transmission command sent by the transmission control unit, obtain the firmware data to be transmitted in this transmission from the data buffer unit based on the transmission command, and generate the write transmission request containing burst transmission parameters based on the firmware data.

[0018] According to a data processing system provided by the present invention, the data transmission unit is configured to set the transmission length in the burst transmission parameters to the maximum burst length when the data transmission length is greater than or equal to the maximum burst length allowed by the bus; and to set the transmission length in the burst transmission parameters to the data transmission length when the data transmission length is less than the maximum burst length.

[0019] The present invention also provides a data processing method, applied to the data processing system as described in any of the preceding claims, the method comprising:

[0020] Read firmware data from external storage and generate a write transfer request based on the read firmware data;

[0021] The firmware data is written based on the write transfer request for use by the chip during startup or operation.

[0022] According to a data processing method provided by the present invention, the step of generating a write transfer request based on the read firmware data includes:

[0023] Write the read firmware data into the data buffer unit;

[0024] If the total amount of data sent has not reached the target amount of data, the effective amount of data in the data buffer unit is determined; the total amount of data sent is the total amount of firmware data corresponding to the cumulative write transmission requests initiated, and the target amount of data is the preset amount of firmware data to be transmitted.

[0025] A transmission instruction is generated based on the effective data volume. The transmission instruction includes the starting read address and data transmission length of the firmware data corresponding to the effective data volume being transmitted in the data buffer unit.

[0026] Based on the transmission command, the firmware data for this transmission is obtained from the data buffer unit, and a write transmission request containing burst transmission parameters is generated based on the firmware data.

[0027] The present invention also provides a data processing apparatus, applied to a data processing system as described in any of the preceding claims, the apparatus comprising:

[0028] The read module is used to read firmware data from external storage and generate a write transfer request based on the read firmware data;

[0029] The storage module is used to write the firmware data based on the write transfer request for use by the chip during startup or operation.

[0030] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the data processing method as described above.

[0031] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data processing method as described above.

[0032] The data processing system, method, apparatus, electronic device, and storage medium provided by this invention fundamentally change the data transfer mode by enabling the interface control unit to actively read data from external memory and generate write transfer requests. It can directly and actively write external firmware data into the on-chip target storage unit without the chip's main control unit participating in the entire process of data polling or frequently configuring DMA handshake signals. This greatly reduces the load on the main control unit, avoids pipeline blockage caused by waiting for data, and reduces the interaction delay of data on the transmission path, thereby greatly improving the efficiency of firmware data transfer and speeding up the chip's startup or operation. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of the data processing system provided by the present invention;

[0035] Figure 2 This is a schematic diagram of one of the conventional solutions provided by the present invention;

[0036] Figure 3 This is a second schematic diagram of the conventional solution provided by the present invention;

[0037] Figure 4 This is an overall architecture diagram of the data processing system provided by the present invention;

[0038] Figure 5 This is a flowchart illustrating the data processing method provided by the present invention;

[0039] Figure 6 This is a schematic diagram of the data processing device provided by the present invention;

[0040] Figure 7 This is a schematic diagram of the structure of the electronic device provided by the present invention.

[0041] Figure label:

[0042] 110: Interface control unit; 120: Bus; 130: Target storage unit;

[0043] 111: Data buffer unit; 112: Buffer management unit; 113: Transmission control unit;

[0044] 114: Data transmission unit; 610: Reading module; 620: Storage module;

[0045] 710: Processor; 720: Communication interface; 730: Memory; 740: Communication bus. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0047] With the rapid development of integrated circuit technology, modern chips, especially graphics processing units (GPUs) and artificial intelligence (AI) chips, are widely used in high-performance computing scenarios across various industries. The boot phase is a crucial part of the chip's lifecycle. Typically, at different stages of chip initialization, different types of firmware data (fw) need to be loaded from external sources to complete hardware configuration or software environment setup.

[0048] Since this firmware data is typically large, reaching tens or even hundreds of kilobytes, and stored in off-chip non-volatile memory such as Flash, the overall initialization time is directly determined by the chip's internal control unit, such as the microprocessor unit (MPU), its ability to quickly and efficiently retrieve this firmware data from the external source. In other words, improving the efficiency of on-chip data transfer of external firmware data is of significant importance for improving the overall startup speed of GPUs, AI chips, and other similar devices.

[0049] In current chip design architectures, to execute the boot process, multiple different firmware data segments are typically pre-stored in external Flash memory. The on-chip processor generally communicates with the external Flash memory via a Serial Peripheral Interface (SPI) to obtain data. Currently, data transfer from SPI to the on-chip MPU mainly occurs in the following two ways:

[0050] Figure 2 This is a schematic diagram of one of the conventional solutions provided by the present invention, such as... Figure 2As shown, the first method uses a handshake mode combining Direct Memory Access (DMA) and SPI. Specifically, the MPU needs to configure both DMA and SPI, setting the total amount of data to be transferred. During transmission, when the SPI prepares a 32-bit data entry, it sends a level signal to trigger the DMA. Upon receiving the trigger signal, the DMA reads the 32-bit data from the SPI, and then writes it to the memory area specified by the MPU. This process repeats until all firmware data has been transferred.

[0051] Figure 3 This is a second structural schematic diagram of the conventional solution provided by the present invention, as shown below. Figure 3 As shown, the second method is the MPU-polling active read mode. In this mode, the MPU only configures the SPI and the amount of data to be transferred. The MPU then enters a continuous polling state, constantly reading the status register inside the SPI. Once it detects that the SPI has prepared a minimum of 32 bits of data, the MPU actively reads that data from the SPI. This process is also performed in 32-bit units until all data has been read.

[0052] However, both of the aforementioned existing technologies suffer from significant efficiency bottlenecks when dealing with large-scale firmware transfers:

[0053] For the first DMA method, due to the lack of a bulk transfer mechanism, the MPU needs to go through a complete handshake process—from SPI triggering to DMA response, then reading the data, and finally pulling the signal low to reset—every time it acquires a 32-bit data segment. This segment-by-segment 32-bit interaction not only has a long acquisition path but also complex control logic, and the frequent handshake signal exchanges waste a significant amount of time.

[0054] While the second MPU polling method eliminates the DMA handshake, the MPU still consumes computing power to continuously read the SPI status, leading to high processor load. More seriously, because the MPU can only read in 32-bit units and lacks burst read capability, its read speed often lags behind the SPI's data retrieval speed from Flash. This causes the SPI's internal buffer queue to frequently be full, forcing SPI to pause data retrieval from Flash, resulting in data accumulation on the transmission path, disrupting the pipeline and significantly wasting Flash's high-speed read capability.

[0055] In summary, whether it's the cumbersome handshake or the inefficient polling, these tiny amounts of time wasted accumulate into huge delays when dealing with data volumes of tens or hundreds of KB, severely slowing down the chip's boot speed.

[0056] In response, this invention provides a data processing system designed to address the problems of long interaction paths, low single-transmission efficiency, and pipeline blockage in the firmware data transfer process in existing technologies. It enables the interface control unit to actively read and burst write external firmware data, thereby fundamentally eliminating the bandwidth bottleneck in data transfer and significantly accelerating the chip startup process.

[0057] Figure 1 This is a schematic diagram of the data processing system provided by the present invention, which is applied to a chip. The chip here can be a GPU, a Central Processing Unit (CPU), a System-on-Chip (SoC), a Neural Network Processing Unit (NPU), a Microcontroller Unit (MCU), or other integrated circuits that include computing and storage functions. During the boot or running phase of these chips, in order to complete hardware initialization or functional configuration, it is necessary to efficiently load basic programs or configuration parameters. The embodiments of the present invention are designed to solve this data loading efficiency problem. Figure 1 As shown, the system includes:

[0058] The interface control unit 110 is used to read firmware data from external memory and generate write transfer requests for the firmware data.

[0059] The target storage unit 130 is connected to the interface control unit via the bus 120. It is used to receive write transfer requests transmitted by the interface control unit via the bus and write firmware data based on the write transfer requests for chip startup or operation.

[0060] Specifically, the interface control unit, as the key hub for communication between the chip's internal and external systems, can be a Serial Peripheral Interface (SPI) controller, a Quad Serial Peripheral Interface (QSPI) controller, or other hardware circuits that support external bus protocols. This embodiment of the invention does not impose any specific limitations on this.

[0061] Unlike existing technologies where interfaces often serve as passive transmission channels, the interface control unit in this embodiment of the invention is configured to have active data transfer capabilities. Specifically, the interface control unit is connected to an external memory outside the chip. The external memory, as the source of data, is a medium for non-volatile data storage. It can be a flash memory, such as NAND Flash (Not AND Flash Memory) or NOR Flash (Not OR Flash Memory), or an electrically erasable programmable read-only memory.

[0062] When the system is working, the interface control unit first needs to read data, that is, it actively accesses the external memory to read firmware data. The firmware data here is the key data required for the chip to start or run, which may include the bootloader program, microkernel code, microcode, various configuration instruction sets, etc.

[0063] After acquiring the firmware data, the interface control unit does not temporarily store the data waiting to be retrieved; instead, it actively generates a write transfer request. That is, based on the chip's internal bus protocol, such as AHB (Advanced High Performance Bus) or AXI (Advanced eXtensible Interface), it actively generates a write transfer request for the firmware data. This request encapsulates the data read address, data transfer length, and firmware data, meaning the interface control unit possesses the permissions of a bus master device and can actively write data into the chip.

[0064] Subsequently, the interface control unit transmits the write transfer request to the target memory unit via the chip's internal buses, such as the system bus or Network on Chip (NoC). The target memory unit, which communicates with the interface control unit via the bus, is an internal storage space within the chip used to store programs or data to be executed; examples include static random access memory, tightly coupled memory, and on-chip cache.

[0065] As the receiving end, the target storage unit responds to the write transfer request transmitted by the interface control unit by directly writing the firmware data carried in the request into its internal storage space. Once the firmware data is successfully written to the target storage unit, the chip's internal computing core, such as the MCU, can directly retrieve the data from that storage unit to complete the chip's startup or maintain subsequent operation.

[0066] The data processing system provided by this invention fundamentally changes the data transfer mode by enabling the interface control unit to actively read data from external memory and generate write transfer requests. It can directly and actively write external firmware data into the on-chip target storage unit without the chip's main control unit participating in the entire process of data polling or frequently configuring DMA handshake signals. This greatly reduces the load on the main control unit, avoids pipeline blockage caused by waiting for data, and reduces the interaction delay of data on the transmission path, thereby greatly improving the efficiency of firmware data transfer and speeding up the chip's startup or running speed.

[0067] Based on the above embodiments, the interface control unit includes:

[0068] The data buffer unit 111 is configured as a multi-row storage structure, with each row of storage structure associated with a valid bit identifier, used to temporarily store firmware data read from external memory;

[0069] The buffer management unit 112 is used to write the read firmware data into the data buffer unit line by line and set the associated valid bit flag, and to clear the associated valid bit flag after the write transfer request is transmitted to the target storage unit via the bus.

[0070] Specifically, in order to further optimize the data flow efficiency within the interface control unit, the internal architecture of the interface control unit was designed in this embodiment of the invention. Figure 4 This is an overall architecture diagram of the data processing system provided by the present invention, such as... Figure 4 As shown, the interface control unit includes a data buffer unit and a buffer management unit, which work together.

[0071] In detail, in this embodiment of the invention, the data buffer unit does not employ a traditional single-port First-In-First-Out (FIFO) queue, but rather a multi-row storage structure, i.e., a Tab structure. This structure contains several independent storage rows, capable of accommodating multiple sets of data. More importantly, to precisely manage the status of each row of data, each row of storage structure in the data buffer unit of this embodiment is associated with a valid bit flag. This flag is used to intuitively indicate whether the firmware data temporarily stored in the current row, read from external memory, is valid, or whether the current row is ready.

[0072] Correspondingly, the buffer management unit can manage data writing and reading by manipulating the valid bit flag. Specifically, during the data writing phase, when the interface control unit continuously reads firmware data from external memory, the buffer management unit writes the read firmware data line by line into the data buffer unit. Each time a line of data is written, the buffer management unit immediately sets the valid bit flag associated with that line, for example, setting Valid to 1. This setting operation indicates that the line of data is ready and can be packaged and sent. In this way, data reading operations can be performed continuously; firmware data can be continuously written as long as there are free lines in the data buffer unit.

[0073] Accordingly, during the data reading phase, once the interface control unit generates a write transfer request based on valid firmware data and transmits it to the target storage unit via the bus, it means that the data for that row has completed its transfer mission. At this point, the buffer management unit performs a cleanup operation, which clears the valid bit flag associated with that row of data, for example, by setting Valid to 0. This cleanup operation indicates that the space occupied by that row of data has been released and can be used to temporarily store the next batch of new firmware data read from external memory, thereby achieving the recycling of storage space.

[0074] In this embodiment of the invention, a multi-row storage structure with valid bit identifiers and a corresponding management unit are used to achieve flexible management of the data buffer. Compared with the traditional first-in-first-out queue, this Tab structure based on valid bit identifiers can more clearly define the data preparation state, thereby achieving parallelism and decoupling between external reading and internal writing in time. That is, the data reading unit is responsible for reading, and the data transmission unit is responsible for transmission, and the two do not interfere with each other, thus greatly improving the continuity of data reading and writing and the utilization rate of the buffer.

[0075] Based on the above embodiments, the interface control unit is also configured with a write pointer and a read pointer; the write pointer points to the row address of the currently temporarily stored data in the data buffer unit, and the read pointer points to the row address of the currently pending data in the data buffer unit;

[0076] The buffer management unit is used to write firmware data to the data buffer unit based on the write pointer and update the write pointer, and to read firmware data from the data buffer unit based on the read pointer to generate a write transfer request and update the read pointer.

[0077] Specifically, to achieve orderly control of the data flow within the Tab structure, this embodiment of the invention further improves the addressing logic of the interface control unit. In terms of configuration, the interface control unit internally maintains two key dynamic indicators: a write pointer and a read pointer. These two pointers respectively indicate the specific locations where data is written and read from the data buffer unit.

[0078] In detail, in this embodiment of the invention, the write pointer is configured to point to the currently temporary data in the data buffer unit, i.e., the line address of the firmware data to be written; while the read pointer points to the currently pending data in the data buffer unit, i.e., the line address of the firmware data to be read. The buffer management unit drives the entire data read and write process by changing the relative positions of these two pointers.

[0079] Specifically, during the data writing phase, when the interface control unit reads firmware data back from external memory, the buffer management unit first reads the current write pointer value, locates the corresponding free row in the data buffer unit based on the write pointer, and writes the firmware data into that free row. Once the write operation of the current row is completed, the buffer management unit immediately updates the write pointer, such as by performing an increment or wrap-around operation, so that the write pointer points to the next available storage row, thereby preparing for the temporary storage / reception of the next batch of firmware data.

[0080] Correspondingly, during the data reading phase, when firmware data needs to be written to the target storage unit, the buffer management unit accurately locates and reads the pre-stored firmware data from the data buffer unit based on the current read pointer. Subsequently, it generates a write transfer request conforming to the bus protocol using the read firmware data and sends it through the bus. After the write transfer request is generated or transmitted to the target storage unit, the buffer management unit synchronously updates the read pointer, making it point to the next line of valid firmware data to be sent.

[0081] In this embodiment of the invention, the physical storage location of data and the logical processing order are efficiently bound by an independent read and write pointer mechanism. This means that the movement of data in the buffer unit only requires changing the value of the pointer, without having to shift data like a traditional shift register, such as a first-in-first-out queue. This not only reduces the dynamic power consumption of the hardware logic, but also greatly improves the processing speed of data entry and exit, ensuring that data read and write operations do not block each other during the high-speed startup process.

[0082] Based on the above embodiments, the interface control unit further includes:

[0083] The transmission control unit 113 is connected to the buffer management unit and is used to determine the effective amount of data in the data buffer unit based on the write pointer and the read pointer when the total amount of data sent has not reached the target total amount of data.

[0084] The total amount of data sent is the total amount of firmware data corresponding to the write transmission requests that the interface control unit has initiated to the target storage unit. The total amount of target data is the preset total amount of firmware data to be transmitted.

[0085] The transmission control unit is also used to generate transmission instructions based on the effective data volume. The transmission instructions include the starting read address and data transmission length of the firmware data corresponding to the effective data volume of this transmission in the data buffer unit.

[0086] The data transmission unit 114 is used to receive the transmission command sent by the transmission control unit, and obtain the firmware data for this transmission from the data buffer unit based on the transmission command, and generate a write transmission request containing burst transmission parameters based on the firmware data.

[0087] Specifically, after the orderly management of the data buffer unit is achieved through the write pointer and the read pointer, in order to further write the temporarily stored firmware data into the target storage unit, in this embodiment of the invention, a transmission control unit and a data transmission unit are also configured in the interface control unit. The two work together to complete the burst writing of data.

[0088] For details, see Figure 4 It is understood that the transmission control unit is connected to the buffer management unit, which is responsible for monitoring the overall progress of data transfer, i.e., determining whether there is any remaining firmware data to be transferred. Therefore, in this embodiment of the invention, a target data volume is pre-configured, which is the total amount of firmware data that needs to be transferred from external storage during this startup or configuration process, for example, 1MB. The transmission control unit will count the total amount of data sent in real time, i.e., the total amount of firmware data included in the write transfer requests initiated by the interface control unit to the target storage unit up to date. If the total amount of data sent has not reached the target data volume, it indicates that the transfer task has not yet ended. At this time, the transmission control unit will immediately initiate a new transmission evaluation. That is, it will read the current values ​​of the write pointer and read pointer, and use the difference between the two (considering the winding situation) to determine the effective data volume in the data buffer unit in real time. This effective data volume represents the amount of firmware data accumulated in the current data buffer unit.

[0089] Furthermore, the transmission control unit can generate a transmission command based on the effective data volume. This transmission command is crucial for guiding subsequent data transmission / transfer, and it contains the starting read address of the firmware data to be transmitted in the data buffer unit (usually indicated by the current read pointer) and the data transmission length (usually equal to the effective data volume). This means that the system does not mechanically fix the transmission length, but flexibly formulates a transmission plan based on the currently accumulated data volume.

[0090] Following this, the data transmission unit, acting as the specific execution mechanism, receives the transmission command sent by the transmission control unit and performs data transmission accordingly. Specifically, the data transmission unit accurately retrieves the firmware data to be transmitted from the data buffer unit based on the starting read address and data transmission length in the transmission command.

[0091] It is worth noting that after acquiring the firmware data for this transmission, the data transmission unit generates a write transmission request containing burst transmission parameters based on this firmware data. These burst transmission parameters are defined by the bus protocol and "inform" the bus that this transmission is a continuous batch write. In other words, the data transmission unit packages the fragmented firmware data into efficient burst write operation packets for simultaneous transmission through the bus.

[0092] In this embodiment of the invention, dynamic data transmission is achieved through the coordinated cooperation of the transmission control unit and the data transmission unit. That is, the most matching transmission instruction can be intelligently generated based on the current effective data volume of the data buffer unit and encapsulated as a burst transmission request to achieve efficient data transmission. This not only makes full use of the burst transmission bandwidth of the bus and avoids the bus arbitration overhead caused by a single small data volume transmission, but also ensures the real-time performance of data transfer and avoids unnecessary delays caused by waiting for the buffer to be full.

[0093] Based on the above embodiments, the data transmission unit is configured to set the transmission length in the burst transmission parameters to the maximum burst length when the data transmission length is greater than or equal to the maximum burst length allowed by the bus; and to set the transmission length in the burst transmission parameters to the data transmission length when the data transmission length is less than the maximum burst length.

[0094] Specifically, to ensure that the generated write transfer requests can make full use of the bus bandwidth and strictly comply with the bus protocol specifications, a key parameter needs to be considered in this embodiment of the invention, namely, the transfer length in the transmission parameters.

[0095] In detail, after receiving a transmission command, the data transmission unit will compare the data transmission length in the transmission command, that is, the amount of firmware data accumulated in the current data buffer unit, with the maximum burst length allowed by the bus, that is, the upper limit of a single burst transmission specified by the bus protocol, in real time.

[0096] Furthermore, if the data transmission length is greater than or equal to the maximum burst length, it means that the amount of data accumulated in the current data buffer unit is sufficient to support a full-load transmission. In this case, to achieve the highest transmission efficiency, the data transmission unit will set the transmission length in the burst transmission parameters to the maximum burst length. This is analogous to a truck: although the warehouse is piled high with goods (data), the truck can only carry its maximum capacity (maximum burst length) at a time. Therefore, this departure is configured to be at full capacity, and the remaining data will be reserved for the next transmission.

[0097] Conversely, if the data transmission length is less than the maximum burst length, it means that the amount of data accumulated in the current data buffer unit is insufficient for a full-load transmission, or that this is the last remaining piece of firmware data to be transmitted. In this case, to avoid unnecessary waiting delays, the data transmission unit will flexibly set the transmission length in the burst transmission parameters directly to the data transmission length. This means that the system is implementing a "send as much as you can" strategy, ensuring that these scattered pieces of firmware data can also be packaged and sent out in a timely manner.

[0098] In this embodiment of the invention, an adaptive length configuration mechanism based on effective data volume and bus constraints achieves a balance between full utilization of bus bandwidth and protocol compatibility. When data is sufficient, the maximum burst length is used for data transmission to maximize throughput; while when data is fragmented, small packet transmission is switched to ensure the real-time nature of data flow, thereby effectively avoiding transmission errors caused by violations of the bus protocol, and also eliminating startup delays caused by waiting for data to be rounded up.

[0099] The present invention also provides a data processing method, which is applied to data loading scenarios during chip startup or runtime. Figure 5 This is a flowchart illustrating the data processing method provided by the present invention. This method is applied to the data processing system described in any of the preceding claims, such as... Figure 5 As shown, the method includes:

[0100] Step 510: Read firmware data from external memory and generate a write transfer request based on the read firmware data;

[0101] Step 520: Write firmware data based on the write transfer request for chip startup or operation.

[0102] Specifically, during data processing, the first step is to actively generate read and write transfer requests for firmware data. That is, the interface control unit inside the chip no longer passively waits for instructions from the main control unit, but actively accesses external memory, such as Flash, to continuously read firmware data, such as the Bootloader program, microkernel code, microcode, and various configuration instruction sets.

[0103] After reading the firmware data, in this embodiment of the invention, the data is not simply piled up in the data buffer unit, but is immediately subjected to protocol conversion processing. Specifically, the interface control unit dynamically generates a write transfer request based on the currently accumulated data volume and the read firmware data. This write transfer request encapsulates the data read address, data transfer length, and firmware data, preparing for subsequent data writing.

[0104] Next, the generated write transfer request is sent to the target memory unit via the chip's internal bus. The target memory unit is the internal storage space within the chip used to store the program or data to be executed, such as static random access memory, tightly coupled memory, or on-chip cache. The target memory unit can respond to the request and directly write the firmware data carried in the request into its internal storage space.

[0105] As firmware data is continuously written to the target memory unit, the chip's internal processing cores, such as the MCU, do not need to participate in the data transfer process. They only need to fetch instructions directly from the target memory unit to execute once the data is ready. Thus, this firmware data, which is transferred in at high speed, is ultimately used for chip startup or operation, completing a seamless transfer from external non-volatile memory to internal high-speed execution space.

[0106] The data processing method provided by this invention breaks the inefficient cycle of polling and reading by the main control unit in the traditional solution. It can directly and actively write external firmware data into the on-chip target storage unit, realizing a fundamental change in the data transfer mode. This not only greatly reduces the load on the main control unit and avoids pipeline blockage caused by waiting for data, but also utilizes the burst transmission capability of the bus through active write transmission requests, significantly shortening the chip startup time and improving the overall response speed of the system.

[0107] Based on the above embodiments, step 510, which generates a write transfer request based on the read firmware data, includes:

[0108] Write the read firmware data into the data buffer unit;

[0109] If the total amount of data sent has not reached the target amount of data, determine the effective amount of data in the data buffer unit; the total amount of data sent is the total amount of firmware data corresponding to the cumulative write transmission requests initiated, and the target amount of data is the preset amount of firmware data to be transmitted.

[0110] A transmission instruction is generated based on the effective data volume. The transmission instruction includes the starting read address and data transmission length of the firmware data corresponding to the effective data volume of this transmission in the data buffer unit.

[0111] Based on the transmission command, the firmware data for this transmission is obtained from the data buffer unit, and a write transmission request containing burst transmission parameters is generated based on the firmware data.

[0112] Specifically, the process of generating a write transfer request based on the read firmware data can include:

[0113] When the interface control unit continuously reads data from external memory, it does not immediately forward the data mechanically. Instead, it first writes the read firmware data into the data buffer unit. This process is equivalent to establishing a buffer at the chip interface to smooth out the difference between the external read speed and the internal bus transmit speed, ensuring that the continuous data stream is not lost due to momentary congestion.

[0114] While continuously writing the read firmware data to the data buffer unit, the overall progress of the data transfer task is monitored in real time, that is, the total amount of data sent is compared with the target total amount of data. The target total amount of data is the total amount of firmware data that needs to be transferred from external storage in this startup or configuration process; the total amount of data sent is the total amount of firmware data included in the cumulative write transfer requests initiated to the target storage unit so far.

[0115] If the total amount of data sent has not reached the target amount, the data transfer task is not yet complete. At this point, it's necessary to determine how much data to send next. That is, to determine the effective data volume in the data buffer unit, which represents the amount of firmware data accumulated in the current data buffer unit. After this, a transmission command can be generated based on this effective data volume. This command includes the starting address of the firmware data corresponding to the effective data volume to be sent in the data buffer unit (i.e., where to start retrieving the data) and the specific data transmission length (i.e., how much to retrieve this time, usually equal to the effective data volume). This means that the data transmission / transfer process is not mechanically fixed in terms of transmission length, but rather flexibly plans the transmission based on the currently accumulated data volume.

[0116] Then, according to the transmission command, the firmware data to be transmitted can be accurately retrieved from the data buffer unit. The retrieved firmware data can be encapsulated according to the protocol to generate a write transmission request containing burst transmission parameters. The burst transmission parameters here are parameters defined based on the bus protocol, which can ensure that the corresponding firmware data can be written to the target storage unit efficiently and continuously through the bus in the form of burst transmission.

[0117] In this embodiment of the invention, the size of the data packet for each transmission is dynamically adjusted according to the current data accumulation in the buffer and the remaining task volume. This not only ensures that the bus bandwidth can be fully utilized for efficient burst transmission when there is sufficient data, but also ensures that the remaining data can be accurately processed when the data is scattered or the task is about to end. Thus, while ensuring the correctness of transmission, the throughput and flexibility of data transfer are maximized.

[0118] The data processing apparatus provided by the present invention will be described below. The data processing apparatus described below can be referred to in correspondence with the data processing method described above.

[0119] Figure 6This is a schematic diagram of the data processing device provided by the present invention, as shown below. Figure 6 As shown, the apparatus is applied to a data processing system as described in any of the preceding claims, the apparatus comprising:

[0120] The reading module 610 is used to read firmware data from an external memory and generate a write transfer request based on the read firmware data;

[0121] Storage module 620 is used to write firmware data based on the write transfer request for chip startup or operation.

[0122] The data processing device provided by this invention breaks away from the inefficient cycle of polling and reading by the main control unit in traditional solutions. It can directly and actively write external firmware data into the on-chip target storage unit, realizing a fundamental change in the data transfer mode. This not only greatly reduces the load on the main control unit and avoids pipeline blockage caused by waiting for data, but also utilizes the burst transmission capability of the bus through active write transmission requests, significantly shortening the chip startup time and improving the overall response speed of the system.

[0123] Based on the above embodiments, the reading module 610 is used for:

[0124] Write the read firmware data into the data buffer unit;

[0125] If the total amount of data sent has not reached the target amount of data, the effective amount of data in the data buffer unit is determined; the total amount of data sent is the total amount of firmware data corresponding to the cumulative write transmission requests initiated, and the target amount of data is the preset amount of firmware data to be transmitted.

[0126] A transmission instruction is generated based on the effective data volume. The transmission instruction includes the starting read address and data transmission length of the firmware data corresponding to the effective data volume being transmitted in the data buffer unit.

[0127] Based on the transmission command, the firmware data for this transmission is obtained from the data buffer unit, and a write transmission request containing burst transmission parameters is generated based on the firmware data.

[0128] Figure 7 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 7As shown, the electronic device may include a processor 710, a communications interface 720, a memory 730, and a communication bus 740, wherein the processor 710, communications interface 720, and memory 730 communicate with each other via the communication bus 740. The processor 710 can invoke logical instructions in the memory 730 to execute a data processing method. This method is applied to the data processing system described in any of the preceding claims. The method includes: reading firmware data from an external memory and generating a write transfer request based on the read firmware data; and writing the firmware data based on the write transfer request for chip startup or operation.

[0129] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0130] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, wherein when the program instructions are executed by a computer, the computer is able to execute the data processing method provided by the above methods, the method being applied to a data processing system as described in any of the above claims, the method comprising: reading firmware data from an external memory and generating a write transfer request based on the read firmware data; and writing the firmware data based on the write transfer request for chip startup or operation.

[0131] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the data processing methods provided by the methods described above. The method is applied to a data processing system as described in any of the preceding claims, and includes: reading firmware data from an external memory and generating a write transfer request based on the read firmware data; and writing the firmware data based on the write transfer request for use by the chip to start or run.

[0132] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0133] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing system, characterized in that, Applied to chips, including: An interface control unit is used to read firmware data from an external memory and generate a write transfer request for the firmware data; the interface control unit has active data transfer capability and can actively write the firmware data into the chip. The target storage unit is connected to the interface control unit via a bus, and is used to receive the write transfer request transmitted by the interface control unit via the bus, and write the firmware data based on the write transfer request for the chip to start or run. The interface control unit is also configured with a write pointer and a read pointer; the interface control unit includes: The data buffer unit is configured as a multi-row storage structure, with each row of storage structure associated with a valid bit identifier, for temporarily storing the firmware data read from the external memory; A buffer management unit is used to write the read firmware data line by line into the data buffer unit and set the associated valid bit identifier, and to clear the associated valid bit identifier after the write transfer request is transmitted to the target storage unit through the bus. A transmission control unit, connected to the buffer management unit, is used to determine the effective amount of data in the data buffer unit based on the write pointer and the read pointer when the total amount of data sent has not reached the target total amount of data; and to generate a transmission instruction based on the effective amount of data. The data transmission unit is used to receive the transmission command sent by the transmission control unit, obtain the firmware data to be transmitted in this transmission from the data buffer unit based on the transmission command, and generate the write transmission request containing burst transmission parameters based on the firmware data.

2. The data processing system according to claim 1, characterized in that, The write pointer points to the row address of the currently temporarily stored data in the data buffer unit, and the read pointer points to the row address of the currently pending data in the data buffer unit; The buffer management unit is configured to write the firmware data to the data buffer unit based on the write pointer and update the write pointer, and read the firmware data from the data buffer unit based on the read pointer to generate the write transfer request and update the read pointer.

3. The data processing system according to claim 1, characterized in that, The total amount of data sent is the total amount of firmware data corresponding to the write transmission requests that the interface control unit has initiated to the target storage unit, and the total amount of target data is the preset total amount of firmware data to be transmitted. The transmission instruction includes the starting read address and data transmission length of the firmware data corresponding to the effective data volume transmitted in this transmission in the data buffer unit.

4. The data processing system according to claim 3, characterized in that, The data transmission unit is configured to set the transmission length in the burst transmission parameters to the maximum burst length when the data transmission length is greater than or equal to the maximum burst length allowed by the bus; and to set the transmission length in the burst transmission parameters to the data transmission length when the data transmission length is less than the maximum burst length.

5. A data processing method, characterized in that, Applied to the data processing system as described in any one of claims 1 to 4, the method comprises: Read firmware data from external storage and generate a write transfer request based on the read firmware data; The firmware data is written based on the write transfer request for use by the chip during startup or operation.

6. The data processing method according to claim 5, characterized in that, The step of generating a write transfer request based on the read firmware data includes: Write the read firmware data into the data buffer unit; If the total amount of data sent has not reached the target amount of data, the effective amount of data in the data buffer unit is determined; the total amount of data sent is the total amount of firmware data corresponding to the cumulative write transmission requests initiated, and the target amount of data is the preset amount of firmware data to be transmitted. A transmission instruction is generated based on the effective data volume. The transmission instruction includes the starting read address and data transmission length of the firmware data corresponding to the effective data volume being transmitted in the data buffer unit. Based on the transmission command, the firmware data for this transmission is obtained from the data buffer unit, and a write transmission request containing burst transmission parameters is generated based on the firmware data.

7. A data processing apparatus, characterized in that, The apparatus is applied to the data processing system as described in any one of claims 1 to 4, the apparatus comprising: The read module is used to read firmware data from external storage and generate a write transfer request based on the read firmware data; The storage module is used to write the firmware data based on the write transfer request for use by the chip during startup or operation.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the data processing method as described in claim 5 or 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data processing method as described in claim 5 or 6.

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