Bus sharing for running hammer mitigation alerts

Abstract

The invention relates to bus sharing for hammer mitigation alerts. Systems, apparatus, and methods for a shared one-way bus for transferring commands from a controller to a memory and transferring target refresh alerts from a memory device to the controller. The memory includes shared bus logic circuitry for managing transmission of target refresh alerts and reception of commands on a shared bidirectional bus. The controller also includes shared bus logic circuitry for managing transmission of commands and reception of target refresh alerts from one or more memory devices coupled to the controller through one or more shared bidirectional buses. Each of the one or more shared bidirectional buses may transmit a different command, such as a reset command or a calibration command, to the one or more memory devices.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to memory devices. Background Technology

[0002] Specifically, this disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information is stored in memory on memory cells as physical signals (e.g., charge on capacitive elements). Information can decay in memory cells over time. For example, memory cells can discharge over time. To maintain the integrity of the stored information, memory cells can be refreshed to, for example, restore the initial charge level associated with the stored information.

[0003] Certain access patterns can cause an increased rate of information decay in nearby memory cells (e.g., memory cells along nearby word lines). Memory devices can use various schemes to identify these access patterns, enabling a target refresh operation. To initiate a target refresh operation, the memory device can send an alert to the controller. Summary of the Invention

[0004] Embodiments of this disclosure provide a system comprising: a controller; a memory; and a shared bidirectional bus, wherein the shared bidirectional bus is coupled between the controller and the memory, and wherein the controller is configured to transmit commands on the shared bidirectional bus, and the memory is configured to transmit target refresh alarms on the shared bidirectional bus.

[0005] Another embodiment of this disclosure provides an apparatus comprising: a shared bus logic circuit configured to receive commands and transmit a target refresh alarm on a shared bidirectional bus; and a refresh control circuit coupled to the shared bus logic circuit, wherein the refresh control circuit is configured to perform a refresh operation and cause the shared bus logic circuit to transmit the target refresh alarm.

[0006] Another embodiment of this disclosure provides a method comprising: transmitting a target refresh alarm by the memory device on the shared bidirectional bus in response to determining that the memory device should perform a target refresh operation; receiving a command on the shared bidirectional bus from a controller coupled to the shared bidirectional bus; and performing the operation according to the command. Attached Figure Description

[0007] Figure 1 This is a block diagram of a system according to at least one embodiment of the present disclosure.

[0008] Figure 2 This is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure.

[0009] Figure 3 This is a schematic diagram of a shared bus RHR logic circuit that can be included on a memory device according to at least one embodiment of the present disclosure.

[0010] Figure 4 This is a schematic diagram of a shared bus RHR logic circuit that can be included on a controller according to at least one embodiment of the present disclosure.

[0011] Figure 5 This is a timing diagram of the instance behavior of a signal according to at least one embodiment of the present disclosure.

[0012] Figure 6 This is a block diagram of a system according to at least one embodiment of the present disclosure.

[0013] Figure 7 This is a block diagram of an arbitrator circuit according to some embodiments of the present disclosure.

[0014] Figure 8 This is a timing diagram of the instance behavior of a signal according to at least one embodiment of the present disclosure.

[0015] Figure 9 This is a block diagram of refresh management (RFM) logic circuitry according to some embodiments of the present disclosure.

[0016] Figure 10 This is a flowchart of a method according to some embodiments of the present disclosure.

[0017] Figure 11 This is a flowchart of a method according to some embodiments of the present disclosure. Detailed Implementation

[0018] Certain details are set forth below to provide a full understanding of examples of this disclosure. However, those skilled in the art will appreciate that examples of this disclosure can be practiced without these specific details. Furthermore, the specific examples of this disclosure described herein should not be construed as limiting the scope of this disclosure to those specific examples. In other examples, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail to avoid unnecessarily obscuring this disclosure. Additionally, terms such as “coupled” and “via coupled” mean, for example, that two components can be electrically coupled directly or indirectly. Indirect coupling may imply that two components are coupled through one or more intermediate components.

[0019] Information in a memory array contained on a memory device can be accessed via one or more access operations (e.g., read or write operations). During an instance access operation, a word line can be activated based on a row address. Then, selected memory cells along this activated word line can have their information read or written based on which bit lines are selected. Bit lines can be selected based on column addresses. The memory array can be refreshed row by row (e.g., as part of an auto-refresh and / or self-refresh mode), where memory cells along each row are refreshed periodically. Rows can be refreshed as part of a normal refresh or self-refresh mode. The rate at which rows are refreshed can be determined based on the expected information decay rate (e.g., the longest time any given row will elapse between refreshes). In other words, the longest time any given row will elapse between refreshes is calculated to be less than the expected amount of time required for information decay in the row.

[0020] Various access patterns to a row (e.g., an aggressor row) can lead to an increased rate of information decay in nearby memory cells (e.g., along the victim row). For example, a "row hammer" can involve repeated accesses to an aggressor row, which increases the decay rate of neighboring (and / or more distant) rows. Therefore, the memory array can track the number of accesses to each row to determine if it is an aggressor, so that the victim row can be identified and refreshed as part of a targeted refresh operation.

[0021] During a target refresh operation, the memory device may need to send a refresh command to the controller. The memory device can be connected to the controller via multiple buses. Each bus can be a conductive element that couples a corresponding terminal or "pin" between the memory device and the controller. The bus can carry signals in voltage form along the conductive element. Multiple buses can exist to carry various types of signals, such as command / address buses, data buses, clock buses, and the like. Some buses can be unidirectional, meaning that the bus carries signals only in one direction. For example, a unidirectional bus can only carry signals from the controller to the memory device. Some buses can be bidirectional, meaning that they carry signals in both directions. For example, the controller and the memory device can use a bidirectional bus to transmit and receive signals to each other.

[0022] The controller can use the bus to send signals to the memory device instructing it to perform operations. These signals from the controller to the memory device can be commands. The memory device can use the bus to send alarms or signals to the controller indicating its status or requesting commands. For example, the memory device can transmit a refresh alarm requesting a refresh command to the controller. Using an existing bus to carry refresh alarms can be useful to avoid adding an additional bus.

[0023] This disclosure relates to apparatus, systems, and methods for transmitting target refresh alarms on a bus, which is also used to transmit commands. In other words, the bus is shared by target refresh alarms and other commands transmitted using the bus. The shared bus is bidirectional. The shared bus carries target refresh alarms transmitted from a memory device to a controller and carries commands transmitted from the controller to the memory device. The shared bidirectional bus is used to carry commands from the controller to the memory device and to carry target refresh alarms from the memory device to the controller. In some embodiments, the command may be a reset command. In a conventional memory device, a reset command may be carried along a first unidirectional bus and the target refresh alarm may be carried along a second separate bus.

[0024] To prevent conflicts, the controller and memory may include corresponding shared bus logic to manage different signals. The shared bus logic can prioritize some signals over others along the bus. In an example implementation where the bus is used for both target refresh alarms and reset commands, the reset command may have a higher priority than the target refresh alarm. For example, if the controller begins providing a reset command along the shared bus when the memory shared bus logic provides a target refresh alarm, then the reset command may override the target refresh alarm and be passed through the memory shared bus logic to the memory's reset logic.

[0025] Figure 1This is a block diagram of a system according to at least one embodiment of the present disclosure. System 100 includes a controller 102 and a memory device 104. In some embodiments of the present disclosure, the memory device 104 may be dynamic random access memory (DRAM), such as low-power double data rate (LPDDR) DRAM. The controller 102 and the memory device 104 communicate via several buses. For example, a command / address (C / A) bus, a data bus (not shown), and / or a clock bus (not shown) may couple the memory device 104 to the controller 102. The controller 102 may transmit commands to the memory device 104, and in response to transmitting commands, the memory device 104 may perform operations. In some embodiments, the controller 102 may transmit commands to the memory device 104 on a command / address (C / A) bus 140, such as refresh management (RFM) commands. Other buses may also couple the controller 102 to the memory device 104 to carry other types of signals, such as a reset bus or a calibration bus that carries reset commands or calibration commands, respectively. In some embodiments, the reset bus RESET_n is coupled to the controller 102 and the memory device 104 and is used to transmit a reset command RST from the controller to the memory. Some buses may be bidirectional buses that carry more than one signal in more than one direction. System 100 may include a shared bidirectional bus 142 that couples the controller 102 to the memory 104, which carries alarms from the memory 104 to the controller 102 and also carries commands from the controller 102 to the memory 104. Each of the buses may include one or more signal lines on which signals are provided. For example, a shared bidirectional bus may include a single conductive element (e.g., the bus has a width of one bit). In some embodiments, the C / A bus 140 may include more signal lines than the shared bidirectional bus 142. For example, the shared bidirectional bus 142 may be a single signal line, while the C / A bus 140 includes multiple signal lines.

[0026] Controller 102 may include RHR circuitry 110. RHR circuitry 110 may transmit an RFM command to memory device 104 causing memory device 104 to perform a target refresh operation. For example, RHR circuitry 110 may transmit the RFM command to memory device 104 via command / address (C / A) bus 140. Memory device 104 may perform a target refresh operation in response to the RFM command. Controller 102 may transmit RFM commands in response to signals received from memory device 104. For example, when memory device 104 determines that it should perform a target refresh operation, memory device 104 may transmit an alarm, such as a target refresh alarm RHR_Alert, to controller 102. In response to the target refresh alarm RHR_Alert, controller 102 may issue an RFM command to memory device 104.

[0027] Controller 102 may include shared bus RHR logic 112. In some embodiments, shared bus RHR logic 112 may manage multiple signals transmitted on a bidirectional bus. In other words, the bidirectional bus is used for at least one alarm from memory device 104 to controller 102 and at least one command from controller 102 to memory device 104. For example, system 100 may include a shared bidirectional bus 142 coupling controller 102 to memory device 104. Controller 102 may transmit commands to memory device 104 on shared bidirectional bus 142, and memory device 104 may also transmit alarms to controller 102 on shared bidirectional bus 142. In some embodiments, shared bidirectional bus 142 may be a RESET_n bus and controller 102 uses it to transmit a reset command RST to memory device 104. Controller 102 may transmit the reset command RST to memory device 104 to reset the memory. When memory device 104 determines that it should perform a target refresh operation, the memory device may also use the shared bidirectional bus RESET_n to transmit a target refresh alarm RHR_Alert to the controller.

[0028] The shared bidirectional bus 142 may be coupled to the shared bus RHR logic circuit 112 on the controller 102. The shared bus RHR logic circuit 112 may contain logic that prioritizes signals transmitted and received by the controller 102 on the shared bidirectional bus 142. For example, when the memory device 104 provides a target refresh alarm RHR_Alert along the shared bidirectional bus 142, if the controller 102 begins to provide a reset command RST along the shared bidirectional bus 142, then the reset command RST may override the target refresh alarm RHR_Alert.

[0029] The reset command RST may originate from the reset control circuitry 114 included in the controller 102. The reset control circuitry 114 may contain logic that resets the memory device 104 by transmitting the reset command RST and a reset enable signal RST_EN to the shared bus RHR logic circuitry 112 of the controller 102. Based on these signals, the shared bus RHR logic circuitry 112 of the controller 102 then transmits the reset command RST to the memory device 104 to initiate a reset operation. In some embodiments, the reset command RST is transmitted to the memory device 104 via the shared bus RHR logic circuitry 112 of the controller 102 on a shared bidirectional bus 142.

[0030] Memory device 104 may include shared bus RHR logic circuitry 122 coupled to shared bidirectional bus 142. Shared bus RHR logic circuitry 122 of memory device 104 may contain logic managing signals transmitted and received by memory device 104 on shared bidirectional bus 142. For example, when memory device 104 provides a target refresh alarm RHR_Alert along shared bidirectional bus 142, shared bus RHR logic circuitry 112 of controller 102 may transmit a row hammer (RH) relief enable RH_M_En signal to RHR circuitry 110, thereby causing RHR circuitry to transmit an RFM command to memory device 104. If controller 102 begins providing a reset command RST along shared bidirectional bus 142 when memory device 104 provides a target refresh alarm RHR_Alert, then the reset command RST may override the logic of shared bus RHR logic circuitry 122 of memory device 104. In some embodiments, if the shared bus RHR logic circuit 122 of memory device 104 receives a command to override its logic (e.g., a reset command RST) on the shared bidirectional bus 142, the command is passed to the reset control circuit 124, which may also be included on memory device 104. The reset control circuit 124 of memory device 104 manages the reset operation of memory device 104 in response to the reset command RST.

[0031] The memory device 104 may also include refresh control circuitry 120. Refresh control circuitry 120 can perform refresh operations. For example, refresh control circuitry 120 can perform a target refresh operation in response to an RFM command from controller 102. In some embodiments, when the memory device 104 determines that it should perform a target refresh operation, refresh control circuitry 120 can transmit a target refresh alarm RHR_Alert. Target refresh alarm RHR_Alert can be transmitted to shared bus RHR logic circuitry 122 of the memory device 104. Shared bus RHR logic circuitry 122 of the memory device 104 can then transmit the target refresh alarm RHR_Alert to controller 102 on a shared bidirectional bus 142 based on its logic. In response to the target refresh alarm RHR_Alert, controller 102 can issue an RFM command to memory device 104 along C / A bus 140 coupled to refresh control circuitry 120.

[0032] Figure 2 This is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. Semiconductor device 200 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. In some embodiments, semiconductor device 200 may be... Figure 1 An implementation scheme of the memory device 104 in the middle.

[0033] Semiconductor device 200 includes memory array 218. Memory array 218 is shown as comprising multiple memory banks. Figure 2 In one embodiment, memory array 218 is shown to include memory banks BANK0 to BANK7. The number of memory banks in memory array 218 may be, for example, 4, 8, 16, or 32. More or fewer memory banks may be included in memory array 218 in other embodiments. Each memory bank includes multiple word lines WL (rows), multiple bit lines BL (columns), and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL.

[0034] Some memory cells can be reserved as counter memory cells 226. The counter memory cells can store count values ​​XCount, each of which is associated with a word line. Each count value XCount can be stored in the counter memory cell 226 along the word line associated with it. The count value XCount can be stored as a binary number, with each bit stored in the memory cell along the word line. For clarity, Figure 2 The image shows a single bit line of counter memory cell 226. However, the number of counter memory cells along each word line can be based on the number of bits of the count value XCount.

[0035] The selection of word line WL is performed by row decoder 208, and the selection of bit line BL is performed by column decoder 210. Figure 2 In this embodiment, row decoder 208 includes a corresponding row decoder for each memory bank, and column decoder 210 includes a corresponding column decoder for each memory bank. Bit line BL is coupled to a corresponding sense amplifier (not shown). Data read from bit line BL is amplified by the sense amplifier and transmitted to read / write amplifier 220 via complementary local data lines (not shown), a gate (not shown), and a complementary main data line (not shown). Conversely, write data output from read / write amplifier 220 is transmitted to the sense amplifier and written to memory cell MC coupled to bit line BL via complementary main data lines, a gate, and complementary local data lines. Information can generally be read from and written to counter memory cell 226 in a similar manner, except that data in counter memory cell 226 is read and written by refresh control circuitry 216.

[0036] Semiconductor device 200 may employ multiple external terminals, including those coupled to command and address buses (e.g., Figure 1The 140) includes a command and address (C / A) terminal for receiving command and address and CS signals, a clock terminal for receiving clock CK and / or CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. In some embodiments, the semiconductor device 200 may include a data I / O terminal or pin RESET_n for receiving data from a controller (e.g., Figure 1 102) Receives a command (e.g., a reset command RST) and transmits an alarm (e.g., a target refresh alarm RHR_Alert) to the controller.

[0037] The clock terminal is supplied with an external clock CK and / CK to the input circuit 212. The external clocks may be complementary. The input circuit 212 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 206 and the internal clock generator 214. The internal clock generator 214 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 222 to time the operation of circuits contained in the input / output (IO) circuit 222, for example, to the data receiver to time the receipt of written data.

[0038] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 204 via the command / address input circuit 202. The address decoder 204 receives the address and supplies the decoded row address XADD to the row decoder 208 and the decoded column address YADD to the column decoder 210. The address decoder 204 may also supply a decoded memory bank address BADD, which indicates the memory bank of the memory array 218 containing the decoded row address XADD and column address YADD. The C / A terminal may be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. The C / A terminal may be supplied with refresh commands, such as refresh management (RFM) commands (e.g., refresh commands for performing write operations). Figure 1 (RFM). Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell to be accessed.

[0039] Commands can be provided as internal command signals to command decoder 206 via command / address input circuitry 202. Command decoder 206 includes circuitry that decodes the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 206 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0040] The semiconductor device 200 can receive an access command as a row activation command ACT. When the row activation command ACT is received, the memory address BADD and the row address XADD are supplied together with the row activation command ACT in a timely manner.

[0041] Semiconductor device 200 can receive access commands as read commands. When a read command is received, the bank address BADD and column address YADD are supplied along with the read command, and read data is read from the memory cells in memory array 218 corresponding to row address XADD and column address YADD. The read command is received by command decoder 206, which provides an internal command that causes the data read from memory array 218 to be provided to read / write amplifier 220. The read data is output to the outside via input / output circuit 222 from data terminal DQ. The access count Xcount stored in the counter memory cell 226 of the row associated with row address XADD is read to refresh control circuit 216, and the updated value of access count Xcount (not shown) is written back to the counter memory cell 226 of row XADD.

[0042] Semiconductor device 200 can receive access commands as write commands. When a write command is received, the bank address BADD and column address YADD are supplied along with the write command in a timely manner, and the write data supplied to the data terminal DQ is written to the memory cells in memory array 218 corresponding to the row address and column address. The write command is received by command decoder 206, which provides an internal command causing the write data to be received by the data receiver in input / output (I / O) circuit 222. A write clock can also be provided to an external clock terminal for timing the data receiver in input / output circuit 222 to receive the write data. The write data is supplied to read / write amplifier 220 via input / output circuit 222 and then to memory array 218 by read / write amplifier 220 to be written to memory cell MC. Similar to the read operation described above, the access count Xcount stored in the counter memory cell 226 of the row associated with row address XADD is read by refresh control circuit 216, and the updated value of access count Xcount is written back to the counter memory cell 226 of row XADD.

[0043] The semiconductor device 200 may also receive commands that cause it to perform one or more refresh operations. For example, in response to a refresh command, the command decoder 206 may provide a refresh signal such as REF, RFM, or a combination thereof. In response to a refresh command received from the controller, the refresh control circuit 216 performs one or more normal refresh operations, one or more target refresh operations, or a combination thereof. In response to an RFM command received from the controller, the refresh control circuit 216 performs one or more target refresh operations.

[0044] The refresh signal REF is supplied to the refresh control circuit 216. The refresh control circuit 216 (e.g.) Figure 1 The refresh line address RXADD is supplied to the line decoder 208, which refreshes the word line WL indicated by the refresh line address RXADD. The refresh control circuit 216 controls the timing of the refresh operation and generates and provides the refresh address RXADD. The refresh control circuit 216 can be controlled to change the details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address), or it can operate based on internal logic.

[0045] The refresh control circuit 216 can selectively output a target refresh address (e.g., a victim address) or a normal refresh address as the refresh address RXADD. The normal refresh address can be an address sequence provided based on the activation of the refresh signal REF. The refresh control circuit 216 can cycle through the refresh address sequence at a rate determined by REF. In some embodiments, the refresh address sequence can include all addresses in the memory bank 218. In some embodiments, the refresh signal REF can be emitted at a frequency that refreshes most or all addresses in the memory bank 218 within a certain time period, based on the expected rate of information decay in the memory cell MC.

[0046] The refresh control circuit 216 can also determine the target refresh address (e.g., the victim address corresponding to the victim row) as the address to be refreshed based on the access patterns of nearby addresses in the memory array 218 (e.g., the aggressor address associated with the aggressor row). The refresh control circuit 216 can monitor accesses to different word lines WL of the memory bank. When the row decoder 208 sends an access command to a specific row, the counter memory cell 226 along that row can read its information as the access count Xcount into the refresh control circuit 216. The refresh control circuit 216 can determine the access count of the row based on the value stored in the counter memory cell 226 of the accessed row.

[0047] Refresh control circuitry 216 can determine whether an accessed row is an aggressor row based on the access count from counter memory unit 226. If the current row is not an aggressor row, the access count value can be changed, and refresh control circuitry 216 can then write the new value of the access count back to the counter memory unit 226 of the accessed row. If refresh control circuitry 216 determines that the accessed row is an aggressor, then refresh control circuitry 216 can use the row address XADD of the accessed row to determine one or more victim row addresses and provide them as refresh address RXADD as part of the target refresh operation. When an accessed row is determined to be an aggressor, the access count Xcount associated with this row can be reset (e.g., reset to a minimum value, such as 0). In some embodiments, refresh control circuitry 216 can queue the identified aggressor addresses (e.g., in an aggression queue) for later use in the target refresh operation.

[0048] The memory device 200 can indicate to the controller that a target refresh operation is needed. For example, if the intrusion queue contains more than a threshold number of memory addresses. To initiate a target refresh operation, the refresh control circuit 216 can indicate to the shared bus RHR logic circuit 230 (e.g., Figure 1 122) Issue a target refresh alarm RHR_Alert. In response to the target refresh alarm RHR_Alert, the controller may issue an RFM command, causing the memory 200 to perform one or more target refresh operations. In some embodiments, the target refresh alarm RHR_Alert may be one or more pulses or pulse trains. For example, the target refresh alarm RHR_Alert may consist of two pulses. The first pulse may instruct the controller to begin issuing one or more RFM commands, and the second pulse may instruct the controller to stop issuing RFM commands.

[0049] In some embodiments, the shared bus RHR logic circuit 230 may be included in the command address input circuit 202, such as Figure 2 As shown. In response to receiving a target refresh alarm RHR_Alert from refresh control circuitry 216, shared bus RHR logic circuitry 230 may, for example, be connected via a shared bidirectional bus (e.g., Figure 1 142) to the controller (e.g. Figure 1 102) Transmit target refresh alarm. In some embodiments, a shared bidirectional bus (e.g.) Figure 1 (142) can be coupled to the I / O pin RESET_n. In some implementations, the shared bus RHR logic circuit 230 can also be connected via a shared bidirectional bus (e.g., Figure 1 142) receives external command signals, such as the reset command RST. In response to the reset command RST, the shared bus RHR logic circuit 230 will send a signal to the reset control logic circuit 232 (e.g., Figure 1The 124) issues a reset command RST to perform a reset operation on the semiconductor device 200. In some embodiments, the shared bidirectional bus may be connected to other pins or terminals on the memory device and configured to receive other external commands. For example, the shared bidirectional bus may be connected to the ZQ of the memory device and configured to receive commands from the controller (e.g., Figure 1 102) Receive calibration command.

[0050] The power supply terminals are supplied with power supply potentials VDD and VSS. These potentials VDD and VSS are supplied to the internal voltage generator circuit 224. The internal voltage generator circuit 224 generates various internal potentials VPP, VOD, VARY, VPERI, and similar values ​​based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in the line decoder 208, internal potentials VOD and VARY are primarily used in the sense amplifiers included in the memory array 218, and internal potential VPERI is used in many peripheral circuit blocks. The power supply terminals also supply power supply potentials VDDQ and VSSQ. These potentials VDDQ and VSSQ are supplied to the input / output circuit 222.

[0051] Figure 3 This is a schematic diagram of a shared bus RHR logic circuit that can be included on a memory device according to at least one embodiment of the present disclosure. Circuit 300 may be... Figure 1 Shared bus RHR logic circuit 122 and / or Figure 2 The implementation plan of 230.

[0052] Circuit 300 can be configured to manage on the shared bidirectional bus RESET_n (e.g. Figure 1 142) from memory device (e.g. Figure 1 104 and / or Figure 2 The circuit 300 transmits and receives signals from the memory device. In other words, the circuit 300 can share a bidirectional bus (e.g., ...). Figure 1 The signal is transmitted and received on (142). In some embodiments, the received signal may be from the controller (e.g., Figure 1 The command (e.g., reset command RST) of 102) and the transmitted signal may be an alarm (e.g., target refresh alarm RHR_ALERT).

[0053] Circuit 300 can be configured to allow memory devices (e.g.) Figure 1 The memory device 104 and / or Figure 2 The semiconductor device 200 transmits signals on a shared bidirectional bus, which is coupled to pins or terminals configured to receive external signals. For example, a shared bidirectional bus (e.g., Figure 1142) can be coupled to a pin or terminal on a memory device, such as RESET_n. In some embodiments, a shared bidirectional bus RESET_n (e.g., ...) is coupled to the RESET_n terminal. Figure 1 142) can be configured to receive signals from a controller (e.g. Figure 1 102) Receive reset command (e.g. Figure 1 RST). In some embodiments, a bidirectional bus is shared (e.g., RST). Figure 1 (142) can be connected to other pins or terminals on the memory device and configured to receive other external signals. For example, a shared bidirectional bus can be connected to pin ZQ of the memory device and configured to receive calibration commands from the controller.

[0054] Circuit 300 may include a connection to a shared bidirectional bus RESET_n (e.g., Figure 1 The driver 302 (142) is a tri-state driver. In some embodiments, the driver 302 may be a tri-state driver. The driver 302 can drive signals to a shared bidirectional bus (e.g., Figure 1 142) on the memory device (e.g. Figure 1 104 and / or Figure 2 The 200) is transmitted to, for example, a controller (e.g. Figure 1 (102). In some embodiments, driver 302 may drive the target refresh alarm RHR_Alert to the shared bidirectional bus RESET_n (e.g., Figure 1 On 142). In some embodiments, the target refresh alarm RHR_Alert may be generated by the refresh control circuitry (e.g., 142). Figure 1 120 and / or Figure 2 (216) is issued. Driver 302 can drive the target refresh alarm RHR_Alert to the shared bidirectional bus RESET_n (e.g., when enabled by the enable signal En) when enabled. Figure 1 On 142), the enable signal En can be used together with the target refresh alarm RHR_Alert by the refresh control circuitry (e.g., Figure 1 120 and / or Figure 2 216) was issued.

[0055] Circuit 300 may include coupling to a shared bidirectional bus (e.g. Figure 1 The latch 320 (142) may consist of inverters 304a and 304b and be coupled to the output of driver 302. The latch 320 may be configured such that commands received on a shared bidirectional bus can toggle the latch 320 and reach the applicable memory logic, thereby causing the memory device (e.g., Figure 1 104 and / or Figure 2The desired operation is performed on circuit 300 (e.g., 200). For example, circuit 300 can perform the desired operation on the shared bidirectional bus RESET_n (e.g., Figure 1 From the controller (e.g., 142) Figure 1 102) Receives a reset command RST. The reset command RST may be strong enough to toggle latch 320 and cause a signal to pass through the third inverter 304c to the semiconductor device (e.g., Figure 1 104 and / or Figure 2 Another component of (200), such as the reset control circuit (e.g. Figure 2 (232). In response to receiving a reset command RST, the reset control logic circuit (e.g., Figure 2 232) causes memory devices (e.g. Figure 1 104 and / or Figure 2 200) Perform a reset operation.

[0056] On the other hand, the signal transmitted from driver 302 may not be strong enough to toggle latch 320 and will travel along the shared bidirectional bus RESET_n (e.g. Figure 1 142) is transmitted to, for example, a controller (e.g.) Figure 1 (102). In some embodiments, the transmitted signal may be a target refresh alarm RHR_Alert and latch 320 may cause the target refresh alarm RHR_Alert to be sent along the shared bidirectional bus RESET_n (e.g., Figure 1 142) transmission. In other words, the target refresh alarm RHR_Alert may not reach the shared bidirectional bus RESET_n (e.g., latch 320 coupled to the latch 320). Figure 1 Component 142).

[0057] Figure 4 This is a schematic diagram of a shared bus RHR logic circuit that can be included on a controller according to at least one embodiment of the present disclosure. Circuit 400 may be... Figure 1 An implementation scheme for the shared bus RHR logic circuit 112.

[0058] Circuit 400 can be configured to allow the controller (e.g.) Figure 1 (102) transmits and receives signals on a shared bidirectional bus. For example, a controller (e.g. Figure 1 102) can be configured to operate on a shared bidirectional bus (e.g. Figure 1 142) Upward to semiconductor device (e.g. Figure 1 104 and / or Figure 2 The 200) transmits the reset command RST. In some embodiments, a shared bidirectional bus (e.g., Figure 1 (142) can be used by the controller and configured to transmit other commands. For example, a shared bidirectional bus (e.g.) Figure 1142) can be connected to the controller's ZQ and configured to supply power to semiconductor devices (e.g., Figure 1 104 and / or Figure 2 (200) Transmit calibration command.

[0059] Circuit 400 can be configured to manage on the shared bidirectional bus RESET_n (e.g. Figure 1 From the controller (e.g., 142) Figure 1 102) signals transmitted and received by the controller. For example, in response to receiving a target refresh alarm RHR_Alert, circuit 400 may include a mechanism that causes the controller to send signals to a memory device (e.g., Figure 1 104 and / or Figure 2 The logic for issuing RFM commands (200).

[0060] Circuit 400 may include a 2-bit counter 420. The 2-bit counter 420 may include two latch circuits 404a and 404b. In an example embodiment, it is coupled to a shared bidirectional bus RESET_n (e.g., Figure 1 The clock terminals of the first latch 404b and the second latch 404a (142) can receive the target refresh alarm RHR_Alert. The first latch 404b may have an input terminal coupled to the input of the first inverter 406b. The first inverter 406b may have an output coupled to the input of the second latch 404a. The output of the second latch 404a may be coupled to the input of the second inverter 406a, and the output of the second inverter 406a may be coupled to the output of the first latch 404b and to another component (e.g., the line hammer refresh (RHR) circuit). Figure 1 110)) provides the RH relief enable signal RH_M_En. Therefore, latches 404a and 404b can act as 2-bit counters, where (assuming both latch circuits 404a and 404b start from a reset state) from a memory device (e.g., Figure 1 104 and / or Figure 2 (200) Sending a target refresh alarm RHR_Alert, for example, as a pulse, after which the RH mitigation enable signal RH_M_En will remain high until from the memory device (e.g., Figure 1 104 and / or Figure 2 The next target refresh alarm RHR_Alert is sent, for example, as a second pulse. The next target refresh alarm RHR_Alert is sent by a memory device (e.g., 200). Figure 1 104 and / or Figure 2 A 200 response is sent to indicate that the requested target refresh is complete. This is in response to a response from a controller (e.g., ...). Figure 1 The reset control circuit of (e.g., 102) Figure 1When the reset enable signal RST_EN (114) is received, the 2-bit counter 420 will be disabled.

[0061] Circuit 400 may include a connection to a shared bidirectional bus RESET_n (e.g., Figure 1 The driver 402 (142) is a tri-state driver. In some embodiments, the driver 402 may be a tri-state driver. The driver 402 can drive commands to a shared bidirectional bus (e.g., Figure 1 142) on the controller (e.g. Figure 1 102) is transferred to, for example, a memory device (e.g., a memory device). Figure 1 104 and / or Figure 2 (200). In some embodiments, driver 402 may drive a reset command RST to a shared bidirectional bus RESET_n (e.g., 200). Figure 1 On 142). In some embodiments, the reset command RST may be delivered by the controller (e.g., Figure 1 The reset control circuit of (e.g., 102) Figure 1 The driver 402 can drive the reset command RST to the shared bidirectional bus RESET_n (e.g., 114) when enabled by the reset enable signal RST_EN. Figure 1 On 142), in some embodiments, the reset enable signal RST_EN can also be controlled by the controller (e.g., Figure 1 The reset control circuit of (e.g., 102) Figure 1 (114) was issued.

[0062] Figure 5 This is a timing diagram illustrating the instance behavior of signals according to at least one embodiment of the present disclosure. In an example embodiment, timing diagram 500 may represent shared bus RHR logic circuitry (e.g., Figure 1 112 and 122, Figure 2 230, Figure 3 300 and / or Figure 4 The 400) operation. The line RHR_Alert indicates that it is operated by a semiconductor device (e.g., Figure 1 104 and / or Figure 2 Shared bus RHR logic circuits on the 200) (e.g. Figure 1 122, Figure 2 230 and / or Figure 3 (300) along the shared bidirectional bus (e.g. Figure 1 The target refresh alarm RHR_Alert (142) is sent by the controller. The line RH_M_En indicates that the alarm is sent by the controller (e.g., the controller is located at the controller). Figure 1 Shared bus RHR logic circuits on 102) (e.g. Figure 1 The RH mitigation enable signal RH_M_En issued by (112) causes the controller (e.g., Figure 1 102) on the C / A bus (e.g. Figure 1 140) Upward to memory device (e.g. Figure 1 104 and / or Figure 2 (200) issues an RFM command.

[0063] At the initial time T0, a shared bidirectional bus (e.g.) Figure 1 142 and / or Figures 3 to 4 The target refresh alarm RHR_Alert on RESET_n transitions from a high state to a low state. When the semiconductor device (e.g., RESET_n) Figure 1 104 and / or Figure 2 When the controller (e.g., 200) determines that it should perform a target refresh operation, it can issue a target refresh alarm RHR_Alert. In response to the target refresh alarm RHR_Alert, the controller (e.g., 200) can issue a target refresh alarm RHR_Alert. Figure 1 Shared bus RHR logic circuits on 102) (e.g. Figure 1 112) to the controller (e.g. Figure 1 RHR logic circuits on (e.g., 102) Figure 1 The controller (e.g., 110) issues the RH mitigation enable signal RH_M_En. Also at the initial time T0, the RH mitigation enable signal RH_M_En transitions from a low state to a high state. When the RH mitigation enable signal RH_M_En is high, the controller (e.g., 110) issues the RH mitigation enable signal RH_M_En. Figure 1 102) to memory device (e.g. Figure 1 104 and / or Figure 2 (200) issues an RFM command.

[0064] At time T1, a shared bidirectional bus (e.g.) Figure 1 142 and / or Figures 3 to 4 The target refresh alarm RHR_Alert on RESET_n turns back high. In some embodiments, the target refresh alarm RHR_Alert can be one or more pulses. The pulse can be of any duration, such as 3 nanoseconds. This is in response to a shared bidirectional bus (e.g., Figure 1 142 and / or Figures 3 to 4 Alarm transition on RESET_n, from controller (e.g. Figure 1 The shared bus RHR logic circuit (e.g., 102) Figure 1 The RH mitigation enable signal RH_M_En issued by (112) can remain unchanged and can be kept high. The RH mitigation enable signal RH_M_En can be kept high to indicate to the controller that a target refresh operation is taking place and the controller should continue to transmit RFM commands.

[0065] At T2, a bidirectional bus is shared (e.g. Figure 1 142 and / or Figures 3 to 4 The target refresh alarm RHR_Alert on RESET_n can transition from high to low. The target refresh alarm RHR_Alert can be another pulse. The second pulse indicates that the memory no longer requires a target refresh operation. The second pulse ends at time T3. The second pulse can be of any duration, such as 3 nanoseconds. In response to the second pulse, the RH mitigation enable signal RH_M_En can transition from high to low at time T3, and the controller will stop transmitting RFM commands.

[0066] Figure 6 This is a block diagram of a system according to at least one embodiment of the present disclosure. System 600 may be... Figure 1 An example implementation of system 100. For example, controller 602 may be... Figure 1 An implementation scheme for controller 102. The main die 612 and the sub-die 614 can be... Figure 1 The memory device 104 and / or Figure 2 An implementation scheme for the semiconductor device 200.

[0067] System 600 may include memory module 620. Memory module 620 may include one or more pairs of memory dies 610a to 610n. Figure 6 In one embodiment, system 600 is shown to comprise four pairs of 610a to 610n. The number of pairs can be any number, such as 4, 8, 16, or 32. More or fewer pairs may be included in system 600 in other embodiments. Each pair of 610a to 610n may comprise a pair of memory dies, such as a master die 612 and a daughter die 614. In an exemplary embodiment, system 600 may have 16 pairs of 610, each containing two memory dies 612 and 614, for a total of 32 memory dies.

[0068] Memory dies 612 and 614 can be coupled to controller 602 via multiple buses. For example, the command / address bus ( Figure 6 (Not shown), data bus (not shown), and / or clock bus (not shown). Each of the buses may contain one or more signal lines on which signals are provided. Controller 602 (e.g., Figure 1 102) can transmit commands to and in response to the transmission commands, memory dies 612 and 614 can perform operations. Controller 602 (e.g. Figure 1 102) can be coupled to pairs 610a to 610n via a bus to transmit other types of signals, such as a reset bus or calibration bus carrying a reset command or a calibration command, respectively. In some embodiments, controller 602 (e.g. Figure 1102) The reset bus RESET_n can be used to transmit the reset command RST to pairs 610a to 610n, and the calibration bus ZQ can be used to transmit the calibration command to pairs 610a to 610n. In response to receiving a signal, memory dies 612 and 614 can perform reset and calibration operations. The reset bus RESET_n and the calibration bus ZQ can each be coupled to a pair of memory dies. For example, the reset bus RESET_n can be coupled to both master die 612 and slave die 614 and transmit the same reset command to both dies 612 and 614 simultaneously. The calibration bus ZQ can also be coupled to both master die 612 and slave die 614 and transmit the same calibration command to both dies 612 and 614 simultaneously. Memory module 620 can be coupled to controller 602 (e.g., via a command / address bus (not shown)). Figure 1 (102) The command / address bus transmits commands for operations performed by the memory die. Commands can be targeted at individual dies, such as a target refresh command.

[0069] According to some embodiments, the reset bus RESET_n and the calibration bus ZQ can be... Figure 1 Shared bidirectional bus 142 and / or Figures 3 to 4 The implementation of RESET_n and the memory dies 612 and 614 can use it to send to the controller 602 (e.g. Figure 1 102) Transmit signals. For example, memory dies 612 and 614 can use the bus to transmit a target refresh alarm to the controller to instruct memory dies 612 and 614 to determine that they should perform a target refresh operation.

[0070] Because both memory dies 612 and 614 can be connected to the shared bidirectional buses RESET_n and ZQ, the controller 602 (e.g. Figure 1 The shared bus RHR logic circuit (e.g., 102) Figure 1 112) can assign different shared bidirectional buses to each memory die 612 and 614. For example, controller 602 (e.g. Figure 1 The shared bus RHR logic circuit (e.g., 102) Figure 1 112) may contain logic such that when a target refresh alarm RHR_Alert is received on a particular shared bidirectional bus, the RFM command for the target refresh operation is transferred to the specific memory die assigned to the shared bidirectional bus. In some embodiments, the reset bus RESET_n may be assigned to the master die 612 and the calibration bus ZQ may be assigned to the child die 614. Therefore, if the controller 602 (e.g. Figure 1 The shared bus RHR logic circuit (e.g., 102) Figure 1If the controller 602 (e.g., 112) receives a target refresh alarm RHR_Alert on the reset bus RESTE_n, then the RFM command will be transmitted to the master die 612. However, if the controller 602 (e.g., 112) receives a target refresh alarm RHR_Alert on the reset bus RESTE_n, then the RFM command will be transmitted to the master die 612. Figure 1 The shared bus RHR logic circuit (e.g., 102) Figure 1 If a target refresh alarm RHR_Alert is received on the calibration bus ZQ (112), then the RFM command will be transmitted to the sub-die 614. Determining when and in what order each die receives the RFM command can be implemented by, for example, the arbitrator circuit described herein.

[0071] Figure 7 This is a block diagram of an arbitrator circuit according to some embodiments of the present disclosure. In some embodiments, the arbitrator circuit 700 may be included in a controller (e.g., Figure 1 102 and / or Figure 6 Shared bus RHR logic circuits on 602) (e.g. Figure 1 In section 112), the arbitrator circuit 700 can be controlled by a controller (e.g., Figure 1 102 and / or Figure 6 (602) is used to determine which memory die (e.g., RESET_n and / or ZQ) is to carry the alarm based on which shared bidirectional bus (e.g., RESET_n and / or ZQ) when multiple memory dies transmit a target refresh alarm during an overlapping period. Figure 6 The main die 612 and / or the sub-die 614) send a target refresh alert RHR_Alert.

[0072] For example, each memory die can be sent to the controller (e.g. Figure 1 102 and / or Figure 6 (602) Send a target refresh alarm RHR_Alert. The first target refresh alarm RHR_Alert may be transmitted on the first shared bidirectional bus (e.g., reset bus RESET_n) to indicate the first memory die Die1 (e.g., ... Figure 6 The primary die 612) requires a target refresh operation. A second target refresh alarm RHR_Alert can be transmitted on the second shared bidirectional bus (e.g., calibration bus ZQ) to indicate that the second memory die Die2 (e.g., ...) requires a target refresh operation. Figure 6 The sub-die 614) requires a target refresh operation. In response to a target refresh alarm, the shared bus logic circuitry (e.g., the controller of each shared bidirectional bus RESET_n and ZQ) is coupled to the target refresh alarm. Figure 1 112 and / or Figure 4 Arbitrator 700 can issue an RH mitigation enable signal RH_M_En to each memory die 612 and 614. Arbitrator 700 will then receive the signal from the shared bus logic circuitry (e.g., Figure 1 112 and / or Figure 4The 400) sends multiple RH mitigation enable signals RH_M_En as input, one of the RH mitigation enable signals RH_M_En is coupled to the shared bidirectional bus RESET_n and the other of the RH mitigation enable signals RH_M_En is coupled to the shared bidirectional bus ZQ.

[0073] The first and second RH mitigation enable signals are the first inputs of NAND gates 702a and 702b, respectively. Figure 7 Will be with the main memory die (e.g. Figure 6 The RH mitigation enable signal associated with 612 is described as RH_M_En(RESET_n) because the main memory die is associated with a target refresh alarm transmitted on the bidirectional bus, which also transmits the reset command RST. Figure 7 Will be with the sub-memory die (e.g. Figure 6 The associated RH mitigation enable signal (614) is described as RH_M_En(ZQ) because the sub-memory die is associated with a target refresh alarm transmitted on a bidirectional bus, which also transmits calibration commands ZQ. The second input of each NAND gate 702a and 702b is coupled to the output of another NAND gate. For example, the second input of the first NAND gate 702a is coupled to the output of the second NAND gate 702b (e.g., the second transition signal B), and the second input of the second NAND gate 702b is coupled to the output of the first NAND gate 702a (e.g., the first transition signal A). Transition signals A and B are passed to a set of two p-type transistors 704a and 706a and two n-type transistors 704b and 706b. The source of p-type 706a receives the first transition signal A, and the source of p-type transistor 704a receives the second transition signal B. The drains of the two p-type transistors are coupled to the corresponding drains of n-type transistors 704b and 706b. The drain signals of p-type transistor 704a and n-type transistor 704b are connected to the first memory die Die1 (e.g. Figure 6 The main die 612) is associated with and outputs to the management RFM command transmission to the first memory die Die1 (e.g. Figure 6 The logic of the main die 612. The drain signals of p-type transistor 706a and n-type transistor 706b are connected to the logic of the second memory die Die2 (e.g., Figure 6 The sub-die 614) is associated with and output to the management RFM command transmission to the second memory die Die2 (e.g. Figure 6 The logic of the sub-die 614. The sources of n-type transistors 704b and 706b are coupled to ground. The gates of p-type transistors 704a and n-type transistors 704b are coupled to the first transition signal A, and the gates of p-type transistors 706a and n-type transistors 706b are coupled to the second transition signal B.

[0074] Therefore, the arbitrator circuit 700 causes the first memory die Die1 (e.g.) Figure 6 The master die 612 is associated with the target refresh alarm RHR_Alert transmitted on the first shared bidirectional bus (e.g., RESET_n) and the arbitrator circuit 700 causes the second memory die Die2 (e.g., ... Figure 6 The sub-die 614) is associated with the target refresh alarm RHR_Alert transmitted on the second shared bidirectional bus (e.g., ZQ). If memory dies Die1 and Die2 (e.g., Figure 6 If both the primary die 612 and the secondary die 614 send a target refresh alarm RHR_Alert, then the arbitrator circuit 700 first transmits a signal associated with the die from which the arbitrator receives the target refresh alarm RHR_Alert, and then transmits the received target refresh alarm RHR_Alert a little later after the target refresh operation of the first die is completed.

[0075] In an example embodiment, when the first memory die Die1 (e.g.) Figure 6 The main die 612 sends data to the controller (e.g., the main die 612). Figure 1 102 and / or Figure 6 When the target refresh alarm RHR_Alert is sent from the first input of the first NAND gate 702a, the shared bus logic circuit of the controller (e.g., 602) is accessed. Figure 1 The 112 and / or 400 of the second shared bidirectional bus ZQ receive a logic high. If the signal on the second shared bidirectional bus ZQ remains low, then the high signal associated with the first memory die Die1 is passed as a low transition signal A to the gates of transistors 704a and 704b, thereby activating the p-type transistor 704a and passing a logic high signal (transition signal B) from the output of the second NAND gate to indicate the logic high signal from the first memory die Die1 (e.g., 112 and / or 400 of the second NAND gate). Figure 6 The target refresh alarm RHR_Alert for the main die 612) is triggered if the shared bus logic circuit (e.g., coupled to the shared bidirectional bus ZQ) is located at the first input of the second NAND gate 702b. Figure 1 112 and / or Figure 4 If the 400) reads a high signal, then the signal will be transmitted in the opposite way, and the target refresh alarm RHR_Alert will be sent with the second memory die Die2 (e.g. Figure 6 The NAND gates 702a and 702b are associated with the sub-die 614. If both NAND gates 702a and 702b receive a high signal, in other words, if memory dies Die1 and Die2 (e.g., Figure 6If both the primary die 612 and the secondary die 614 send a target refresh alarm RHR_Alert, then the arbitrator circuit 700 first transmits a signal associated with the die from which the arbitrator receives the target refresh alarm RHR_Alert, and then transmits the received target refresh alarm RHR_Alert a little later after the target refresh operation of the first die is completed.

[0076] Figure 8 This is a timing diagram illustrating the instance behavior of signals according to at least one embodiment of the present disclosure. In some embodiments, timing diagram 800 may represent an arbitrator circuit (e.g., Figure 7 The operation of 700).

[0077] According to an example embodiment, the line RH_M_En(RESET_n) can represent the controller (e.g., Figure 1 The first shared bus logic circuit of (e.g., 102) Figure 1 112 and / or Figure 4 The signal emitted by the 400) is in response to the signal emitted by the first memory die (e.g., 400). Figure 6 The main die 612) is on the first shared bidirectional bus (e.g. Figure 6 The first target refresh alarm RHR_ALERT(RESET_n) is sent by transmitting RESET_n. The line RH_M_En(ZQ) can indicate the source from the controller (e.g., ...). Figure 1 The second shared bus logic circuit (e.g., 102) Figure 1 112 and / or Figure 4 The signal emitted by the 400) is in response to the signal emitted by the second memory die Die2 (e.g. Figure 6 The sub-die 614) is on the second shared bidirectional bus (e.g. Figure 6 The second target refresh alarm RHR_ALERT(ZQ) is transmitted on the shared bidirectional bus (ZQ). The line DUAL represents the signal indicating when both RESET_n and ZQ transmit the target refresh alarm RHR_Alert. The signal DUAL can be generated by passing the signals RH_M_En(RESET_n) and RH_M_En(ZQ) on the two shared bus logic circuits through an AND logic gate. Lines A and B can represent... Figure 7 The transition signals A and B. Lines Die1 and Die2 can correspond to the arbitrator circuit (e.g., Figure 7 The first and second memory die dies of the arbitrator circuit 700 (e.g., Figure 6 The main nude film 612) and Die2 (e.g.) Figure 6 The output associated with the sub-die 614. For example, the output signal Die1 (e.g., Figure 6The main die 612 can correspond to the target refresh alarm RHR_ALERT signal transmitted on the shared bidirectional bus RESET_n and the output signal Die2 (e.g. Figure 6 The sub-die 614 can correspond to the target refresh alarm RHR_ALERT signal transmitted on the shared bidirectional bus ZQ.

[0078] At the initial time T0, the first RH mitigation enable signal RH_M_En (RESET_n) may transition from low to high, for example, in response to a first target refresh alarm RHR_ALERT (RESET_n) transmitted on the first shared bidirectional bus RESET_n. The first target refresh alarm RHR_Alert (RESET_n) may be transmitted from the first memory die (e.g., Figure 6 The main die 612) transmits data to the controller (e.g., Figure 1 102 and / or Figure 6 602) indicates the first memory die (e.g. Figure 6 The main die 612) determines that it should perform a target refresh operation. The first target refresh alarm RHR_ALERT(RESET_n) can be the first pulse. Also at time T0, the first transition signal A (e.g. Figure 7 The transition signal A) can be transformed into a low signal and the output signal Die1 (e.g.) Figure 7 The output signal Die1 can, for example, change from low to high.

[0079] After a period of time, at time T1, the second RH mitigation enable signal RH_M_En (ZQ) may transition from low to high, for example, in response to a second target refresh alarm RHR_ALERT (ZQ) transmitted on the second shared bidirectional bus ZQ. The second target refresh alarm may originate from the second memory die, for example... Figure 6 The sub-die 614. When both the RH mitigation enable signals RH_M_En (RESET_n) and RH_M_En (ZQ) are high, the signal DUAL, indicating this overlap, can also become high. For example, the signal DUAL transitions high at T1, at which point both the target refresh alarm RHR_ALERT (RESET_n) and RHR_Alert (ZQ) are high. In some embodiments, the signal DUAL can be an input to refresh management logic circuitry, such as those described herein, which manages when and to which memory die to send an RFM command when two memory dies transmit target refresh alarms during an overlap period.

[0080] At the next time point T2, the first RH mitigation enable signal RH_M_En (RESET_n) may again transition from high to low, for example, in response to the first target refresh alarm RHR_ALERT (RESET_n) transmitted on the first shared bidirectional bus RESET_n. The first target refresh alarm RHR_ALERT (RESET_n) may be a second pulse to indicate that the target refresh operation is performed on the first memory die (e.g., Figure 6 The transition signal A (e.g., 612) is completed on the main die (612). Also at time T2, the transition signal A (e.g., 612) is completed on the main die (612). Figure 7 The transition signal A) can be transformed, for example, the transition signal A (e.g. Figure 7 A) can change to high in response to the first RH relief signal RH_M_En(RESET_n) going low. Also in response to the change of the first RH relief signal RH_M_En(RESET_n), the output Die1 associated with the first memory die can change. For example, at time T2, in response to the first RH relief signal RH_M_En(RESET_n) going low, the output signal Die1 (e.g.) Figure 7 Die1) can be converted to low to indicate the controller (e.g. Figure 1 102 and / or Figure 6 (602) Stop sending to the first memory die (e.g.) Figure 6 The main chip 612 transmits RFM commands.

[0081] Additionally, the signal DUAL will transition at time T2 because the first RH relief signal RH_M_En (RESET_n) is no longer in the same active or high state as the second RH relief signal RH_M_En (ZQ). In response to this change, at time T2, the transition signal B (e.g., ...) associated with the second RH relief signal RH_M_En (ZQ) will... Figure 7 Transition signal B) can be controlled by a controller (e.g. Figure 1 102 and / or Figure 6 The transition signal (e.g., 602) is delayed and then changed, for example, via arbitrator circuit 700. For example, transition signal B (e.g.) Figure 7 B) can transition to low in response to the second RH relief signal RH_M_En(ZQ) transitioning high, and the output signal Die2 (e.g.) Figure 7 The output signal Die2 can be changed. In response to the first RH relief signal RH_M_En (RESET_n) going low or becoming inactive, and the second RH relief signal RH_M_En (ZQ) remaining high or active, the output signal Die2 can go high to indicate to the controller (e.g., Figure 1 102 and / or Figure 6 602) to the second memory die (e.g. Figure 6 The sub-die 614 transmits RFM commands.

[0082] At the next time point T3, the second RH relief signal RH_M_En(ZQ) may, in response to the second pulse of the second target refresh alarm RHR_ALERT(ZQ), again transition from high to low to indicate that the target refresh operation is performed on the memory die (e.g., Figure 6 The transition signal B (e.g., 614) is completed on the sub-die. Also at time T3, the transition signal B (e.g., 614) is completed on the sub-die. Figure 7 The transition signal B) may, for example, transition from low to high, in response to the second RH relief signal RH_M_En(ZQ) transitioning low. Also in response to the transition of the second RH relief signal RH_M_En(ZQ), the second memory die (e.g.) Figure 6 The output signal Die2 associated with the sub-die 614 can be switched. For example, at time T3, in response to the second RH relief signal RH_M_En(ZQ) going low or inactive, the output signal Die2 can go low to indicate to the controller (e.g., Figure 1 102 and / or Figure 6 (602) Stop sending to the second memory die (e.g.) Figure 6 The sub-die 614 transmits RFM commands.

[0083] Figure 9 This is a block diagram of refresh management (RFM) logic circuitry according to some embodiments of the present disclosure. In some embodiments, RFM logic circuitry 900 may be included in a controller (e.g., Figure 1 102 and / or Figure 6 The RHR circuit on 602) (e.g. Figure 1 In (110). The RFM logic circuit 900 can be used by the controller based on arbitrator circuits (e.g. Figure 7 The arbitrator circuit 700 determines which memory die sends the target refresh alarm RHR_Alert to decide which memory die to send the RFM command to. For example, the RFM logic circuit 900 can be used in memory modules (e.g., Figure 6 Each pair of memory dies on (e.g., 620) Figure 6 (612 / 614).

[0084] The RFM logic circuit 900 may include multiple multiplexers, each associated with a memory die. For example, the RFM logic circuit 900 may include two multiplexers 902a and 902b. The first multiplexer 902a may be associated with the first memory die (e.g., ...). Figure 6 The primary die 612) is associated with the secondary multiplexer 902b, and the secondary multiplexer 902b may be associated with the secondary memory die Die2 (e.g., the primary die 612). Figure 6The sub-die 614 is associated with it. Multiplexers 902a and 902b can transmit the target refresh alarm RHR_Alert and from the arbitrator circuitry (e.g., based on which memory die is transmitted) Figure 7 The output signal of the 700) is used to manage the transmission of RFM commands to the memory die.

[0085] In an example embodiment, in response to the first memory die Die1 (e.g. Figure 6 The first target refresh alarm RHR_Alert(RESET_n) associated with the primary die 612) and the signal Dual indicating when multiple memory dies transmit target refresh alarms during the same time period, and the first memory die Die1 (e.g. Figure 6 The first multiplexer 902a associated with the main die 612 receives a first RH relief signal RH_M_En (RESET_n) as input. As a selection signal, the first multiplexer 902a receives a signal associated with the first memory die (e.g., ...). Figure 6 The arbitrator circuit associated with the main die 612 (e.g.) Figure 7 The output signal Die1 of the 700). Similarly, in response to the second target refresh alarm RHR_Alert(ZQ) and signal Dual associated with the second memory die Die2, the second memory die (e.g., Figure 6 The second multiplexer 902b associated with the second memory die 614 receives the second RH relief signal RH_M_En(ZQ) as input. As a selection signal, the second multiplexer 902b receives the arbitrator circuit (e.g., ...) associated with the second memory die Die2. Figure 7 The output signal of (700).

[0086] When a first target refresh alarm RHR_Alert(RESET_n) is transmitted on the first shared bidirectional bus RESET_n and no second target refresh alarm RHR_Alert(ZQ) is transmitted on the second shared bidirectional bus ZQ, the arbitrator circuit (e.g. Figure 7 The first output Die1 of the first multiplexer 902a will be high and the signal Dual will be low. Therefore, the output of the first multiplexer 902a will cause the RFM command RFM(Die1) to be transmitted high to the first memory die (e.g., 700). Figure 6 The main die 612). If the second target refresh alarm RHR_Alert(ZQ) is transmitted on the second shared bidirectional bus ZQ when the first target refresh alarm RHR_Alert(RESET_n) is transmitted, then the signal Dual will go high, but the arbitrator circuit associated with the second target refresh alarm RHR_Alert(ZQ) (e.g., Figure 7The output Die2 of the second multiplexer 902b will remain low. Therefore, the output of the second multiplexer 902b will cause the RFM command RFM(Die2) to be transmitted to the first memory die (e.g., 700). Figure 6 (Main nude film 612).

[0087] When the first memory die (e.g.) Figure 6 When the main die 612 stops transmitting the first target refresh alarm RHR_Alert(RESET_n), it is in conjunction with the first memory die (e.g., Figure 6 The arbitrator circuit associated with the main die 612 (e.g.) Figure 7 The signals Dual and Die1 of the 700) will both go low. The first multiplexer 902a will turn the RFM (Die1) signal low to indicate a stop to the first memory die (e.g., Figure 6 The main die 612 transmits RFM commands. Also, on the first memory die (e.g., ... Figure 6 When the main die 612 stops transmitting the first target refresh alarm RHR_Alert(RESET_n), it communicates with the second memory die (e.g., Figure 6 The arbitrator circuit associated with the sub-die 614 (e.g.) Figure 7 The output Die2 of the 700 will transition to high. Therefore, the second multiplexer 902b will continue to transmit the RFM command RFM(Die2) to the second memory die (e.g., 700) in a high state. Figure 6 (614 nude photos).

[0088] When the second memory die (e.g.) Figure 6 When the 614-bit die stops transmitting the second target refresh alarm RHR_Alert(ZQ), the arbitrator circuit (e.g., the 614-bit die) stops transmitting the second target refresh alarm RHR_Alert(ZQ). Figure 7 The output Die2 of the 700 will go low and the output of the second multiplexer 902b will cause the RFM (Die2) signal to go low to indicate a stop to the second memory die (e.g., Figure 6 The sub-die 614 transmits RFM commands.

[0089] Figure 10 This is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 1000 may be implemented by one or more of the devices or systems described herein. For example, method 1000 may be implemented by... Figure 1 The memory device 104 and / or Figure 2 The semiconductor device 200 is implemented.

[0090] Method 1000 may typically begin with block 1010, which describes the transmission of target refresh alarms on a shared bidirectional bus. Target refresh alarms may be... Figures 1 to 9The target refresh alarm RHR_Alert. A shared bidirectional bus can provide... Figure 1 Shared bidirectional bus 142 Figure 3 , 4 RESET_n of 6 and / or Figure 6 The implementation scheme of ZQ. For example, method 1000 may be derived from a first memory die (e.g., Figure 6 The main die 612) is implemented, and the first memory die is on a shared bidirectional bus RESET_n (e.g. Figure 1 On 142), the target refresh alarm RHR_Alert is transmitted to the controller (e.g., Figure 1 102 and / or Figure 6 (602) to indicate that the memory device has determined that it should perform a target refresh operation and therefore requests the controller (e.g. Figure 1 102 and / or Figure 6 602) to the first memory device (e.g. Figure 6 The main chip 612) issues a REF command. Once the target refresh alert is transmitted, method 1000 can proceed to box 1020.

[0091] Block 1020 describes receiving commands on a shared bidirectional bus. Commands can be sent by a controller (e.g., Figure 1 102 and / or Figure 6 602) is transferred to a memory device (e.g. Figure 1 104 Figure 2 200 and / or Figure 6 (612 / 614). In some embodiments, the command may be a reset command (e.g., 612 / 614). Figure 1 , 3 4) or calibration command. A shared bidirectional bus can be used for Figure 1 Shared bidirectional bus 142 Figure 3 , 4 RESET_n of 6 and / or Figure 6 The implementation scheme of ZQ. Once the command is received, method 1000 can proceed to box 1030.

[0092] Box 1030 describes the operation performed according to a command. The command can be from a controller (e.g., Figure 1 102 and / or Figure 6 602) to memory device (e.g. Figure 1 Memory device 104, Figure 2 Semiconductor devices 200 and / or Figure 6 External commands, such as reset or calibration commands, are sent to the memory die 612 / 614. For example, the first memory die (e.g., Figure 6 The main die 612 can be transmitted from the controller (e.g., on the shared command bus RESET_n) to the main die 612. Figure 1 102 and / or Figure 6 (602) Receives an external reset command RST to perform a reset operation. In response to a reset command (e.g., Figure 1 , 3 , 4 of RST), the first memory die (e.g. Figure 6 The main die 612 can perform a reset operation.

[0093] Figure 11 This is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 1100 may be implemented by one or more of the devices or systems described herein. For example, method 1100 may be implemented by... Figure 1 Controller 102 and / or Figure 6 The 602 implementation.

[0094] Method 1100 may typically begin at block 1110, which describes receiving a first pulse of a target refresh alarm on a shared bidirectional bus. The target refresh alarm may be generated by a memory device (e.g., Figure 1 Memory device 104, Figure 2 Semiconductor devices 200 and / or Figure 6 The target refresh alarm RHR_ALERT (e.g., for memory die 612 / 614) is transmitted. Figures 1 to 9 (RHR_ALERT). Shared bidirectional bus can be Figure 1 Shared bidirectional bus 142 Figure 3 , 4 RESET_n of 6 and / or Figure 6 The implementation scheme of ZQ. The target refresh alarm RHR_ALERT may contain one or more pulses. The first pulse of the target refresh alarm may be the first pulse transmitted in a series of one or more pulses. When the memory device (e.g., Figure 1 Memory device 104, Figure 2 Semiconductor devices 200 and / or Figure 6 When the memory die (612 / 614) determines that it should perform a target refresh operation, a first pulse may be transmitted. In response to receiving the first pulse of the target refresh alarm, method 1100 may proceed to block 1120.

[0095] Box 1120 describes the activation of the RH mitigation signal. The RH mitigation signal can be an RH mitigation enable signal, such as... Figure 1 , 4 RH_M_En up to 5 and 7 to 9. The RH relief signal can be responded to, for example, by a controller (e.g., Figure 1 102 and / or Figure 6 Shared bus logic circuits (e.g., 602) Figure 1Activated upon receiving a target refresh alarm at (112). In response to the activation of the RH mitigation signal, the controller (e.g., Figure 1 102 and / or Figure 6 602) can be directed to a memory device (e.g. Figure 1 Memory device 104, Figure 2 Semiconductor devices 200 and / or Figure 6 The memory die 612 / 614 transmits RFM commands. After activating the RH mitigation signal, method 1100 can proceed to block 1130. Block 1130 describes receiving a second pulse of the target refresh alarm on the shared bidirectional bus. When the memory device (e.g., Figure 1 Memory device 104, Figure 2 Semiconductor devices 200 and / or Figure 6 When the memory die 612 / 614 determines that the target refresh operation has been completed, a second pulse of the target refresh alarm may be transmitted. In response to receiving the second pulse of the target refresh alarm, method 1100 may proceed to block 1140.

[0096] Box 1140 describes deactivating the RH mitigation signal. The RH mitigation signal can be activated in response to, for example, a controller (e.g., Figure 1 102 and / or Figure 6 Shared bus logic circuits (e.g., 602) Figure 1 The target refresh alarm was received at (112) and deactivation was initiated. In response to the deactivation RH mitigation signal, the controller (e.g., Figure 1 102 and / or Figure 6 602) can stop sending to memory devices (e.g. Figure 1 Memory device 104, Figure 2 Semiconductor devices 200 and / or Figure 6 The memory die (612 / 614) transmits RFM commands.

[0097] It should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be separated from and / or performed between individual devices or device parts according to the system, apparatus, and method of the present invention.

[0098] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the system of the invention has been described in particular detail with reference to exemplary embodiments, it should be understood that those skilled in the art can devise numerous modifications and alternative embodiments without departing from the broader and contemplated spirit and scope of the system of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed illustratively and are not intended to limit the scope of the appended claims.

Claims

1. A system comprising: Controller; Memory; and A shared bidirectional bus, wherein the shared bidirectional bus is coupled between the controller and the memory, and wherein the controller is configured to transmit commands on the shared bidirectional bus, and the memory is configured to transmit target refresh alarms on the shared bidirectional bus.

2. The system according to claim 1, wherein the command is a reset command.

3. The system of claim 1, wherein the controller is further configured to issue a refresh management RFM command to the memory in response to the target refresh alarm.

4. The system of claim 3, further comprising a command / address bus coupled between the controller and the memory, wherein the RFM commands are transmitted on the command / address bus.

5. The system according to claim 1, further comprising: Second memory; and A second shared bidirectional bus is coupled between the controller and the second memory, wherein the controller is configured to transmit a second command on the second shared bidirectional bus, and the second memory is configured to transmit a second target refresh alarm on the second shared bidirectional bus, and wherein the controller is further configured to transmit a refresh command to the second memory in response to receiving the second target refresh alarm on the second shared bidirectional bus.

6. The system of claim 5, wherein the memory is coupled to the second shared bidirectional bus and the second memory is coupled to the shared bidirectional bus, and wherein the second command is a calibration command and the command and the second command are received by the memory and the second memory.

7. An apparatus comprising: Shared bus logic circuitry, configured to receive commands and transmit target refresh alarms on a shared bidirectional bus; and A refresh control circuit coupled to the shared bus logic circuit, wherein the refresh control circuit is configured to perform a refresh operation and cause the shared bus logic circuit to transmit the target refresh alarm.

8. The device of claim 7, further comprising a reset control circuit coupled to the refresh control circuit and configured to perform a reset operation in response to the command, wherein the command is a reset command.

9. The device of claim 7, further comprising a command / address bus coupled between the controller and the refresh control circuitry, wherein the controller is configured to transmit a refresh command in response to receiving the target refresh alarm, and wherein the refresh control circuitry is further configured to perform a target refresh operation in response to receiving the refresh command.

10. The device of claim 7, wherein when the command and the target refresh alarm are transmitted during an overlapping period, the command overrides the target refresh alarm.

11. The device of claim 7, wherein the shared bus logic circuitry further comprises: drive; and A latch, wherein the shared bidirectional bus is coupled to the output of the driver and the input of the latch.

12. The device of claim 11, wherein the driver is a tri-state driver.

13. The device of claim 11, wherein the driver is configured to receive the target refresh alarm and enable signal from the refresh control circuitry, and is further configured to transmit the target refresh alarm on the shared bidirectional bus in response to the enable signal.

14. The device of claim 11, wherein the latch is configured to toggle when the command is transmitted on the bidirectional shared bus, and is further configured to pass the command as an output of the latch to the reset control circuit.

15. A method comprising: In response to a memory device coupled to a shared bidirectional bus determining that the memory device should perform a target refresh operation, the memory device transmits a target refresh alarm on the shared bidirectional bus. Commands are received from a controller coupled to the shared bidirectional bus on the shared bidirectional bus; and Perform the operation according to the command.

16. The method of claim 15, wherein the controller is further configured to issue a command in response to the target refresh alarm.

17. The method of claim 15, wherein the command is a reset command and the shared bidirectional bus is a reset bus.

18. The method of claim 15, wherein the command is a calibration command and the shared bidirectional bus is a calibration bus.

19. The method of claim 15, further comprising: Receive a second command from the controller on a second shared bidirectional bus, wherein the controller is coupled to the second shared bidirectional bus; and Perform the operation according to the second command.

20. The method of claim 19, wherein the second command is a calibration command.

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