Shared memory communication system and method between processing units, electronic equipment and medium

Abstract

The invention provides a shared memory communication system and method between processing units, electronic equipment and a medium, and the system comprises the following steps: a first processing unit is used for configuring a memory address of a preset communication flag bit in a shared memory as a specified address, and initiating a memory access request for the specified address to a cache module to poll the communication flag bit; and the cache module is used for receiving the memory access request, acquiring the latest data of a specified address from the shared memory under the condition of determining that the access address in the memory access request is the specified address, and returning the latest data to the first processing unit. The first processing unit can obtain the latest state of the communication flag bit in time, so that communication synchronism and data consistency between the processing units are ensured, communication errors and data errors caused by cache inconsistency are avoided, the reliability and stability of shared memory communication are improved, and the service life of the shared memory is prolonged. Meanwhile, the problem that the efficiency is reduced due to the fact that effective cache lines are cleared in an existing solution is solved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a shared memory communication system, method, electronic device, and medium between processing units. Background Technology

[0002] With the development of many-core processor technology, a processor typically contains multiple CPU (Central Processing Unit) cores, which interact with each other through shared memory. During multi-core interaction, a segment of memory is usually allocated in the shared memory space as a marker for data transmission and reception, to inform other cores that data has been written or read successfully.

[0003] However, modern processor cores typically include multi-level caches, and there are also multi-level caches between the core and shared memory. When communication flags in shared memory change, the core may not be able to detect the changes in memory data in a timely manner. When polling to read the changed flags in shared memory, the core may keep retrieving outdated values ​​(dirty values) from the cache instead of retrieving the latest values ​​from shared memory via the bus, leading to consistency issues.

[0004] Currently, some computing cores ensure consistency by clearing or invalidating cache lines using custom instruction sets. However, this method may erase cache lines containing valid data, thus reducing efficiency. Summary of the Invention

[0005] This invention provides a shared memory communication system, method, electronic device, and medium between processing units to address the deficiencies of existing shared memory communication methods between processing units.

[0006] The present invention provides a shared memory communication system for processing units, including a first processing unit, a second processing unit, shared memory communicatively connected to the first processing unit and the second processing unit, and a cache module associated with the first processing unit; The first processing unit is used to configure the memory address of the preset communication flag bit in the shared memory as a specified address, and to initiate a memory access request for the specified address to the cache module in order to poll the communication flag bit; The caching module is used to receive the memory access request, and if it is determined that the access address in the memory access request is the specified address, it retrieves the latest data at the specified address from the shared memory and returns the latest data to the first processing unit.

[0007] According to the present invention, a shared memory communication system for processing units is provided, wherein the communication flag bits include mailbox flag bits or semaphore flag bits; The mailbox flag is used to indicate the status of the communication data associated with the mailbox flag; The semaphore flag is used for synchronization control between processing units.

[0008] According to the present invention, a shared memory communication system for processing units further includes a communication data acquisition unit, wherein the communication data acquisition unit is specifically used for: Determine the status of the update communication flag in the latest data; If the state of the mailbox flag bit in the updated communication flag bit changes, the first processing unit performs a cache cleanup operation to retrieve the communication data from the shared memory; or, When the state of the semaphore flag in the updated communication flags changes, the first processing unit performs a cache cleanup operation to retrieve the communication data from the shared memory.

[0009] According to the present invention, a shared memory communication system for processing units is provided, wherein the cache module is specifically used for: The request result corresponding to the memory access request is determined to be a cache miss, thereby triggering the operation of retrieving the latest data from the shared memory.

[0010] According to the present invention, a shared memory communication system for processing units further includes a comparison unit, wherein the comparison unit is specifically used for: If it is determined that the access address in the memory access request is not the specified address, the cache module compares the first cache identifier of the access address with the second cache identifier stored in the cache module to obtain a comparison result; If the comparison result is a cache hit, the cache data corresponding to the access address is retrieved from the cache module; a cache hit occurs when the first cache identifier matches the second cache identifier. If the comparison result is a cache miss, the memory data corresponding to the access address is retrieved from the shared memory; the cache miss occurs when the first cache identifier and the second cache identifier do not match.

[0011] According to the present invention, a shared memory communication system for processing units is provided, wherein the first processing unit is specifically used for: Execute a preset instruction to write the communication flag bit in the memory address in the shared memory into the control status register in the first processing unit as the specified address.

[0012] According to the present invention, a shared memory communication system for processing units is provided, wherein the specified address is an address range, and the address range is determined by a base address and an address mask; It also includes a determining unit, which is specifically used for: If the address range of the access address is within the address interval, the access address is determined to be the designated address.

[0013] The present invention also provides a method for shared memory communication between processing units, comprising: Configure the memory address of the preset communication flag in the shared memory to a specified address, and initiate a memory access request for the specified address to the cache module in order to poll the communication flag; The system receives the latest data returned by the cache module; the latest data is obtained by retrieving the data corresponding to the specified address from the shared memory when the access address in the memory access request is determined to be the specified address.

[0014] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a shared memory communication method between processing units as described above.

[0015] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a shared memory communication method between processing units as described above.

[0016] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements a shared memory communication method between processing units as described above.

[0017] The present invention provides a shared memory communication system, method, electronic device, and medium for processing units. A first processing unit configures a preset communication flag in the shared memory to a specified address and initiates a memory access request to a cache module for that specified address, polling the communication flag. The cache module receives the memory access request and, if it determines that the access address in the request is the specified address, retrieves the latest data at that specified address from the shared memory and returns the latest data to the first processing unit. In this system, the first processing unit can promptly obtain the latest status of the communication flag, thereby ensuring communication synchronization and data consistency between processing units. This avoids communication and data errors caused by cache inconsistency, improves the reliability and stability of shared memory communication, and avoids the efficiency reduction problem caused by clearing valid cache lines in existing solutions. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of the shared memory communication system between processing units provided by the present invention.

[0020] Figure 2 This is a schematic diagram of the interaction between processing units provided by the present invention.

[0021] Figure 3 This is a schematic diagram of the cache active miss process provided by the present invention.

[0022] Figure 4 This is a flowchart illustrating the shared memory communication method between processing units provided by the present invention.

[0023] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] The terms "first," "second," etc., used in this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and that the objects distinguished by "first," "second," etc., are generally of the same class.

[0026] This invention provides a shared memory communication system for processing units. Figure 1 This is a schematic diagram of the structure of the shared memory communication system between processing units provided by the present invention, as shown below. Figure 1 As shown, the system 100 includes a first processing unit 101, a second processing unit 102, a shared memory 103 communicatively connected to the first processing unit 101 and the second processing unit 102, and a cache module 104 associated with the first processing unit 101.

[0027] The first processing unit 101 is used to configure the memory address of the preset communication flag bit in the shared memory 103 as a specified address, and to initiate a memory access request for the specified address to the cache module 104 in order to poll the communication flag bit; The cache module 103 is used to receive the memory access request, and when it is determined that the access address in the memory access request is the specified address, it retrieves the latest data of the specified address from the shared memory 103 and returns the latest data to the first processing unit 101.

[0028] Specifically, the system includes a first processing unit 101, a second processing unit 102, a shared memory 103 communicatively connected to the first processing unit 101 and the second processing unit 102, and a cache module 104 associated with the first processing unit.

[0029] Here, the first processing unit 101 and the second processing unit 102 can be two independent computing cores of the system, such as core 1 and core 2, which can execute instructions in parallel. Shared memory is a storage area that can be accessed by both the first processing unit 101 and the second processing unit 102, and can be, for example, part of dynamic random access memory (DRAM). The first processing unit 101 and the second processing unit 102 can communicate by reading and writing data in the shared memory.

[0030] Here, the cache module associated with the first processing unit 101 can be a memory that is connected to the first processing unit 101 at high speed. It is used to cache data that is frequently accessed by the first processing unit, so as to reduce the number of accesses to the slower shared memory and improve operating efficiency. The cache module 104 can be an L1 cache (level 1 cache), an L2 cache (level 2 cache), etc., and the embodiments of the present invention do not specifically limit it.

[0031] When processing inter-unit communication, one or more communication flags are typically used to synchronize states. For example, after writing new communication data to shared memory, the second processing unit 102 updates a communication flag to notify the first processing unit that the data is ready. Correspondingly, the first processing unit 101 detects state changes by repeatedly reading (i.e., polling) this communication flag. However, due to the presence of a cache module, if the first processing unit 101 always reads the flag from the cache module, it may not be aware of the second processing unit 102's update of the flag in shared memory, leading to communication failure. To address this, in this embodiment of the invention, the first processing unit 101 configures the memory address of the preset communication flag in shared memory 103 to a specified address and initiates a memory access request to the cache module 104 for the specified address to poll the communication flag.

[0032] The communication flag can be one or more bits, and its value changes to carry certain agreed-upon information between processing units. For example, its value "0" and "1" can represent two different states, respectively.

[0033] Here, the designated address is one or a set of special memory addresses used to identify the memory address where the communication flag is located. The first processing unit 101 marks the memory address where the communication flag is located as the designated address through a specific configuration method. This configuration process can be achieved by executing specific instructions to write the memory address where the communication flag is located into a dedicated register inside the processor, thereby informing the cache module of the special nature of the address. The configuration method can be varied, and can be either hardware-based or software-programmable. Software-programmable methods offer greater flexibility, and this embodiment of the invention does not specifically limit this approach.

[0034] After configuration, the first processing unit 101, in order to understand the communication status, initiates a memory access request for a specified address to the cache module in order to poll the communication flag bit. This polling operation is microscopically manifested as the load / store unit within the first processing unit periodically initiating a memory access request (i.e., a read request) for the specified address to the cache module.

[0035] Accordingly, the cache module 104 is used to receive memory access requests, and if it is determined that the access address in the memory access request is a specified address, it retrieves the latest data at the specified address from the shared memory and returns the latest data to the first processing unit.

[0036] Here, the cache module 104 has internal comparison logic. When it receives a memory access request from the first processing unit 101, it first compares the access address in the memory access request with a pre-configured specified address. If the comparison result shows that the access address requested is indeed the marked specified address, the cache module performs a special operation: it bypasses any existing old cached data related to that specified address and directly accesses the shared memory via the bus to obtain the latest data at that address. After obtaining the latest data, the cache module returns the latest data to the first processing unit 101. This mechanism ensures that the first processing unit 101 obtains the actual state of the data in the shared memory each time it polls the communication flag, rather than the stale state in the cache.

[0037] The system provided in this embodiment of the invention includes a first processing unit configured with a preset communication flag in shared memory at a specified address, and initiating a memory access request for the specified address to the cache module to poll the communication flag. The cache module receives the memory access request and, if it determines that the access address in the memory access request is the specified address, retrieves the latest data at the specified address from the shared memory and returns the latest data to the first processing unit. In this system, the first processing unit can promptly obtain the latest status of the communication flag, thereby ensuring communication synchronization and data consistency between processing units, avoiding communication and data errors caused by cache inconsistency, improving the reliability and stability of shared memory communication, and avoiding the efficiency reduction problem caused by clearing valid cache lines in existing solutions.

[0038] Based on the above embodiments, the communication flag bit includes a mailbox flag bit or a semaphore flag bit; The mailbox flag is used to indicate the status of the communication data associated with the mailbox flag; The semaphore flag is used for synchronization control between processing units.

[0039] Specifically, the communication flag can be a mailbox flag or a semaphore flag. The mailbox flag is used to indicate the status of the communication data associated with the mailbox flag, while the semaphore flag is used for synchronization control between processing units.

[0040] Here, "mailbox" is a figurative term referring to a shared memory area used for transferring data blocks between processing units. Therefore, the mailbox flag is used to indicate the status of the communication data associated with that flag. For example, a mailbox flag of "0" indicates that the mailbox is empty, allowing the first processing unit 101 to write data into it; after the second processing unit 102 writes data, it can set the mailbox flag to "1" to indicate that the mailbox is full, notifying the first processing unit to read from it.

[0041] Semaphore flags can be used for synchronization control between processing units. For example, a binary semaphore (also called a mutex) can be used to protect a critical section (a piece of code or a shared resource), ensuring that only one processing unit can access it at a time. When a processing unit needs to access it, it attempts to acquire the semaphore (e.g., by changing the semaphore flag from "available" to "occupied"), and then releases the semaphore after use.

[0042] The system provided in this invention includes a mailbox flag or a semaphore flag. The mailbox flag indicates the status of the communication data associated with it, while the semaphore flag is used for synchronization control between processing units. This system effectively manages communication and synchronization between processing units, ensuring correct data transmission and status management. It also avoids communication and data errors caused by cache inconsistencies, improving system reliability and stability, and thus guaranteeing the efficiency and accuracy of communication between processing units in a multi-core processor.

[0043] Based on the above embodiments, a communication data acquisition unit is further included, wherein the communication data acquisition unit is specifically used for: Determine the status of the update communication flag in the latest data; If the state of the mailbox flag bit in the updated communication flag bit changes, the first processing unit performs a cache cleanup operation to retrieve the communication data from the shared memory; or, When the state of the semaphore flag in the updated communication flags changes, the first processing unit performs a cache cleanup operation to retrieve the communication data from the shared memory.

[0044] Specifically, after the first processing unit 101 obtains the latest data of the communication flag bit, it also needs to perform subsequent operations based on the state change of the communication flag bit.

[0045] Specifically, firstly, the status of the updated communication flag in the latest data is determined. For example, the first processing unit compares the updated communication flag value in the latest data obtained this time with the communication flag value obtained last time. If they are different, it is determined that its status has changed.

[0046] For example, when the state of the mailbox flag in the communication flags changes (e.g., from "empty" to "full"), the first processing unit 101 performs a cache cleanup operation to retrieve communication data from shared memory. Here, communication data refers to the actual business data block associated with the mailbox flag and stored in shared memory. The cache cleanup operation is a means to ensure consistency between cached data and main memory data, and may specifically include cache invalidation or cache flushing. Cache invalidation marks the corresponding cache line in the cache module as invalid, so that it must be reloaded from shared memory on the next access; cache flushing writes the modified data (dirty data) in the cache back to shared memory. By performing this operation, the first processing unit can ensure that when reading communication data next time, it can retrieve the latest content written by the second processing unit from shared memory.

[0047] For example, when updating the state of the semaphore flag in the communication flags (e.g., from "locked" to "available"), the first processing unit can also perform a cache cleanup operation. This is typically because the shared resource protected by the semaphore (e.g., a piece of shared data) may have been modified by another processing unit holding the semaphore. Therefore, after the semaphore is released, the first processing unit also needs to clean up any old data about the resource that may exist in its cache in order to safely access the shared resource.

[0048] The system provided in this invention establishes an efficient two-step data acquisition mechanism. The first step efficiently and accurately polls the communication flag bit, a process with low overhead. The second step only performs a relatively expensive cache clearing operation to acquire the actual communication data after confirming a change in the communication flag bit. This approach avoids large-scale cache clearing with each polling iteration, significantly improving cache utilization efficiency and overall system performance. Through this two-step mechanism, the system can maintain efficient communication while significantly reducing unnecessary cache clearing operations, thereby optimizing communication efficiency and overall performance between processing units in a multi-core processor.

[0049] Based on the above embodiments, the cache module 104 is specifically used for: The request result corresponding to the memory access request is determined to be a cache miss, thereby triggering the operation of retrieving the latest data from the shared memory.

[0050] Specifically, cache module 104 is used for: The result of the memory access request is determined to be a cache miss, thereby triggering the operation of retrieving the latest data from shared memory.

[0051] Specifically, when the internal logic of the cache module 104 determines that the address of the current memory access request is a preset specified address, it will force the lookup result of this access to be judged as a cache miss, even if the cache module actually stores the data at that address and the tag matches. In a normal cache workflow, a cache miss will naturally trigger subsequent operations, that is, to load data from the next level of storage (in this case, shared memory). This embodiment of the invention cleverly utilizes this existing mechanism to achieve the purpose of forcing access to shared memory by creating a cache miss in the front-end logic.

[0052] Based on the above embodiments, a comparison unit is further included, wherein the comparison unit is specifically used for: If it is determined that the access address in the memory access request is not the specified address, the cache module compares the first cache identifier of the access address with the second cache identifier stored in the cache module to obtain a comparison result; If the comparison result is a cache hit, the cache data corresponding to the access address is retrieved from the cache module; a cache hit occurs when the first cache identifier matches the second cache identifier. If the comparison result is a cache miss, the memory data corresponding to the access address is retrieved from the shared memory; the cache miss occurs when the first cache identifier and the second cache identifier do not match.

[0053] Specifically, if it is determined that the access address in the memory access request is not the specified address, the cache module compares the first cache identifier of the access address with the second cache identifier stored in the cache module to obtain the comparison result.

[0054] Here, the first cache identifier and the second cache identifier refer to the high-order part generated based on the memory address, i.e., the tag. The cache module compares the tag of the memory access address with the tag stored in its own cache line.

[0055] If the comparison result is a cache hit, the cached data corresponding to the accessed address is retrieved from the cache module. A cache hit means that the first cache identifier matches the second cache identifier, indicating that the required data already exists in the cache module and can be directly and quickly read from it and returned to the first processing unit.

[0056] If the comparison result is a cache miss, the memory data corresponding to the accessed address is retrieved from shared memory. A cache miss means that the first cache identifier and the second cache identifier do not match, indicating that the required data is not in the cache. At this time, the cache module will initiate the normal miss handling process, that is, access the shared memory to retrieve the data.

[0057] Based on the above embodiments, the first processing unit is specifically used for: Execute a preset instruction to write the communication flag bit in the memory address in the shared memory into the control status register in the first processing unit as the specified address.

[0058] Specifically, the first processing unit 101 executes a preset instruction to write the memory address in the shared memory where the communication flag is located into the control and status register (CSR) within the first processing unit 101 as a specified address.

[0059] The Control Status Register (CSR) is a set of special registers within the processor used to control the processor's operating state and behavior. In this embodiment of the invention, one or more dedicated CSRs can be set to store information at specified addresses.

[0060] Here, the default instructions are special instructions defined in the instruction set architecture for accessing the CSR. For example, in the RISC-V instruction set, instructions such as csrrw can be used to read and write the CSR. Software can execute these instructions to dynamically write the actual memory address of the communication flag into this dedicated CSR during initialization or runtime, thereby configuring a specified address. The hardware logic of the cache module constantly refers to the contents of this CSR to determine whether memory access requests require special handling.

[0061] Based on the above embodiments, the specified address is an address range, which is determined by the base address and the address mask; It also includes a determining unit, which is specifically used for: If the address range of the access address is within the address interval, the access address is determined to be the designated address.

[0062] Specifically, the specified address can be an address range, not just a single address. This address range is determined by a base address and an address mask.

[0063] For example, two CSRs can be set: one to store the base address and the other to store the address mask. The base address defines the starting position of the interval, while the address mask defines the size and alignment of the interval.

[0064] Accordingly, if the accessed address falls within the address range, the accessed address is determined to be the specified address. The comparison logic of the cache module will perform the following judgment: (accessed address & address mask) == (base address & address mask). If this equation is true, it means that the accessed address falls within the range defined by the base address and the mask, should be regarded as the specified address, and the subsequent forced miss operation will be triggered.

[0065] The system provided in this embodiment of the invention expands the specified address to a configurable address range, enabling the method to set a special caching strategy for a contiguous memory region containing multiple communication flags at once. This greatly simplifies configuration and management when dealing with complex communication protocols or managing multiple communication channels, and improves the flexibility and scalability of the solution.

[0066] Based on any of the above embodiments Figure 2 This is a schematic diagram of the interaction between processing units provided by the present invention. Figure 3 This is a schematic diagram of the cache active miss process provided by the present invention, such as... Figure 2 , Figure 3 As shown, this embodiment of the invention is applied to a multi-core processor system, which includes at least a first processing unit, a second processing unit, shared memory, and a cache module associated with the first processing unit. The first processing unit contains at least an execution unit and a Load / Store unit. To address the problem that when the first processing unit polls the communication flag, it may continuously read old flag bits (dirty numbers) that have been updated in the shared memory by the second processing unit due to cache hits, thus causing communication failure, this embodiment of the invention introduces a cache-active miss mechanism. Specifically, the execution unit of the first processing unit can configure a control status register (CSR) by executing a specific instruction (e.g., the csrrw instruction in the RISC-V instruction set), which serves as a cache-active miss register. Through this operation, the memory address used as the communication flag is configured to a specified address, and the cache module's active miss function is enabled.

[0067] After configuration, when the Load / Store unit of the first processing unit initiates a memory access request for a specified address to perform a polling operation, the caching module introduces a judgment logic based on that specified address during the regular tag matching process. This logic divides the memory access request into two cases: When the memory access address is a non-specified address (unrestricted address): The cache module performs standard operations. If the tag matches successfully, it is considered a cache hit, and the data is directly retrieved from the cache line and returned to the Load / Store unit. If the tag fails to match, it is considered a cache miss, triggering the miss handling mechanism, and the data is retrieved from shared memory via the bus.

[0068] When the memory access address is a specified address (a limited address): the cache module will force an active miss. That is, regardless of whether the tag match is successful or whether valid data already exists at that address in the cache, this access will be judged as a cache miss. This forced judgment will require the cache module to bypass the internal cache and directly access shared memory to obtain the latest data at the specified address (i.e., the communication flag). After obtaining the data, the latest data is read back into the cache line and finally returned to the Load / Store unit of the first processing unit.

[0069] Through the above mechanism, when the first processing unit needs to poll the communication status, it can ensure that it reads the latest communication flag in the shared memory each time. When the first processing unit (through its execution unit) detects a preset change in the communication flag (e.g., from 0 to 1), it indicates that the second processing unit is ready for new data. At this point, the first processing unit will perform subsequent large-scale cache line refresh or invalidation operations to clear any old data that may be related to this communication and load entirely new data blocks from the shared memory.

[0070] In summary, this invention employs a two-stage communication strategy: the first stage involves configuration by the execution unit, followed by precise polling of communication flags by the Load / Store unit using a low-overhead cache miss mechanism; the second stage involves high-overhead cache line flushing only after communication is confirmed. This method not only fundamentally guarantees data consistency and real-time performance in communication between processing units, but also significantly improves cache utilization efficiency and overall system performance by avoiding unnecessary, large-scale cache line invalidation operations during the polling phase, while simplifying the synchronization control logic between processing units.

[0071] The shared memory communication method between processing units provided by the present invention is described below. The shared memory communication method between processing units described below can be referred to in correspondence with the shared memory communication system between processing units described above.

[0072] Based on any of the above embodiments, the present invention provides a method for shared memory communication between processing units. Figure 4 This is a flowchart illustrating the shared memory communication method between processing units provided by the present invention, as shown below. Figure 4 As shown, the method includes: Step 410: Configure the memory address of the preset communication flag in the shared memory to a specified address, and initiate a memory access request for the specified address to the cache module in order to poll the communication flag. Step 420: Receive the latest data returned by the cache module; the latest data is obtained by retrieving the data corresponding to the specified address from the shared memory when it is determined that the access address in the memory access request is the specified address.

[0073] The method provided in this embodiment of the invention involves a first processing unit configuring a preset communication flag in shared memory to a specified address, and initiating a memory access request for the specified address to a cache module to poll the communication flag. The cache module receives the memory access request and, if it determines that the access address in the memory access request is the specified address, retrieves the latest data at the specified address from shared memory and returns the latest data to the first processing unit. This method allows the first processing unit to obtain the latest status of the communication flag in a timely manner, thereby ensuring communication synchronization and data consistency between processing units, avoiding communication and data errors caused by cache inconsistency, improving the reliability and stability of shared memory communication, and avoiding the efficiency reduction problem caused by clearing valid cache lines in existing solutions.

[0074] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 5 As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540. The processor 510, communications interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call logical instructions in the memory 530 to execute a shared memory communication method between processing units. This method includes: configuring a preset communication flag in the shared memory at a specified address; initiating a memory access request to a cache module for the specified address to poll the communication flag; receiving the latest data returned by the cache module; the latest data is obtained by retrieving the data corresponding to the specified address from the shared memory when the access address in the memory access request is determined to be the specified address.

[0075] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0076] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the shared memory communication method between processing units provided by the above methods. The method includes: configuring a preset communication flag in the shared memory at a specified address; initiating a memory access request to a cache module for the specified address to poll the communication flag; receiving the latest data returned by the cache module; wherein the latest data is obtained by retrieving the data corresponding to the specified address from the shared memory when it is determined that the access address in the memory access request is the specified address.

[0077] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements a shared memory communication method between processing units provided by the above methods. The method includes: configuring a preset communication flag in the shared memory at a specified address; initiating a memory access request to a cache module for the specified address to poll the communication flag; receiving the latest data returned by the cache module; wherein the latest data is obtained by retrieving data corresponding to the specified address from the shared memory when it is determined that the access address in the memory access request is the specified address.

[0078] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0079] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shared memory communication system for processing units, characterized in that, It includes a first processing unit, a second processing unit, shared memory communicatively connected to the first processing unit and the second processing unit, and a cache module associated with the first processing unit; The first processing unit is used to configure the memory address of the preset communication flag bit in the shared memory as a specified address, and to initiate a memory access request for the specified address to the cache module in order to poll the communication flag bit; The caching module is used to receive the memory access request, and if it is determined that the access address in the memory access request is the specified address, it retrieves the latest data at the specified address from the shared memory and returns the latest data to the first processing unit.

2. The shared memory communication system for processing units according to claim 1, characterized in that, The communication flags include mailbox flags or semaphore flags; The mailbox flag is used to indicate the status of the communication data associated with the mailbox flag; The semaphore flag is used for synchronization control between processing units.

3. The shared memory communication system for processing units according to claim 2, characterized in that, It also includes a communication data acquisition unit, which is specifically used for: Determine the status of the update communication flag in the latest data; If the state of the mailbox flag bit in the updated communication flag bit changes, the first processing unit performs a cache cleanup operation to retrieve the communication data from the shared memory; or, When the state of the semaphore flag in the updated communication flags changes, the first processing unit performs a cache cleanup operation to retrieve the communication data from the shared memory.

4. The shared memory communication system for processing units according to any one of claims 1 to 3, characterized in that, The cache module is specifically used for: The request result corresponding to the memory access request is determined to be a cache miss, thereby triggering the operation of retrieving the latest data from the shared memory.

5. The shared memory communication system for processing units according to any one of claims 1 to 3, characterized in that, It also includes a comparison unit, which is specifically used for: If it is determined that the access address in the memory access request is not the specified address, the cache module compares the first cache identifier of the access address with the second cache identifier stored in the cache module to obtain a comparison result; If the comparison result is a cache hit, the cache data corresponding to the access address is retrieved from the cache module; a cache hit occurs when the first cache identifier matches the second cache identifier. If the comparison result is a cache miss, the memory data corresponding to the access address is retrieved from the shared memory; the cache miss occurs when the first cache identifier and the second cache identifier do not match.

6. The shared memory communication system for processing units according to any one of claims 1 to 3, characterized in that, The first processing unit is specifically used for: Execute a preset instruction to write the communication flag bit in the memory address in the shared memory into the control status register in the first processing unit as the specified address.

7. The shared memory communication system for processing units according to any one of claims 1 to 3, characterized in that, The specified address is an address range, which is determined by a base address and an address mask. It also includes a determining unit, which is specifically used for: If the address range of the access address is within the address interval, the access address is determined to be the designated address.

8. A method for shared memory communication between processing units, characterized in that, include: Configure the memory address of the preset communication flag in the shared memory to a specified address, and initiate a memory access request for the specified address to the cache module in order to poll the communication flag; Receive the latest data returned by the cache module; The latest data is obtained by retrieving the data corresponding to the specified address from the shared memory when the access address in the memory access request is determined to be the specified address.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the shared memory communication method between processing units as described in claim 8.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the shared memory communication method between processing units as described in claim 8.

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