Multiple key activation logic locking system and method

Abstract

This application discloses a multi-key activation logic locking system and method. By storing a function key and N activation keys in memory, and combining the trigger module and correction circuit design of the activation module, dynamic verification of the activation key sequence and correction locking of erroneous inputs are achieved. When the input activation key logic value matches the trigger state output signal, the correction circuit outputs a valid key, driving the trigger state transition; otherwise, it locks the corrected value, significantly increasing the difficulty of brute-force attacks. Simultaneously, the blocking logic circuit controls the validity of the function key and signal transmission through the activation signal. The embodiments of this application construct a multi-stage key control mechanism, disrupting the single-key model relied upon by SAT attacks. It combines high security, low hardware overhead, and strong scalability, flexibly adapting to integrated circuits of different scales, fundamentally enhancing the anti-attack capability of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit hardware security, and in particular to a multi-key activation logic locking system and method. Background Technology

[0002] Logic locking technology is the core defense method, but existing timing circuit locking schemes have obvious defects: most of them use a single global key, which is vulnerable to SAT attacks guided by Oracle, and they lack modular compatibility and are difficult to flexibly adapt to circuits of different sizes. Summary of the Invention

[0003] This application aims to propose a multi-key activation logic locking system and method that can effectively reduce the impact of SAT attacks and can flexibly adapt to circuits of different sizes.

[0004] A multi-key activation logic locking system according to a first aspect embodiment of this application includes:

[0005] The memory internally stores a function key and M activation keys, each of which has an N-bit logical value, where M is less than or equal to N.

[0006] The activation module includes a correction circuit, a first AND gate, and N trigger modules. Each trigger module includes a flip-flop, a first OR gate, a first XOR gate, and a set AND gate. The first input of the first OR gate is connected to the output of the first AND gate, the second input is connected to the output of the first XOR gate, and the output is connected to the input of the flip-flop. The first input of each first XOR gate is connected to the output of the corresponding set AND gate. Each flip-flop corresponds to a preset set logic signal, and each set logic signal has an N-bit logic value corresponding to the N flip-flops. The N inputs of each set AND gate are connected to the positive or negative output of each flip-flop according to the corresponding set logic signal. M activation keys are determined according to the N preset set AND gates. The set logic signal is determined; the positive output terminal of the flip-flop is pre-determined as either the positive output terminal or the negative output terminal of the flip-flop, and the output values ​​of the N positive output terminals constitute a state output signal; the positive output terminals of the N flip-flops are all connected to the input terminals of the first AND gate; the correction circuit includes N first input terminals corresponding to the input N-bit logic values, N second input terminals connected to the N positive output terminals, and N output terminals connected to the second input terminals of the N first XOR gates; the memory is used to select the activation key according to the state output signal and output it to the correction circuit; the correction circuit is used to output the N logic values ​​to the second input terminals of the N first XOR gates when the input N-bit logic values ​​are consistent with the state output signal at the current time;

[0007] The blocking logic circuit includes a first input terminal for inputting the function key, a second input terminal connected to the output terminal of the first AND gate, and a third input terminal for inputting the data to be output, and is used to complete the output according to the data to be output when the function key is valid and the first AND gate outputs a valid value.

[0008] The multi-key activation logic locking method according to a second aspect of this application is applied to the multi-key activation logic locking system as described in the first aspect embodiment, the multi-key activation logic locking method comprising:

[0009] In response to the activation command, the first activation key among the N activation keys stored in the memory is input to the activation module, so that the first AND gate in the activation module outputs a valid value to the blocking logic circuit.

[0010] Wherein, when a function key is input at the first input terminal of the blocking logic circuit and a valid value is input at the second input terminal of the blocking logic circuit, the blocking logic circuit completes the output based on the output data input at the third input terminal of the blocking logic circuit;

[0011] Wherein, if the logic values ​​of the N first input terminals of the correction circuit are inconsistent with the current state output signal, the output signals of the N output terminals of the correction circuit are locked as correction signals.

[0012] The multi-key activation logic locking system and method of this application, by storing a function key and N activation keys in memory and combining the trigger module and correction circuit design of the activation module, realizes dynamic verification of the activation key sequence and correction locking of erroneous inputs. When the input activation key logic value matches the trigger state output signal, the correction circuit outputs a valid key, driving the trigger state transition; otherwise, it locks the corrected value, significantly increasing the difficulty of brute-force attacks. Simultaneously, it blocks the logic circuit from controlling the validity of the function key and signal transmission through the activation signal. This application's embodiments construct a multi-stage key control mechanism, disrupting the single-key model relied upon by SAT attacks, combining high security, low hardware overhead, and strong scalability. It can flexibly adapt to integrated circuits of different scales, fundamentally enhancing the anti-attack capability of integrated circuits.

[0013] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0014] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0015] Figure 1 A system diagram of the multi-key activation logic locking system provided in the embodiments of this application;

[0016] Figure 2 A circuit diagram of the locking module provided in an embodiment of this application;

[0017] Figure 3 A circuit diagram of the blocking logic circuit provided in the embodiments of this application;

[0018] Figure 4 A circuit diagram of a blocking logic circuit provided in another embodiment of this application;

[0019] Figure 5 A circuit diagram of a blocking logic circuit provided for another embodiment of this application.

[0020] Figure label:

[0021] Memory 100, activation module 200, blocking logic circuit 300. Detailed Implementation

[0022] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0023] In the description of this application, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0024] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0025] In the description of this application, it should be noted that, unless otherwise explicitly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0026] The technical solution of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are some embodiments of this application, not all embodiments.

[0027] See Figures 1 to 5 As shown, one embodiment of this application provides a multi-key activation logic locking system, which includes:

[0028] The memory 100 internally stores a function key and M activation keys, each activation key having an N-bit logical value, where M is less than or equal to N.

[0029] Activation module 200 includes a correction circuit and a first AND gate (e.g., Figure 2 As shown in AND1), and N trigger modules; each trigger module includes a trigger (such as ... Figure 2 (as shown by FF0, FF1, FF2, FF3), first OR gate (e.g.) Figure 2 OR1, OR2, OR3, OR4 are shown (e.g.) Figure 2 The diagram shows XOR1, XOR2, XOR3, XOR4, and set AND gates (not shown in the diagram). The first input of the first OR gate is connected to the output of the first AND gate, the second input is connected to the output of the first XOR gate, and the output is connected to the input of the flip-flops. The first input of each XOR gate is connected to the output of the corresponding set AND gate. Each flip-flop corresponds to a preset set logic signal, and each set logic signal has an N-bit logic value corresponding to the N flip-flops. The N inputs of each set AND gate are connected to the positive or negative output of each flip-flop according to the corresponding set logic signal. M activation keys are determined based on the N set logic signals. The positive output terminal is pre-determined as either the positive or negative output terminal of the flip-flop, and the output values ​​of the N positive output terminals constitute the state output signal; the positive output terminals of the N flip-flops are all connected to the input terminals of the first AND gate; the correction circuit includes N first input terminals corresponding to the input N-bit logic values, N second input terminals connected to the positive output terminals of the N flip-flops, and N output terminals connected to the second input terminals of the N first XOR gates; the memory 100 is used to select an activation key according to the state output signal and output it to the correction circuit; the correction circuit is used to output the N logic values ​​to the second input terminals of the N first XOR gates when the input N-bit logic values ​​are consistent with the state output signal at the current moment;

[0030] The blocking logic circuit 300 includes a first input terminal for inputting a function key, a second input terminal connected to the output terminal of a first AND gate, and a third input terminal for inputting data to be output. It is used to complete the output based on the data to be output when the function key is valid and the first AND gate outputs a valid value.

[0031] In this embodiment, by storing the function key and N activation keys in the memory 100, and combining the trigger module and correction circuit design of the activation module 200, dynamic verification of the activation key sequence and correction locking of erroneous inputs are achieved. This ensures that when the input activation key logic value matches the trigger state output signal, the correction circuit outputs a valid key, driving the trigger state transition; otherwise, it locks the value to the correction value, significantly increasing the difficulty of brute-force attacks. Simultaneously, the blocking logic circuit 300 controls the validity of the function key and signal transmission through the activation signal. This embodiment constructs a multi-stage key control mechanism, disrupting the single-key model relied upon by SAT attacks. It combines high security, low hardware overhead, and strong scalability, flexibly adapting to integrated circuits of different scales, fundamentally enhancing the anti-attack capability of integrated circuits.

[0032] The aforementioned memory 100 can be a tamper-proof memory 100 with lookup table capability, enabling the memory 100 to have a certain data processing capability, and to automatically retrieve the correct key for the next moment from the output value of multiple triggers in the activation module 200 and connect it to the activation module 200 and the blocking module.

[0033] The aforementioned set logic signal is a preset signal or preset value, which has a logic value with the same number of bits as the number of flip-flops. It is generated by combining the set logic values ​​of all flip-flops. For details, please refer to [link / reference]. Figure 2 As shown, the activation module 200 contains four flip-flops FF3, FF2, FF1, and FF0, whose corresponding set logic signals are preset to "0111", "0011", "0001", and "0000", respectively. In this case, the set AND gate has four inputs. For FF0, its corresponding set logic signal is "0000", so its set AND gate needs to be connected to the negative output of each flip-flop to correspond to the set logic signal "0000". For FF1, its corresponding set logic signal is "0001", so one input of its set AND gate needs to be connected to the positive output of the FF0 flip-flop. The output terminals are connected, and the other three input terminals need to be connected to the negative output terminals of FF1, FF2, and FF3 to correspond to the set logic signal "0001". Similarly, for FF2, the two input terminals of its corresponding set AND gate need to be connected to the positive output terminals of FF0 and FF1, and the other two input terminals need to be connected to the negative output terminals of FF2 and FF3 to correspond to the set logic signal "0011". For FF3, the three input terminals of its corresponding set AND gate need to be connected to the positive output terminals of FF0, FF1, and FF2, and the other input terminal needs to be connected to the negative output terminal of FF3 to correspond to the set logic signal "0111".

[0034] As can be seen, the N bits of the set logic signal corresponding to each flip-flop correspond to N flip-flops, and the logic value of each bit determines whether the corresponding flip-flop needs to be connected to the input of the corresponding set AND gate by the negative output terminal or the positive output terminal according to whether the logic value of each bit is "0" or "1". Specifically, when it is "0", the negative output terminal of the corresponding bit flip-flop can be connected to the input terminal of the set AND gate, and when it is "1", the positive output terminal of the corresponding bit flip-flop can be connected to the input terminal of the set AND gate.

[0035] The activation key mentioned above is essentially the same as the set logic signal. If the set logic signals are all different, the number of activation keys must be the same as the number of set logic signals, and the N-bit logic value of each activation key must also be the same as the logic value of the set logic signal.

[0036] It should be noted that when there are identical set logic signals, the number of activation keys can be reduced. That is, one activation key can be used to trigger multiple flip-flops with the same set logic signals. In essence, the number of activation keys is the number of different position logic signals among the N set logic signals that are the same as the number of flip-flops. Therefore, M will be less than or equal to N.

[0037] Still attached Figure 2 Taking the circuit as an example, during operation, when the initial state output signal of the flip-flop group is "0000", the activation key "0000" is input. Under the action of the activation key input and the first XOR gate, only the state of FF0 changes to "1" in the next moment, while the states of other flip-flops remain "0". Therefore, the state output signal of the flip-flop group in the next moment is "0001". "0001" is the set logic signal of FF1. At this time, the activation key "0001" is input. Although the set logic value of FF0 is "0", it will remain "1" in the next moment under the condition that the activation key input is "1". As before, the state of FF2 will change to "1", while the states of the other flip-flops remain "0". Therefore, the state of the flip-flops in the next moment is "0011". And so on. If the activation key input sequence value is equal to the set logic signal of the flip-flops, and the input order is equal to the flip-flop transition order, then a new flip-flop will be set to "1" in each clock cycle, and the flip-flops that have already been set to "1" will maintain their state until all flip-flops transition to "1", the activation signal takes effect and locks the state of all flip-flops, and only then is the activation phase considered over.

[0038] The aforementioned activation keys are simultaneously input to the first input terminal of the correction circuit of the activation module 200 according to their position, such as... Figure 2 As shown, Figure 2The diagram shows key input 0, key input 1, key input 2, and key input 3. In this example, the activation key also has four positions. Taking the activation key "0001" as an example, when it is input to the calibration circuit, the "1" is input to key input 0, and the other three positions of "0" are input to key input 1, key input 2, and key input 3. Taking the activation key "0011" as an example, when it is input to the calibration circuit, the lowest position "1" is input to key input 0, the second to last position "1" is input to key input 1, and the other two positions of "0" are input to key input 2 and key input 3.

[0039] When the activation key is stored in memory 100, it can be stored in a fixed order. At this time, the next key output can be determined by looking up the table using the real-time status output signal.

[0040] Specifically, with Figure 2 Taking the activation module 200 as an example, there are four flip-flops FF3, FF2, FF1, and FF0, whose corresponding set logic signals are "0111", "0011", "0001", and "0000" respectively. The activation keys stored in the memory 100 are "0000", "0001", "0011", and "0111" respectively, and the corresponding addresses are "0000", "0001", "0011", and "0111". When an activation command is detected, the memory 100 will select the key "0000" at the corresponding address according to the initial state output signal "0000" of the flip-flop group and input it into the correction circuit. If the activation key is correct, the state output signal of the flip-flop group will change to "0001". The memory 100 will detect "0001" and obtain the key "0001" from that address and output it to the correction circuit. This process is repeated to complete the sequential input of all activation keys to activate the activation module 200 and output a valid activation signal. It should be noted that in actual operation, the address of the activation key stored in memory 100 can be further complicated. That is, the state output signal needs to be mathematically transformed to obtain the correct address, so as to further improve security.

[0041] The activation signal described above can be defined as the logical AND result of the output states of all flip-flops, and fed back to the inputs of each flip-flop through the first AND gate. This means that the activation signal is only effective when all flip-flop states are "1", and forces all flip-flops to remain in the "1" state, marking the circuit entering the functional stage.

[0042] The aforementioned correction circuit is used during the activation process when an incorrect key is input to the activation module 200. It ensures that the activation key is only input to the trigger if the real-time input activation key matches the current state output signal; otherwise, the output is locked or prevented from being output to the trigger, thus providing a protective measure. Specifically, if an incorrect activation key is input during activation, the correction circuit will activate, triggering a key correction signal. In the circuit shown, the correction signal will eventually lock to "1010". At this point, the key correction signal replaces the current key input, driving the state transition. This carefully designed key correction logic ensures that the state transitions to the incorrect state set and cannot autonomously return to the correct path.

[0043] The activation signal is input to the blocking logic circuit 300. Before the end of the activation phase, the logic value of the activation signal is always "0", which disables the function key. That is, even if the function key is input to the blocking logic circuit and the data to be output is also input to the blocking logic circuit, the data to be output cannot be output or cannot be output correctly, thus blocking the normal signal transmission of the circuit. After the activation phase ends, the activation signal is set to "1", and the function key can then take effect. At this time, only by inputting the correct function key can the normal function of the circuit be unlocked, that is, the data to be output will be output correctly.

[0044] In some implementations, the correction circuit is also used to lock the output signal of the N output terminals of the correction circuit as the correction signal when the logic values ​​of the N first input terminals of the correction circuit are inconsistent with the current state output signal.

[0045] In this embodiment, the design effectively blocks the transition of the trigger state to the correct path by locking the output of the correction circuit to a correction signal when an incorrect key is input, thus preventing attackers from approaching the valid key sequence through trial and error. This mechanism enhances the system's resistance to brute-force and SAT attacks, preventing the state from continuing along the normal path after an incorrect input, further compressing the attack space. This function requires no additional complex hardware, strengthening the security of logic locking without increasing hardware overhead and ensuring the effectiveness of the multi-key activation mechanism.

[0046] The locking of the aforementioned correction signal can be directly determined by the circuit, such as... Figure 2 In the circuit shown, the correction signal will eventually lock to "1010".

[0047] In some implementations, reference Figure 2 The correction circuit includes:

[0048] N second XOR gates (e.g.) Figure 2As shown in XOR5, XOR6, XOR7, XOR8), the first input of N second XOR gates is used to input N-bit logic values, and the second input of N second XOR gates is connected to the positive output of N flip-flops.

[0049] Second OR gate (e.g.) Figure 2 As shown in OR5), it has N inputs connected to the outputs of N second XOR gates;

[0050] N combination gates are configured to correspond to N trigger modules. The first input of each combination gate is used to input N-bit logic values. The second input is connected to the output of the second OR gate, and the output is connected to the second input of the corresponding first XOR gate. This is used to allow the logic value input to the second input of the combination gate to be output through the output of the combination gate when the signal output by the second OR gate is invalid.

[0051] In this embodiment, the logic of the correction circuit performs an XOR operation on the activation key input and the output value of each flip-flop individually, then performs an OR operation on the combined results of the individual XOR operations, and finally processes the result through a combination gate to generate a correction signal, which is then re-inputted to the activation module 200. This logic dynamically binds the correct key to the current flip-flop output value, requiring the key input to strictly match a preset sequence. If an incorrect key is input, the correction signal will overwrite the current key input, causing the flip-flop state to deviate from the correct path and enter a predefined set of error states. Since the error state cannot be reset automatically, a reset key is required to complete the reset. Therefore, no matter how the codebreaker adjusts the key input, they cannot activate the activation module 200.

[0052] The above N combination doors can be the same or different, depending on the correction signal that the designer needs to lock. For example, Figure 2 The value is locked as "1010". If it needs to be adjusted to "1011", the combination gate corresponding to the highest bit can be used to increase the value of the combination gate corresponding to the lowest bit. In addition, the design of the combination gate can be flexibly adjusted to meet the requirement that the value of the correction signal does not change no matter how the input activation key changes.

[0053] In some implementations, reference Figure 2 The combination door includes:

[0054] NOT gate (e.g.) Figure 2 The inputs of NOT1, NOT2, NOT3, and NOT4 are connected to the output of the second OR gate.

[0055] Second AND gate (e.g.) Figure 2 As shown in AND1), its first input is used to input logic values, its second input is connected to the output of the NOT gate, and its output is connected to the second input of the first XOR gate.

[0056] In this embodiment, the combined gate adopts a simple structure design of NOT gate and second AND gate. When the key matches, the NOT gate and second AND gate work together to allow the correct logic value; when the key does not match, the signal input to the activation module 200 can be forcibly locked at "0", quickly blocking the transmission of effective signal and ensuring that the correction signal is accurately effective.

[0057] In some implementations, reference Figure 2 The combination door includes:

[0058] Third OR gate (e.g.) Figure 2 As shown in OR6 and OR7, the first input terminal is connected to the output terminal of the second OR gate, the second input terminal is used to input logic values, and the output terminal is connected to the second input terminal of the first XOR gate.

[0059] In this embodiment, the combined gate uses a third OR gate. When the keys match, the third OR gate allows the correct logic value to pass; when the keys do not match, the signal input to the activation module 200 can be forcibly locked at "1", quickly blocking the transmission of valid signals and ensuring that the correction signal is accurately effective.

[0060] In some implementations, reference Figure 2 The activation module 200 also includes a third AND gate (such as...). Figure 2 As shown in AND3), the third AND gate has N inputs connected to the outputs of N second XOR gates, and an output for outputting a reset signal; the memory 100 also stores a reset key, which is set according to the correction signal.

[0061] The reset signal of the activation module 200 is generated by XORing the key input with the output value of the flip-flop, followed by a logical AND operation. Considering that the input of the flip-flop group is locked by the correction signal after an incorrect key input, the output of the flip-flop will also eventually be locked in a fixed state. In this case, if the third AND gate is to output a valid reset signal, the key input needs to be a parameter that is opposite to the locking signal (it can be seen that the reset key needs to be set according to the correction signal). This will make the output of each second XOR gate "1", thereby making the output of the third AND gate "1", thus obtaining a valid reset signal.

[0062] Upon detecting a reset signal, the built-in control unit of memory 100 or an external control unit can reset each trigger. Subsequent users can still activate the device using normal activation logic, while external intruders will still face the blocking effect of the dynamic key during intrusion.

[0063] In some implementations, reference Figure 3 The blocking logic circuit 300 includes:

[0064] The fourth AND gate has a first input terminal for inputting the function key and a second input terminal connected to the output terminal of the first AND gate.

[0065] An XOR gate has an output terminal, a first input terminal connected to the output terminal of a fourth AND gate, and a second input terminal for inputting data to be output.

[0066] In this embodiment, the blocking logic circuit 300 adopts a simple combination structure of a fourth AND gate and an XOR NOT gate, resulting in low hardware overhead and high integration. The fourth AND gate performs dual verification of the function key and the activation signal, triggering subsequent signal transmission only when both are valid; the XOR NOT gate works together to accurately select the data to be output. In the inactive state, it can effectively shield the function key, blocking correct data transmission and effectively resisting unauthorized unlocking; after activation, it allows normal data output, adapting to multi-key activation mechanisms, and enhancing the security of logic locking and the reliability of signal transmission without increasing system complexity.

[0067] In some implementations, reference Figure 4 The blocking logic circuit 300 includes:

[0068] The third XOR gate has a first input for inputting the function key and a second input for inputting the data to be output.

[0069] The fifth AND gate has an output terminal, a first input terminal connected to the output terminal of the third XOR gate, and a second input terminal connected to the output terminal of the first AND gate.

[0070] In this embodiment, the blocking logic circuit 300 employs a simplified combination of a third XOR gate and a fifth AND gate, resulting in a concise structure and low hardware overhead. The third XOR gate achieves logical fusion of the function key and the data to be output, while the fifth AND gate implements transmission access control through an activation signal, forming a dual verification mechanism. When inactive, the fifth AND gate forcibly blocks signal transmission, completely shielding against unauthorized use of the function key; when activated, it precisely allows valid data, perfectly adapting to multi-key activation logic. It requires no complex hardware expansion, simplifying system design while enhancing the circuit's resistance to unauthorized unlocking, balancing security and signal transmission stability.

[0071] In some implementations, reference Figure 5 The blocking logic circuit 300 includes:

[0072] The fifth AND gate has its first input terminal used to input the data to be output, and its second input terminal connected to the output terminal of the first AND gate;

[0073] The fourth XOR gate has an output, a first input connected to the output of the fifth AND gate, and a second input for inputting a function key.

[0074] In this embodiment, the blocking logic circuit 300 adopts a simplified structure design using a fifth AND gate and a fourth XOR gate, resulting in low hardware overhead and clear logic. The fifth AND gate controls the transmission permission of the data to be output through an activation signal, while the fourth XOR gate, in conjunction with the function key, performs secondary verification, forming a dual protection mechanism. In the inactive state, the fifth AND gate forcibly blocks data transmission, completely preventing unauthorized unlocking by the function key; after activation, it precisely allows data transmission through logical matching between the key and the data. It requires no complex hardware expansion, simplifying system design while enhancing resistance to illegal attacks, perfectly adapting to multi-key activation logic, and balancing security and signal transmission stability.

[0075] The above Figures 3 to 5 In the diagram, X represents the data to be output from the blocking logic circuit 300, and Y represents the data output by the blocking logic circuit 300 based on the data to be output.

[0076] This application also provides a multi-key activation logic locking method for controlling the aforementioned multi-key activation logic locking system, including:

[0077] In response to the activation command, the first activation key among the N activation keys stored in the memory 100 is input to the activation module 200, so that the first AND gate in the activation module 200 outputs a valid value to the blocking logic circuit 300.

[0078] Specifically, when a function key is input at the first input terminal of the blocking logic circuit 300 and a valid value is input at the second input terminal of the blocking logic circuit 300, the blocking logic circuit 300 completes the output based on the output data input at the third input terminal of the blocking logic circuit 300.

[0079] In cases where the logic values ​​of the N first input terminals of the correction circuit are inconsistent with the current state output signal, the output signals of the N output terminals of the correction circuit are locked as the correction signal.

[0080] In this embodiment, the multi-key activation logic locking method can be applied to an independent control unit or to the control unit of a memory 100 that has simple logic functions such as table lookup.

[0081] The activation command mentioned above can be triggered by power-on, external control signal, or other methods.

[0082] Upon receiving the activation command, the control unit triggers the memory 100 to initiate the key output process. The memory 100 sorts the pre-stored activation keys, retrieves and extracts the first key from the N activation keys, and outputs its complete N-bit logic value to the correction circuit of the activation module 200. The correction circuit receives this key and matches it with the current flip-flop group's state output signal. Upon successful verification, it drives the flip-flop state transition, causing all flip-flops to gradually output valid levels at their positive outputs, ultimately causing the first AND gate to output a valid value—that is, outputting a valid activation signal—which is then transmitted to the blocking logic circuit 300 to initiate the subsequent signal control process.

[0083] In this implementation, the activation command triggers the precise input of the first activation key, initiating the multi-key verification process in an orderly manner and laying the foundation for subsequent activation signal generation. The blocking logic circuit 300 only outputs data when both the function key and the activation signal are valid, forming a double protection to prevent unauthorized unlocking in the inactive state. When keys mismatch, the correction circuit locks the output correction signal, preventing the trigger from migrating to the correct state and avoiding attackers from approaching the valid key through trial and error, significantly reducing the attack space. These three elements work together to achieve orderly verification, dual control, and error interception, significantly improving the system's resistance to brute-force attacks and unauthorized intrusion without increasing hardware complexity, while balancing the standardization of the activation process with the high security of the logic lock.

[0084] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A multiple key activated logic locking system, comprising: The application relates to a function key storage device. The function key storage device comprises a memory, an activation module, and a correction circuit. The memory internally stores a function key and M activation keys, each of the activation keys having N-bit logic values, and M is less than or equal to N. The activation module comprises the correction circuit, a first AND gate, and N trigger modules. Each of the trigger modules comprises a flip-flop, a first OR gate, a first XOR gate, and a set gate. The first input end of the first OR gate is connected with the output end of the first AND gate, the second input end is connected with the output end of the first XOR gate, and the output end is connected with the input end of the flip-flop. The first input end of each of the first XOR gates is connected with the output end of the corresponding set gate. Each of the flip-flops corresponds to a preset set logic signal, each of the set logic signals has N-bit logic values corresponding to the N flip-flops, and the N input ends of each of the set gates are connected with the positive output end or the negative output end of each of the flip-flops according to the corresponding set logic signal. The M activation keys are determined according to the N set logic signals.

2. The multiple key activated, logical lock system of claim 1 wherein, The output values of the positive output ends of the N flip-flops form a state output signal. The positive output ends of the N flip-flops are all connected with the input end of the first AND gate. The correction circuit comprises N first input ends for inputting N-bit logic values, N second input ends connected with the positive output ends, and N output ends connected with the second input ends of the N first XOR gates. The memory is used for selecting the activation keys according to the state output signal and outputting to the correction circuit. The correction circuit is used for outputting N logic values to the second input ends of the N first XOR gates when the input N-bit logic values are consistent with the state output signal at the current time. The correction circuit is also used for locking the output signals of the N output ends of the correction circuit as correction signals when the logic values input to the N first input ends of the correction circuit are inconsistent with the state output signal at the current time. The blocking logic circuit comprises a first input end for inputting the function key, a second input end connected with the output end of the first AND gate, and a third input end for inputting data to be outputted. The blocking logic circuit is used for completing the output according to the data to be outputted when the function key is valid and the first AND gate outputs a valid value. The correction circuit comprises: N second XOR gates, the first input ends of the N second XOR gates are used for inputting N-bit logic values, and the second input ends of the N second XOR gates are connected with the positive output ends of the N flip-flops. A second OR gate has N input ends connected with the output ends of the N second XOR gates. N combination gates are arranged corresponding to the N trigger modules. The first input end of each of the combination gates is used for inputting N-bit logic values, the second input end is connected with the output end of the second OR gate, the output end is connected with the second input end of the corresponding first XOR gate, and the logic value inputted by the second input end of the combination gate is outputted through the output end of the combination gate when the signal outputted by the second OR gate is invalid. The combination gate comprises: A NOT gate, the input end of which is connected with the output end of the second OR gate. a second AND gate having a first input terminal for inputting a logic value, a second input terminal connected to the output terminal of the NOT gate, and an output terminal connected to the second input terminal of the first XOR gate.

3. The multiple key activated, logical lock system of claim 1 wherein, The combination gate comprises: a third OR gate having a first input terminal connected to the output terminal of the second OR gate, a second input terminal for inputting a logic value, and an output terminal connected to the second input terminal of the first XOR gate.

4. The multiple key activated, logical lock system of claim 1 wherein, The activation module further comprises a third AND gate having N input terminals connected to the output terminals of the N second XOR gates, and an output terminal for outputting a reset signal; and a reset key is further stored in the memory, and the reset key is set according to the correction signal.

5. The multiple key activated, logical lock system of claim 1 wherein, The blocking logic circuit comprises: a fourth AND gate having a first input terminal for inputting the function key, and a second input terminal connected to the output terminal of the first AND gate; a XNOR gate having an output terminal, a first input terminal connected to the output terminal of the fourth AND gate, and a second input terminal for inputting data to be outputted.

6. The multiple key activated, logical lock system of claim 1 wherein, The blocking logic circuit comprises: a third XOR gate having a first input terminal for inputting the function key, and a second input terminal for inputting data to be outputted; a fifth AND gate having an output terminal, a first input terminal connected to the output terminal of the third XOR gate, and a second input terminal connected to the output terminal of the first AND gate.

7. The multiple key activated, logical lock system of claim 1 wherein, The blocking logic circuit comprises: a fifth AND gate having a first input terminal for inputting data to be outputted, and a second input terminal connected to the output terminal of the first AND gate; a fourth XOR gate having an output terminal, a first input terminal connected to the output terminal of the fifth AND gate, and a second input terminal for inputting the function key.

8. A method of multi-key activation logic locking, the method comprising: The multi-key activation logic locking method is applied to the multi-key activation logic locking system as claimed in any one of claims 1 to 7, and the multi-key activation logic locking method comprises: in response to an activation instruction, inputting a first-order activation key of N activation keys stored in the memory to the activation module, so that the first AND gate in the activation module outputs a valid value to the blocking logic circuit; wherein, in the case that the function key is inputted to the first input terminal of the blocking logic circuit, and the valid value is inputted to the second input terminal of the blocking logic circuit, the blocking logic circuit completes outputting according to the data to be outputted inputted to the third input terminal of the blocking logic circuit; wherein, in the case that the logic values inputted to the N first input terminals of the correction circuit are inconsistent with the state output signal at the current time, the output signals of the N output terminals of the correction circuit are locked as the correction signal.

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