Functional ECO automatic partition correction method

Abstract

The invention provides a large-scale netlist-oriented ECO improvement method, which comprises the following steps of: receiving an original netlist and a target netlist as input, and dynamically dividing an error output port set into a plurality of scale-controllable subsets based on calculation complexity evaluation; an Auto Partition correction strategy is adopted, one subset is selected each time for priority processing, and corresponding function patches are generated and merged into an original netlist; reevaluating the residual error set based on the updated netlist state, and repeating the process until all errors are completely eliminated; according to the method, a global correction task is decomposed into a plurality of sub-problems capable of being efficiently solved, the processing capacity of the ECO algorithm on a large-scale netlist is remarkably improved, comprehensive performance optimization is achieved in the aspects of patch quality, operation efficiency and the like, and ECO is achieved through a large-scale design which cannot be successfully corrected in the past.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of ECO and particularly relates to a functional ECO automatic partition correction method. BACKGROUND

[0002] When the RTL code needs to be modified after the layout is generated, without a special tool (such as an ECO tool), the entire process must be re-executed from the beginning, and using an ECO (Engineering Change Order) tool is equivalent to directly applying a patch to the existing layout (i.e., an executable file), without the need for full-process redo, thereby greatly saving time and resources.

[0003] One of the core indicators of the current ECO technology in the EDA field is the patch size, and the smaller the patch, the more efficient the algorithm generally is. The traditional ECO algorithm has the following technical problems when processing large-scale netlists: the patch size is too large, which is difficult to meet the actual application requirements; the running time is too long, which cannot be completed within a reasonable time; when the number of error output ports (POs) is large, the algorithm is prone to failure, and it cannot be guaranteed that an effective patch can always be generated; for large-scale netlists, the calculation complexity and memory consumption of the traditional algorithm increase exponentially, which seriously affects the processing efficiency. SUMMARY

[0004] The application provides a functional ECO automatic partition correction method, and aims to solve the problems of low processing efficiency and high resource consumption caused by the large size of the netlist in the traditional ECO algorithm.

[0005] The scheme of the application is as follows: A functional ECO automatic partition correction method for reducing the patch size of large-scale netlist ECO and realizing fast ECO of large-scale netlists, the method comprising the following steps: Step S1, receiving a user-input original netlist and a target netlist, comparing the original netlist and the target netlist through logic equivalence checking, and identifying an error PO set of output ports in the original netlist.

[0006] Step S2, attempting to perform one-time ECO correction on the error PO set, and if the correction is successful, ending the process, and if the correction fails, entering step S3.

[0007] Step S3, selecting a controllable error PO subset from the error PO set according to a preset calculation resource constraint condition.

[0008] Step S4, generating a functional patch for the selected error PO subset.

[0009] Step S5, merging the functional patch into the current original netlist to generate an updated netlist.

[0010] Step S6, based on the updated netlist re-performs logical equivalence check, obtain the remaining error PO set; determine whether to meet the termination condition, if meet then end the process, if not meet then enter step S7.

[0011] Step S7, with the updated netlist as the new original netlist, with the remaining error PO set as the new error PO set, repeat steps S3 to S6.

[0012] Further, in the error PO set, analyze the logical correlation between the error POs, calculate the computing resources required to correct each error PO subset, select the error PO subset that meets the screening condition at the same time, and obtain the error PO subset with controllable size.

[0013] The screening condition includes: the number of error POs in the subset does not exceed the preset number threshold; the error POs in the subset meet the logical correlation threshold; and the computing resources required to correct the subset do not exceed the current available computing resources.

[0014] Further, the logical equivalence check in step S1 uses a combination equivalence check, which constructs a mixer Miter circuit, performs an exclusive OR operation on the corresponding outputs of the original netlist and the target netlist, and uses a SAT solver to determine whether the exclusive OR result is always 0.

[0015] Further, the specific steps of generating a functional patch are: Step S4.1, construct a local netlist model based on the selected error PO subset, the MFFC (maximum fanout free cone) of the error PO subset; the MFFC of a node n or gate g refers to a subset of the fan-in cone of the gate g, which contains some nodes that meet the condition that every path through these nodes to the final output PO needs to pass through the gate g or the node n, so that a subset of the fan-in cone can be called MFFC; that is, once the node is removed, the partial predecessor nodes cannot reach the PO, then the set of these predecessor nodes is the MFFC.

[0016] Step S4.2, use a matching algorithm to analyze the logical differences between the error PO subset and the corresponding part of the target netlist, and use a binary decision diagram BDD or an and-invert graph AIG to represent and compare functions.

[0017] Step S4.3, generate a minimum functional patch that can eliminate the logical differences through logic synthesis, and the functional patch includes input ports, output ports and internal logic gates.

[0018] Further, the function patch needs to correct at least the logical function of one error PO in the subset; and does not change the logical behavior of other correct POs in the original netlist; the input port of the patch is connected to the internal signal node of the original netlist, and the output port replaces the corresponding error PO.

[0019] The number of logic gates of the function patch is generally not more than 1.5 times the corresponding logic of the original error PO subset, so as to control the area overhead; if the area overhead is not considered, only the logic is correct, and there is no upper limit for the number of logic gates, and finally one of the results of multiple tasks is selected as the final result.

[0020] Further, the function patch merging operation in step S5 includes: connecting the input port of the function patch with the corresponding signal node in the original netlist; replacing the corresponding error PO in the original netlist with the output port of the function patch; updating the topology and signal propagation relationship of the netlist to ensure the integrity and consistency of the netlist.

[0021] Further, based on the updated netlist, logical equivalence checking is performed again to obtain a remaining error PO set, and when the remaining error PO set is empty, or the remaining error PO cannot form a subset satisfying the computing resource constraint, or the number of AutoPartition reaches a preset maximum AutoPartition number, it is judged that the termination condition is satisfied, and the process is ended.

[0022] Further, the preset maximum AutoPartition number is 1-12.

[0023] Further, the computing resource constraint conditions include: memory usage constraint, computing time constraint, logic gate number constraint and netlist size constraint. The memory usage of a single ECO operation is not more than 60% of the total system memory; the computing time of a single ECO operation is not more than a preset time limit, and the preset time limit is 30 minutes-2 hours; the number of logic gates contained in a single function patch is not more than 1000-5000; and the local netlist size corresponding to the error PO subset processed at a time is not more than 20% of the original netlist size.

[0024] Compared with the prior art, the present application has the following advantages: The present application divides the large-scale netlist into a plurality of controllable scale sub-problems, so that the originally unable to handle large-scale design can be successfully corrected; through the Auto Partition processing mode, the global correction task is decomposed into a plurality of efficient solvable sub-stages, which greatly reduces the calculation complexity and memory consumption of single solving; compared with the traditional method, a smaller scale and better quality functional patch can be generated, the ECO correction effect is improved, the ECO algorithm can adapt to larger scale modern chip design, and good scalability is obtained. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A functional ECO automatic partition correction method flow chart of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the present application will be described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0027] EMBODIMENT As shown in the figure, it is a functional ECO automatic partition correction method flow chart of the present application, which comprises the following steps: Figure 1 Step S1, receiving the original netlist and the target netlist input by the user, comparing the original netlist and the target netlist through logical equivalence checking, and identifying the output port error PO set in the original netlist. The original netlist is Old Netlist, that is, the chip version that has completed physical design; the target netlist is New Netlist, that is, the ideal chip version expected to be achieved.

[0028] In the embodiment, the logical equivalence checking adopts combination equivalence checking, which constructs a mixer Miter circuit to perform exclusive or operation on the corresponding outputs of the original netlist and the target netlist, and uses a SAT solver to judge whether the exclusive or result is always 0; specifically, for each output port

[0029] , an exclusive or gate is constructed When the exclusive or result can satisfy 1, it indicates that there is a logical difference in the output port.

[0030] Step S2, attempting to perform one-time ECO correction on the error PO set, if the correction is successful, ending the flow, if the correction fails, entering step S3.

[0031] First, try the traditional global correction method to obtain a better correction result (not necessarily global is the best), global correction can consider all the logical association between the error PO, in theory, can generate the minimum size of the functional patch; however, when the number of error PO is more or involves complex logical relationship, global correction often fails due to high computational complexity.

[0032] In this embodiment, the failure conditions of global ECO correction include: the estimated memory requirement exceeds 60% of the system available memory; the estimated calculation time exceeds the preset time limit (30 minutes-2 hours); the SAT solver cannot converge within the preset time; when any of the failure conditions is met, the algorithm automatically enters the Auto Partition correction mode.

[0033] Step S3, according to the preset calculation resource constraint condition, select a size-controllable error PO subset from the error PO set.

[0034] It should be noted that the traditional ECO method often directly fails when facing large-scale error set, and the present application divides the complex problem into multiple solvable sub-problems through intelligent partition strategy.

[0035] In the error PO set, analyze the logical association between the error POs, calculate the calculation resources required to correct each error PO subset, select the error PO subset that meets the filtering condition at the same time, and obtain the size-controllable error PO subset; The filtering condition includes: the number of error POs in the subset does not exceed the preset number threshold, the preset number threshold is 8-20; the error POs in the subset meet the logical association threshold, the logical association threshold is 0.3-0.8; the calculation resources required to correct the subset do not exceed the current available calculation resources.

[0036] Based on the logical association analysis, the algorithm uses a greedy strategy to select the error PO subset; specifically, first select the error PO with the highest association degree as the seed node, then gradually add other error POs with high association degree and meet the resource constraints to the selected nodes, until a subset that meets the filtering condition is formed.

[0037] The logical association between the error POs is based on the topological distance of the error POs in the netlist, and the specific calculation method is: for any two error And , calculate the shortest path distance in the netlist directed graph, define the logical association: , wherein, is the distance attenuation coefficient, the value range is 0.1-0.5; smaller The value makes the influence of distance on relevance more moderate, and is suitable for designs with relatively scattered logical structures; a larger value places more emphasis on local relevance, and is suitable for highly modularized designs.

[0038] When the distance is greater than the logical relevance threshold value, it is considered that the error PO and the target PO have logical relevance.

[0039] Step S4, generating a functional patch for the selected error PO subset.

[0040] The specific steps of generating a functional patch are as follows: Step S4.1, constructing a local netlist model based on the selected error PO subset, the local netlist model including the fan-in cone of the error PO subset and the MFFC of the error PO subset.

[0041] Step S4.2, analyzing the logical difference between the error PO subset and the corresponding part of the target netlist by using a matching algorithm, the matching algorithm using binary decision diagram (BDD) or and-in graph (AIG) for function representation and comparison.

[0042] In this embodiment, the matching algorithm preferentially uses binary decision diagram (BDD) for function representation because of its normalization feature, which can quickly determine function equivalence; the algorithm first constructs a BDD representation of the error PO, and then compares it with the BDD of the corresponding output of the target netlist, directly obtaining the logical difference function through BDD operations (XOR, simplification); for complex functions, an and-in graph (AIG) is used as an auxiliary representation, and its structural features are used for difference positioning.

[0043] Step S4.3, generating a minimum functional patch that can eliminate the logical difference through logic synthesis, the functional patch including input ports, output ports, and internal logic gates.

[0044] The number of input ports is determined according to the number of support variables of the difference function, and the number of output ports is equal to the number of error POs in the subset.

[0045] It should be noted that the functional patch allows partial correction, and at least one error PO can be corrected; the patch cannot change the logical behavior of other correct POs in the original netlist, and formal verification is used to ensure that there is no side effect.

[0046] Step S5, merging the functional patch into the current original netlist to generate an updated netlist.

[0047] The functional patch merging operation includes: ​​​​First, establish connections between the patch input port and the signal nodes within the original netlist. The selection of connection points is based on the analysis results from the patch generation phase, ensuring the logical semantics of the signals are correct. During the connection process, the signal's driving capability needs to be considered, and buffers should be inserted if necessary to meet load requirements.

[0048] Secondly, replace the corresponding faulty PO in the original netlist with the output port of the patch; the replacement process requires updating all related signal references, including internal wiring and external interface definitions; to avoid naming conflicts, the signal nodes in the patch adopt a unified naming convention, usually adding the "patch" prefix to distinguish them.

[0049] Finally, update the netlist topology and signal propagation relationships. Topology updates include adding nodes, reconstructing connections, and adjusting hierarchical relationships.

[0050] Step S6: Perform a logical equivalence check again based on the updated netlist to obtain the remaining set of error POs; determine whether the termination condition is met. If it is met, the process ends; otherwise, proceed to step S7.

[0051] Based on the updated netlist, a logical equivalence check is performed again to obtain the set of remaining error POs. When the set of remaining error POs is empty, or the remaining error POs cannot form a subset that satisfies the computing resource constraints, or the number of Auto Partitions reaches the preset maximum number of Auto Partitions, it is determined that the termination condition is met and the process ends.

[0052] When the set of remaining error POs is empty, it indicates that all errors have been successfully corrected and the algorithm has reached the optimal termination state. When the remaining error POs cannot form a subset that satisfies the computational resource constraints, it indicates that the remaining errors are too complex or scattered and cannot be processed under the current algorithm parameters. At this time, the algorithm terminates and reports the partial correction results. When the number of Auto Partitions reaches the preset maximum number of Auto Partitions (1-12 times), the algorithm is forcibly terminated to avoid infinite loops.

[0053] The logical equivalence check of the updated netlist uses the same method as in step S1, but focuses on the remaining uncorrected errors. During the check, corrected POs should be completely consistent with the target netlist, while the number and distribution of remaining erroneous POs provide guidance for the next round of Auto Partition.

[0054] The computing resource constraints include: memory usage constraint, computing time constraint, logic gate number constraint and netlist size constraint; the memory usage of a single ECO operation does not exceed 60% of the total system memory; the computing time of a single ECO operation does not exceed a preset time limit, and the preset time limit is 30 minutes-2 hours; the number of logic gates contained in a single functional patch does not exceed 1000-5000; the local netlist size corresponding to a single processed error PO subset does not exceed 20% of the original netlist size.

[0055] Step S7, taking the updated netlist as a new original netlist and taking the remaining error PO set as a new error PO set, repeating steps S3-S6.

[0056] Before each Auto Partition starts, the algorithm updates the global state information, including the current netlist snapshot, the remaining error statistics, the resource consumption record and the convergence trend analysis.

[0057] To improve the efficiency of Auto Partition, the algorithm uses an adaptive parameter adjustment strategy: when the error reduction of two consecutive Auto Partitions is lower than a threshold, the logical association requirement is appropriately relaxed, and the candidate subset range is expanded; when a certain type of error repeatedly occurs, its priority is increased to ensure that it is processed first in subsequent Auto Partitions; when resource consumption continues to rise, the subset size limit is tightened to maintain the stability of the algorithm.

[0058] At the same time, the algorithm maintains detailed Auto Partition logs, recording the input state, processing process, output result and performance indicators of each Auto Partition.

[0059] To better illustrate the actual application effect of the method of the present application, a specific digital signal processing unit (DSP Unit) design case is described in detail below.

[0060] A digital signal processing unit developed by a company needs to be upgraded. The original version (version A) implements basic digital filtering functions, including low-pass filter, high-pass filter and band-pass filter. The target version (version B) adds an adaptive dynamic noise reduction algorithm and optimizes the original filter coefficient calculation logic to improve processing accuracy and reduce power consumption.

[0061] The DSP unit contains about 1.5 million logic gates, with 64 main output ports, belonging to the design of large-scale integrated circuits. After completing the RTL code modification, the logic equivalence checking tool detects that there are 35 output ports with inconsistent functions, and these errors are distributed in the filter coefficient calculation module, the data path control module and the output formatting module.

[0062] The following problems are encountered when using the traditional ECO method to correct these 35 errors at one time: the calculation complexity is too high, it is estimated that 40GB of memory and more than 6 hours of calculation time are needed; the available resources are limited, the server is configured with 32GB of memory, and the single task time limit is 2 hours; the correction fails, and the traditional ECO tool cannot generate an effective function patch before the resources are exhausted.

[0063] In this case, the design team faces two choices: either upgrade the computing resources (costly and not guaranteed to succeed), or adopt a way of redesigning from scratch (huge time cost).

[0064] Using the Auto Partition ECO method of the present application, the system configuration is as follows: the upper limit of the size of the error PO subset: 20; the logical correlation threshold: 0.5; the distance decay coefficient: 0.3; the memory limit of a single Auto Partition: 19GB (60% of the total system memory); the time limit of a single Auto Partition: 1 hour; the maximum number of Auto Partitions: 10.

[0065] The first round of Auto Partition correction for the filter coefficient module, the system first attempts to correct all 35 error POs at one time. Through the resource estimation algorithm, it is determined that this operation requires about 40GB of memory, which exceeds the system limit, and the correction fails, and the process enters the Auto Partition mode.

[0066] The algorithm analyzes the logical correlation of the 35 error POs. Through netlist topology analysis, it is found that 17 of them are concentrated in the filter coefficient calculation module, and the logical correlation between them is relatively high (the average correlation degree is 0.65). Based on the greedy selection strategy, the algorithm selects these 17 errors as the first processing subset (Subset_1). Resource evaluation shows that processing Subset_1 is expected to require 15GB of memory and 45 minutes of calculation time, both of which are within the constraint range.

[0067] ​For Subset_1, the algorithm constructs a local netlist model containing the filter coefficient calculation logic, which contains about 120,000 logic gates. Through the BDD function matching algorithm analysis, the main logic difference is concentrated in the coefficient precision expansion (from 16 bits to 24 bits) and the rounding method change (from truncation to rounding).

[0068] The functional patch patch_1.v generated by logic synthesis contains input ports: 23 (connected to the coefficient input and control signal of the original netlist); output ports: 17 (corresponding to the error PO in Subset_1); internal logic: 1247 gates (equivalent to 1.35 times the original logic).

[0069] patch_1.v is successfully merged into the original netlist to generate the intermediate netlist ecoed_netlist_v1. Formal verification confirms that all 17 errors in Subset_1 are corrected, and the logic function of other POs is not affected. Area increase: about 1800 equivalent gates.

[0070] Re-execute the logic equivalence check, and the number of remaining error POs is reduced to 18, and the first round of Auto Partition is successfully completed.

[0071] The second round of Auto Partition corrects the data path control module based on the remaining 18 errors, and the algorithm executes the partition strategy again. Analysis found that 12 of the errors are located in the data path control module, with moderate degree of logical correlation (average correlation degree 0.42). Select these 12 errors as the second processing subset (Subset_2).

[0072] The generated functional patch patch_2.v mainly corrects the multiplexing logic of the data path and the pipeline control signal. Patch size: 956 logic gates, successfully corrects all 12 errors.

[0073] The merged netlist ecoed_netlist_v2 has 6 remaining errors.

[0074] The third round of Auto Partition corrects the output formatting module, and the remaining 6 errors are distributed in the output formatting module, with low correlation degree (average correlation degree 0.28) between each other. However, due to the small number, the algorithm decides to handle them at once.

[0075] The generated functional patch patch_3.v mainly involves output data bit width adjustment and format conversion logic. Patch size: 342 logic gates, successfully corrects all 6 errors.

[0076] The final netlist ecoed_netlist_v3 is completely consistent with the target netlist, and the number of error POs is 0.

[0077] Through three rounds of Auto Partition, the ECO correction of the DSP unit is successfully completed by the method of the application, the correction by the traditional method fails and cannot generate a result, and the total calculation time of the three rounds of Auto Partition of the method of the application is 2.3 hours and the peak memory usage is 17 GB.

[0078] Total patch size: 3545 logic gates; area overhead: about 2.4% (relative to the original design); timing impact: the critical path delay increases by 3%, which is within an acceptable range; power consumption increases: about 1.8%.

[0079] The application example fully embodies that the algorithm of the application can automatically identify errors in the filter coefficient module having strong relevance through logical relevance analysis, and the errors are preferentially processed to achieve the maximum correction benefit. Three rounds of Auto Partition show a clear convergence trend, and each round of Auto Partition significantly reduces the number of remaining errors, verifying the convergence of the algorithm. By decomposing a large-scale problem into multiple sub-problems, a correction task that cannot be handled originally can be completed under limited resources. The generated patch size is reasonable, and the area overhead and timing impact are within the engineering acceptable range, which embodies the effective control of the algorithm on the patch quality.

[0080] The application example shows that the Auto Partition type ECO method of the application can effectively solve the resource bottleneck and convergence problem faced by the traditional ECO technology in large-scale netlist correction, and provides a practical ECO solution for modern large-scale integrated circuit design.

[0081] The application is described through specific embodiments, and those skilled in the art should understand that various transformations and equivalent substitutions can be made to the application without departing from the scope of the application. In addition, various modifications can be made to the application for specific situations or materials without departing from the scope of the application. Therefore, the application is not limited to the disclosed specific embodiments, but should include all embodiments falling within the scope of the claims of the application.

Claims

1. A functional ECO auto-partitioning correction method for implementing fast ECO of large scale netlist, characterized in that, The method comprises the following steps: Step S1, receiving a user inputted original netlist and target netlist, comparing the original netlist and the target netlist through logical equivalence checking, and identifying a set of output port errors PO in the original netlist; Step S2, attempting to make one-time ECO correction to the set of error POs, and if the correction is successful, ending the process, and if the correction fails, entering step S3; Step S3, selecting a subset of error POs with controllable size from the set of error POs according to preset computing resource constraints; Step S4, generating a function patch for the selected subset of error POs; Step S5, merging the function patch into the current original netlist to generate an updated netlist; Step S6, re-performing logical equivalence checking based on the updated netlist to obtain a set of remaining error POs; determining whether a termination condition is met, and if so, ending the process, and if not, entering step S7; Step S7, taking the updated netlist as a new original netlist, taking the set of remaining error POs as a new set of error POs, and repeating steps S3 to S6.

2. The functional ECO automatic partitioning correction method of claim 1, wherein, In the set of error POs, the logical correlation between error POs is analyzed, the computing resources required for correcting each subset of error POs are calculated, the subset of error POs that meets the filtering condition is selected, and the subset of error POs with controllable size is obtained; The filtering condition includes that the number of error POs in the subset does not exceed a preset number threshold, the error POs in the subset meet a logical correlation threshold, and the computing resources required for correcting the subset do not exceed the current available computing resources.

3. The functional ECO automatic partitioning correction method of claim 2, wherein, The logical equivalence checking in step S1 uses combination equivalence checking, which constructs a mixer Miter circuit, performs an exclusive OR operation on the corresponding outputs of the original netlist and the target netlist, and uses a SAT solver to determine whether the exclusive OR result is always 0.

4. The functional ECO automatic partitioning correction method of claim 3, wherein, The specific steps for generating a function patch are as follows: Step S4.1, constructing a local netlist model based on the selected subset of error POs, the local netlist model including fan-in cones and shared logic of the subset of error POs; Step S4.2, using a matching algorithm to analyze the logical differences between the subset of error POs and the corresponding part of the target netlist, the matching algorithm using binary decision diagram BDD or and-inverter graph AIG for function representation and comparison; Step S4.3, generating a minimum function patch that can eliminate the logical differences through logic synthesis, the function patch including input ports, output ports, and internal logic gates.

5. The functional ECO automatic partitioning correction method of claim 4, wherein, The function patch needs to correct at least the logical function of one error PO itself; and does not change the logical behavior of other correct POs in the original netlist; the input ports of the patch are connected to the internal signal nodes of the original netlist, and the output ports replace the corresponding error POs.

6. The functional ECO automatic partitioning correction method of claim 5, wherein, The function patch merging operation in step S5 includes: establishing a connection between the input ports of the function patch and the corresponding signal nodes in the original netlist; replacing the corresponding error POs in the original netlist with the output ports of the function patch; updating the topology and signal propagation relationship of the netlist to ensure the integrity and consistency of the netlist.

7. The functional ECO automatic partitioning correction method of claim 6, wherein, Re-perform the logic equivalence check based on the updated netlist to obtain a remaining error PO set, and determine that a termination condition is met and end the process when the remaining error PO set is empty, or the remaining error POs cannot form a subset that meets the computing resource constraints, or the number of Auto Partition times reaches a preset maximum Auto Partition times.

8. The functional ECO auto-partition revision method of claim 7, wherein, The computing resource constraint conditions include a memory usage constraint, a computing time constraint, a logic gate number constraint, and a netlist size constraint.

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