A method and device for generating a CSI protocol excitation based on an emulation platform

Abstract

The application discloses an emulation platform-based CSI protocol excitation generation method and device, relates to the chip verification technical field, and is characterized in that the method is based on an emulation platform, a CSI2 virtual generator is realized through a Verilog language, and the method comprises the following steps: obtaining external register configuration information and performing analysis, the register configuration information comprises PHY mode selection and channel selection and the like, the PHY mode selection supports a DPHY protocol and a CPHY protocol; reading image data from an image storage memory based on the analyzed register information, performing image data packetization according to the PHY mode selection, and performing sending; and performing polling according to the channel configuration, outputting the image data packet to a PPI interface, and realizing image excitation input to a SOC. The application can solve the technical problems of slow simulation speed and reduced verification efficiency in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and in particular to a CSI protocol excitation generation method and device based on an emulation platform. BACKGROUND

[0002] In the chip design process, chip verification is a very important link. Chip verification engineers need to verify whether the chip design specific implementation conforms to the design intention according to the design implementation specification description. SOC (System On Chip, system-level chip) is getting larger and larger, and the function is getting more and more, and the chip research and development cycle is getting more and more nervous, which brings great challenges to chip verification. How to complete the verification work faster and more efficiently within the specified time is a problem that every verification engineer has been thinking about.

[0003] As shown in Figure 1 The prior art scheme uses CPHY or DPHY protocol when used, and needs to decide to use CPHY model or DPHY model according to whether CSI2 (Camera Serial Interface 2, camera serial interface) in SOC uses CPHY or DPHY protocol, to replace CSI2 C / DPHY in SOC for excitation at PPI (PHY-Protocol Interface) interface. If there are two kinds of CSI2 PHY protocols of CPHY and DPHY in SOC, DPHY model needs to be used when verifying DPHY, and CPHY model needs to be replaced and recompiled when verifying CPHY. The simulation process of the emulation platform is: first step model integration, second step version compilation, third step verification simulation, so when switching the model, model integration and version compilation need to be performed again.

[0004] After the compiled version is completed, the simulation is started. First, the relevant configuration of CMODLE (C model) is completed on the software side through c / c++ language, then the transmission of image data is completed through the software and hardware interaction interface, and finally the excitation generated according to the CSI2 protocol is output to the SOC DUT (Design Under Test, design under test) through the BFM. Since the scheme contains a non-comprehensive part, the CSI excitation must be generated based on the SA mode on the emulation platform. Since the third step verification simulation is realized through the cooperation of software and hardware, there is a time loss of software side processing, software and hardware synchronization and hardware side processing. Through the related data generated by the emulation self-owned statistics function, it can be found that the software side and the software and hardware synchronization time consumption proportion is 47.86% and 48.2% respectively, and the two parts of the time consumption proportion adds up to more than 95%, while the actual hardware side processing time is only 3.94%, which leads to slow simulation speed and low verification efficiency. SUMMARY

[0005] The application provides a CSI protocol excitation generation method and device based on an emulation platform, which can solve the technical problems of slow simulation speed and reduced verification efficiency in the prior art.

[0006] In a first aspect, the embodiments of the application provide a CSI protocol excitation generation method based on an emulation platform, which is based on an emulation platform and realizes a CSI2 virtual generator through a Verilog language, and includes the following steps:

[0007] Obtaining and parsing external register configuration information, wherein the register configuration information includes PHY mode selection and channel configuration, and the PHY mode selection supports DPHY protocol and CPHY protocol;

[0008] Reading image data from an image memory based on the parsed register information, and performing image data packetization and sending according to the PHY mode selection;

[0009] Outputting the image data packet to a PPI interface according to the polling of the channel configuration, to realize image excitation input to a SOC.

[0010] In combination with the first aspect, in an implementation mode, the step of obtaining and parsing external register configuration information includes the following steps:

[0011] Determining the configuration register value of the DPHY protocol or the CPHY protocol according to the PHY mode selection, and determining the channel number and interleaving mode according to the channel configuration, wherein the interleaving mode includes row interleaving and frame interleaving;

[0012] Parsing the image resolution and image format according to the register configuration information, and calculating the image data amount to read corresponding image data from the image memory.

[0013] In combination with the first aspect, in an implementation mode, the step of obtaining and parsing external register configuration information includes the following steps:

[0014] If the register configuration information contains abnormal excitation parameters, adjusting the data packetization according to the abnormal excitation parameters to generate a data packet of an unexpected format or an error resolution.

[0015] In combination with the first aspect, in an implementation mode, the register configuration information is received through multiple configuration modes, including automatic configuration based on a rom, a general configuration interface based on a standard apb bus, and signal forced setting based on a tcl script; and the configuration modes support dynamic reconfiguration or error insertion during simulation.

[0016] In combination with the first aspect, in an implementation, if the rom-based automatic configuration is adopted, the configuration file is stored in the rom by a backdoor mode, is actively read from the rom by the CSI2 virtual generator, and is parsed into the register configuration information; the PHY mode selection and the channel configuration are set according to the configuration file, and a start signal is enabled to activate data reading.

[0017] In combination with the first aspect, in an implementation, if the tcl script-based signal forced setting is adopted, corresponding signal values are directly forced, and the image format and the timing parameter are parsed according to the signal values.

[0018] Alternatively, if the tcl script-based signal forced setting is adopted, the configuration is completed by a packaged register read-write function, wherein the register read-write function operates on a single register or a single function domain in a certain register.

[0019] In combination with the first aspect, in an implementation, the image data packetization according to the PHY mode selection comprises:

[0020] The image data read from the image memory is determined to have a packetization format according to the PHY mode selection, a virtual channel identifier value is inserted into the image data according to the channel configuration, and a frame start packet and a frame end packet are added to the image data.

[0021] If the register configuration information indicates that a line start packet and a line end packet are added, the line start packet and the line end packet are inserted into each line of data.

[0022] In combination with the first aspect, in an implementation, the polling according to the channel configuration to output the image data packet to the PPI interface comprises:

[0023] A plurality of channels are determined according to the strobe signal in the channel configuration, and fair polling is performed to select a current output channel.

[0024] The amount of transmitted data and the number of frames are independently calculated for each channel to determine whether data needs to be output, and the data packet is output to the PPI interface.

[0025] In combination with the first aspect, in an implementation, new register configuration information is received in the simulation process, and new configuration parameters are parsed.

[0026] The second aspect provides a CSI protocol excitation generation device based on an emulation platform, which is realized by using a Verilog language to implement a CSI2 virtual generator based on the emulation platform, and comprises:

[0027] a register configuration and analysis module configured to acquire and analyze external register configuration information, the register configuration information including PHY mode selection and channel configuration, the PHY mode selection supporting DPHY protocol and CPHY protocol;

[0028] an image data packetization module configured to read image data from an image memory based on the analyzed register information, packetize and send the image data according to the PHY mode selection;

[0029] an image data output module configured to output the image data packet to a PPI interface according to the channel configuration, and realize image stimulus input to a SOC.

[0030] The technical scheme provided by the embodiments of the present application has the following beneficial effects:

[0031] Based on the emulation platform, the CSI2 virtual generator is implemented in a pure hardware (Verilog language) manner, eliminating the time loss of software side and software and hardware synchronization. For the same image data, the single-frame sending time is reduced from more than 1 hour to 2 minutes and 30 seconds, and the data and the hardware side processing time consumption ratio in the prior art scheme are 3.94%, which is basically consistent. Therefore, it can be seen that the subsequent simulation efficiency is obviously improved. Moreover, since the part of the code is completely synthesizable, it can be used not only in the ICE mode, but also in the SA mode, and is no longer limited by the use mode.

[0032] The external register configuration information is acquired and analyzed, the register configuration information includes PHY mode selection and channel configuration, the PHY mode selection supports DPHY protocol and CPHY protocol, and since the compatibility design of CPHY and DPHY is made, when the two PHYs are switched, it is not necessary to remount or compile the version, but only the configuration of a register can be realized, and the subsequent simulation of the multi-media channel can be faster and more efficient. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A CSI protocol stimulus generation scheme based on an emulation platform in the background art of the present application;

[0034] Figure 2 A CSI protocol stimulus generation method flowchart based on an emulation platform in the embodiments of the present application;

[0035] Figure 3 A CSI protocol stimulus generation and verification schematic diagram based on an emulation platform in the embodiments of the present application;

[0036] Figure 4Fig. 1 is a schematic diagram of an implementation architecture of a CSI2 virtual generator according to an embodiment of the present application.

[0037] Figure 5 Fig. 2 is a schematic diagram of different configuration schemes of registers according to an embodiment of the present application.

[0038] Figure 6 Fig. 3 is a schematic diagram of an image data packet grouping process according to an embodiment of the present application.

[0039] Figure 7 Fig. 4 is a schematic diagram of an image data output process according to an embodiment of the present application.

[0040] Figure 8 Fig. 5 is a schematic diagram of an embodiment of a SOC containing multiple CSI2 controllers according to the present application.

[0041] Figure 9 Fig. 6 is a schematic diagram of a CSI protocol stimulus generation device based on an emulation platform according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0043] First, some technical terms in the present application are explained and described in order to facilitate the understanding of the present application by those skilled in the art.

[0044] CSI2: Camera Serial Interface2, camera serial interface; CSI2 refers to the second generation protocol of CSI.

[0045] ICE mode: In-Circuit Emulation mode, in-circuit emulation mode.

[0046] SA mode: Simulation Acceleration mode, software simulation acceleration mode.

[0047] CMODLE: a model written based on c / c++, c / c++ is a computer programming language.

[0048] PPI: PHY-Protocol Interface, which is a key interface between the physical layer and the protocol layer defined in the MIPI PHY specification, and its core function is to realize fine control at the data lane level.

[0049] rom: read-only memory, read-only memory.

[0050] APB: Advanced Peripheral Bus, is the peripheral bus in the AMBA (Advanced Microcontroller Bus Architecture) bus architecture proposed by ARM Company, mainly used for connecting low-speed, low-power peripheral devices and configuration registers.

[0051] ls: line start, line start marker.

[0052] le: line end, line end marker.

[0053] For the multimedia image processing link in SOC, a more typical scenario is: taking the camera as the input source, and then performing various image algorithms (such as time domain denoising, distortion correction, color difference correction, image scaling, etc.) processing, and finally outputting as display or other purposes.

[0054] For the conventional UVM (Universal Verification Methodology) verification method, single-subsystem high-resolution image (such as 2K, 4K) single-frame simulation often needs several days or even longer time. If the multi-media link is debugged, single-frame simulation may need to be calculated by week. When there are more subsystems on the multimedia link, the simulation time consumption will certainly increase accordingly. If you consider the debug and multiple iterations, the multi-subsystem (generally considered 3 or more) debugging based on the UVM platform is obviously not a good choice.

[0055] Therefore, the debugging of the multimedia subsystem is selected on a more efficient emulation platform. Emulation mainly provides two simulation modes, one is ICE mode (In-Circuit emulation mode), using this mode, the design must be completely synthesizable, and this part is all running on the palladium emulator. The other is SA mode (Simulation Acceleration mode), using this mode, the design can contain non-synthesizable parts, and only the synthesizable part is running on the palladium emulator.

[0056] In the SA mode, the advantage is that non-synthesizable code can be used through the software and hardware interaction interface, such as the cmodel part written in c / c++ in the original scheme. This mode can also interact with the system verilog implementation used in the UVM verification, and can use part of the code of the UVM verification environment to complete the register configuration, data comparison and other functions. However, in this mode, if the operation includes a software part, since this part of the operation cannot directly act on the hardware, it will inevitably cause time consumption of the software part and the software and hardware synchronization part. The interaction between the software side and the hardware side is usually through the way of task / function call. The software side calls the task / function defined on the hardware side or the hardware side calls the task / function defined on the software side, which is called tbcall. Each tbcall causes synchronization between the software and the hardware. The more signals that need to be synchronized between the software side and the hardware side, the more consumption caused by the synchronization. For the scene of starting only the CSI work in the multimedia link and using the original scheme to stimulate the CSI, the profile option provided by the emulation is used to perform time consumption statistics on the simulation stage, and it is found that the time consumption proportions of the software side, the software and hardware synchronization and the hardware side are 47.86%, 48.2% and 3.94% respectively. The actual simulation running time of a frame of 33ms image transmission is greater than 1h.

[0057] Compared with the UVM platform, the simulation efficiency of the original scheme is obviously improved. However, considering that there are many multimedia links that need to be debugged in the actual SOC, there are many subsystems on a single link, the image resolution is large (the data amount processed is large), and different paths and applications may need to use different configuration transmission modes, it is hoped that a scheme can be provided to support more flexible configuration and further improve the simulation efficiency.

[0058] From the simulation efficiency and time consumption proportion based on the SA mode, it can be seen that the proportion of time actually processed by the hardware is relatively small, so the application adopts a pure hardware (verilog language) mode to eliminate the time loss of the software side and the software and hardware synchronization. In combination with the verification requirement, it is necessary to complete the simulation of multiple multimedia paths faster and more efficiently, so it is necessary to use as simple logic as possible to realize relatively complete verification stimulation, instead of realizing complete CSI functions according to the CSI protocol.

[0059] Therefore, the CSI protocol stimulation generation method based on the emulation platform provided in the embodiments of the application is based on the emulation platform and realizes a CSI2 virtual generator in the Verilog language.

[0060] As shown in Figure 2 The CSI protocol stimulation generation method includes the following steps:

[0061] S1: Obtain and parse external register configuration information, the register configuration information including PHY mode selection and channel configuration, the PHY mode selection supporting DPHY protocol and CPHY protocol.

[0062] S2: Read image data from an image memory based on the parsed register information, pack the image data according to the PHY mode selection, generate an image data packet and send the image data packet.

[0063] S3: Poll and output the image data packet to a PPI interface according to the channel configuration, to realize image excitation input to a SOC.

[0064] In the embodiment, the CSI2 Virtual Generator is implemented by using the emulation platform in the manner of the Verilog language, the Verilog language is a hardware description language, thus eliminating the time loss of software side and software and hardware synchronization. Moreover, since the code is completely synthesizable, it can be used not only in the ICE mode but also in the SA mode, and is no longer limited by the use mode. The PHY mode selection supports the DPHY protocol and the CPHY protocol, when the two PHYs are switched, it is not necessary to remount or compile the version, but only a register configuration can be implemented, and the subsequent simulation of the multi-media channel can be faster and more efficient.

[0065] As shown in Figure 3 , it is a schematic diagram of CSI protocol excitation generation and verification based on the emulation platform of the embodiment of the application. In the whole verification environment, the CSI2 Virtual Generator is used to replace the original CSI2 C / DPHY of the SOC CSI2 controller at the PPI interface, and the CSI2 Virtual Generator is also used to replace the CPHY model and the DPHY model outside the SOC in the prior art (such as the blue part in Figure 1 ).

[0066] In order to adapt to more scene excitation, the application provides a relatively flexible register configuration mode, which can be dynamically configured and provide excitation of part of abnormal scenes, and can support multiple configurations.

[0067] In the step S1, the external register configuration information is acquired and parsed, including: determining the configuration register value of DPHY protocol or CPHY protocol for PHY mode selection. Specifically, since CPHY and DPHY have differences in PPI port output (such as different packet assembly formats for data packets, different output data arrangements, etc.), the common practice is to treat the two as independent stimulation models. However, when simulation is performed on an emulation platform, different models need to be integrated with different versions, and the compilation of a large SOC version may take more than tens of hours. In the embodiment, CPHY and DPHY are designed for compatibility, and the CSI2 virtual generator can automatically assemble and output data according to the CPHY or DPHY standard protocol only by configuring the phy_mode register.

[0068] In addition, in the step S1, the external register configuration information is acquired and parsed, including determining the number of channels and the interleaving mode by combining channel configuration, and the interleaving mode includes row interleaving and frame interleaving. Specifically, considering that in actual applications, several camera data often converge and input to a group of CSI2 PHY+controller channels at the same time, and the specific source of each camera is distinguished by different vcid (virtual channel id) values. Therefore, the method supports input of 1-8 different data sources, and realizes this by configuring and adding different VCID values and channel gating signals. In addition, the final output form of image data on the PPI interface can also be configured by interleave_mode to select the output mode of row interleaving or frame interleaving.

[0069] Since the mainstream of the current application supports CPHY 3lane and DPHY 4lane, in an embodiment, a lane_num register is provided to control the number of lanes, which is used in combination with the PHY mode (PHY mode selection) to support 3lane or 4lane mode output.

[0070] The PPI interface currently uses DPHY 8bit / 16bit and CPHY 16bit. In an embodiment, a bit_mode register is provided to control whether 8bit or 16bit is used. The register is used in combination with the PHY mode and lane_num.

[0071] Usually a frame image input needs to include frame start and frame end packets to control the start and end of the image. Whether each line of data needs to contain line start and line end is determined according to the input source. In the design of the scheme, the ls_le_bypass register is reserved to control whether the addition needs to be added in each line of data.

[0072] In order to better construct different timing, in an embodiment, a part of the registers are reserved to control the timing, such as controlling the inter-row or inter-frame blanking addition of inter-row banking (hbanking) and inter-frame blanking (vblanking), the stop_state_time register for controlling the stop state, etc., supporting the configuration of hbanking, vblanking and other timing parameters.

[0073] In addition, in order to support the configuration of image resolution, a set of vactive and hactive registers are provided for each channel to control the configuration of image resolution.

[0074] A data_type register is provided for each channel to control the image format. Different channels of the same CSI2 virtual generator support the need to send different resolutions, frame numbers and image formats. The image format supports mainstream RAW12, RGB888, YUV420-8bit, YUV422-8bit, YUV420-10bit, and YUV422-10bit.

[0075] For the same CSI2 virtual generator, channel_sel is provided to select which of the 8 channels, and independent resolution configuration, transmission frame number, image format, vcid and other configuration information are provided for the 8 channels to realize the independent transmission mode of different channels.

[0076] Further, if the register configuration information contains abnormal excitation parameters, the data group packet is adjusted according to the abnormal excitation parameters to generate abnormal data packets of unexpected format or error resolution, etc. For example, in order to support the abnormal excitation scene of unexpected format, error resolution, non-standard timing, etc. The unexpected format output can be configured by data_type, the error resolution can be configured by configuring vactive and hactive, the non-standard timing can be configured by configuring the timing control register, and additional frame start, frame end, line start, line end and other abnormal scenes can be configured to verify whether there is an abnormal report and whether the processing meets the expectation.

[0077] As Figure 4 shown, it is an implementation architecture diagram of a CSI2 virtual generator of an embodiment of the present application. The implementation architecture mainly includes three parts of register configuration and analysis (csi2_regblock+csi2_rom), image data packetization (csi2_data_manager), and image data output (csi2_lane_manager). Wherein, csi2 refers to the second generation protocol of CSI.

[0078] The register configuration and analysis part implements the above step S1, completes the register configuration and analysis of the CSI2 virtual generator, and all the configuration information mentioned above is analyzed in this part, including the selection of CPHY and DPHY modes, the dynamic reconfigurable values of each register, the configuration of abnormal implementation dynamic error insertion, etc. The register configuration and analysis part will receive and analyze the externally input register configuration information, and then output the analysis value to the image data packetization part and the image data output part, so that these two parts complete the packetization and transmission of data according to the user's configuration of the expected scene.

[0079] Further, in the above step S1, the register configuration information can be received by multiple configuration methods, including automatic configuration based on rom, general configuration interface based on standard apb bus, and signal forced setting based on tcl script; the configuration method supports dynamic reconfiguration or error during simulation.

[0080] As Figure 5 shown, it is a schematic diagram of different register configuration schemes, providing four configuration methods, the main purpose of which is to provide a relatively flexible register configuration method, which can cope with different scene requirements through the configuration of registers, including but not limited to the selection of PHY mode, dynamic reconfigurable and dynamic error insertion. In actual application, the user can select any one of them to complete the configuration of the register according to the use habit and the condition possessed. Configuration method 1 is to obtain configuration information from rom, and the other three configuration methods are not directly obtained from rom.

[0081] Configuration method 1: automatic configuration based on rom storage, store configuration file in rom through backdoor, then read and analyze it into register configuration information by CSI2 virtual generator, set PHY mode selection and channel configuration according to pre-stored configuration file, and enable start signal to activate data reading.

[0082] Specifically, the read_rom signal force needs to be set to 1, so as to select the rom register value reading mode. Then the written register configuration file VIP CFG HEX is stored into the rom through the backdoor mode. When the enable is enabled, the CSI2 virtual generator starts to automatically read the configuration value stored in the rom and completes the analysis, and inputs the analysis value to the image data group packaging part and the image data output part to complete the image data output. Wherein, the force refers to the forced setting of the signal value, and the read_rom signal force being 1 means that the user needs to use the forced command of the simulation tool to force the read_rom signal to be high, so as to select the rom reading configuration value mode.

[0083] The advantage of the configuration mode 1 is that it does not need to depend on external excitation, and the emulaiton self-provided backdoor storage instruction can be directly used to store the configuration file. The disadvantage is that the user needs to separately write the VIP CFG HEX (VIP configuration file) file, and the more the VIP CFG HEX files need to be maintained when the scene is different.

[0084] The configuration mode 2 is a general configuration interface based on the standard apb bus, and the user needs to mount the apb driver to complete the register configuration. Each register is configured, and the CSI2 virtual generator immediately analyzes the signal configuration value corresponding to the register. When all the registers are configured, the enable signal is enabled, and the CSI2 virtual generator starts to work according to the configuration value.

[0085] The advantage of the configuration mode 2 is that as long as the register address and domain value arrangement is unchanged, no matter how the internal signal level or processing is changed, the mounting and configuration of the external apb driver are not affected. The disadvantage is that it needs to depend on external excitation, and the user needs to have an additional available apb driver. Moreover, if the register corresponding address or domain value arrangement is changed, the address or domain value needs to be synchronized on the apb driver side.

[0086] The configuration mode 3 adopts the signal forced setting based on the tcl script, directly forces the corresponding signal value, and analyzes the image format and timing parameters according to the signal value. Specifically, the tcl script based on the emulation can be directly used to complete the force corresponding signal. For example, the value of the lane_num signal needs to be set to 3, and the force statement is used to set the corresponding signal to the expected value, and the code form is as follows:

[0087] force csi2_vip_top.lane_num == 3;

[0088] After all the configuration signals force are verified, the enable signal, CSI2 Virtual Generator starts to work according to the configuration values.

[0089] The advantage of configuration method 3 is that it does not need to rely on external excitation, and the corresponding configuration value of the specific configuration signal is intuitive. The disadvantage is that the more related configurations, the more force signals are needed, resulting in relatively complex file maintenance. When the internal signal name or integrated path changes, the signal cannot be found, and needs to be modified.

[0090] Configuration method 4: Provide a tcl script based signal forced setting more suitable for emulation environment, through the encapsulated register read-write function to complete the configuration, wherein the register read-write function operates on a single register, and the register read-write filed function operates on a single field in a single register. Specifically, because the CSI2 virtual generator will provide a corresponding register document for users to view the configuration information of each register. These configuration information includes the address of the register, one or more functional fields contained in the register, the offset and width of each functional field, etc. This embodiment provides a script, which can generate a register model according to these key information after calling the script to specify the register document. Through the naming of the register, all related information can be found. At the same time, four register read-write functions are encapsulated in the tcl file, which are csi2_vip_reg_write_proc, csi2_vip_reg_read_proc, csi2_vip_reg_field_write_proc and csi2_vip_reg_field_read_proc. csi2_vip_reg_write_proc and csi2_vip_reg_read_proc mainly complete the read-write operation of the register, and a register is taken as a unit of 32 bits. csi2_vip_reg_field_write_proc and csi2_vip_reg_field_read_proc mainly complete the read-write operation of a single functional field of a register. Each time the function is called, a register configuration operation will be completed at the apb interface. This embodiment solves the problem of file maintenance difficulty caused by too many direct force register signals in the above-mentioned configuration methods 2 and 3, and the need for additional mounting of apb driver. When the register address changes and the field changes, the table (such as Table 1) needs to be updated, and a new model needs to be generated by calling the script again.

[0091] The following describes configuration mode 4 by means of a specific embodiment. As shown in Table 1 below, a 32-bit lane_config register needs to be configured, which contains 7 fields, i.e. a lane num field for controlling the number of lanes, an interleave_mode field for selecting frame interleaving or line interleaving, a phy_mode field for selecting CPHY or DPHY, a bit_mode field for selecting 8-bit or 16-bit output of a PPI port, a stop_state_time field for controlling a stop_state timing, an ls_le_bypass field for indicating whether to add line start and line end packet data, and a channel_sel field for selecting a 1-8 channel selection signal.

[0092] Table 1 (Register field description of the lane_config register)

[0093]

[0094] The traditional force mode of configuration mode 3 needs to force each field independently, which requires 7 lines of code to complete. The code form is as follows:

[0095] force csi2_vip_top.lane_num == 3

[0096] force csi2_vip_top.interleave_mode == 0

[0097] force csi2_vip_top.phy_mode == 0

[0098] force csi2_vip_top.bit_mode == 1

[0099] force csi2_vip_top.stop_state_time == 58

[0100] force csi2_vip_top.ls_le_bypass == 1

[0101] force csi2_vip_top.channel_sel == 3

[0102] However, according to configuration mode 4, only one line of code is needed to call the csi2_vip_reg_write_proc function once and pass in the register name csi2_0_lane_config and the write data (0x39d23). The code form is as follows:

[0103] csi2_vip_reg_write_proc $csi2_0_lane_config 0x39d23 0

[0104] The last 0 of the code represents the first group of CSI2 virtual generators (CSI2 Virtual Generator) to achieve multiplexing, and independent configuration of different CSI2 virtual generators. The CSI2 virtual generator automatically completes the analysis of each functional domain signal according to the register configuration value.

[0105] It can be seen that the configuration method 4 can reduce the complexity of the code to a certain extent. With the subsequent iteration and upgrade of the CSI2 virtual generator, the register configuration will be more and more, and the benefit of the configuration method 4 will be more obvious.

[0106] The embodiment also provides csi2_vip_reg_field_write_proc and csi2_vip_reg_field_read_proc for the assignment function of each functional domain in the register. For example, only want to change the lane_num field in the Lane_config register to 2, without changing other field values. One way is to keep other field values unchanged, and only change the lane_num field value to configure the entire register.

[0107] csi2_vip_reg_write_proc $csi2_0_lane_config 0x39d23 0

[0108] Another way is:

[0109] csi2_vip_reg_field_write_proc $csi2_0_lane_config_lane_num 0x2 0.

[0110] The above four configuration methods all support dynamic reconfiguration or error during simulation. As long as the register configuration is reconfigured during running, the new register configuration information is received and analyzed to select a new PHY mode and channel configuration during simulation.

[0111] For example Figure 4As shown, the above step S2 is implemented by the image data packetizing (csi2_data_manager) part. In the above step S1, the image resolution and image format can be parsed according to the register configuration information, and the image data amount can be calculated, so in the above step S2, the image data packetizing part can calculate the image data amount and the storage mode according to the image resolution and image format information configured by the register, read the image data from the image memory (image_rom), determine the packetizing format according to the PHY mode selection, insert the virtual channel identification value (vcid) according to the channel configuration, add the frame start packet (frame start) and the frame end packet (frame end) to the image data; if the register configuration information indicates that the line start packet (line start) and the line end packet (line end) are added, the line start packet and the line end packet are inserted in each line of data.

[0112] As shown, the specific steps include the following steps: Figure 6

[0113] S21: reading the image data from the image memory according to the image resolution and image format information.

[0114] S22: determining whether to packetize according to DPHY according to the configured phy_mode selection, if yes, entering S23; if no, entering S25.

[0115] S23: generating the data packet according to the DPHY protocol by the DPHY packet generator sub-module, while adding the vcid information corresponding to the channel configuration, to generate the packet information meeting the requirements of the DPHY protocol, such as frame start, line start, payload, line end, frame end, etc.

[0116] S24: outputting the data packet to the image data output part according to the byte sequence of DPHY.

[0117] S25: generating the data packet according to the CPHY protocol by the CPHY packet generator sub-module, while adding the vcid information corresponding to the channel configuration, to generate the packet information meeting the requirements of the CPHY protocol, such as frame start, line start, payload, line end, frame end, etc.

[0118] S26: outputting the data packet to the image data output part according to the byte sequence of CPHY.

[0119] As shown, the specific steps include the following steps: Figure 4 ​As shown, the image data output (csi2_lane_manager) part is used to implement the above step S3, and the image data output part determines a plurality of channels according to a gating signal in the channel configuration, and performs fair polling to select a current output channel. The amount of transmitted data and the number of frames are calculated independently for each channel to determine whether there is data to be output, and the data packet is output to the PPI interface. Specifically, fair polling is performed according to the channel selected by channel_sel. First, it is necessary to determine whether to output according to frame polling or line polling according to the interleave_mode information. When the channel is selected, it is necessary to calculate whether there is data to be transmitted according to the configuration information and the transmitted image data information. Then, the timing is constructed according to the value of the timing related register configuration. Finally, it is necessary to determine the final output standard according to the PHY mode, bitmode and lane num information. If the interleave mode is configured as line interleaving, the data packets of the plurality of channels are alternately output by line.

[0120] As shown, the image data output flowchart in the embodiment is shown, and the steps include: Figure 7

[0121] S31: The channel is selected, and it is determined whether there is image data to be transmitted. If yes, S32 is entered; if no, S36 is entered.

[0122] S32: It is determined whether interleave_mode is frame interleaving. If yes, S33 is entered; if no, S34 is entered.

[0123] S33: The complete frame data of the current channel is transmitted, and S35 is entered.

[0124] S34: The data packet of the current channel is transmitted according to the current transmission position (frame start, line start, packet, line end, frame end), and S35 is entered.

[0125] S35: The final output standard is determined according to the configuration values PHY mode, bit mode and lane num information.

[0126] S36: The next channel is determined (polling), and S31 is entered.

[0127] In an embodiment, when a plurality of CSI2 controllers are contained in a SOC, a CSI2 virtual generator is mounted for each CSI2 controller as shown in the following figure, and each CSI2 virtual generator is independently configured. In the tcl configuration scheme, the value in the csi2_idx column is determined.​Figure 8 The csi_idx shown is 0, and the first group of CSI2 virtual generators is configured.

[0128] The CSI2 virtual generator considers a certain scalability in module division, such as being able to support a maximum of 8 channels of row interleaving or frame interleaving output mode by default according to the current design, if it is needed to be expanded to 16 channels, the image data packet can be instantiated 16 times, and the arbitration mechanism can be expanded to 16 in the image data output.

[0129] In a second aspect, the embodiments of the present application also provide a CSI protocol stimulus generation device based on an emulation platform. As shown in the figure, Figure 9 Based on the emulation platform, the CSI2 virtual generator is implemented by using the Verilog language, and the device includes a register configuration and analysis module, an image data packet module, and an image data output module.

[0130] The register configuration and analysis module is used to obtain and analyze external register configuration information, the register configuration information includes PHY mode selection and channel configuration, and the PHY mode selection supports DPHY protocol and CPHY protocol;

[0131] The image data packet module is used to read image data from an image storage based on the analyzed register information, and perform image data packet and sending according to the PHY mode selection;

[0132] The image data output module outputs the image data packet to a PPI interface according to the polling of the channel configuration, and realizes image stimulus input to a SOC.

[0133] In the CSI protocol stimulus generation device based on the emulation platform, the functions of each module correspond to the steps in the CSI protocol stimulus generation method based on the emulation platform, and the functions and implementation processes will not be described here.

[0134] It should be noted that the serial numbers of the embodiments of the present application described above are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0135] The terms “include,” “comprise,” “have,” and any variations thereof, in the Specification and in the Claims of the present application, and the above-mentioned drawings, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a list of steps or units is not limited to the listed steps or units, but can optionally further include steps or units not listed, or can optionally further include other steps or units inherent to such processes, methods, products, or devices. The terms “first,” “second,” and “third” and the like descriptions are used to distinguish different objects, and do not represent a sequence or limit the types of “first,” “second,” and “third.”

[0136] In the description of the embodiments of the present application, “exemplary”, “for example”, or “for instance” is used to represent an example, an illustration, or a description. Any embodiment or design scheme described as “exemplary”, “for example”, or “for instance” in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words “exemplary”, “for example”, or “for instance” are intended to present the relevant concept in a specific manner.

[0137] In the description of the embodiments of the present application, unless otherwise specified, “ / ” represents the meaning of or, for example, A / B can represent A or B; “and / or” in the text only represents a description of the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. In addition, in the description of the embodiments of the present application, “multiple” means two or more than two.

[0138] In some of the processes described in the embodiments of the present application, a plurality of operations or steps are included in a specific order, but it should be understood that these operations or steps can be executed or performed in parallel or in an order different from that in which they appear in the embodiments of the present application. The serial number of the operation is only used to distinguish different operations, and the serial number itself does not represent any execution order. In addition, these processes can include more or fewer operations, and these operations or steps can be executed in sequence or in parallel, and these operations or steps can be combined.

[0139] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and a general hardware platform as required, of course, it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, an optical disk) as described above, and includes a plurality of instructions for causing a terminal device to execute the methods described in the embodiments of the present application.

[0140] The preferred embodiments of the present application have been described above with the illustrated embodiments, and are not intended to limit the scope of patent protection for the present application. Any equivalent structure or equivalent process variations, which directly or indirectly incorporate the contents of the specification and drawings of the present application, are also intended to be included within the scope of patent protection for the present application.

Claims

1. A method for generating CSI protocol excitations based on an emulation platform, characterized in that, The method is based on an emulation platform, and a CSI2 virtual generator is implemented by using a Verilog language, and includes the following steps: Obtaining and parsing external register configuration information, wherein the register configuration information includes PHY mode selection and channel configuration; determining the configuration register value of the DPHY protocol or the CPHY protocol according to the PHY mode selection, and determining the number of channels and interleaving modes according to the channel configuration, wherein the interleaving modes include row interleaving and frame interleaving; parsing the image resolution and the image format according to the register configuration information, and calculating the image data amount to read corresponding image data from an image memory; Reading the image data from the image memory based on the parsed register information, and performing image data packetization and sending according to the PHY mode selection; According to the channel configuration, polling is performed to output the image data packet to a PPI interface, so as to realize image excitation input to an SOC.

2. The emulation platform based CSI protocol stimulus generation method of claim 1, wherein, Obtaining and parsing external register configuration information, including: If the register configuration information contains abnormal excitation parameters, adjusting the data packetization according to the abnormal excitation parameters to generate a data packet in an unexpected format or an error resolution.

3. The CSI protocol excitation generation method based on an emulation platform according to claim 1, wherein: The register configuration information is received through multiple configuration modes, including automatic configuration based on a rom, a general configuration interface based on a standard apb bus, and signal forced setting based on a tcl script; and the configuration modes support dynamic reconfiguration or error insertion during the simulation process.

4. The CSI protocol excitation generation method based on an emulation platform according to claim 3, wherein: If the automatic configuration based on the rom is adopted, a configuration file is stored in the rom through a backdoor mode, the CSI2 virtual generator actively reads the configuration file from the rom, and the configuration file is parsed into the register configuration information; the PHY mode selection and the channel configuration are set according to the configuration file, and an enable start signal is enabled to activate data reading.

5. The CSI protocol excitation generation method based on an emulation platform according to claim 3, wherein: If the signal forced setting based on the tcl script is adopted, corresponding signal values are directly forced, and the image format and timing parameters are parsed according to the signal values; Or, if the signal forced setting based on the tcl script is adopted, the configuration is completed through a packaged register read-write function, wherein the register read-write function operates on a single register or a single function domain in a certain register.

6. The emulation platform based CSI protocol stimulus generation method of claim 1, wherein, The image data read from the image memory is packetized according to the PHY mode selection, virtual channel identifier values are inserted according to the channel configuration, and a frame start packet and a frame end packet are added to the image data; If the register configuration information indicates that a row start packet and a row end packet are added, the row start packet and the row end packet are inserted in each row of data. According to the channel configuration, polling is performed to output the image data packet to a PPI interface, including:

7. The emulation platform based CSI protocol stimulus generation method of claim 1, wherein, ​ A plurality of channels are determined according to the selected channel signal in the channel configuration, and a fair round-robin is performed to select a current output channel; The transmitted data amount and frame number are independently calculated for each channel to determine whether data needs to be output, and the data packet is output to the PPI interface.

8. The emulation platform based CSI protocol stimulus generation method of claim 1, wherein, In the simulation process, new register configuration information is received, and new configuration parameters are parsed.

9. A CSI protocol stimulus generation device based on an emulation platform, characterized by Based on the emulation platform, a CSI2 virtual generator is realized by using a Verilog language, and the device comprises: A register configuration and parsing module is configured to acquire and parse external register configuration information, wherein the register configuration information comprises a PHY mode selection and a channel configuration; a DPHY protocol or a CPHY protocol configuration register value is determined according to the PHY mode selection, and a channel number and an interleaving mode are determined in combination with the channel configuration, wherein the interleaving mode comprises row interleaving and frame interleaving; an image resolution and an image format are parsed according to the register configuration information, and an image data amount is calculated to read corresponding image data from an image memory; An image data packetization module is configured to read image data from the image memory based on the parsed register information, packetize and send the image data according to the PHY mode selection; An image data output module is configured to output the image data packet to a PPI interface according to the channel configuration, thereby realizing image excitation input to an SOC.

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