Trigger signal identification method and device, equipment and storage medium

Abstract

The invention relates to a trigger signal identification method and device, equipment and a storage medium. The trigger signal identification method comprises the following steps: acquiring an FPGA design code to be subjected to trigger signal identification; traversing at least one module code in the FPGA design codes, and extracting trigger signal features from block statements in the module codes and / or a target list; wherein the target list is composed of at least one field corresponding to the preset identifier, and the at least one field is used for representing the trigger signal information; performing function identification on the trigger signal features, and determining at least one trigger signal; and generating a trigger signal identification result according to the at least one trigger signal and the reference name of the at least one trigger signal in the corresponding module code. According to the method provided by the invention, the accuracy of trigger signal identification is improved, and the adaptability to complex design scenes is higher.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer technology, and in particular to a trigger signal identification method, device, equipment and storage medium. BACKGROUND

[0002] In the existing FPGA design process, the identification of clock signals and reset signals is crucial for timing analysis and logic verification in the code. Related methods mostly rely on naming rule matching, which matches the signal name by predefining a keyword, and classifies the signals that meet the naming rule as clock signals or reset signals. However, this method is limited by the standard naming signals (such as the clk keyword) in the naming rule, and is prone to miss non-standard naming signals (such as refcl), and may also misjudge irrelevant signals containing keywords (such as clk_en), resulting in low recognition accuracy and difficulty in adapting to complex design scenarios. SUMMARY

[0003] To solve the above technical problems, the embodiments of the present disclosure provide a trigger signal identification method, device, equipment and storage medium.

[0004] In a first aspect, the embodiments of the present disclosure provide a trigger signal identification method, comprising: obtaining FPGA design code to be identified for trigger signals; traversing at least one module code in the FPGA design code to extract trigger signal features from block statements and / or target lists in the module code; wherein the target list is composed of at least one field corresponding to a preset identifier, and the at least one field is used to represent trigger signal information; functionally identifying the trigger signal features to determine at least one trigger signal; generating a trigger signal identification result according to the at least one trigger signal and the reference name of the at least one trigger signal in the corresponding module code.

[0005] Optionally, the block statement is an always block, the target list is a sensitive list in the always block, and the at least one field includes the trigger signal and the edge type of the trigger signal.

[0006] Optionally, after functionally identifying the trigger signal features to determine at least one trigger signal, the method further comprises: analyzing the design hierarchy of the FPGA design code, and establishing a bidirectional transmission path for representing the global signal relationship according to the design hierarchy; verifying the at least one trigger signal along the transmission path in at least one direction of the bidirectional transmission path, and determining a final trigger signal from the at least one trigger signal if the verification is passed.

[0007] Optionally, the bidirectional transmission path comprises a forward transmission path and a reverse transmission path, and the verification of the at least one trigger signal along the transmission path in at least one direction of the bidirectional transmission path comprises: In the case of verification by the forward transmission path, the at least one trigger signal is verified layer by layer along the mapping relationship of the same signal recorded in the design hierarchy between different modules; wherein the mapping relationship is used to represent the hierarchical relationship between the combined name composed of the signal name and the module name; and / or, In the case of verification by the reverse transmission path, the trigger signal is verified by backtracking from the target sub-module corresponding to the trigger signal to the top-level module through a reverse search algorithm, and according to the known signal in the top-level module; wherein the FPGA design code comprises the code of the target sub-module and the top-level module.

[0008] Optionally, the verification of the at least one trigger signal along the transmission path in at least one direction of the bidirectional transmission path comprises: If it is determined that the trigger signal feature is a fuzzy feature, the at least one trigger signal is directly verified by the reverse transmission path.

[0009] Optionally, after the function identification of the trigger signal feature and the determination of the at least one trigger signal, the method further comprises: In the case that the at least one trigger signal comprises a reset signal, the trigger condition and / or execution logic in the target block statement corresponding to the reset signal are analyzed to determine the reset type of the reset signal; According to the at least one trigger signal and the reference name of the at least one trigger signal in the corresponding module code, a trigger signal identification result is generated, comprising: According to the at least one trigger signal, the reset type and the reference name of the at least one trigger signal in the corresponding module code, a trigger signal identification result is generated.

[0010] Optionally, after the generation of the trigger signal identification result, the method further comprises: Obtaining adjustment information of the FPGA design code; Updating the bidirectional transmission path according to the adjustment information, and re-determining the at least one trigger signal according to the updated bidirectional transmission path.

[0011] In a second aspect, the embodiments of the present disclosure provide a trigger signal identification device, comprising: An obtaining unit is configured to obtain FPGA design code to be identified for trigger signals; A feature extraction unit is configured to traverse at least one module code in the FPGA design code, and extract a trigger signal feature from a block statement and / or a target list in the module code; wherein the target list is composed of at least one field corresponding to a preset identifier, and the at least one field is used to represent trigger signal information. a signal determination unit configured to perform function recognition on the trigger signal features and determine at least one trigger signal; a result generation unit configured to generate a trigger signal recognition result according to the at least one trigger signal and a reference name of the at least one trigger signal in the corresponding module code.

[0012] In a third aspect, the embodiments of the present disclosure provide an electronic device, comprising: a memory; a processor; and a computer program; The computer program is stored in the memory and configured to be executed by the processor to implement the method of the first aspect as described above.

[0013] In a fourth aspect, the embodiments of the present disclosure provide a computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the method of the first aspect as described above.

[0014] The trigger signal recognition method provided by the present disclosure comprises: obtaining FPGA design code to be subjected to trigger signal recognition; traversing at least one module code in the FPGA design code, and extracting trigger signal features from block statements and / or target lists in the module code; wherein the target list is composed of at least one field corresponding to a preset identifier, and the at least one field is used to represent trigger signal information; performing function recognition on the trigger signal features to determine at least one trigger signal; and generating a trigger signal recognition result according to the at least one trigger signal and a reference name of the at least one trigger signal in the corresponding module code. The method provided by the present disclosure improves the accuracy of trigger signal recognition and is more adaptable to complex design scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure together with the specification.

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced here. Obviously, for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0017] Figure 1 A flowchart of a trigger signal recognition method provided by the embodiments of the present disclosure; Figure 2 A design block diagram of FPGA design code provided by the embodiments of the present disclosure; Figure 3A technical framework diagram of a trigger signal identification method provided by an embodiment of the present disclosure is shown in the following figure. Figure 4 A structural schematic diagram of a trigger signal identification device provided by an embodiment of the present disclosure is shown in the following figure. Figure 5 A structural schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown in the following figure. DETAILED DESCRIPTION

[0018] In order to more clearly understand the above-mentioned purposes, features and advantages of the present disclosure, the schemes of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0019] In the following description, many specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure can also be implemented in other ways different from those described herein; obviously, the embodiments in the description are only some of the embodiments of the present disclosure, not all the embodiments.

[0020] In view of the above technical problems, the present disclosure provides a trigger signal identification method. The method is specifically described in one or more of the following embodiments.

[0021] The trigger signal identification method provided by the embodiments of the present disclosure can be applied to the trigger signal identification scene. The method can be executed by a trigger signal identification device, which can be implemented by software and / or hardware, and the device can be integrated in an electronic device. The electronic device can include but is not limited to mobile terminals such as smart phones, notebook computers, digital broadcast receivers, personal digital assistants (PDA), tablet computers (Tablet PC), PMP (portable multimedia player), vehicle terminal (such as vehicle navigation terminal), wearable devices, and fixed terminals such as digital television, desktop computer, smart home device, etc.

[0022] Figure 1 A flowchart of a trigger signal identification method provided by an embodiment of the present disclosure is shown in the following figure, which specifically includes the following steps as shown in the figure. Figure 1 S101, obtaining FPGA design code to be identified for trigger signal.

[0023] ​It is understandable that the FPGA design code is usually written using a hardware description language to describe an independent functional unit. The FPGA design code is composed of a plurality of module codes, each of which is responsible for implementing a specific function, such as the description of the clock signal and / or reset signal related function of the module code, wherein the module is the basic building block of the design, which can include logic, registers, state machines, etc. In the module design of the FPGA, there can also be a hierarchical relationship between a plurality of modules, and the hierarchical relationship between the modules can also be reflected in the module codes.

[0024] Exemplary, Figure 2 The design diagram of the FPGA design code provided by the embodiment of the present disclosure shows a hierarchical FPGA module design, as shown in Figure 2 As shown, the plurality of modules includes a top module (also referred to as a first layer module) and a plurality of sub-modules subA, subB, subC and subD, wherein subA and subC are second layer modules, subB and subD are third layer modules, subA and subC are sub-modules of the top, and subB and subD are sub-modules of subA and subC, respectively, and so on. That is Figure 2 It also shows the interconnection relationship between the top module and the plurality of sub-modules, and is synchronized through a clock signal distribution network. A clock signal forward transmission path, the top transmits a clock signal a to subA, and subA transmits a clock signal b to subB, wherein the clock signal b is determined based on the clock signal a, or the clock signal b is the clock signal a. Other possible transmission paths are not described.

[0025] It is understandable that the trigger signal identification refers to the identification of the clock signal and / or the reset signal, and other trigger signals in the FPGA design code can also be identified according to requirements, which are not limited here.

[0026] S102, traversing at least one module code in the FPGA design code, extracting a trigger signal feature from a block statement and / or a target list in the module code.

[0027] The target list is composed of at least one field corresponding to a preset identifier, and the at least one field is used to represent trigger signal information.

[0028] Understandably, on the basis of S101, the module code includes at least one block statement, and the target block statement to be triggered signal feature extraction is determined in the at least one block statement. The module code usually starts with the module keyword and ends with the endmodule. Among them, the module name (such as subA) and the port list (such as clk_a) in the module code define the input and output interface of the module. The block statement is a logical block formed by combining a plurality of statements together, and the block statement includes at least one list, such as a port list, a parameter list, and a sensitive list, etc. The list is composed of at least one field, and the field is used to represent the corresponding attribute information. The at least one list includes a target list, such as (posedge clk or negedgereset), wherein @ is a preset identifier, posedge clk or negedge reset is at least one field corresponding to @, for example, the first field is posedge clk, and the second field is negedge reset. The target list is used to represent the attribute information of the trigger signal. Subsequently, the trigger signal feature can be extracted from the entire block statement, the trigger signal feature has context information, or the trigger signal feature can be directly extracted from the target list, the trigger signal feature can accurately reflect the name feature of the trigger signal, or the trigger signal feature is extracted from the block statement and the target list. The trigger signal feature can not only accurately reflect the name feature of the trigger signal, but also has the context information of the name. The specific trigger signal feature extraction method is not limited. This kind of traversal FPGA design code structure for the semantic inference of the trigger signal function effectively reduces the dependence on the naming rules, further reduces the missed detection rate and the misjudgment rate, and improves the recognition accuracy.

[0029] Among them, the block statement is an always block, the target list is a sensitive list in the always block, and the at least one field includes a trigger signal and an edge type of the trigger signal.

[0030] It can be understood that the target block statement represents the execution logic and / or trigger condition of the trigger signal, which can be an always block, which is a procedural block in Verilog language for describing sequential logic or combinational logic. The internal statements are procedural statements, which are executed in sequence. In addition, the always block will continue to run after the simulation starts until the simulation ends. The target list is a sensitive list in the target block statement, which can be a sensitive list in the always block. The execution of the always block is controlled by the sensitive list. For example, the sensitive list is always @(posedge clk or posedge reset), which means that the logic in the block is executed once when the rising edge of clk or the rising edge of reset arrives. For example, the target block statement includes multiple statements: "always@(posedge clk or negedge reset);begin;if(!reset);q≤1b;else;q≤data;end", wherein "posedge clk or negedge reset" is the content in the target list, "clk and reset" are the trigger signals, and "posedge and negedge" are the edge types of the trigger signals.

[0031] S103, functionally identifying the trigger signal characteristics to determine at least one trigger signal.

[0032] It can be understood that, on the basis of the above S102, the function of the trigger signal characteristics is identified, such as the alias (i.e. the name), the function, the logic and / or the condition of the trigger signal in the trigger signal characteristics, to determine at least one trigger signal. Other possible trigger signal identification methods are not limited. It can be understood that each target block statement in each module code included in the FPGA design code can identify at least one trigger signal, such as a clock signal and / or a reset signal. For example, "aa1" is identified as a clock signal from target block statement a1 in module a, and "aa2" is also identified as a clock signal from target block statement a2 in module a, i.e. the number of target block statements included in each module is indefinite. The identification, alias or field name of the same signal identified in a certain number of target block statements can be different, such as "aa1" and "aa2". The identification of the same signal identified between different modules can also be different. For example, "bb" is identified as a reset signal from target block statement b in module a, i.e. the number and type of trigger signals identified from a module are indefinite.

[0033] Optionally, after functionally identifying the trigger signal characteristics to determine at least one trigger signal, the method further comprises: Analyze the design hierarchy of the FPGA design code and establish a bidirectional transmission path to characterize global signal relationships based on the design hierarchy; verify at least one trigger signal along the transmission path in at least one direction of the bidirectional transmission path, and if the verification is successful, determine the final trigger signal from at least one trigger signal.

[0034] The bidirectional transmission path includes the forward transmission path and the reverse transmission path.

[0035] Understandably, after completing the block statement feature analysis or reset signal type determination, the design hierarchy of the FPGA design code is analyzed, for example, by traversing the design hierarchy from top to bottom, as described above. Figure 2 The hierarchical structure shown traverses from top to subA and then to subB, achieving full module coverage of the design through a hierarchical traversal algorithm. Furthermore, the design hierarchy can be recorded in the form of "top, subA, subB," with no restrictions on other possible formats representing the hierarchy between modules. Subsequently, a bidirectional transmission path is established based on the design hierarchy, representing the global signal relationships in the FPGA design code. This bidirectional transmission path includes a forward transmission path and a reverse transmission path. A forward transmission path refers to transmission from the top-level module to the last sub-module, such as "top→subA→subB," while a reverse transmission path refers to transmission from the last sub-module to the top-level module, such as "subB→subA→top." This bidirectional path verification mechanism effectively avoids missed detections and false positives, exhibiting high accuracy.

[0036] Optionally, at least one trigger signal is verified along the transmission path in at least one direction of the bidirectional transmission path, which can be achieved through the following steps: When using a forward transmission path for verification, at least one trigger signal is verified layer by layer along the mapping relationship between different modules of the same signal recorded in the design hierarchy; wherein the mapping relationship is used to characterize the hierarchical relationship between the combined names composed of signal names and module names; and / or, when using a reverse transmission path for verification, the trigger signal is verified by backtracking from the target submodule corresponding to the trigger signal to the top-level module through a reverse search algorithm, and the trigger signal is verified based on the known signals in the top-level module; wherein the FPGA design code includes the code of the target submodule and the top-level module.

[0037] It can be understood that any one of the transmission paths in the bidirectional transmission path can be selected to verify the at least one trigger signal, or the bidirectional transmission path can be selected to verify the at least one trigger signal, and the specific verification order is not limited, and accordingly it is checked whether a certain trigger signal is correct in the FPGA design. Specifically, the verification path to be used in the bidirectional transmission path is determined. If the forward transmission path is used for verification, the at least one trigger signal is verified layer by layer along the mapping relationship of the same signal recorded in the design hierarchy between different modules. The verification process of the forward transmission path is also the process of forward propagation, and the path search is performed along the signal alias mapping relationship recorded in the design hierarchy, such as the design hierarchy shown in Figure 2 The forward propagation is: top.clk→subA.clk_a→subB.clk_b, that is, the clock port of the top-level module is sequentially transmitted to the transmission port of each sub-module, wherein subA.clk_a represents the clk_a clock port of subA (module name), and the signal name can be a port name (such as clk_a) or a specific name of a certain signal, and subA.clk_a is recorded as a combination name. If the reverse transmission path is used for verification, the trigger signal is started from the sub-module where the trigger signal is located (i.e., the target sub-module), and the reverse search algorithm is used to search upward along the reverse transmission path until the top-level module is found. The known input signal in the top-level module is used to determine whether the trigger signal meets the expectation, that is, whether the trigger signal is correct is verified by backtracking. The flow of the reverse search algorithm (such as DFS, Depth-First Search, based on depth-first search) is: starting from the target sub-module, finding the source of the signal upward, then tracking in the reverse direction along the signal transmission direction, and gradually backtracking to the upper module, and finally reaching the top-level module, such as the reverse traversal flow shown in Figure 2 In addition, the top-level module usually has a clear input interface (such as clock, reset, control signal, etc.), which is known, confirmed, predictable, and then the known signal is used as a reference to derive the behavior of the trigger signal in the sub-module, and finally the trigger signal is compared with the theoretical value to determine whether it is correct or whether there is a logic error. Using the DFS algorithm can further improve the processing efficiency and optimize the efficiency.

[0038] Optionally, the at least one trigger signal is verified along the transmission path in at least one direction of the bidirectional transmission path, which can be specifically implemented by the following steps: If it is determined that the trigger signal feature is a fuzzy feature, the reverse transmission path is directly used to verify the at least one trigger signal.

[0039] It can be understood that, before verifying the trigger signal through the bidirectional transmission path, it can also be determined whether the extracted trigger signal feature is a fuzzy feature. Based on the fuzzy feature, the specific trigger signal cannot be determined. For example, when identifying based on the trigger signal feature, it cannot be determined whether the trigger signal is a clock signal, that is, the trigger signal is an unknown signal. In this case, the identity verification link is established by directly tracing back from the unknown signal belonging to the target submodule to the trigger signal (denoted as the confirmed signal) of the top-level module that has been confirmed, and then identifying the unknown signal according to the confirmed signal. That is, when the trigger signal feature cannot confirm the signal identity, the global signal transmission relationship is further judged.

[0040] It can be understood that, if it is determined that the trigger signal feature is an obvious feature or the feature is obvious, the clock signal and / or the reset signal can be directly determined, and the above-mentioned bidirectional transmission path can not be used for backtracking verification, such as the standard names clk and reset. In one embodiment, a plurality of trigger signals include part unknown signals and part explicit signals, that is, some trigger signal features are obvious and some trigger signal features are fuzzy. In another embodiment, the target signal to be verified through the bidirectional transmission path is selected from the plurality of trigger signals, that is, the trigger signal to be verified and the path to be verified can be selected.

[0041] Optionally, after the function identification of the trigger signal feature and the determination of the at least one trigger signal, the method further comprises: In the case where the at least one trigger signal includes a reset signal, the trigger condition and / or the execution logic in the target block statement corresponding to the reset signal are analyzed to determine the reset type of the reset signal.

[0042] It can be understood that, if the identified trigger signal is a reset signal, the trigger condition and / or the execution logic in the target block statement where the reset signal is located are further analyzed to determine the reset type, and the reset type includes asynchronous reset and synchronous reset. This kind of association analysis of the block statement trigger feature and the execution logic solves the problem of the naming rule limitation and improves the judgment accuracy. It can be understood that, after the reset type is determined, the bidirectional transmission path verification can be performed.

[0043] S104, generating a trigger signal identification result according to the at least one trigger signal and the reference name of the at least one trigger signal in the corresponding module code.

[0044] Understandably, on the basis of S103, the reference name refers to the name actually used by the trigger signal in the target module code (such as reset, enable, trig_in, etc.). Mapping the trigger signal and its name in the target module code forms a structured output result, which is convenient for subsequent analysis or verification. The trigger signal can be determined directly based on the trigger signal feature (such as in the case of obvious features), or it can be the final trigger signal after verification through the bidirectional transmission path, or it can be determined based on the reverse trace (such as in the case of ambiguous features). In addition, the verification process of the trigger signal can also be recorded in the identification result to intuitively show the user the entire identification process of the trigger signal.

[0045] Optionally, according to the at least one trigger signal and the reference name of the at least one trigger signal in the corresponding module code, a trigger signal identification result is generated, which can be achieved through the following steps: According to the at least one trigger signal, the reset type, and the reference name of the at least one trigger signal in the corresponding module code, a trigger signal identification result is generated.

[0046] Understandably, the identification result can further include the reset type of the reset signal, and other possible information in the identification process can be added to the identification result, which is not described here.

[0047] Optionally, after generating the trigger signal identification result, the method further includes: Obtaining adjustment information of the FPGA design code; updating the bidirectional transmission path according to the adjustment information, and re-determining the at least one trigger signal according to the updated bidirectional transmission path.

[0048] Understandably, after the identification result is displayed to the user, the adjustment information of the FPGA design code is received from the user. The adjustment information can be adjustment information of the execution logic and the reference name. Subsequently, the trigger signal feature is re-extracted according to the adjustment information, the bidirectional transmission path is updated, and the at least one trigger signal is re-determined according to the updated bidirectional transmission path, that is, the FPGA design code and the identification result can be adjusted in real time according to user feedback. For specific implementation, refer to the above embodiments, which are not described here.

[0049] Exemplarily, Figure 3 A technical framework diagram of a trigger signal identification method provided by the embodiment of the present disclosure, Figure 3The technical framework shown includes a single-module feature extraction engine, hierarchical signal tracking, and global signal correlation verification. The single-module feature extraction engine is used to trigger signal feature extraction, including block statement feature analysis and reset type discrimination. Block statement feature analysis is used to analyze block statement trigger signals, and reset type discrimination is used to discriminate reset types. Hierarchical signal tracking is used for DFS signal tracking and propagation path establishment, including top-down traversal of levels and construction of level connection relationships. Specifically, a DFS algorithm is used for forward propagation path recording. Global signal correlation verification includes submodule signal triggering, DFS reverse search, and top-level signal correlation on the reverse path backtracking. The forward path transmission process is described in the above example and will not be repeated here.

[0050] The trigger signal identification method provided by the embodiments of the present disclosure uses a hierarchical traversal algorithm to automatically scan and analyze all modules in FPGA design, ensuring that the verification process covers the complete design structure without human intervention, thereby improving the automation level of the verification process. Subsequently, a bidirectional path verification mechanism is introduced to perform forward tracking from the top to the target and backward tracking from the target to the top. Double verification effectively avoids missed detection and misjudgment, significantly improving the accuracy and reliability of the verification results. In addition, the path search and signal propagation analysis process are optimized based on the DFS algorithm during the verification process, significantly improving the processing speed and resource utilization, shortening the verification period, and meeting the development needs of high-performance FPGAs. At the same time, it also supports complex engineering scenarios such as multi-level nested modules, cross-module signal transmission, and signal renaming, and has good compatibility and flexibility for complex design structures. It can be widely applied to various large-scale FPGA design projects. The generated verification results can be used as reliable input for subsequent FPGA design inspection tasks, helping to detect potential logic errors and interface abnormalities in advance, thereby reducing design risks and improving overall design quality and stability.

[0051] Figure 4 A structural diagram of a trigger signal identification device provided by the embodiments of the present disclosure is shown. The trigger signal identification device provided by the embodiments of the present disclosure can execute the processing flow provided by the trigger signal identification method embodiments, as shown in Figure 4 The trigger signal identification device 400 includes: An acquisition unit 401 is configured to acquire FPGA design code to be subjected to trigger signal identification. A feature extraction unit 402 is configured to traverse at least one module code in the FPGA design code and extract trigger signal features from block statements and / or target lists in the module code. The target list is composed of at least one field corresponding to a preset identifier, and the at least one field is used to represent trigger signal information. A signal determination unit 403 is configured to perform function identification on the trigger signal features and determine at least one trigger signal. The result generation unit 404 is configured to generate a trigger signal identification result according to the at least one trigger signal and a reference name of the at least one trigger signal in the corresponding module code.

[0052] The block statement is an always block, the target list is a sensitive list in the always block, and the at least one field includes the trigger signal and an edge type of the trigger signal.

[0053] Optionally, the trigger signal identification apparatus 400 is further configured to: analyze a design hierarchy of the FPGA design code, and establish a bidirectional transmission path for representing a global signal relationship according to the design hierarchy; verify the at least one trigger signal along a transmission path in at least one direction of the bidirectional transmission path, and determine a final trigger signal from the at least one trigger signal in a case of passing the verification.

[0054] The bidirectional transmission path includes a forward transmission path and a reverse transmission path.

[0055] Optionally, the signal determination unit 403 is configured to: in a case of verifying along the forward transmission path, verify the at least one trigger signal layer by layer along a mapping relationship of a same signal between different modules recorded in the design hierarchy; wherein the mapping relationship is used to represent a hierarchical relationship between a combined name composed of a signal name and a module name; and / or, in a case of verifying along the reverse transmission path, backtrack from a target submodule corresponding to the trigger signal to a top-level module by using a reverse search algorithm, and verify the trigger signal according to a known signal in the top-level module; wherein the FPGA design code includes code of the target submodule and the top-level module.

[0056] Optionally, the signal determination unit 403 is configured to: if it is determined that the trigger signal feature is a fuzzy feature, directly verify the at least one trigger signal by using the reverse transmission path.

[0057] Optionally, the trigger signal identification apparatus 400 is further configured to: in a case that the at least one trigger signal includes a reset signal, analyze a trigger condition and / or execution logic in a target block statement corresponding to the reset signal, and determine a reset type of the reset signal; generate a trigger signal identification result according to the at least one trigger signal and a reference name of the at least one trigger signal in the corresponding module code, including: generate a trigger signal identification result according to the at least one trigger signal, the reset type, and the reference name of the at least one trigger signal in the corresponding module code.

[0058] Optionally, the trigger signal identification apparatus 400 is further configured to: obtain adjustment information of the FPGA design code; update the bidirectional transmission path according to the adjustment information, and re-determine the at least one trigger signal according to the updated bidirectional transmission path.

[0059] Figure 4 The trigger signal identification apparatus of the illustrated embodiment can be used to implement the technical solutions of the method embodiments described above, and has similar implementation principles and technical effects, which will not be described here again.

[0060] Figure 5 The structure schematic diagram of the electronic device provided by the embodiments of the present disclosure is shown in FIG. 5. The following specifically refers to Figure 5 which shows a structure schematic diagram of an electronic device 500 suitable for implementing the embodiments of the present disclosure. The electronic device 500 in the embodiments of the present disclosure can include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet PCs), PMPs (Portable Multimedia Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), wearable electronic devices, and the like, as well as fixed terminals such as digital TVs, desktop computers, smart home devices, and the like. Figure 5 The electronic device shown is only an example, and should not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0061] As shown in Figure 5 , the electronic device 500 can include a processing apparatus 501 (such as a central processor, a graphics processor, etc.) which can perform various appropriate actions and processes to implement the trigger signal identification method of the embodiments of the present disclosure according to programs stored in a read-only memory (ROM) 502 or loaded from a storage apparatus 508 to a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device 500 are also stored. The processing apparatus 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0062] Generally, the following apparatuses can be connected to the I / O interface 505: input apparatuses 506 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output apparatuses 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage apparatuses 508 including, for example, a magnetic tape, a hard disk, etc.; and communication apparatuses 509. The communication apparatuses 509 can allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 5Electronic device 500 is shown with various means, but it is understood that not all of the shown means need be implemented or present. More or less means can alternatively be implemented or present.

[0063] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for executing the methods illustrated by the flowcharts, thereby implementing the above trigger signal identification method. In such embodiments, the computer program can be downloaded and installed from a network through communication means 509, or installed from storage means 508, or installed from ROM 502. When the computer program is executed by processing means 501, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.

[0064] It should be noted that the computer-readable medium described above in the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination thereof. The computer-readable storage medium, for example, can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination thereof. More specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program used or used in conjunction with an instruction execution system, apparatus, or device. In the present disclosure, the computer-readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained in the computer-readable medium can be transmitted by any suitable medium, including but not limited to a wire, a cable, a radio frequency (RF) link, or the like, or any suitable combination thereof.

[0065] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0066] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0067] Optionally, when one or more of the above-described procedures are executed by the electronic device, the electronic device may also execute other steps of the above embodiments.

[0068] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0069] The computer program product of the first aspect can include one or more non-transitory computer-readable media storing instructions that, when executed, cause one or more processors to perform the operations of the method of the first aspect. The computer program product of the first aspect can include a computer-readable medium storing instructions that, when executed, cause one or more processors to perform the operations of the method of the first aspect.

[0070] The units described in the embodiments of the present disclosure can be implemented by software, or by hardware, or by a combination of software and hardware. In some cases, the names of the units do not constitute a limitation on the units themselves.

[0071] The functions described in this document can be implemented in part or in whole in hardware, firmware, software, or any combination thereof. For example, the functions can be implemented in hardware, such as through one or more ASICs modified in entirety for a particular design, or through one or more ASICs having some circuits modified. Said one or more ASICs can comprise one or more processors operating in a vacuum, in air, in a liquid, or in some other medium. In software, the functions can be stored as one or more instructions and / or data on non-transitory computer-readable storage medium or media including, without limitation, memory 104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204, 1304, and / or 1404 in the aforementioned system, server or device, etc. In that case, the computer-readable storage medium or media can include RAM, ROM, programmable ROM (e.g., EEPROM, erasable programmable ROM, electrically erasable programmable ROM, programmable read-only memory (PROM), etc.), magnetic RAM, flash memory, magnetic disks, optical disks, tape, solid-state memory devices, etc. The aforementioned system, server or device, etc. of this disclosure can include non-transitory computer-readable storage media. The instructions can include, for example, instructions 106, 206, 306, 406, 506, 606, 706, 806, 906, 1006, 1106, 1206, 1306, and / or 1406 or some or all of the modules in the aforementioned system, server or device, etc. The instructions can also include, without limitation, machine code, assembly language code, high-level languages interpreted on an interpreter, high-level languages compiled to an intermediate representation, high-level languages compiled to machine code, firmware, etc. All such implementations can be part of a single product, or of different products. The computer-readable storage medium or media can also include propagated signals, for example, where desired feature is implemented at least in part using software and signals are propagating over a communication medium such as electrical wiring, optical fiber, or a wireless transport mechanism. The term "non-transitory" simply means a computer-readable storage medium or media that do not include a propagated signal per se (for example, that are tangible, non-transitory memory storage products). The terms "machine-readable storage medium" or "computer-readable storage medium" include, but are not limited to, one or more types of tangible memory components or media manufactured using a manufacturing process, such as, for example, semiconductor manufacturing processes; other types of manufacturing processes; or combinations thereof. The terms "machine-readable storage medium" or "computer-readable storage medium" include, but are not limited to, one or more types of computer-readable storage media capable of storing data, including volatile memory or volatile storage (such as, for example, random access memory (RAM), dynamic random access memory (DRAM), or variants thereof); or non-volatile memory or non-volatile storage (such as, for example, read only memory (ROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, solid state memory device, or variants thereof).

[0072] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium can include a tangible, non-transitory memory device, such as, for example, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0073] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or gateway that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or gateway. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or gateway that includes said element.

[0074] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A trigger signal identification method, characterized in that, include: Obtain the FPGA design code for trigger signal recognition; Traverse at least one module code within the FPGA design code and extract trigger signal features from block statements and / or target lists within the module code; wherein, the target list consists of at least one field corresponding to a preset identifier, and the at least one field is used to characterize trigger signal information; The trigger signal features are functionally identified to determine at least one trigger signal; Based on the at least one trigger signal and the name of the at least one trigger signal in the corresponding module code, a trigger signal identification result is generated.

2. The method according to claim 1, characterized in that, The block statement is an always block, the target list is a sensitivity list in the always block, and the at least one field includes a trigger signal and the edge type of the trigger signal.

3. The method according to claim 1, characterized in that, After performing functional identification on the trigger signal features to determine at least one trigger signal, the method further includes: Analyze the design hierarchy of the FPGA design code, and establish a bidirectional transmission path to characterize global signal relationships based on the design hierarchy; The at least one trigger signal is verified along the transmission path in at least one direction of the bidirectional transmission path, and if the verification is successful, the final trigger signal is determined from the at least one trigger signal.

4. The method according to claim 3, characterized in that, The bidirectional transmission path includes a forward transmission path and a reverse transmission path, and verifying the at least one trigger signal along the transmission path in at least one direction of the bidirectional transmission path includes: When verifying using the forward transmission path, the at least one trigger signal is verified layer by layer along the mapping relationship between different modules of the same signal recorded in the design hierarchy; wherein, the mapping relationship is used to characterize the hierarchical relationship between the combined names composed of signal names and module names; and / or, When using the reverse transmission path for verification, the reverse search algorithm traces back from the target submodule corresponding to the trigger signal to the top-level module, and verifies the trigger signal based on the known signals in the top-level module; wherein, the FPGA design code includes the code of the target submodule and the top-level module.

5. The method according to claim 4, characterized in that, Verifying the at least one trigger signal along the transmission path in at least one direction of the bidirectional transmission path includes: If the trigger signal feature is determined to be an ambiguous feature, then the at least one trigger signal is directly verified using the reverse transmission path.

6. The method according to claim 1, characterized in that, After performing functional identification on the trigger signal features to determine at least one trigger signal, the method further includes: When the at least one trigger signal includes a reset signal, analyze the triggering conditions and / or execution logic in the target block statement corresponding to the reset signal to determine the reset type of the reset signal; The step of generating a trigger signal identification result based on the at least one trigger signal and its corresponding module code name includes: Based on the at least one trigger signal, the reset type, and the name of the at least one trigger signal in the corresponding module code, a trigger signal identification result is generated.

7. The method according to claim 3, characterized in that, After generating the trigger signal identification result, the method further includes: Obtain adjustment information for the FPGA design code; The bidirectional transmission path is updated based on the adjustment information, and at least one trigger signal is re-determined based on the updated bidirectional transmission path.

8. A trigger signal identification device, characterized in that, include: The acquisition unit is used to acquire the FPGA design code to be identified by the trigger signal; The feature extraction unit is used to traverse at least one module code within the FPGA design code and extract trigger signal features from block statements and / or target lists in the module code; wherein the target list is composed of at least one field corresponding to a preset identifier, and the at least one field is used to characterize trigger signal information; A signal determination unit is used to perform functional identification on the characteristics of the trigger signal and determine at least one trigger signal; The result generation unit is used to generate a trigger signal identification result based on the at least one trigger signal and the name of the at least one trigger signal in the corresponding module code.

9. An electronic device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the trigger signal identification method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the trigger signal recognition method as described in any one of claims 1 to 7.

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