A high stability multi-stage low noise amplifier architecture

Abstract

This invention discloses a highly stable multi-stage low-noise amplifier architecture, belonging to the field of radio frequency integrated circuits. The architecture includes an input matching circuit, a first-stage Cascode amplifier circuit, an inter-stage matching circuit, a second-stage CS amplifier circuit, and an output matching circuit. The IN terminal of the input matching circuit receives the radio frequency signal and outputs it to the first common-source transistor M1 of the first-stage Cascode amplifier circuit. After being received by the gate of M1, the signal is output from its drain to the source of the second common-gate transistor M2. The signal is further amplified by M2 and output from its drain. It is then transmitted through the inter-stage matching circuit to the gate of the third common-source transistor M3 of the second-stage CS amplifier circuit. After two stages of amplification, the signal is output to the OUT terminal of the output matching circuit. M1 and M2 constitute the pre-stage common-source Cascode, and M3 is the post-stage common-source CS. Utilizing the extremely high reverse isolation of the pre-stage Cascode structure, i.e., the extremely low S12 parameter, the stability factor of the amplifier is significantly increased, enabling it to achieve unconditional stability across the entire frequency band.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuits and relates to a highly stable multi-stage low-noise amplifier architecture. Background Technology

[0002] With the rapid development of wireless communication technology, higher requirements have been placed on the integration, systematization, and miniaturization of communication equipment.

[0003] Low-noise amplifiers (LNAs) are widely used in millimeter-wave radar, 5G communication, and satellite receiving systems. As a key module in the receiving front-end, their performance directly affects the sensitivity and dynamic range of the entire system, requiring a low noise figure and a certain level of gain. Simultaneously, amplifier stability and return loss must also be considered. Traditional single-stage common-source amplifiers struggle to simultaneously meet system requirements in terms of gain, noise, and stability.

[0004] The cascode structure is widely used in high-frequency, low-noise amplifier designs due to its high gain, high reverse isolation, and good stability. However, single-stage cascode structures still have limitations in terms of stability and gain optimization. Therefore, stability and gain are further improved by using a common-source (CS) structure in subsequent stages, and broadband performance and good input-output matching are achieved through inter-stage matching networks.

[0005] Traditional two-stage amplifiers use a CS (Constant Controller) preamp and Cascode (Cascode) postamp structure. While they also have excellent performance in terms of high gain and low noise, they are difficult to meet the requirements of full-band stability. Summary of the Invention

[0006] This invention proposes a highly stable multi-stage low-noise amplifier architecture suitable for the 12-18 GHz frequency band. By improving it to combine the pre-stage Cascode structure with the post-stage CS structure and introducing multiple stability enhancement technologies, it effectively solves the full-band stability problem of traditional two-stage amplifiers, achieving high gain, high stability, low noise figure and good input-output matching.

[0007] The architecture specifically includes an input matching circuit, a first-stage Cascode amplifier circuit, an inter-stage matching circuit, a second-stage CS amplifier circuit, and an output matching circuit.

[0008] The input matching circuit receives the radio frequency signal at its input terminal IN and outputs it to the first-stage Cascode amplifier circuit. The first-stage Cascode amplifier circuit amplifies the signal and transmits it to the second-stage CS amplifier circuit through the inter-stage matching circuit for two-stage amplification. The output terminal of the second-stage CS amplifier circuit is connected to the input terminal of the output matching circuit and outputs the two-stage amplified signal to the signal output terminal OUT of the output matching circuit.

[0009] The input matching circuit includes: a first inductor L1 and a first DC blocking capacitor C. block1 ;

[0010] In this circuit, the first terminal of the first inductor L1 is connected to the signal input terminal IN of the input matching circuit, and the second terminal of L1 is grounded; simultaneously, the first terminal of L1 is connected to the first DC blocking capacitor C. block1 The first end, C block1 The second end is connected to the first-stage Cascode amplifier circuit;

[0011] The first-stage Cascode amplifier circuit includes: a first common-source transistor M1, a second common-gate transistor M2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first RF choke inductor RF. choke1 Second RF choke inductor choke2 ;

[0012] The gate of the first common-source transistor M1 is connected to C. block1 The second terminal is connected, the source of M1 is grounded, and the drain of M1 is connected to the source of M2; simultaneously, the gate of M1 is connected to the first RF choke inductor RF. choke1 First end connection; RF choke1 The second terminal is connected to the first terminal of the first resistor R1, and the second terminal of R1 is connected to the gate bias voltage V. g Connection; at the same time, RF choke1 The second terminal of M1 is connected to the second terminal of the first capacitor C1, and the first terminal of C1 is grounded; the gate of M1 is also connected to the first terminal of the second capacitor C2; the second terminal of C2 is connected to the first terminal of the second resistor R2; the second terminal of R2 is connected to the drain of the second common-gate transistor M2; the first terminal of the third resistor R3 is connected to the power supply V. DD Connection; The second end of R3 is connected to the gate of M2; The gate of M2 is also connected to the first end of the third capacitor C3; The second end of C3 is grounded; Between the gate of the first common source transistor M1 and the drain of the second common gate transistor M2, the series circuit of the second capacitor C2 and the second resistor R2 forms the first RC negative feedback network.

[0013] The drain of M2 and the second RF choke inductor RF choke2 First end connection; RFchoke2 The second terminal is related to the drain bias voltage V DD Connection; at the same time, RF choke2 The second terminal is connected to the first terminal of the fourth resistor R4; the second terminal of R4 is connected to the first terminal of the fourth capacitor C4; the second terminal of C4 is grounded.

[0014] The interstage matching network includes: a second DC blocking capacitor C block2 C block2 The first terminal is connected to the drain of the second common-gate transistor M2; C block2 The second terminal is connected to the second-stage CS amplifier circuit;

[0015] The second-stage CS amplifier circuit includes: a third common-source transistor M3, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a third RF choke inductor RF. choke3 and the fourth RF choke inductor choke4 ;

[0016] The gate of the third common-source transistor M3 is connected to the second DC blocking capacitor C. block2 The second terminal is connected; simultaneously, the gate of M3 is connected to the third RF choke inductor RF. choke3 The second end is connected; RF choke3 The first terminal is connected to the second terminal of the fifth resistor R5; the first terminal of R5 is connected to the gate bias voltage V. g Connect; simultaneously, the second terminal of R5 is connected to the second terminal of the fifth capacitor C5; the first terminal of C5 is grounded; the gate of M3 is also connected to the first terminal of the sixth capacitor C6; the second terminal of C6 is connected to the first terminal of the sixth resistor R6; the second terminal of R6 is connected to the drain of M3; the source of M3 is grounded;

[0017] The series circuit of the sixth capacitor C6 and the sixth resistor R6 connected between the gate and drain of M3 forms the second RC negative feedback network.

[0018] Meanwhile, the drain of M3 is connected to the fourth RF choke inductor RF. choke4 The first end; RF choke4 The second terminal is related to the drain bias voltage V DD Connection; at the same time, RF choke4 The second terminal is connected to the first terminal of the seventh resistor R7, and the second terminal of R7 is connected to the first terminal of the seventh capacitor C7; the second terminal of C7 is grounded.

[0019] The output matching network includes: a third DC blocking capacitor C. block3 Second inductor L2;

[0020] The third DC blocking capacitor C block3 The first terminal is connected to the drain of the third common-source transistor M3; Cblock3 The second terminal of C is connected to the signal output terminal OUT; at the same time, C block3 The second terminal is connected to the second terminal of the second inductor L2, and the first terminal of L2 is grounded;

[0021] The working principle is as follows: the input signal enters the gate of the first common source transistor M1 through the input matching circuit, and after being amplified by M1, it is output from its drain to the source of the second common gate transistor M2; the signal is further amplified by M2 and output from its drain, and coupled to the gate of the third common source transistor M3 through the interstage matching circuit; M3 performs the final amplification of the signal and outputs it to the load through the output matching circuit.

[0022] In this structure, the first common-source transistor M1 and the second common-gate transistor M2 constitute the pre-stage common-source cascode, and the third common-source transistor M3 is the post-stage common-source CS, forming a two-stage amplification structure that combines the pre-stage common-source cascode and the post-stage common-source CS. This utilizes the extremely high reverse isolation of the pre-stage cascode structure, i.e., extremely low S... 12 The parameters significantly increased the amplifier's stability. Factors that ensure it satisfies the requirements across the entire frequency band. >1.

[0023] The factor is defined as follows:

[0024] (1)

[0025] in, These are S-parameters; =S 11 S 22 -S 12 S 21 .

[0026] The auxiliary criterion for unconditional stability is: , It is an auxiliary stability factor. When the amplifier simultaneously satisfies K>1 and B1>0, it indicates that the circuit is unconditionally stable.

[0027] exist When S is in the denominator of the factor 12 When the parameter value is very small, It will become very large and easily satisfied. The unconditional stability condition is greater than 1.

[0028] The advantages of this invention are:

[0029] 1) This invention optimizes the performance of the entire amplifier by adopting an improved sequential structure of "pre-stage Cascode - post-stage CS". The pre-stage Cascode has excellent isolation characteristics, providing a stable foundation for the circuit; the post-stage CS structure facilitates impedance matching, further increasing gain and optimizing output performance. This design structurally ensures that the amplifier simultaneously possesses high gain, low noise, and high stability.

[0030] 2) By introducing an RC negative feedback structure, bandwidth, stability, and gain flatness are synergistically optimized. This structure effectively extends the amplifier's 3dB bandwidth without excessively sacrificing gain; simultaneously, by increasing the negative feedback resistor, the input and output impedance of the circuit is increased, thereby improving circuit stability and gain flatness.

[0031] 3) By adding a grounding feedback capacitor to the gate of the Cascode common gate transistor, high-frequency resonance points are significantly suppressed, improving the overall circuit stability. First, a grounding capacitor is connected in parallel, utilizing its low impedance characteristic at high frequencies to effectively suppress parasitic resonances in the millimeter-wave band. At the same time, a series resistor is used to achieve bias isolation and provide damping for the mid-to-low frequency bands, thereby achieving wideband stability control from low frequencies to the millimeter-wave band while ensuring normal DC bias. Attached Figure Description

[0032] Figure 1 This is a circuit diagram of a highly stable multi-stage low-noise amplifier architecture according to the present invention;

[0033] Figure 2 The stability of the multi-stage low-noise amplifier described in this invention varies with the feedback capacitor C. x The change curve.

[0034] Figure 3 The graph shows the stability of the present invention and the conventional cascode amplifier as a function of frequency.

[0035] Figure 4 This is a schematic diagram of the CS structure amplifier circuit with RC negative feedback used in this invention;

[0036] Figure 5 The maximum usable gain G of this invention and conventional common-source (CS) amplifiers. ma Curve showing the change with frequency;

[0037] Figure 6 The graph shows the stability versus frequency curves of the present invention and the conventional common-source (CS) amplifier.

[0038] Figure 7 The input return loss (S) of the low-noise amplifier of this invention 11) and output return loss (S 22 Curve showing the variation of frequency;

[0039] Figure 8 This is a noise comparison curve between the amplifier of the present invention and the conventional CS-Cascode structure;

[0040] Figure 9 This is a comparison curve of the stability of the amplifiers of the present invention and the traditional CS-Cascode structure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0042] This invention proposes a highly stable multi-stage low-noise amplifier architecture, employing a combination of a cascode front-stage and a common-source (CS) rear-stage structure. Several independent technologies are utilized: the cascode front-stage achieves high gain, high reverse isolation, and a low noise figure; the CS rear-stage provides additional gain and optimizes output matching; an RC negative feedback network is introduced to extend bandwidth and improve matching characteristics; and a grounded feedback capacitor network is used on the gate of the common-gate transistor to suppress high-frequency oscillations and enhance circuit stability. The amplifier is fabricated using a 0.25-μm GaAs pHEMT process, is reproducible, and can operate in the 12 GHz to 18 GHz frequency band; it is particularly suitable for high-gain, low-noise applications in the Ku-band.

[0043] like Figure 1 As shown, the architecture specifically includes an input matching circuit, a first-stage Cascode amplifier circuit, an inter-stage matching circuit, a second-stage CS amplifier circuit, and an output matching circuit.

[0044] The input matching circuit receives the radio frequency signal at its input terminal IN and outputs it to the first-stage Cascode amplifier circuit after matching.

[0045] The first-stage Cascode amplifier circuit has its input terminal connected to the output of the input matching circuit. After amplifying the signal, it is transmitted to the second-stage CS amplifier circuit through the inter-stage matching circuit for two-stage amplification. This is used to provide high-gain and low-noise pre-amplification.

[0046] The output of the second-stage CS amplifier circuit is connected to the input of the output matching circuit, and the signal after two stages of amplification is output to the signal output terminal OUT of the output matching circuit.

[0047] The input matching circuit includes: a first inductor L1 and a first DC blocking capacitor Cblock1;

[0048] In this circuit, the first terminal of the first inductor L1 is connected to the signal input terminal IN of the input matching circuit, and the second terminal of L1 is grounded; simultaneously, the first terminal of L1 is connected to the first DC blocking capacitor C. block1 The first end, C block1 The second end is connected to the first-stage Cascode amplifier circuit;

[0049] The first-stage Cascode amplifier circuit includes: a first common-source transistor M1, a second common-gate transistor M2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first RF choke inductor RF. choke1 Second RF choke inductor choke2 ;

[0050] The gate of the first common-source transistor M1 is connected to C. block1 The second terminal is connected, the source of M1 is grounded, and the drain of M1 is connected to the source of M2; simultaneously, the gate of M1 is connected to the first RF choke inductor RF. choke1 First end connection; RF choke1 The second terminal is connected to the first terminal of the first resistor R1, and the second terminal of R1 is connected to the gate bias voltage V. g Connection; at the same time, RF choke1 The second terminal of M1 is connected to the second terminal of the first capacitor C1, and the first terminal of C1 is grounded; the gate of M1 is also connected to the first terminal of the second capacitor C2; the second terminal of C2 is connected to the first terminal of the second resistor R2; the second terminal of R2 is connected to the drain of the second common-gate transistor M2; the first terminal of the third resistor R3 is connected to the power supply V. DD Connection; the second end of R3 is connected to the gate of M2; the gate of M2 is simultaneously connected to the first end of the third capacitor C3; the second end of C3 is grounded; between the gate of the first common source transistor M1 and the drain of the second common gate transistor M2, the series circuit of the second capacitor C2 and the second resistor R2 forms the first RC negative feedback network.

[0051] The drain of M2 and the second RF choke inductor RF choke2 First end connection; RF choke2 The second terminal is related to the drain bias voltage V DD Connection; at the same time, RF choke2 The second terminal is connected to the first terminal of the fourth resistor R4; the second terminal of R4 is connected to the first terminal of the fourth capacitor C4; the second terminal of C4 is grounded.

[0052] The interstage matching network includes: a second DC blocking capacitor Cblock2 C block2 The first terminal is connected to the drain of the second common-gate transistor M2; C block2 The second terminal is connected to the second-stage CS amplifier circuit;

[0053] The second-stage CS amplifier circuit includes: a third common-source transistor M3, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a third RF choke inductor RF. choke3 and the fourth RF choke inductor choke4 ;

[0054] The gate of the third common-source transistor M3 is connected to the second DC blocking capacitor C. block2 The second terminal is connected; simultaneously, the gate of M3 is connected to the third RF choke inductor RF. choke3 The second end is connected; RF choke3 The first terminal is connected to the second terminal of the fifth resistor R5; the first terminal of R5 is connected to the gate bias voltage V. g Connect; simultaneously, the second terminal of R5 is connected to the second terminal of the fifth capacitor C5; the first terminal of C5 is grounded; the gate of M3 is also connected to the first terminal of the sixth capacitor C6; the second terminal of C6 is connected to the first terminal of the sixth resistor R6; the second terminal of R6 is connected to the drain of M3; the source of M3 is grounded;

[0055] The series circuit of the sixth capacitor C6 and the sixth resistor R6 connected between the gate and drain of M3 forms the second RC negative feedback network.

[0056] Meanwhile, the drain of M3 is connected to the fourth RF choke inductor RF. choke4 The first end; RF choke4 The second terminal is related to the drain bias voltage V DD Connection; at the same time, RF choke4 The second terminal is connected to the first terminal of the seventh resistor R7, and the second terminal of R7 is connected to the first terminal of the seventh capacitor C7; the second terminal of C7 is grounded.

[0057] The output matching network includes: a third DC blocking capacitor C. block3 Second inductor L2;

[0058] The third DC blocking capacitor C block3 The first terminal is connected to the drain of the third common-source transistor M3; C block3 The second terminal of C is connected to the signal output terminal OUT; at the same time, C block3 The second terminal is connected to the second terminal of the second inductor L2, and the first terminal of L2 is grounded;

[0059] Furthermore, the first common-source transistor M1, the second common-gate transistor M2, and the third common-source transistor M3 are E-pHEMT transistors.

[0060] The working principle is as follows: the input signal enters the gate of the first common source transistor M1 through the input matching circuit, and after being amplified by M1, it is output from its drain to the source of the second common gate transistor M2; the signal is further amplified by M2 and output from its drain, and coupled to the gate of the third common source transistor M3 through the interstage matching circuit; M3 performs the final amplification of the signal and outputs it to the load through the output matching circuit.

[0061] In this structure, the first common-source transistor M1 and the second common-gate transistor M2 constitute the pre-stage common-source cascode, and the third common-source transistor M3 is the post-stage common-source CS, forming a two-stage amplification structure that combines the pre-stage common-source cascode and the post-stage common-source CS. This utilizes the extremely high reverse isolation of the pre-stage cascode structure, i.e., extremely low S... 12 The parameters significantly increase the amplifier's stability K-factor, enabling it to achieve unconditional stability (K>1) across the entire frequency band.

[0062] The Cascode structure provides high gain, high reverse isolation, and good frequency stability, effectively suppressing the Miller effect. The subsequent CS structure further provides additional gain, and the frequency response and matching are optimized through a load network. By introducing an RC negative feedback network, namely, connecting a first RC series network between the gate of the common source transistor M1 and the drain of the common gate transistor M2 in the Cascode structure, and connecting a second RC series network between the gate and drain of the common source transistor M3 in the subsequent CS structure, the bias is stabilized, the amplifier bandwidth is expanded, and the gain flatness is improved. By introducing a ground feedback capacitor (first connecting a ground capacitor in parallel, then connecting a resistor in series to ground) at the gate of the common gate transistor M2, high-frequency self-oscillation is further suppressed and the circuit stability is improved.

[0063] By employing a Cascode structure in the preamplifier stage, the influence of the subsequent CS circuit on the input matching is effectively isolated, thus eliminating the possibility of oscillation caused by the interaction between the preamplifier and CS stage in principle, laying the foundation for realizing a highly robust amplifier.

[0064] In radio frequency (RF) engineering, the Rollett Stability Factor (K) is commonly used to determine whether a two-port network is unconditionally stable. The K factor is defined as follows:

[0065] (1)

[0066] in, These are S-parameters; =S 11 S 22 -S 12 S 21 .

[0067] The criterion for unconditional stability is: , It is an auxiliary stability factor. When the amplifier simultaneously satisfies K>1 and B1>0, it indicates that the circuit is unconditionally stable.

[0068] There is a key term in the denominator of the K factor: When S 12 When the value of is very small, K will become very large, and it is easy to satisfy the unconditional stability condition of K>1.

[0069] like Figure 2 As shown, the stability of the multi-stage low-noise amplifier architecture described in this invention varies with the feedback capacitance C. x The curve of C shows that stability has a minimum value in the 30-35GHz frequency range. x When C = 60pF, the minimum stability is 0.2; when C x When C = 180pF, the minimum stability is 0.35; when C x When C = 300pF, the minimum stability is -0.1; when C x When C = 420pF, the minimum stability is 1.6; when C x At a capacitance of 540pF, the minimum stability is 2.5. Therefore, the stability varies with the feedback capacitor C. x The value increases with the increase of the input voltage, so try to choose a larger feedback capacitor.

[0070] The stability versus frequency curves of a traditional cascode amplifier and a cascode amplifier using a grounded feedback capacitor network in this embodiment are shown below; Figure 3 As shown, within the frequency range of 0-100GHz, without a grounding capacitor, the minimum K value is -0.43, which does not meet the full-band stability requirement; with a grounding capacitor, the minimum K value is 2.17, which meets the full-band stability requirement. Therefore, adding a grounding capacitor can effectively improve stability.

[0071] The CS structure amplifier circuit with RC negative feedback used in this embodiment is as follows: Figure 4 As shown, R6 and C6 are connected in series between the gate and drain of the common-source transistor to form a gate-drain RC negative feedback network. The circuit gain and input / output impedance can be expressed as:

[0072] (1)

[0073] (2)

[0074] (3)

[0075] in, This is the source impedance of the transistor; The load impedance; For gate-drain negative feedback resistor; This refers to the transconductance of the transistor. The gain of the circuit is affected by... , as well as The impact.

[0076] When the transistor size is fixed, increasing... This results in a decrease in gain, while simultaneously increasing input and output impedance. This structure, at the cost of a certain degree of gain reduction, effectively enhances circuit stability and improves gain flatness.

[0077] The maximum usable gain G of a conventional common-source (CS) amplifier and the CS amplifier with RC negative feedback in this embodiment. ma And the stability (Stabfact) versus frequency curve; such as Figure 5 and Figure 6 As shown, in the 12-18 GHz frequency range, the gain flatness before adding RC negative feedback is 20 dB, and the gain flatness after adding RC negative feedback is 0.7 dB; in the 0-100 GHz frequency range, the minimum K value before adding RC negative feedback is 0.8, and the minimum K value after adding RC negative feedback is 2.1, satisfying full-band stability. It can be seen that the RC negative feedback network can effectively improve gain flatness and stability.

[0078] The input return loss (S) of the low-noise amplifier obtained in the embodiments of the present invention 11 ) and output return loss (S 22 ) varies with frequency, such as Figure 7 As shown, both the input and output return losses are better than 10dB.

[0079] A comparison of noise and stability between a traditional CS-Cascode amplifier and the Cascode-CS amplifier of this invention, as shown below. Figure 8 and Figure 9 As shown, both structures satisfy low noise, but clearly, the amplifier of this invention, which uses a Cascode structure in the pre-stage and a CS structure in the post-stage, has better stability. In the 0-100GHz frequency range, the minimum K-value of a conventional amplifier using a CS pre-stage and a Cascode post-stage is -3.8; the minimum K-value of an amplifier using a Cascode pre-stage and a CS post-stage is 1.5. Therefore, this structure simultaneously possesses high gain, low noise, and high stability, and also has good input-output matching.

Claims

1. A highly stable multi-stage low-noise amplifier architecture, characterized in that, The improvement is to combine the pre-stage Cascode structure with the post-stage CS structure, introduce an RC negative feedback structure, and add a grounding feedback capacitor to the gate of the Cascode common gate transistor. Specifically, it includes an input matching circuit, a first-stage Cascode amplifier circuit, an inter-stage matching circuit, a second-stage CS amplifier circuit, and an output matching circuit; The input terminal IN of the input matching circuit receives the radio frequency signal and matches it to the gate of the first common source transistor M1 of the first stage Cascode amplifier circuit. After being amplified by M1, the signal is output from its drain to the source of the second common gate transistor M2. The signal is further amplified by M2, and its drain output is transmitted to the gate of the third common source transistor M3 in the second stage CS amplifier circuit through the interstage matching circuit. M3 amplifies the signal in two stages, and the two-stage amplified signal is output to the signal output terminal OUT of the output matching circuit through the output matching circuit. In this structure, the first common-source transistor M1 and the second common-gate transistor M2 constitute the pre-stage common-source cascode, and the third common-source transistor M3 is the post-stage common-source CS, forming a two-stage amplification structure that combines the pre-stage common-source cascode and the post-stage common-source CS. This utilizes the extremely high reverse isolation of the pre-stage cascode structure, i.e., extremely low S... 12 The parameters significantly increased the amplifier's stability. Factors that ensure it satisfies the requirements across the entire frequency band. >1; Between the gate of the first common-source transistor M1 and the drain of the second common-gate transistor M2, the series circuit of the second capacitor C2 and the second resistor R2 forms the first RC negative feedback network. The series circuit of the sixth capacitor C6 and the sixth resistor R6 connected between the gate and drain of the third common source transistor M3 forms the second RC negative feedback network.

2. The high-stability multi-stage low-noise amplifier architecture as described in claim 1, characterized in that, The The factor is defined as follows: in, These are S-parameters; intermediate variables. =S 11 S 22 -S 12 S 21 ; The auxiliary criterion for unconditional stability is: , It is an auxiliary stability factor; when the amplifier simultaneously satisfies K>1 and B1>0, it indicates that the circuit is unconditionally stable. exist When S is in the denominator of the factor 12 When the parameter value is very small, It will become very large and easily satisfied. The unconditional stability condition is greater than 1.

3. The high-stability multi-stage low-noise amplifier architecture as described in claim 1, characterized in that, The input matching circuit includes: a first inductor L1 and a first DC blocking capacitor Cblock1; Wherein, the first end of the first inductor L1 is connected with the signal input end IN of the input matching circuit, and the second end of L1 is grounded; meanwhile, the first end of L1 is connected with the first end of the first direct-current isolation capacitor C block1 , and the second end of C block1 is connected with the first stage Cascode amplification circuit.

4. The high-stability multi-stage low-noise amplifier architecture as described in claim 1, characterized in that, The first-stage Cascode amplifier circuit includes: a first common-source transistor M1, a second common-gate transistor M2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first RF choke inductor RF. choke1 Second RF choke inductor choke2 ; The gate of the first common-source transistor M1 is connected to C. block1 The second terminal is connected, the source of M1 is grounded, and the drain of M1 is connected to the source of M2; simultaneously, the gate of M1 is connected to the first RF choke inductor RF. choke1 First end connection; RF choke1 The second terminal is connected to the first terminal of the first resistor R1, and the second terminal of R1 is connected to the gate bias voltage V. g Connection; at the same time, RF choke1 The second terminal of M1 is connected to the second terminal of the first capacitor C1, and the first terminal of C1 is grounded; the gate of M1 is also connected to the first terminal of the second capacitor C2; the second terminal of C2 is connected to the first terminal of the second resistor R2; the second terminal of R2 is connected to the drain of the second common-gate transistor M2; the first terminal of the third resistor R3 is connected to the power supply V. DD Connections: The second terminal of R3 is connected to the gate of M2; the gate of M2 is also connected to the first terminal of the third capacitor C3; the second terminal of C3 is grounded. The drain of M2 and the second RF choke inductor RF choke2 First end connection; RF choke2 The second terminal is related to the drain bias voltage V DD Connection; at the same time, RF choke2 The second terminal is connected to the first terminal of the fourth resistor R4; the second terminal of R4 is connected to the first terminal of the fourth capacitor C4; the second terminal of C4 is grounded.

5. The high-stability multi-stage low-noise amplifier architecture as described in claim 1, characterized in that, The interstage matching network includes: a second DC blocking capacitor C block2 C block2 The first terminal is connected to the drain of the second common-gate transistor M2; C block2 The second end is connected to the second-stage CS amplifier circuit.

6. The high-stability multi-stage low-noise amplifier architecture as described in claim 1, characterized in that, The second-stage CS amplifier circuit includes: a third common-source transistor M3, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a third RF choke inductor RF. choke3 and the fourth RF choke inductor choke4 ; The gate of the third common-source transistor M3 is connected to the second DC blocking capacitor C. block2 The second terminal is connected; simultaneously, the gate of M3 is connected to the third RF choke inductor RF. choke3 The second end is connected; RF choke3 The first terminal is connected to the second terminal of the fifth resistor R5; the first terminal of R5 is connected to the gate bias voltage V. g Connect; simultaneously, the second terminal of R5 is connected to the second terminal of the fifth capacitor C5; the first terminal of C5 is grounded; the gate of M3 is simultaneously connected to the first terminal of the sixth capacitor C6; the second terminal of C6 is connected to the first terminal of the sixth resistor R6; the second terminal of R6 is connected to the drain of M3; the source of M3 is grounded; Meanwhile, the drain of M3 is connected to the fourth RF choke inductor RF. choke4 The first end; RF choke4 The second terminal is related to the drain bias voltage V DD Connection; at the same time, RF choke4 The second end is connected to the first end of the seventh resistor R7, and the second end of R7 is connected to the first end of the seventh capacitor C7; the second end of C7 is grounded.

7. The high-stability multi-stage low-noise amplifier architecture as described in claim 1, characterized in that, The output matching network includes: a third DC blocking capacitor C. block3 Second inductor L2; The third DC blocking capacitor C block3 The first terminal is connected to the drain of the third common-source transistor M3; C block3 The second terminal of C is connected to the signal output terminal OUT; at the same time, C block3 The second end of L1 is connected to the second end of the second inductor L2, and the first end of L2 is grounded.

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