Power-on reset circuit with self-detecting back latch and electronic device

Abstract

This invention discloses a power-on reset circuit with self-detection lockout, comprising a first detection unit, a second detection unit, and a logic comparison unit. The first detection unit performs power supply voltage detection and pre-charging via a first RC charging / discharging unit, and performs lockout and signal locking via a first lockout shutdown unit to obtain a first detection voltage. The second detection unit performs power supply voltage detection and pre-charging via a second RC charging / discharging unit, and performs lockout and signal locking via a second lockout shutdown unit to obtain a second detection voltage. The logic comparison unit outputs a corresponding reset signal based on the first and second detection voltages using a NAND gate. This significantly reduces power consumption and decreases the overall circuit area.

Description

Technical Field

[0001] This invention relates to the field of reset circuit technology, and in particular to a power-on reset circuit with self-detection lockout and an electronic device. Background Technology

[0002] In related technologies, existing power-on reset circuits detect Pbias and Nbias signals generated by internal bias generators and startup circuits. During the POR power-on process, the POR only starts detecting after Pbias and Nbias are activated. Then, the node capacitors charge and discharge, and finally, the power-on reset occurs. During the startup process, the bias generator and the core circuit have open paths, resulting in significant power consumption. Summary of the Invention

[0003] The present invention aims to at least partially solve one of the technical problems in the aforementioned technologies. To this end, one objective of the present invention is to provide a power-on reset circuit with self-detection lockout, which, through an RC charging / discharging unit and a lockout shutdown unit, avoids the risk of self-starting of the bias circuit and performs lockout shutdown of the POR circuit, thereby significantly reducing power consumption and reducing the overall circuit area.

[0004] To achieve the above objectives, this invention proposes a power-on reset circuit with self-detection lockout, comprising: a first detection unit, which includes a first RC charging / discharging unit and a first lockout shutdown unit. The first RC charging / discharging unit is used for power supply voltage detection and pre-charging, and the first lockout shutdown unit is used for lockout shutdown and signal locking to obtain a first detection voltage; a second detection unit, which includes a second RC charging / discharging unit and a second lockout shutdown unit. The second RC charging / discharging unit is used for power supply voltage detection and pre-charging, and the second lockout shutdown unit is used for lockout shutdown and signal locking to obtain a second detection voltage; and a logic comparison unit, which includes a NAND gate. The first input terminal of the NAND gate is connected to the first detection unit, and the second input terminal of the NAND gate is connected to the second detection unit. The NAND gate outputs a corresponding reset signal based on the first detection voltage and the second detection voltage. Thus, by using the RC charging / discharging unit and the lockout shutdown unit, the risk of self-starting of the bias circuit is avoided, and the POR circuit is locked out, thereby greatly reducing power consumption and reducing the overall circuit area.

[0005] In addition, the power-on reset circuit with self-detection lockout proposed in the embodiments of the present invention may also have the following additional technical features:

[0006] Optionally, the first RC charging and discharging unit includes: a first Res resistor, one end of which is connected to a power source and the other end of which serves as a first node; a second capacitor, one end of which is connected to the power source and the other end of which is connected to the first node; and a fifth capacitor, one end of which is connected to the power source.

[0007] Optionally, the first lockout shutdown unit includes: a first MOSFET, the drain of which is connected to the other end of the fifth capacitor, and the source of which is connected to ground; a second MOSFET, the source of which is connected to a power supply; and a first transmission gate, one end of which is connected to the other end of the second capacitor, and the other end of which is connected to the other end of the fifth capacitor.

[0008] Optionally, the second RC charging and discharging unit includes: a second Res resistor, one end of which is connected to ground and the other end of which serves as a second node; a fourth capacitor, one end of which is connected to ground and the other end of which is connected to the second node; and a sixth capacitor, one end of which is connected to ground.

[0009] Optionally, the second lockout shutdown unit includes: a third MOSFET, the drain of which is connected to the other end of the sixth capacitor, and the source of which is connected to a power supply; a fourth MOSFET, the source of which is connected to ground; and a second transmission gate, one end of which is connected to the other end of the fourth capacitor, and the other end of which is connected to the other end of the sixth capacitor.

[0010] Optionally, the first detection unit further includes: a first resistor, one end of which is connected to the drain of the second MOS transistor; a second resistor, one end of which is connected to the other end of the first resistor, and the other end of which is grounded; a first capacitor, one end of which is connected between the first resistor and the second resistor, and the other end of which is connected to ground; and a fifth MOS transistor, the gate of which is connected between the first resistor and the second resistor, the source of which is connected to ground, and the drain of which is connected to the first node.

[0011] Optionally, the second detection unit further includes: a third resistor, one end of which is connected to a power supply; a fourth resistor, one end of which is connected to the other end of the third resistor; a third capacitor, one end of which is connected to a power supply, and the other end of which is connected between the third resistor and the fourth resistor; and a sixth MOS transistor, the gate of which is connected between the third resistor and the fourth resistor, the source of which is connected to a power supply, and the drain of which is connected to the second node.

[0012] Optionally, the logic comparison unit further includes a first inverter, a second inverter, and a third inverter. The input terminal of the first inverter is connected to the output terminal of the first detection unit, the output terminal of the first inverter is connected to the first input terminal of the NAND gate, the input terminal of the second inverter is connected to the output terminal of the second detection unit, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the second input terminal of the NAND gate.

[0013] To achieve the above objectives, a second aspect of the present invention provides an electronic device including a power-on reset circuit with self-detection lockout as described above.

[0014] The electronic device according to embodiments of the present invention avoids the risk of self-starting of the bias circuit by means of an RC charging and discharging unit and a lock-back shutdown unit, and performs lock-back shutdown of the POR circuit, thereby greatly reducing power consumption and reducing the overall circuit area. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the existing power-on reset circuit with self-detection lockout.

[0016] Figure 2 A schematic diagram of the circuit structure of a power-on reset circuit with self-detection lockout according to an embodiment of the present invention;

[0017] Figure 3 This is a waveform diagram of a power-on reset circuit with self-detection lockout according to an embodiment of the present invention. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0019] In related technologies, such as Figure 1As shown, in the prior art, the POR startup circuit requires an additional bias generator and self-starting circuit for detection, and the overall circuit power consumption cannot be turned off, accounting for a large proportion of the overall chip power consumption. To address this, this application proposes a power-on reset circuit with self-detection lockout. Through the RC charging and discharging unit and the lockout shutdown unit, the risk of self-starting of the bias circuit is avoided, and the POR circuit is locked out, thereby greatly reducing power consumption and reducing the overall circuit area.

[0020] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0021] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0022] The power-on reset circuit with self-detection lockout according to an embodiment of the present invention will now be described with reference to the accompanying drawings.

[0023] refer to Figure 2 As shown, the power-on reset circuit with self-detection lockout proposed in this embodiment of the invention includes a first detection unit 100, a second detection unit 200, and a logic comparison unit 300.

[0024] The first detection unit 100 includes a first RC charging and discharging unit and a first lockout shutdown unit. The first RC charging and discharging unit is used for power supply voltage detection and pre-charging, and the first lockout shutdown unit is used for lockout shutdown and signal locking to obtain the first detection voltage IPOSB.

[0025] As one embodiment, the first RC charging and discharging unit includes a first Res resistor Res1, a second capacitor C2, and a fifth capacitor C5; one end of the first Res resistor Res1 is connected to the power supply, and the other end of the first Res resistor Res1 serves as a first node A; one end of the second capacitor C2 is connected to the power supply, and the other end of the second capacitor C2 is connected to the first node A; one end of the fifth capacitor C5 is connected to the power supply.

[0026] In other words, such as Figure 3 As shown, the node voltage IPP is pre-charged through the first Res resistor Res1, the second capacitor C2 and the fifth capacitor C5, and the node voltage IPP changes from L→H, that is, from low level to high level; after POR starts, the switch SW in the circuit is opened, and the IP voltage and IPOSB voltage change from H→L.

[0027] It should be noted that by using RC charge and discharge delay, the power supply voltage (VDD) is ensured to rise steadily to the POR start-up threshold, thus avoiding false triggering caused by power fluctuations.

[0028] As one embodiment, the first lockout shutdown unit includes a first MOSFET SW1, a second MOSFET SW2, and a first transmission gate SW3; the drain of the first MOSFET SW1 is connected to the other end of the fifth capacitor C5, and the source of the first MOSFET SW1 is connected to ground; the source of the second MOSFET SW2 is connected to the power supply; one end of the first transmission gate SW3 is connected to the other end of the second capacitor C2, and the other end of the first transmission gate SW3 is connected to the other end of the fifth capacitor C5.

[0029] In other words, when the IPP voltage reaches the POR start-up threshold, the circuit enters the latching stage, shutting off the power consumption path and locking the reset signal through a three-step switching action.

[0030] It should be noted that after the POR circuit starts, the first step is to turn on the first MOSFET SW1 and pull the IPOSB to VSS; the second step is to turn on the second MOSFET SW2 and turn off the resistor path, pulling IP to VSS; the third step is to turn on the first transmission gate SW3 and cut off the path to prevent the pull-up from generating a competition relationship, so that the POR is stably latched and all related power consumption is turned off.

[0031] In one specific embodiment, the first detection unit 100 further includes a first resistor R1, a second resistor R2, a first capacitor C1, and a fifth MOSFET NM1; one end of the first resistor R1 is connected to the drain of the second MOSFET SW2; one end of the second resistor R2 is connected to the other end of the first resistor R1, and the other end of the second resistor R2 is grounded; one end of the first capacitor C1 is connected between the first resistor R1 and the second resistor R2, and the other end of the first capacitor C1 is connected to ground; the gate of the fifth MOSFET NM1 is connected between the first resistor R1 and the second resistor R2, the source of the fifth MOSFET NM1 is connected to ground, and the drain of the fifth MOSFET NM1 is connected to the first node A.

[0032] The second detection unit 200 includes a second RC charging and discharging unit and a second lock-out unit. The second RC charging and discharging unit is used for power supply voltage detection and pre-charging, and the second lock-out unit is used for lock-out and signal locking to obtain the second detection voltage INOS.

[0033] As one embodiment, the second RC charging and discharging unit includes a second Res resistor Res2, a fourth capacitor C4, and a sixth capacitor C6; one end of the second Res resistor Res2 is connected to ground, and the other end of the second Res resistor Res2 serves as the second node B; one end of the fourth capacitor C4 is connected to ground, and the other end of the fourth capacitor C4 is connected to the second node B; one end of the sixth capacitor C6 is connected to ground.

[0034] In other words, such as Figure 3 As shown, the node voltage INN is pre-charged through the second Res resistor Res2, the fourth capacitor C4, and the sixth capacitor C6, and the node voltage INN changes from L to H, that is, from low level to high level; after POR is started, the switch SW in the circuit is opened, and the INN voltage changes from H to L.

[0035] As one embodiment, the second lockout shutdown unit includes a third MOSFET SW4, a fourth MOSFET SW5, and a second transmission gate SW6; the drain of the third MOSFET SW4 is connected to the other end of the sixth capacitor C6, and the source of the third MOSFET SW4 is connected to the power supply; the source of the fourth MOSFET SW5 is connected to ground; one end of the second transmission gate SW6 is connected to the other end of the fourth capacitor C4, and the other end of the second transmission gate SW6 is connected to the other end of the sixth capacitor C6.

[0036] In other words, when the INN voltage reaches the POR start-up threshold, the circuit enters the latching stage. It shuts off the power consumption path and locks the reset signal through a three-step switching action, maintains the voltage state through the node capacitor, and ensures the reset signal by combining the switching logic, thus providing a reliable power-on reset signal for other modules of the chip.

[0037] It should be noted that after the POR circuit starts, in the first step, the third MOSFET SW4 turns on, pulling INOS to VDD; in the second step, the fourth MOSFET SW5 turns on, turning off the resistor path and pulling IN to VDD. In the third step, the second transmission gate SW6 turns on, cutting off the path and preventing competition caused by pull-down, thus stabilizing the POR latch and turning off all related power consumption.

[0038] In one specific embodiment, the second detection unit 200 further includes a third resistor R3, a fourth resistor R4, a third capacitor C3, and a sixth MOSFET PM1; one end of the third resistor R3 is connected to the power supply; one end of the fourth resistor R4 is connected to the other end of the third resistor R3; one end of the third capacitor C3 is connected to the power supply, and the other end of the third capacitor C3 is connected between the third resistor R3 and the fourth resistor R4; the gate of the sixth MOSFET PM1 is connected between the third resistor R3 and the fourth resistor R4, the source of the sixth MOSFET PM1 is connected to the power supply, and the drain of the sixth MOSFET PM1 is connected to the second node B.

[0039] The logic comparison unit 300 includes a NAND gate N1. The first input terminal of the NAND gate N1 is connected to the first detection unit 100, and the second input terminal of the NAND gate N1 is connected to the second detection unit 200. The NAND gate N1 outputs a corresponding reset signal according to the first detection voltage IPOSB and the second detection voltage INOS.

[0040] As an embodiment, the logic comparison unit 300 further includes a first inverter 10, a second inverter 20, and a third inverter 30. The input terminal of the first inverter 10 is connected to the output terminal of the first detection unit 100, and the output terminal of the first inverter 10 is connected to the first input terminal of the NAND gate N1. The input terminal of the second inverter 20 is connected to the output terminal of the second detection unit 200, and the output terminal of the second inverter 20 is connected to the input terminal of the third inverter 30. The output terminal of the third inverter 30 is connected to the second input terminal of the NAND gate N1.

[0041] Specifically, such as Figure 3 As shown, when switch SW is open, the voltage states of each node are as follows: node voltage IP changes from high level to low level; node voltage IN changes from low level to high level; node voltage IPP changes from low level to high level; node voltage INN changes from high level to low level; node voltage IPOSB changes from high level to low level; node voltage INOS changes from low level to high level; node voltage IPO changes from low level to high level; node voltage INO changes from low level to high level.

[0042] Additionally, the signals ZPOR, ZPOR1, ZPOR2, ZPORB, ZPOR1B, and ZPOR2B are the switch control signals for SW1, SW2, SW3, SW4, SW5, and SW6 in the diagram, respectively. These are signals indicating successful power-on detection; only after successful power-on will local latch-up occur, turning off the switches. Figure 2 As shown, the detection signal ZPORB is the first signal, and the subsequent signals are delayed by an inverter. That is, the timing of the circuit lockout is as shown in the figure, labeled 1 (first turn-off), 2, 3 (last turn-off).

[0043] It should be noted that the inverter ensures that the signal input to the NAND gate N1 is time-matched, eliminates glitches or unstable states, and converts the analog voltage signal generated by capacitor charging and discharging into a steep digital logic level, thus meeting the logic threshold requirements of the NAND gate N1 for the input signal.

[0044] In summary, the power-on reset circuit with self-detection lockout proposed in this embodiment of the invention detects and pre-charges the power supply voltage through the first RC charging and discharging unit of the first detection unit, and performs lockout shutdown and signal locking through the first lockout shutdown unit of the first detection unit to obtain the first detection voltage; detects and pre-charges the power supply voltage through the second RC charging and discharging unit of the second detection unit, and performs lockout shutdown and signal locking through the second lockout shutdown unit of the second detection unit to obtain the second detection voltage; and outputs a corresponding reset signal through the NAND gate of the logic comparison unit based on the first and second detection voltages. Thus, by replacing the existing Pbias and Nbias detection with resistor Res detection, the uncertainty risk caused by the start-up of the bias circuit can be avoided. Since a bias generation circuit and a start-up circuit are required, the circuit power consumption is high, and it will continue to consume a large current after the overall circuit is powered on and reset. This application performs lockout in the POR circuit, and locks and shuts down the circuit after detecting that the POR circuit is successfully powered on, thereby greatly reducing power consumption and reducing the overall circuit area.

[0045] In addition, embodiments of the present invention also provide an electronic device including a power-on reset circuit with self-detection lockout as described above.

[0046] The electronic device according to embodiments of the present invention avoids the risk of self-starting of the bias circuit by means of an RC charging and discharging unit and a lock-back shutdown unit, and performs lock-back shutdown of the POR circuit, thereby greatly reducing power consumption and reducing the overall circuit area.

[0047] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0049] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0050] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0051] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0052] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A power-on reset circuit with self-detection lockout, characterized in that, include: The first detection unit includes a first RC charging and discharging unit and a first lock-out unit. The first RC charging and discharging unit is used for power supply voltage detection and pre-charging, and the first lock-out unit is used for lock-out and signal locking to obtain the first detection voltage. The second detection unit includes a second RC charging and discharging unit and a second lock-out unit. The second RC charging and discharging unit is used for power supply voltage detection and pre-charging, and the second lock-out unit is used for lock-out and signal locking to obtain the second detection voltage. The logic comparison unit includes a NAND gate, the first input terminal of which is connected to the first detection unit, the second input terminal of which is connected to the second detection unit, and the NAND gate outputs a corresponding reset signal based on the first detection voltage and the second detection voltage. The first RC charging and discharging unit includes: The first Res resistor has one end connected to the power supply and the other end serving as the first node. A second capacitor, one end of which is connected to the power source, and the other end of which is connected to the first node; The fifth capacitor, one end of which is connected to the power supply; The first lockout shutdown unit includes: The first MOSFET has its drain connected to the other end of the fifth capacitor, its source connected to ground, and its gate connected to the ZPOR signal to detect whether the circuit has been successfully powered on. The second MOSFET has its source connected to the power supply and its gate connected to the ZPOR1 signal to detect whether the circuit has been successfully powered on. A first transmission gate, one end of which is connected to the other end of the second capacitor, and the other end of which is connected to the other end of the fifth capacitor; The second RC charging and discharging unit includes: The second Res resistor has one end connected to ground and the other end serving as the second node. The fourth capacitor has one end connected to ground and the other end connected to the second node; The sixth capacitor, one end of which is connected to ground; The second lockout shutdown unit includes: The third MOS transistor has its drain connected to the other end of the sixth capacitor, its source connected to the power supply, and its gate connected to the ZPORB signal to detect whether the circuit has been successfully powered on. The fourth MOSFET has its source connected to ground and its gate connected to the ZPOR1B signal to detect whether the circuit has been successfully powered on. The second transmission gate has one end connected to the other end of the fourth capacitor and the other end connected to the other end of the sixth capacitor.

2. The power-on reset circuit with self-detection lockout according to claim 1, characterized in that, The first detection unit further includes: The first resistor, one end of which is connected to the drain of the second MOSFET; The second resistor has one end connected to the other end of the first resistor, and the other end of the second resistor is grounded. A first capacitor, one end of which is connected between the first resistor and the second resistor, and the other end of which is connected to ground; The fifth MOS transistor has its gate connected between the first resistor and the second resistor, its source connected to ground, and its drain connected to the first node.

3. The power-on reset circuit with self-detection lockout according to claim 1, characterized in that, The second detection unit further includes: The third resistor, one end of which is connected to the power supply; The fourth resistor has one end connected to the other end of the third resistor, and the other end of the fourth resistor is connected to the drain of the fourth MOS transistor. The third capacitor has one end connected to the power supply and the other end connected between the third resistor and the fourth resistor; The sixth MOS transistor has its gate connected between the third and fourth resistors, its source connected to the power supply, and its drain connected to the second node.

4. The power-on reset circuit with self-detection lockout according to claim 1, characterized in that, The logic comparison unit further includes a first inverter, a second inverter, and a third inverter. The input terminal of the first inverter is connected to the output terminal of the first detection unit, and the output terminal of the first inverter is connected to the first input terminal of the NAND gate. The input terminal of the second inverter is connected to the output terminal of the second detection unit, and the output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the second input terminal of the NAND gate.

5. An electronic device, characterized in that, Includes a power-on reset circuit with self-detection lockout as described in any one of claims 1 to 4.

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