Cxl switch chip with multi-corelet architecture and cross-corelet routing switching method thereof

Abstract

The application belongs to the field of PCIe chips and relates to a CXL switching chip with a multi-corelet architecture and a cross-corelet routing and switching method thereof. Multiple CXL switching corelets with unified specifications are connected through packaging interconnection to form a CXL switching chip. Each CXL switching corelet contains a plurality of ports, each of which can be configured as a CXL mode or a D2D mode. Each port of each CXL switching corelet at least includes a physical layer, a CXL link layer, a CXL transaction layer, a D2D routing layer, a bypass and a multiplexing module. The CXL switching chip further includes a multi-VC on-chip CXL switching network, which contains at least one in-order switching VC and one out-of-order switching VC. The application can flexibly construct CXL switching chips of multiple specifications, effectively reduce the design complexity and verification difficulty of large-scale or multi-port CXL switching chips and improve the chip production yield.

Description

TECHNICAL FIELD

[0001] The present application relates to a CXL exchange chip of a multi-corelet architecture and a cross-corelet routing exchange method thereof, and belongs to the technical field of PCIe exchange chips. BACKGROUND

[0002] With the continuous increase of the demand for CXL interconnection bandwidth in data center and high-performance computing scenarios, a multi-corelet architecture becomes a key path to realize an ultra-large-scale exchange chip. However, in a system composed of multiple CXL exchange corelets, cross-corelet data routing faces the following core challenges: how to improve the cross-corelet transmission efficiency of CXL messages, reduce the design and verification complexity of a multi-port CXL exchange chip, and improve the chip yield under the premise of guaranteeing bandwidth and delay performance.

[0003] Specifically, in an ultra-large-scale exchange scenario that needs to support hundreds of ports, the existing solution usually needs to encapsulate or carry specific routing identification information in addition to the original CXL transaction layer packet (TLP) when processing cross-corelet message forwarding. The insertion and analysis process of this additional information increases the exchange delay on the one hand, and directly occupies the channel bandwidth for the payload on the other hand, resulting in a loss of overall exchange capacity. At the same time, ensuring the in-order transmission of protocol messages under a complex cross-corelet path (especially messages that need to be strictly transmitted in order), improving the exchange efficiency of non-in-order messages, and realizing flexible and efficient utilization of the interconnection link bandwidth between multiple corelets, are difficult problems that must be solved for such an architecture in a more efficient way to organize a large-specification multi-port CXL exchange chip with small-specification CXL exchange corelets.

[0004] Based on this, the present application is proposed. SUMMARY

[0005] The present application provides a CXL exchange chip of a multi-corelet architecture and a cross-corelet routing exchange method thereof, and the specific technical solutions are as follows:

[0006] In a first aspect, a CXL exchange chip of a multi-corelet architecture includes:

[0007] A plurality of CXL exchange corelets of uniform specifications constitute a CXL exchange chip through encapsulation interconnection;

[0008] Each CXL exchange corelet contains a plurality of ports, and each port can be configured as:

[0009] A CXL mode for interconnection between the CXL exchange chip and other CXL exchange chips or CXL devices;

[0010] A D2D mode for interconnection between the CXL exchange chip and other CXL exchange chips or CXL devices;

[0011] Each port of the CXL switch core includes at least:

[0012] The physical layer is shared by the CXL mode and the D2D mode, and is responsible for physical connection between multiple CXL switch chips and between different CXL switch cores in a single CXL switch chip;

[0013] The CXL link layer is shared by the CXL mode and the D2D mode, and is responsible for processing encapsulation, error detection and correction, and flow control mechanism of CXL data frames;

[0014] The CXL transaction layer is implemented according to the standard CXL protocol specification, and is responsible for implementing CXL transaction layer message type resolution and message attribute acquisition;

[0015] The D2D routing layer is responsible for implementing D2D message type conversion, routing information and VC ID number encapsulation, D2D routing information reverse analysis and stripping;

[0016] The bypass: if the port mode is the CXL mode, the transaction layer message will enter the bypass and be directly transmitted to the multi-VC on-chip CXL switch network;

[0017] The multiplexing module is responsible for selecting and distributing the messages output by the D2D routing layer and the bypass;

[0018] The CXL switch chip further includes a multi-VC on-chip CXL switch network, which is responsible for implementing message switching;

[0019] The multi-VC on-chip CXL switch network includes at least one in-order switching VC and one out-of-order switching VC;

[0020] The in-order switching VC is responsible for in-order switching of messages;

[0021] The out-of-order switching VC is responsible for out-of-order switching of messages;

[0022] The messages distributed by the multiplexing module, wherein the messages that need to be in-order are distributed to the in-order switching VC in the multi-VC on-chip CXL switch network, and the messages that do not need to be in-order are distributed to the out-of-order switching VC.

[0023] Further improvement, the D2D routing layer is configured to:

[0024] convert the transaction layer message parsed by the CXL transaction layer into a corresponding type, and bind the converted message to a corresponding switching VC;

[0025] wherein the message type that needs to be in-order transmitted is bound to the in-order switching VC, and the message type that can be out-of-order transmitted is bound to the out-of-order switching VC.

[0026] Further improvement, the D2D routing layer is configured to perform type conversion, including:

[0027] When the CXL.io packet is in FLIT mode, and the packet Type field is Cpl or CplD, and the RO field is equal to 1, perform non-ordered I / O to ordered I / O conversion:

[0028] If the Type field is Cpl, modify it to UIORdCpl;

[0029] If the Type field is CplD, modify it to UIORdCplD;

[0030] And after completing the conversion, set an identification bit in the packet header to mark that the packet has been type-converted.

[0031] Further improvement, the D2D routing layer is configured to implement cross-grain routing, including:

[0032] Add a set of sideband signals DID based on the standard CXL packet format;

[0033] The D2D routing layer maintains a primary routing table and a secondary routing sub-table, which are used to perform pipeline table lookup according to the BDF number in the packet to determine the destination DID of the packet.

[0034] Further improvement, the primary routing table contains routing ID1, table entry type, and destination CXL port or secondary routing table ID2;

[0035] Wherein, the table entry type is used to decide whether the packet is locally routed or cross-grain routed:

[0036] If it is locally routed, directly assign the destination DID as the port ID of the destination CXL port, and skip the secondary routing table query;

[0037] If it is cross-grain routed, further query the secondary routing sub-table indexed by the secondary routing table ID2.

[0038] Further improvement, the secondary routing sub-table is designed as a multi-bank structure to support parallel processing of multiple query requests;

[0039] The secondary routing sub-table contains routing ID2, D2D routing strategy, and at least one destination D2D port;

[0040] Wherein, the D2D routing strategy decides the strategy for selecting the egress port from the destination D2D port according to the VC ID bound to the packet:

[0041] When the packet is bound to the in-order exchange VC, a static routing strategy is adopted to select a preset destination D2D port fixedly;

[0042] When the packet is bound to the out-of-order exchange VC, a dynamic routing strategy is adopted to select based on the congestion state of each destination D2D port.

[0043] Further improvement, the dynamic routing strategy judges the port congestion state by monitoring the port credit information from the CXL link layer;

[0044] When there is no congestion, the exit is selected from the available destination D2D port according to the polling algorithm.

[0045] Further improvement, after the CXL exchange chip is packaged, the internal CXL exchange core particles are interconnected by 2.5D or 3D integration technology to form a Mesh or Ring topology.

[0046] The second aspect is a cross-particle routing exchange method of a CXL exchange chip with a multi-particle architecture, comprising the following steps:

[0047] Receiving a CXL packet at the port of the CXL exchange core particle;

[0048] Parsing the packet type and BDF information of the CXL packet;

[0049] Converting the packet type that needs to be converted at the D2D routing layer, and binding the packet to the VC ID;

[0050] Obtaining the DID of the packet by querying the routing table, and encapsulating the DID into the CXL packet;

[0051] Sending the encapsulated packet to the multi-VC on-chip CXL exchange network for in-order or out-of-order exchange;

[0052] Forwarding the exchanged packet to the target port;

[0053] If the target port is a D2D port, the original CXL packet is sent to the next pointed CXL exchange core particle after stripping the DID information;

[0054] If the target port is a CXL port, it is judged whether the packet has been type-converted; if yes, reverse type conversion is performed to restore the original packet type, and then the packet is sent to an external CXL device; if not, the packet content remains unchanged, and the packet is sent to other CXL devices.

[0055] Further improvement, the query of the routing table is performed in a staged pipeline manner, comprising:

[0056] First stage: extract the BDF number of the packet, query the first-level routing table to determine the table item type; if it is a local route, directly generate a DID;

[0057] Second stage: if it is a cross-grain routing, use the BDF number to query the second-level routing sub-table, and determine the destination D2D port according to the routing strategy, so as to generate a DID;

[0058] Third stage: merge the query results of the first stage and the second stage, and complete the encapsulation of the DID.

[0059] The beneficial effects of the present application are:

[0060] 1. In the cross-grain switching process, the present application realizes the conversion of ordered packets and unordered packets of CXL, and the unordered packets can be routed and switched in a dedicated unordered switching VC, so that the ordered packets which need to maintain a fixed path static route can be transmitted between multiple grains according to a dynamic routing mode in the cross-grain, supporting more flexible multi-grain non-tree topology structure and multi-path transmission of CXL packets, and improving the performance and flexibility of cross-grain data transmission.

[0061] 2. In order to achieve the optimal performance in different scenarios, the present application provides two routing modes:

[0062] The static routing mode guarantees the in-order transmission of CXL protocol packets (such as packets with strong sequence requirements) through a predefined deterministic path;

[0063] The dynamic routing mode transmits data streams in multiple paths among the multi-grain interconnection links according to the real-time traffic state, maximizing the total effective bandwidth utilization of the multi-grain interconnection.

[0064] The method of the present application solves the key bottleneck of efficient and reliable switching under the multi-grain architecture, and provides a basic support for constructing a super-large-scale, high-bandwidth and low-cost CXL switching system.

[0065] 3. The chip of the present application takes a single-specification CXL switching grain as a basic unit, and can flexibly construct CXL switching chips of multiple specifications. Since the number of channels of the single-specification grain is limited, its architecture can be simplified, thereby effectively reducing the design complexity and verification difficulty of large-scale or multi-port CXL switching chips. The reduction of the design complexity of the grain directly leads to the reduction of its area, thereby greatly improving the chip production yield and significantly reducing the tape-out cost. BRIEF DESCRIPTION OF DRAWINGS

[0066] Figure 1 It is a schematic diagram of a CXL switching chip of a multi-grain architecture;

[0067] Figure 2 It is a schematic diagram of the internal structure of a CXL switching grain;

[0068] Figure 3 For D2D routing table multi-stage pipeline and segmented lookup flowchart;

[0069] Figure 4 For the structure of a level routing table;

[0070] Figure 5 For the structure of a two-level routing table;

[0071] Figure 6 For CXL switch chiplet message processing flowchart;

[0072] Figure 7 For 2-chiplet structure CXL switch chip architecture diagram;

[0073] Figure 8 For 3-chiplet structure CXL switch chip architecture diagram;

[0074] Figure 9 For 4-chiplet structure CXL switch chip architecture diagram. DETAILED DESCRIPTION

[0075] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and do not limit the present application.

[0076] Abbreviations and key terms definition

[0077] CXL: Compute Express Link, a new high-speed interconnection standard, which extends CXL.io, CXL.mem and CXL.cache protocols based on PCIe protocol, for high-speed interconnection of input / output (I / O), memory (mem) and cache (cache);

[0078] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard;

[0079] I / O: Input / Output, computer input / output component;

[0080] Chiplet: a technology that splits a complex chip into multiple independent modules (chiplets) for design and manufacture, and then integrates them to improve yield and reduce cost;

[0081] ID: Identifier, unique port identifier;

[0082] ROM: Read-Only Memory, a non-volatile memory, data is pre-written and can only be read, not modified, used to store fixed programs or data;

[0083] round-robin: a scheduling algorithm, in a fixed order, to allocate resources, to ensure that each task request fair access to processing opportunities;

[0084] D2D: Die To Die, from the core to the core of the interconnection;

[0085] Die: core die, that is, each small chip that makes up the chip;

[0086] VC: Virtual Channel, each virtual channel has its own cache and flow control mechanism;

[0087] UIO: Unorder I / O, out-of-order I / O operation;

[0088] NUIO: Non-Unoder I / O, in-order I / O operation;

[0089] TLP: Transaction Layer Packet, transaction layer packet;

[0090] S2M: Subordinate to Master, from memory to memory initiator;

[0091] M2S: Master to Subordinate, from memory initiator to memory;

[0092] D2H: Device to Host, from device to host;

[0093] H2D: Host to Device, from host to device;

[0094] NDR: No Data Response, no data response;

[0095] DRS: Data Response, data response;

[0096] RSP: Response, response;

[0097] REQ: Request, request;

[0098] RWD: Request with Data, request with data;

[0099] DATA: Data, data;

[0100] BISnp: Back-Invalidate Snoop, Back-Invalidation Snooping;

[0101] BIRsp: Back-Invalidate Response, Back-Invalidation Response;

[0102] VC_ID: VC Number;

[0103] FLIT: Flow Control Unit, Data is divided into fixed-size packets, becoming Flow Control Units (FLITs), each of which is fixed in size;

[0104] Cpl: Completion, Completion Packet;

[0105] CplD: Completion with Data, Completion Packet with Data;

[0106] UIORdCpl: UIO Read Completion, UIO Type Read Completion Packet;

[0107] UIORdCplD: UIO Read Completion with Data, UIO Type Read Completion Packet with Data;

[0108] BDF: Bus Device Function, Bus / Device / Function Number, Each CXL device has one or more BDF numbers in the system, and each BDF number is unique;

[0109] Mesh (Mesh): A kind of network topology, each node (or chip) is directly connected to the nodes adjacent to it in the up, down, left and right directions, forming a two-dimensional grid structure;

[0110] Ring (Ring): A kind of network topology, all nodes are connected in a ring order, each node is connected to only two nodes in front and back, forming a closed loop;

[0111] 2.5D topology: Two-dimensional half-solid (2.5-dimensional) topology; In 2.5D topology, each core particle is placed side by side in the same plane, and horizontal interconnection is achieved through an interposer or other substrate;

[0112] 3D topology: Three-dimensional (3D) topology; In 3D topology, multiple core particles are stacked in the vertical direction, and vertical interconnection between core particles is achieved through TSV (through-hole) or micro-bump, forming a truly three-dimensional interconnection network;

[0113] Memory: Memory space.

[0114] The application is based on a CXL cross-chiplet routing method to build a CXL switch chip of a multi-chiplet architecture. Each CXL switch chiplet is designed with a unified specification, including the same size, interface and functional module, to ensure high compatibility and reusability, thereby flexibly building CXL switch chips of various specifications. Small-area chiplets have a lower defect rate in semiconductor processes. As shown in the figure, a CXL switch chip is composed of multiple CXL switch chiplets, each CXL switch chiplet has several ports, and each port can be configured in two modes: Figure 1

[0115] 1) CXL mode;

[0116] 2) D2D mode.

[0117] Among them, the CXL mode port is used for interconnection between the CXL switch chip and other CXL switch chips, and the D2D mode port is used for interconnection between each CXL switch chiplet in the CXL switch chip.

[0118] Embodiment 1

[0119] As shown in the figure, each port of each CXL switch chiplet is designed uniformly to ensure consistency and interoperability, including the following protocol layers: Figure 2

[0120] Physical layer: CXL mode and D2D mode are shared, responsible for physical connection between multiple CXL switch chips and each CXL switch chiplet in a single CXL switch chip, realizing signal transmission, clock synchronization and electrical interface matching to ensure stable docking;

[0121] CXL link layer: CXL mode and D2D mode are shared, responsible for processing CXL data frame packaging, error detection and correction, and flow control mechanism to ensure link reliability;

[0122] CXL transaction layer: strictly according to the standard CXL protocol specification, responsible for realizing CXL transaction layer message type analysis and message attribute acquisition;

[0123] D2D (Die-to-Die) routing layer: responsible for realizing D2D message type conversion, routing information and VC ID number packaging, D2D routing information reverse analysis and stripping;

[0124] Bypass: if the port mode is CXL mode, the transaction layer message will enter the bypass and be directly transmitted to the multi-VC on-chip CXL switch network;

[0125] Multi-VC on-chip CXL switch network: responsible for realizing message switching, specifically divided into 2 switching VC (Virtual Channel): ​​

[0126] In-order exchange VC: responsible for the in-order exchange of messages, fixed VC ID=0 is used;

[0127] Out-of-order exchange VC: responsible for the out-of-order exchange of messages, fixed VC ID=3 is used;

[0128] The CXL exchange chip group topology interconnection structure of each CXL exchange chip is fixed after packaging, so during the configuration process before use of the CXL exchange chip, the firmware initializes and sets the transaction layer port of each CXL exchange chiplet through preset fixed configuration parameters, and the specific configuration includes:

[0129] 1) Configure the port type (two options) for each port of the CXL exchange chiplet:

[0130] Type 1: CXL mode;

[0131] Type 2: D2D mode;

[0132] 2) Assign a unique chiplet ID number to each CXL exchange chiplet: CID (Chiplet ID, chiplet identifier, used to uniquely identify the number of each CXL exchange chiplet);

[0133] 3) Assign a unique port ID number to each port of the CXL exchange chiplet: PID (Port ID, port identifier, used to uniquely identify the number of each port on the exchange chiplet).

[0134] Multiplexing module: responsible for selecting and distributing CXL messages of the D2D routing layer and bypass output, wherein messages that need to be in order are distributed to the in-order exchange VC in the multi-VC on-chip CXL exchange network, and messages that do not need to be in order are distributed to the out-of-order exchange VC.

[0135] After the CXL message is input from the CXL port (the port corresponding to the CXL mode on the CXL exchange chiplet) to the CXL exchange chiplet, it reaches the CXL transaction layer via the physical layer and the CXL link layer, and is parsed and classified by the CXL transaction layer according to the corresponding message type:

[0136] For CXL.io messages, they are classified as UIO (Unorder I / O) and NUIO (Non-Unorder I / O);

[0137] For CXL.mem messages, they are classified as S2M_NDR, S2M_DRS, S2M_RWD, S2M_BISnp, and S2M_BIRsp;

[0138] For CXL.cache packet, it is classified as H2D_REQ, H2D_RSP, H2D_DATA, D2H_RSP, D2H_DATA;

[0139] The D2D routing layer converts the NUIO (Non-Unorder I / O) packet type to the UIO (Unorder I / O) packet type according to the transaction layer packet type: when the CXL.io packet transmission mode is the FLIT mode, the packet Type (transaction type) field is Cpl or CplD, and the RO (Relaxed Ordering) domain is equal to 1, the packet content is modified as follows:

[0140] If the packet Type field is Cpl, the Type field is changed to UIORdCpl;

[0141] If the packet Type field is CplD, the Type field is changed to UIORdCplD;

[0142] If the above type conversion is completed, the highest bit of the 11th byte of the packet header is written as '1', indicating that the packet is a packet converted from NUIO to UIO, otherwise the highest bit of the 11th byte of the packet header is written as '0'.

[0143] The D2D routing layer binds the above-mentioned 8 types of CXL packets, NUIO, S2M_NDR, S2M_DRS, D2H_RSP, D2H_DATA, M2S_REQ, H2D_REQ, and H2D_RSP, to the in-order switching VC (VC 0). The other 5 types of CXL packets, UIO, S2M_RWD, S2M_BISnp, S2M_BIRsp, and H2D_DATA, are bound to the out-of-order switching VC (VC 3).

[0144] Embodiment 2

[0145] The CXL switching core particle increases a set of sideband signals DID (Destination ID, destination identifier) on the basis of the standard CXL packet format when passing through the D2D routing layer, which is used to indicate the target CXL switching core particle port to which the packet goes.

[0146] The D2D routing layer implements a cross-core routing table, which is indexed by BDF (Bus Device Function) number (Hash or direct indexing, Hash: Hash). The cross-core routing table lookup process is designed to be a phased and pipelined lookup, and its parallelism is embodied in the pipelined processing of multiple CXL packets, with each phase processing different CXL packets.

[0147] The cross-core routing table is divided into two-level table structure:

[0148] DID primary routing table and secondary routing sub-tables. Among them, the secondary routing sub-tables are designed as a multi-bank structure to support simultaneous processing of queries from multiple upstream ports.

[0149] The multi-stage pipeline and segmented lookup process of the D2D routing table are shown in Figure 3 ;

[0150] Pipeline first stage: extract the BDF number in the CXL packet, the group of sideband signals first performs a primary routing table query to determine the table item type in the analysis process; use the BDF number as an index to access all possible associated sub-tables in parallel (or directly locate the primary routing table through hashing), which can be completed in a very small number of clock cycles; if the group of sideband signals queries the routing ID1 in the primary routing table and the result is 0x0 (this string represents the value of the query result in the routing table is 0), then the packet table item type is local routing, and the packet directly goes to another CXL port of the CXL switch core, and the DID is directly assigned to the value of the PID corresponding to the destination CXL port, skipping the secondary routing table lookup process.

[0151] As shown in Figure 4 , the primary routing table includes routing ID1 (for matching), table item type (for decision-making), destination CXL port / secondary routing table ID2 (for execution).

[0152] Routing ID1: a unique number identifying the routing table item, used for matching of the routing table;

[0153] Table item type: distinguishes the source of the routing (such as static routing, dynamic routing) or the forwarding type;

[0154] Destination CXL port / secondary routing table ID2:

[0155] If it is a "destination CXL port", the packet is directly forwarded to the specified hardware port;

[0156] If it is a "secondary routing table ID2", the next level routing table needs to be called to further refine the forwarding path.

[0157] For example, Figure 9 , when the CXL switch core 0 receives a packet from an external CXL switch chip, and the sideband signal query result is 0x0, the packet will be encapsulated and sent by the CXL switch core 0 to other external CXL switch chips, not the CXL switch core 1.

[0158] Pipeline second stage: if the result of querying the routing ID1 in the first-level routing table is 0x1 (the string indicates that the value of the query result in the routing table is 1), the message table type is cross-grain routing, and the second-level routing sub-table needs to be further queried. Each BDF corresponds to a second-level routing sub-table, and the sub-table contains the mapping of all devices under the BDF. By using a high-speed memory (SRAM) and an optimized data structure, cross-grain routing table hardware can be used to process multiple queries in parallel or check multiple table entries in parallel in one query: in the hit (or all possible) second-level routing sub-table, the BDF pair is used as the key, and the index is performed in the SRAM.

[0159] When the VC is 0, a static routing strategy is adopted, and port 1 of the destination CXL switch grain D2D port is fixedly used.

[0160] When the VC is 3, a dynamic routing strategy is adopted, and the destination port is selected according to the congestion of each D2D port.

[0161] D2D port congestion detection is realized by receiving port credit information from the CXL link layer, which can reflect the back pressure state of the port. When there is no congestion, the messages are distributed to each D2D port fairly according to the RR (Round-Robin) algorithm, and the DID is assigned the value of the PID corresponding to the destination D2D port. The routing table is relatively static after system enumeration, but supports dynamic updating in scenarios such as hot plug.

[0162] See Figure 5 , the second-level routing table contains routing ID2, D2D routing strategy, destination D2D port 1, destination D2D port 1... destination D2D port n.

[0163] Routing ID2: takes the upper-level routing and locates to the correct sub-table.

[0164] D2D routing strategy: defines the logic and behavior of data forwarding, and is the key to realizing high-performance and high-availability network.

[0165] Destination D2D port 1... n: provides specific export options for forwarding.

[0166] Pipeline third stage: merge the results of the previous two stages, encapsulate the DID information into the CXL message information, and forward the CXL message to the multi-VC on-chip CXL switch network.

[0167] The above cross-grain CXL routing table lookup method is different from the conventional CXL switch chip routing table lookup in that:

[0168] 1. The conventional CXL switch chip routing lookup method needs to strictly follow the CXL protocol specification, and its topology is fixed bit tree structure. The cross-grain routing switching method of the application can be based on flexible 2.5D, 3D topology (such as Mesh or Ring, etc.).

[0169] 2. The conventional CXL switch chip routing lookup method needs a globally unified address space (BDF number and Memory space), and its routing table is usually centrally operated, all ports sharing the same global routing table. The cross-grain routing switching method described in the application can use a distributed, segmented address space, each grain may only maintain local routing information, and the lookup may need cross-grain collaboration, which is no longer a single operation.

[0170] 3. The conventional CXL switch chip routing lookup method needs to be based on fixed routing keys: BDF (ID routing) + Memory address (address routing). The application uses the routing key of target grain ID + in-chip address offset.

[0171] 4. The routing information of the conventional CXL switch chip routing lookup method is dynamically configured by the system BIOS (Basic Input Output System) / OS (Operating System) during enumeration, while the grain information in the routing information of the application is semi-statically configured (ROM) during chip design.

[0172] Embodiment 3

[0173] As shown in Figure 6 , the processing flow of the CXL message in the CXL switch grain is as follows:

[0174] 1. After the other CXL devices / CXL switch grains send the message into the CXL switch grain, the CXL switch grain port parses the message type and BDF information;

[0175] 2. The D2D routing layer of the CXL switch grain port converts the related message type and binds the VC ID;

[0176] 3. The DID of the message is obtained through the routing table lookup, the DID is encapsulated into the CXL message, and the message is further sent to the corresponding multi-VC on-chip CXL switch network for ordered or unordered switching;

[0177] 4. The ordered switching VC realizes the dedicated buffer for each message type, and strictly performs message switching according to the protocol rules that must be crossed or cannot be crossed between different types;

[0178] 5. The unordered switching VC realizes the common buffer for all message types, and performs message switching according to the fair polling rule;

[0179] 6. After the message is forwarded to the corresponding CXL port / D2D port, the port type is judged;

[0180] 7. If the port type is a D2D port, the original CXL message after stripping is sent to the next CXL switch chiplet. After receiving the message, the next CXL switch chiplet re-executes the processes of parsing, conversion, table lookup, and switching;

[0181] 8. If the port type is a CXL port, it is judged whether the highest bit of the 11th byte of the message header is '1'. If yes, UIO to NUIO type conversion is performed, and the Type field of the message is rewritten. Otherwise, the CXL message content remains unchanged, and the message is sent to other CXL devices.

[0182] Embodiment 4

[0183] Based on the cross-chiplet routing and switching method described in the present application, a variety of multi-chiplet architecture CXL switch chips based on chiplet technology can be constructed. Each chiplet is designed with a unified specification, including the same size, interface, and functional modules, ensuring high compatibility and reusability. For example, a 2-chiplet structure (at most 1 hop between chiplets) CXL switch chip architecture includes CXL switch chiplet 0 and CXL switch chiplet 1, as shown in Figure 7 .

[0184] For example, a 3-chiplet structure (at most 2 hops between chiplets) CXL switch chip architecture includes CXL switch chiplet 0, CXL switch chiplet 1, and CXL switch chiplet 2, as shown in Figure 8 .

[0185] See Figure 9 , according to the method of the present application, a 4-chiplet architecture PCIe architecture with at most 3 hops between chiplets is constructed, including CXL switch chiplet 0, CXL switch chiplet 1, CXL switch chiplet 2, and CXL switch chiplet 3.

[0186] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A CXL switching chip with a multi-core architecture, characterized in that, include: Multiple CXL switching cores of uniform specifications are interconnected through packaging to form a CXL switching chip; Each CXL switch core contains several ports, and each port can be configured as follows: CXL mode is used for interconnecting the CXL switching chip with other CXL switching chips or CXL devices; D2D mode is used for interconnection between CXL switching chips within the CXL switching chip; Each CXL switch core has at least the following ports: Physical layer: Shared by CXL mode and D2D mode, responsible for the physical connection between multiple CXL switching chips and between individual CXL switching cores within a single CXL switching chip; CXL Link Layer: Shared by CXL mode and D2D mode, it is responsible for handling the encapsulation of CXL data frames, error detection and correction, and flow control mechanisms; CXL Transaction Layer: Implemented according to the standard CXL protocol specification, responsible for parsing CXL transaction layer message types and obtaining message attributes; D2D Routing Layer: Responsible for implementing D2D message type conversion, encapsulation of routing information and VC ID number, and reverse parsing and stripping of D2D routing information; Bypass: If the port mode is CXL mode, the transaction layer message will be bypassed and directly passed through to the multi-VC on-chip CXL switching network; Multiplexing module: responsible for selecting and distributing packets from the D2D routing layer and bypass output; The CXL switching chip also includes a multi-VC on-chip CXL switching network, which is responsible for implementing message switching; The multi-VC on-chip CXL switching network includes at least one order-preserving switching VC and one out-of-order switching VC; The order-preserving switching VC is responsible for order-preserving switching of messages; The out-of-order switching VC is responsible for out-of-order switching of messages; Messages distributed by the multiplexing module are divided into those requiring order preservation and those requiring order preservation and those requiring no order preservation and are distributed to out-of-order switching VCs in the multi-VC on-chip CXL switching network.

2. The CXL switching chip with a multi-core architecture according to claim 1, characterized in that: The D2D routing layer is configured as follows: The transaction layer messages parsed by the CXL transaction layer are type-converted, and the converted messages are bound to the corresponding switching VC; Specifically, message types that require ordered transmission are bound to the ordered switching VC, and message types that can be transmitted out of order are bound to the out-of-order switching VC.

3. The CXL switching chip with a multi-core architecture according to claim 2, characterized in that: The D2D routing layer is configured to perform type conversion, including: When the CXL.io message is in FLIT mode, and the message Type field is Cpl or CplD, and the RO field is equal to 1, a conversion from non-order-preserving I / O to order-preserving I / O is performed: If the Type field is Cpl, then change it to UIORdCpl; If the Type field is CplD, then change it to UIORdCplD; After the conversion is completed, a flag is set in the message header to indicate that the message has undergone type conversion.

4. The CXL switching chip with a multi-core architecture according to claim 1, characterized in that: The D2D routing layer is configured to implement cross-core routing, including: Add a set of sideband signals, DID, to the standard CXL message format; The D2D routing layer maintains a primary routing table and a secondary routing sub-table, which are used to perform a pipelined table lookup based on the BDF number in the packet to determine the destination DID of the packet.

5. A CXL switching chip with a multi-core architecture according to claim 4, characterized in that: The primary routing table includes route ID1, entry type, and destination CXL port or secondary routing table ID2. The table entry type is used to determine whether a message is routed locally or across kernels: If it is a local route, the destination DID is directly assigned to the port ID of the destination CXL port, and the secondary routing table lookup is skipped; If it is a cross-core routing, then it is necessary to further query the secondary routing sub-table indexed by the secondary routing table ID2.

6. The CXL switching chip with a multi-core architecture according to claim 5, characterized in that: The secondary routing sub-table is designed with a multi-storage structure to support parallel processing of multiple query requests; The secondary routing sub-table contains route ID2, D2D routing policy, and at least one destination D2D port; The D2D routing policy determines the strategy for selecting the egress port from the destination D2D port based on the VC ID bound to the packet. When a message is bound to a sequence-preserving switch (VC), a static routing strategy is used, and a preset destination D2D port is always selected. When a message is bound to an out-of-order switching VC, a dynamic routing strategy is adopted, which selects the destination D2D port based on its congestion status.

7. A CXL switching chip with a multi-core architecture according to claim 6, characterized in that: The dynamic routing strategy determines port congestion status by monitoring port credit information from the CXL link layer. When there is no congestion, an exit point is selected from the available destination D2D ports according to the round-robin algorithm.

8. The CXL switching chip with a multi-core architecture according to claim 1, characterized in that: After packaging, the CXL switching chips are interconnected through 2.5D or 3D integration technology to form a Mesh or Ring topology.

9. A cross-core routing and switching method based on the CXL switching chip with a multi-core architecture according to any one of claims 1 to 8, characterized in that, Includes the following steps: Receive CXL messages at the port of the CXL switching core; Parse the message type and BDF information of the CXL message; The message type to be converted is transformed at the D2D routing layer, and the message is bound to the VC ID; The packet DID is obtained by querying the routing table, and the DID is then encapsulated into the CXL packet. The encapsulated message is sent to the multi-VC on-chip CXL switching network for either ordered or out-of-order switching. Forward the exchanged message to the target port; If the target port is a D2D port, the original CXL message is sent to the next CXL switching core after stripping the DID information. If the target port is a CXL port, determine whether the message has undergone type conversion; if so, perform reverse type conversion to restore the original message type, and then send the message to the external CXL device; if not, keep the message content unchanged and send the message to other CXL devices.

10. The cross-core routing and switching method according to claim 9, characterized in that: The routing table lookup is performed using a phased pipeline approach, including: Phase 1: Extract the BDF number of the packet and query the first-level routing table to determine the entry type; if it is a local route, generate the DID directly. Second stage: If it is a cross-core routing, the BDF number is used to query the secondary routing sub-table, and the destination D2D port is determined according to the routing policy, thereby generating the DID; The third stage: merge the query results from the first and second stages to complete the encapsulation of the DID.

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