Pseudo-symmetrical circuit board stack compression method and circuit board

Abstract

The application discloses a pseudo-symmetrical circuit board stack pressing method and a circuit board. The pseudo-symmetrical circuit board stack pressing method comprises the following steps which are sequentially performed: taking a first core plate and a second core plate with a thickness ratio greater than or equal to 5; taking a first interlayer bonding plate; aligning and combining: sequentially aligning and combining the first core plate, the first interlayer bonding plate and the second core plate and then fusing and fixing; taking a second interlayer bonding plate with a thickness ratio of 0.7-1.3 to that of the first interlayer bonding plate, and the surface of the second interlayer bonding plate is provided with a copper layer; pressing and combining: taking a metal mold to be embedded to drive the first core plate and the second core plate to be conductive, and then pressing and fixing the second interlayer bonding plate, the first core plate, the first interlayer bonding plate and the second core plate. The core plate is constructed in layers and provided with a pseudo-symmetrical structure, the problem of serious plate warping during high-temperature pressing of an existing asymmetric stack circuit board is effectively solved, the flatness of the plate surface is controlled to be within 2 mm, and the product yield is greatly improved to 100%.

Description

Technical Field

[0001] This invention relates to the field of circuit board manufacturing technology, and in particular to a method for laminating and pressing symmetrical circuit boards, and circuit boards manufactured using the method for laminating and pressing symmetrical circuit boards. Background Technology

[0002] With the rapid development of electronic information technology towards high-density integration and high-performance computing, printed circuit boards (PCBs), as the core carriers of electronic components, are experiencing continuous increases in structural complexity and functional integration. Especially in high-end application areas such as data centers, cloud computing, industrial internet, artificial intelligence, 5G communications, and automotive electronics, asymmetric stacked single-sided laminated circuit boards have become core components of critical electronic devices in these fields due to their unique advantages in space utilization, signal transmission efficiency, and functional module integration. For example, in AI servers, asymmetric stacked circuit boards achieve efficient heat dissipation through single-sided laminated metal heat sink modules, ensuring the stability of chips under high load operation; in automotive electronic control units, asymmetric stacked circuit boards meet the separation requirements of sensor signals and power lines through asymmetric interlayer design, while integrating conductive modules to achieve rapid circuit conduction.

[0003] However, the current manufacturing process of such asymmetric laminated single-sided circuit boards faces a long-standing industry-wide technical challenge: severe board warpage during the high-temperature lamination process. The typical structure of existing asymmetric laminated circuit boards features a combination of prepreg and copper foil on one side of the core board. During the high-temperature lamination process (typically 180-220°C), the resin in the prepreg undergoes viscous flow and gradually solidifies, while the fiberglass cloth of the prepreg shrinks due to heat. Because the shrinkage stress from the resin and fiberglass in the PP layer on one side cannot be balanced by the structure on the opposite side, the circuit board warps significantly towards the side without the asymmetric prepreg. While the normal warpage of traditional symmetrical laminated circuit boards can generally be controlled within 2mm, actual production data shows that the warpage of such asymmetric laminated circuit boards after lamination can reach over 10mm, far exceeding the allowable tolerances for subsequent production processes, such as laser drilling requiring a board surface flatness of ≤3mm and circuit etching requiring ≤2mm. Furthermore, the board warping issue has triggered a series of chain production problems: First, during lamination and subsequent processes such as drilling and electroplating, severely warped boards are prone to getting stuck in the transmission mechanism or positioning fixtures of production equipment; Second, warping deformation prevents the board from fitting tightly with production fixtures such as the positioning platform of a laser drilling machine or the conductive rollers of an electroplating tank, resulting in frequent problems such as laser drilling position deviation, uneven electroplating thickness, and short circuits / open circuits in circuit etching. Industry practice shows that the production yield of traditional asymmetric stacked circuit boards is almost 0%; Third, in high-power density applications, where metal modules such as T-shaped copper blocks or heat sinks need to be embedded on one side, board warping and unevenness of the metal module surface will further aggravate the stress concentration at the connection point. During high-temperature lamination, the warped board forces the contact surface between the metal module and the core board to have local gaps or excessive compression, ultimately leading to micro-cracks at the connection point between the metal block and the core board, which seriously affects the electrical connection reliability and mechanical structure stability of the product. Summary of the Invention

[0004] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a method for laminating a symmetrical circuit board, which constructs the core board in layers and sets up a symmetrical structure, effectively solving the serious board warping problem during high-temperature lamination of existing asymmetrical laminated circuit boards, controlling the board surface flatness within 2mm, significantly improving the product yield to 100%, eliminating the risk of equipment jamming and damage, ensuring the stable connection of metal modules, and reducing production costs and safety hazards.

[0005] The present invention also proposes a circuit board manufactured using the above-described pseudo-symmetric circuit board stacking and lamination method.

[0006] The method for laminating a pseudo-symmetrical circuit board according to the present invention includes the following steps:

[0007] Core board: Take a first core board and a second core board, the thickness ratio of the first core board to the second core board is greater than or equal to 5, the first core board is provided with a first mounting groove, and the second core board is provided with a second mounting groove corresponding to the first mounting groove;

[0008] Remove the inner bonding plate: Remove the first interlayer bonding plate, which is provided with a third mounting groove;

[0009] Alignment assembly: After taking the core board and the bonding board, the first core board, the first interlayer bonding board and the second core board are stacked in sequence to drive the first mounting groove, the second mounting groove and the third mounting groove to align, and then the first core board, the first interlayer bonding board and the second core board are fused and fixed.

[0010] Take an outer bonding plate: Take a second interlayer bonding plate, the thickness ratio of the second interlayer bonding plate to the first interlayer bonding plate is between 0.7 and 1.3, and a copper layer is provided on the surface of the second interlayer bonding plate;

[0011] Press-fit assembly: After alignment and assembly and removal of the outer bonding plate, the metal module is removed and embedded into the first mounting groove, the second mounting groove and the third mounting groove to drive the first core board and the second core board to conduct electricity; the second interlayer bonding plate is stacked on the side of the first core board away from the first interlayer bonding plate, and the copper layer is driven to be located on the side of the second interlayer bonding plate away from the first core board; then the second interlayer bonding plate, the first core board, the first interlayer bonding plate and the second core board are pressed and fixed.

[0012] The pseudo-symmetrical circuit board stacking and lamination method of the present invention has at least the following beneficial effects: By selecting a first core board with a thickness ratio ≥ 5 as the main bearing layer and a second core board as an auxiliary layer, and setting corresponding first and second mounting slots in both, and combining them with a first interlayer adhesive board with a third mounting slot, the metal module is then embedded in the three-layer slot to achieve core board conductivity. At the same time, a second interlayer adhesive board with a thickness ratio of 0.7 to 1.3 and configured with a copper layer is stacked to form a pseudo-symmetrical structure of "thick central core board + symmetrical adhesive layer + metal module integration". Furthermore, the overall shrinkage force can be balanced during high-temperature lamination, and the board warpage is strictly controlled to ≤ 2 mm, solving the technical problem of warpage of more than 10 mm in traditional methods. At the same time, it ensures the reliable connection between the metal module and the core board, improves the electrical connection stability and product yield, and provides a reliable manufacturing method for the core circuit boards of high power density and high integration electronic devices.

[0013] According to the pseudo-symmetric circuit board stacking method of the present invention, the thickness ratio of the copper layer to the second core board is between 0.35 and 1.05.

[0014] According to the pseudo-symmetric circuit board stacking method of the present invention, the thickness ratio of the copper layer to the second core board is 1, and the thickness ratio of the second interlayer bonding plate to the first interlayer bonding plate is 1.

[0015] According to the pseudo-symmetric circuit board stacking method of the present invention, the surface of the first core board has a first circuit layer, and the surface of the second core board has a second circuit layer. During alignment and assembly, the first circuit layer and the second circuit layer are arranged back to back.

[0016] The method for laminating a pseudo-symmetrical circuit board according to the present invention further includes the following steps: surface circuit processing: after lamination assembly, the copper layer is processed to drive the copper layer to conduct electricity with the first core board.

[0017] The method for laminating a pseudo-symmetrical circuit board according to the present invention further includes the following steps: pressing film: during or after lamination assembly, pressing a dry film onto the surface of the second core board away from the first interlayer bonding plate to cover the second core board.

[0018] The method for laminating a pseudo-symmetrical circuit board according to the present invention further includes the following steps: alignment grooves: before alignment and assembly, the first core board, the first interlayer bonding board and the second core board are stacked and aligned, and the first mounting groove, the second mounting groove and the third mounting groove are processed simultaneously.

[0019] According to the symmetrical circuit board stacking method of the present invention, the metal module is provided with an alignment protrusion on the side away from the second core board; it also includes the following steps: alignment processing: before the pressing assembly, an alignment blind hole is processed on the side of the second interlayer bonding plate away from the copper layer, and the shape of the alignment blind hole matches the shape of the alignment protrusion.

[0020] The circuit board according to the present invention is manufactured using the pseudo-symmetric circuit board stacking and lamination method described in the present invention.

[0021] The circuit board according to the present invention has at least the following beneficial effects: during the high-temperature pressing process, due to the stress balance characteristics of the pseudo-symmetrical stacked structure, the board warpage is strictly controlled within 2mm, solving the industry problem that traditional asymmetrical stacked products cannot be produced normally; at the same time, by embedding metal modules, layered circuit layout and circuit protection, it meets the comprehensive requirements of complex electronic devices for signal integrity, heat dissipation efficiency, electrical performance, mechanical connection stability and production yield, and has wide applicability. While improving product performance, it reduces production costs and equipment safety hazards, and is the core technical solution to solve the manufacturing problem of asymmetrical stacked circuit boards.

[0022] According to the circuit board of the present invention, the thickness of the copper layer is 0.1 mm; the thickness of the second interlayer bonding board is 0.2 mm; the thickness of the first core board is 1.0 mm; the thickness of the first interlayer bonding board is 0.2 mm; and the thickness of the second core board is 0.1 mm.

[0023] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0025] Figure 1 This is a schematic diagram of the simulated symmetrical circuit board stacked structure according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a simulated symmetrical circuit board stacked structure according to another embodiment of the present invention;

[0027] Figure 3 This is an exploded view of a pseudo-symmetrical circuit board stacked structure according to another embodiment of the present invention;

[0028] Figure 4 This is a flowchart of the simulated symmetrical circuit board stacking and lamination method according to an embodiment of the present invention.

[0029] Explanation of icon numbers:

[0030] First core board 100; First mounting slot 101; First circuit layer 110;

[0031] First interlayer bonding plate 200; Third mounting groove 201;

[0032] Second interlayer bonding plate 300; Through hole 301; Alignment blind hole 302; Copper layer 310;

[0033] Second core board 400; Second mounting slot 401; Second circuit layer 410;

[0034] Metal module 500; Alignment protrusion 510;

[0035] Dry film 600. Detailed Implementation

[0036] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0037] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0038] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0039] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0040] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0041] With the rapid development of electronic information technology towards high-density integration and high-performance computing, printed circuit boards (PCBs), as the core carriers of electronic components, are experiencing continuous increases in structural complexity and functional integration. Especially in high-end application areas such as data centers, cloud computing, industrial internet, artificial intelligence, 5G communications, and automotive electronics, asymmetric stacked single-sided laminated circuit boards have become core components of critical electronic devices in these fields due to their unique advantages in space utilization, signal transmission efficiency, and functional module integration. For example, in AI servers, asymmetric stacked circuit boards achieve efficient heat dissipation through single-sided laminated metal heat sink modules, ensuring the stability of chips under high load operation; in automotive electronic control units, asymmetric stacked circuit boards meet the separation requirements of sensor signals and power lines through asymmetric interlayer design, while integrating conductive modules to achieve rapid circuit conduction.

[0042] However, the current manufacturing process of such asymmetric laminated single-sided circuit boards faces a long-standing industry-wide technical challenge: severe board warpage during the high-temperature lamination process. The typical structure of existing asymmetric laminated circuit boards features a combination of prepreg and copper foil on one side of the core board. During the high-temperature lamination process (typically 180-220°C), the resin in the prepreg undergoes viscous flow and gradually solidifies, while the fiberglass cloth of the prepreg shrinks due to heat. Because the shrinkage stress from the resin and fiberglass in the PP layer on one side cannot be balanced by the structure on the opposite side, the circuit board warps significantly towards the side without the asymmetric prepreg. While the normal warpage of traditional symmetrical laminated circuit boards can generally be controlled within 2mm, actual production data shows that the warpage of such asymmetric laminated circuit boards after lamination can reach over 10mm, far exceeding the allowable tolerances for subsequent production processes, such as laser drilling requiring a board surface flatness of ≤3mm and circuit etching requiring ≤2mm. Furthermore, the board warping issue has triggered a series of chain production problems: First, during lamination and subsequent processes such as drilling and electroplating, severely warped boards are prone to getting stuck in the transmission mechanism or positioning fixtures of production equipment; Second, warping deformation prevents the board from fitting tightly with production fixtures such as the positioning platform of a laser drilling machine or the conductive rollers of an electroplating tank, resulting in frequent problems such as laser drilling position deviation, uneven electroplating thickness, and short circuits / open circuits in circuit etching. Industry practice shows that the production yield of traditional asymmetric stacked circuit boards is almost 0%; Third, in high-power density applications, where metal modules such as T-shaped copper blocks or heat sinks need to be embedded on one side, board warping and unevenness of the metal module surface will further aggravate the stress concentration at the connection point. During high-temperature lamination, the warped board forces the contact surface between the metal module and the core board to have local gaps or excessive compression, ultimately leading to micro-cracks at the connection point between the metal block and the core board, which seriously affects the electrical connection reliability and mechanical structure stability of the product.

[0043] Therefore, such as Figure 1As shown, the pseudo-symmetrical circuit board stacked structure proposed in this invention includes a first core board 100, a second core board 400, a metal module 500, a first interlayer bonding plate 200, and a second interlayer bonding plate 300. The first interlayer bonding plate 200 and the second interlayer bonding plate 300 are respectively arranged on both sides of the first core board 100. Specifically, the thickness ratio of the first interlayer bonding plate 200 to the second interlayer bonding plate 300 is between 0.7 and 1.3. Furthermore, the second core board 400 is located on the side of the first interlayer bonding plate 200 opposite to the first core board 100, and the thickness of the second core board 400 is less than the thickness of the first core board 100. Further, the metal module 500 is embedded in the first core board 100 and the second core board 400 to drive the first core board 100 and the second core board 400 to communicate. It should be noted that, with the thicker first core board 100 as the center, a first interlayer bonding plate 200 and a second interlayer bonding plate 300 with a thickness ratio of 0.7 to 1.3 are symmetrically arranged on both sides. A metal module 500 is embedded in the first core board 100 and the second core board 400 to achieve communication. Through the collaborative design of "central symmetry + material matching + stress balance", the shrinkage stress of the single-sided PP resin in the traditional asymmetric stacked structure is transformed into a double-sided symmetrical distribution, so that the shrinkage forces on the upper and lower sides cancel each other out during high-temperature pressing, fundamentally solving the pressing problem of asymmetric stacked circuit boards. Addressing the industry challenge of board warpage exceeding 10mm after assembly, this design strictly controls board warpage to within 2mm, ensuring the board's flatness meets the precision requirements of subsequent critical processes such as laser drilling, electroplating, and circuit etching. Secondly, this structure provides an integrated foundation for embedded metal modules 500, such as T-shaped copper blocks and heat sinks. Relying on the stress balance characteristics of the pseudo-symmetrical stacked structure, it avoids the risk of cracks caused by unevenness at the connection between the metal module 500 and the core board, ensuring a reliable connection between the metal module 500 and the circuit board, and improving the electrical connection stability and structural integrity of the product.

[0044] Optionally, the thickness ratio of the first core board 100 to the second core board 400 is greater than or equal to 8, which significantly enhances the "thick center" structural characteristics with the first core board 100 as the core. This allows the first core board 100 to serve as the main load-bearing layer, providing the main structural rigidity and stress balance foundation, while the thinner second core board 400 serves as an auxiliary layer to adapt to specific functional requirements, such as local circuit layout or lightweight design. In some embodiments of the present invention, the thickness ratio of the first core board 100 to the thickness of the second core board 400 is equal to 10. In this case, the first core board 100, with a thickness ten times that of the second core board 400, becomes the main stress-bearing layer of the stack. Its larger volume and mass effectively absorb and disperse the bidirectional stress generated by the viscous flow of the prepreg resin and the shrinkage of the glass fiber during high-temperature pressing, avoiding stress concentration in a single direction. Meanwhile, the extremely thin second core board 400 precisely adapts to local functional integration needs, such as small signal lines or specific connection positions. Without significantly increasing the overall stack thickness, through its synergistic effect with the first core board 100 and the stress balance design of the symmetrical interlayer bonding plate, board warpage is controlled to an extremely low level. In experiments, this ratio is particularly suitable for scenarios with extremely high structural rigidity requirements and the need to embed large-size metal modules 500, ensuring a tight fit between the metal module 500 and the core board contact surface, avoiding local gaps or excessive compression caused by warpage, thereby ensuring the reliability of electrical connections and the stability of the mechanical structure.

[0045] Refer to Figure 1In some embodiments of the present invention, a copper layer 310 is provided on the side of the second interlayer bonding plate 300 opposite to the first core board 100. The second interlayer bonding plate 300 is provided with a through hole 301 to coat copper in the through hole 301 to connect the copper layer 310 and the first core board 100. On the one hand, the copper layer 310 serves as the surface layer of the circuit board, expanding the signal transmission path and functional integration capability of the circuit board; on the other hand, the symmetrical arrangement of the copper layer 310 relative to the second core board 400 with the first core board 100 as the center further optimizes the stress balance characteristics of the stacked structure. For example, the thickness ratio of the copper layer 310 to the second core board 400 is between 0.35 and 1.05, which further balances the distribution of shrinkage stress in each layer of the stack, ensuring that the deformation of the copper layer 310 and the second core board 400 is coordinated during high-temperature pressing, and finally strictly controlling the board warpage to ≤2mm. At the same time, it ensures the precision of circuit etching, avoids uneven etching due to excessive thickness of the copper layer 310, and improves the product yield. In some embodiments of the present invention, the thickness ratio of the copper layer 310 to the second core board 400 is 1, and the thickness ratio of the second interlayer bonding plate 300 to the first interlayer bonding plate 200 is 1, achieving a completely symmetrical match. This ensures that the differences in physical properties such as the coefficient of thermal expansion and resin shrinkage rate of the overall structure are minimized during high-temperature pressing, avoiding local stress concentration caused by thickness imbalance. It should be noted that this specific ratio combination fundamentally eliminates the defect of unbalanced shrinkage stress of the single-sided semi-cured layer in traditional asymmetrical stacking, strictly controlling the board warpage to ≤2mm, while ensuring zero-gap bonding between the metal module 500 and the core board connection position, greatly improving the reliability of electrical connection and the stability of mechanical structure, and achieving a product yield of 100%.

[0046] Refer to Figure 2 and Figure 3 In some embodiments of the present invention, the first core board 100 has a first wiring layer 110 on the side facing the second interlayer bonding board 300. The first wiring layer 110 and the copper layer 310 are connected by copper in a via 301. For example, copper is plated in the via 301 through a copper plating process, thus constructing a complete vertical interconnect channel to meet the needs of multi-level signal transmission in complex circuit designs. Furthermore, the second core board 400 has a second wiring layer 410 on the side facing away from the first interlayer bonding board 200, expanding the multi-level functional layout capability of the stacked structure. The second wiring layer 410 can be designed as a signal line, power line, or ground line according to actual needs, meeting the multi-level signal transmission requirements of complex electronic devices, solving the board warping problem while improving the functional density and design flexibility of the product.

[0047] It should be noted that in the above thickness ratio relationships, the thickness of the second interlayer bonding board 300 does not include the thickness of the copper layer 310, and the thickness of the second core board 400 includes the thickness of the second circuit layer 410. Taking the thickness ratio of the copper layer 310 to the second core board 400 as 1, and the thickness ratio of the second interlayer bonding board 300 to the first interlayer bonding board 200 as 1, the specific thickness application can be as follows:

[0048] The thickness of copper layer 310 is 0.1 mm;

[0049] The thickness of the second interlayer bonding board 300 is 0.2mm;

[0050] The thickness of the first core board 100 is 1.0 mm, including the thickness of the insulation board and the thickness of the first circuit layer 110;

[0051] The thickness of the first interlayer bonding board 200 is 0.2 mm;

[0052] The thickness of the second core board 400 is 0.1mm, including the thickness of the insulation board and the second circuit layer 410.

[0053] In specific design applications, the existing single-sided asymmetrical stacked structure consists of a 1.3mm thick core board + a 0.2mm thick PP board + a 0.1mm thick copper foil. Accordingly, a first interlayer bonding board 200 and a second core board 400 are designed based on the 0.2mm thick PP board + 0.1mm thick copper foil. The 1.3mm thick core board is then split into a 1.0mm thick first core board 100 + a 0.2mm thick first interlayer bonding board 200 + a 0.1mm thick second core board 400. A second interlayer bonding board 300 with the same thickness as the first interlayer bonding board 200 is selected, and a copper layer 310 with the same thickness as the second core board 400 is plated onto the second interlayer bonding board 300.

[0054] After lamination, key processes such as laser drilling, electroplating, and line etching can be performed on the copper layer 310 to manufacture the circuit board circuit.

[0055] Furthermore, in some embodiments of the present invention, such as Figure 2 As shown, a dry film 600 is disposed on the surface of the second core board 400 to protect the second circuit layer 410. Covering the surface of the second circuit layer 410 with a dry film 600, such as photoresist or a protective film, effectively isolates it from subsequent processing steps, such as electroplating, etching, and mechanical drilling, by chemical solutions, particulate contamination, or physical scratches, preventing short circuits, open circuits, or uneven plating in the second circuit layer 410. Furthermore, the dry film 600 also protects the copper surface of the metal module 500 from damage.

[0056] The circuit board according to an embodiment of the present invention includes a pseudo-symmetric circuit board stacked structure according to an embodiment of the present invention.

[0057] The circuit board according to embodiments of the present invention, by adopting the pseudo-symmetrical circuit board stacked structure of the present invention, achieves strict control of board warpage within 2mm during high-temperature pressing due to the stress balance characteristics of the pseudo-symmetrical stacked structure, thus solving the industry problem that traditional asymmetrical stacked products cannot be produced normally. At the same time, by embedding metal modules 500, layered circuit layout and circuit protection, it meets the comprehensive requirements of complex electronic devices for signal integrity, heat dissipation efficiency, electrical performance, mechanical connection stability and production yield, and has wide applicability. While improving product performance, it reduces production costs and equipment safety hazards, and is the core technical solution to solve the manufacturing problems of asymmetrical stacked circuit boards.

[0058] Furthermore, a method for laminating and stacking pseudo-symmetrical circuit boards to fabricate the aforementioned circuit boards is proposed, referring to... Figure 4 This includes the following steps:

[0059] S100, Core board: Take a first core board 100 and a second core board 400. The thickness ratio of the first core board 100 to the second core board 400 is greater than or equal to 5. The first core board 100 is provided with a first mounting groove 101, and the second core board 400 is provided with a second mounting groove 401 corresponding to the first mounting groove 101.

[0060] S200, Take the inner bonding plate: Take the first interlayer bonding plate 200, which is provided with a third mounting groove 201;

[0061] S300, Alignment and Assembly: After taking the core board and the bonding board, the first core board 100, the first interlayer bonding board 200 and the second core board 400 are stacked in sequence to drive the first mounting groove 101, the second mounting groove 401 and the third mounting groove 201 to align, and then the first core board 100, the first interlayer bonding board 200 and the second core board 400 are fused and fixed.

[0062] S400, Take the outer bonding plate: Take the second interlayer bonding plate 300, the thickness ratio of the second interlayer bonding plate 300 to the first interlayer bonding plate 200 is between 0.7 and 1.3, and the surface of the second interlayer bonding plate 300 is provided with a copper layer 310.

[0063] S500, Pressing Assembly: After aligning the assembly and removing the outer bonding plate, take out the metal module 500 and embed the metal module 500 into the first mounting groove 101, the second mounting groove 401 and the third mounting groove 201 to drive the first core board 100 and the second core board 400 to conduct electricity; the second interlayer bonding plate 300 is stacked on the side of the first core board 100 away from the first interlayer bonding plate 200, and the copper layer 310 is driven to be located on the side of the second interlayer bonding plate 300 away from the first core board 100; then press and fix the second interlayer bonding plate 300, the first core board 100, the first interlayer bonding plate 200 and the second core board 400.

[0064] To address this, a first core board 100 with a thickness ratio ≥ 5 is selected as the main bearing layer, and a second core board 400 is selected as the auxiliary layer. Corresponding first mounting grooves 101 and second mounting grooves 401 are set in both. Combined with a first interlayer bonding plate 200 with a third mounting groove 201, a metal module 500 is embedded in the three-layer groove to achieve core board conductivity. At the same time, a second interlayer bonding plate 300 with a thickness ratio of 0.7 to 1.3 and equipped with a copper layer 310 is stacked to form a pseudo-symmetrical structure of "thick central core board + symmetrical bonding layer + metal module 500 integration". This allows for balanced overall shrinkage force during high-temperature pressing, ultimately strictly controlling board warpage to ≤ 2 mm. This solves the technical problem of warpage exceeding 10 mm in traditional methods, while ensuring reliable connection between the metal module 500 and the core board, improving electrical connection stability and product yield. This provides a reliable manufacturing method for core circuit boards of high power density and high integration electronic devices.

[0065] It should be noted that, depending on the application scenario and design requirements, the thickness of the copper layer 310 is generally 1 oz to 6 oz, or 0.035 mm to 0.21 mm. Optionally, referring to the above structural description, the thickness ratio of the copper layer 310 to the second core board 400 is 0.35 to 1.05, the thickness ratio of the first core board 100 to the second core board 400 is equal to 10, the thickness ratio of the copper layer 310 to the second core board 400 is 1, and the thickness ratio of the second interlayer bonding plate 300 to the first interlayer bonding plate 200 is 1. The corresponding beneficial effects are as described above and will not be elaborated here.

[0066] In applications, the surface warpage of the laminated board is strictly controlled to ≤2mm, ensuring the precision requirements of subsequent processes and improving the electrical performance and manufacturing yield of the circuit board. For this, refer to... Figure 4 It also includes the following steps:

[0067] S600, Surface Circuit Processing: After lamination and assembly, circuit processing is performed on the copper layer 310 to enable conductivity between the copper layer 310 and the first core board 100. Circuit processing generally employs common procedures such as laser drilling and circuit etching, which will not be detailed here. It should be noted that performing circuit processing on the copper layer 310 after lamination and assembly achieves conductivity between the copper layer 310 and the first core board 100, constructing a complete surface signal transmission network and meeting the multi-layer signal interconnection requirements of high-density interconnect circuit boards.

[0068] Furthermore, it also includes the following steps:

[0069] S520, Lamination: During or after lamination assembly, a dry film 600 is pressed onto the surface of the second core board 400 facing away from the first interlayer bonding plate 200 to cover the second core board 400. The physical barrier effect of the dry film 600 effectively isolates the risks of chemical corrosion and mechanical scratches in subsequent circuit processing, ensuring the integrity of the surface pattern and superior electrical performance.

[0070] Furthermore, it includes the following steps:

[0071] S310, Alignment Grooves: Before alignment and assembly, the first core board 100, the first interlayer bonding board 200, and the second core board 400 are stacked and aligned, while simultaneously machining the first mounting groove 101, the second mounting groove 401, and the third mounting groove 201. It is understood that the precise alignment of the first core board 100, the first interlayer bonding board 200, and the second core board 400 ensures the spatial consistency of the mounting grooves, allowing the metal module 500 to be embedded into the grooves without deviation, forming a stable conductive structure. At the same time, pre-machining the grooves reduces material deformation interference during subsequent fusion and pressing processes, maintains the overall symmetry of the stack, strictly controls board warpage to ≤2mm, and ensures reliable connection between the metal module 500 and the core board, as well as the electrical performance of the circuit board.

[0072] Refer to Figure 3 and Figure 4 The metal module 500 has an alignment protrusion 510 on the side opposite to the second core plate 400.

[0073] Furthermore, it includes the following steps:

[0074] S510, Alignment Processing: Before lamination, alignment blind holes 302 are machined on the side of the second interlayer bonding plate 300 away from the copper layer 310. The shape of the alignment blind hole 302 matches the shape of the alignment protrusion 510, achieving precise alignment between the metal module 500 and the second interlayer bonding plate 300 before lamination. It can be understood that the precise matching of the geometry of the alignment protrusion 510 and the alignment blind hole 302 ensures accurate alignment of the metal module 500 when embedded in the mounting slot. On the one hand, this avoids localized stress concentration or connection failure caused by misalignment, reducing adjustment errors during lamination and better ensuring the stress balance of the stack during lamination. On the other hand, it ensures the accurate relative position of the metal module 500 and the second interlayer bonding plate 300, further improving the connection stability between the subsequent patterned circuitry of the copper layer 310 and the metal module 500, thereby enabling a more precise multi-layer circuit structure to be constructed in conjunction with the circuit layer of the core board.

[0075] Other components and operations of the pseudo-symmetric circuit board stacking and lamination method are known to those skilled in the art and will not be described in detail here.

[0076] The circuit board according to an embodiment of the present invention is manufactured using the above-described symmetrical circuit board stacking method. During the high-temperature pressing process, due to the stress balance characteristics of the symmetrical stacking, the board warpage is strictly controlled within 2mm, solving the industry problem of the inability to produce traditional asymmetrical stacked products normally. Simultaneously, by embedding metal modules 500, layered circuit layout, and circuit protection, it meets the comprehensive requirements of complex electronic devices for signal integrity, heat dissipation efficiency, electrical performance, mechanical connection stability, and production yield. It has wide applicability, improving product performance while reducing production costs and equipment safety hazards, and is a core technical solution for solving the manufacturing difficulties of asymmetrical stacked circuit boards.

[0077] Similarly, in the above thickness ratio relationship, the thickness of the second interlayer bonding plate 300 does not include the thickness of the copper layer 310, and the thickness of the second core board 400 includes the thickness of the second circuit layer 410. Taking the thickness ratio of the copper layer 310 to the second core board 400 as 1, and the thickness ratio of the second interlayer bonding plate 300 to the first interlayer bonding plate 200 as 1, the specific thickness application can be as follows:

[0078] The thickness of copper layer 310 is 0.1 mm;

[0079] The thickness of the second interlayer bonding board 300 is 0.2mm;

[0080] The thickness of the first core board 100 is 1.0 mm;

[0081] The thickness of the first interlayer bonding board 200 is 0.2 mm;

[0082] The thickness of the second core board 400 is 0.1mm.

[0083] The specific design application approach is as follows: The existing structure consists of a 1.3mm thick core board with a single-sided asymmetrical stack, a 0.2mm thick PP board on one side, and a 0.1mm thick copper foil. Based on this, a first interlayer bonding board 200 and a second core board 400 are designed corresponding to the 0.2mm thick PP board and the 0.1mm thick copper foil. The 1.3mm thick core board is then divided into a 1.0mm thick first core board 100, a 0.2mm thick first interlayer bonding board 200, and a 0.1mm thick second core board 400. A second interlayer bonding board 300 with the same thickness as the first interlayer bonding board 200 is selected, and a copper layer 310 with the same thickness as the second core board 400 is plated onto the second interlayer bonding board 300.

[0084] The other components and operation of the circuit board described above are known to those skilled in the art and will not be described in detail here.

[0085] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for laminating and stacking symmetrical circuit boards, characterized in that, Includes the following steps: Core board: Take a first core board and a second core board, the thickness ratio of the first core board to the second core board is greater than or equal to 5, the first core board is provided with a first mounting groove, and the second core board is provided with a second mounting groove corresponding to the first mounting groove; Remove the inner bonding plate: Remove the first interlayer bonding plate, which is provided with a third mounting groove; Alignment assembly: After taking the core board and the bonding board, the first core board, the first interlayer bonding board and the second core board are stacked in sequence to drive the first mounting groove, the second mounting groove and the third mounting groove to align, and then the first core board, the first interlayer bonding board and the second core board are fused and fixed. Take an outer bonding board: Take a second interlayer bonding board, the thickness ratio of the second interlayer bonding board to the first interlayer bonding board is 0.7 to 1.3, and a copper layer is provided on the surface of the second interlayer bonding board, the thickness ratio of the copper layer to the second core board is 0.35 to 1.05; Pressing assembly: After aligning the assembly and removing the outer bonding plate, remove the metal module and embed the metal module into the first mounting slot, the second mounting slot and the third mounting slot to drive the first core board and the second core board to conduct electricity; The second interlayer bonding plate is stacked on the side of the first core plate away from the first interlayer bonding plate, and the copper layer is driven to be located on the side of the second interlayer bonding plate away from the first core plate; then the second interlayer bonding plate, the first core plate, the first interlayer bonding plate and the second core plate are pressed and fixed.

2. The method for laminating and stacking pseudo-symmetrical circuit boards according to claim 1, characterized in that: The thickness ratio of the copper layer to the second core board is 1, and the thickness ratio of the second interlayer bonding plate to the first interlayer bonding plate is 1.

3. The method for laminating and stacking pseudo-symmetrical circuit boards according to claim 1, characterized in that: The surface of the first core board has a first circuit layer, and the surface of the second core board has a second circuit layer. During alignment and assembly, the first circuit layer and the second circuit layer are arranged back to back.

4. The method for laminating and stacking pseudo-symmetrical circuit boards according to claim 1, characterized in that: It also includes the following steps: Surface circuit processing: After lamination and assembly, the copper layer is processed to drive the copper layer to conduct electricity with the first core board.

5. The method for laminating and stacking pseudo-symmetrical circuit boards according to claim 1 or 4, characterized in that: It also includes the following steps: Pressing film: During or after pressing assembly, a dry film is pressed onto the surface of the second core board away from the first interlayer adhesive board to cover the second core board.

6. The method for laminating and stacking pseudo-symmetrical circuit boards according to claim 1, characterized in that: It also includes the following steps: Alignment slots: Before alignment and assembly, the first core board, the first interlayer bonding board and the second core board are stacked and aligned, and the first mounting slot, the second mounting slot and the third mounting slot are machined at the same time.

7. The method for laminating and stacking pseudo-symmetrical circuit boards according to claim 1, characterized in that: The metal module has an alignment protrusion on the side opposite to the second core board; It also includes the following steps: Alignment processing: Before lamination and assembly, alignment blind holes are processed on the side of the second interlayer bonding plate away from the copper layer, and the shape of the alignment blind holes matches the shape of the alignment protrusions.

8. A circuit board, characterized in that: It is manufactured using the pseudo-symmetric circuit board stacking and lamination method as described in any one of claims 1 to 7.

9. The circuit board according to claim 8, characterized in that: The thickness of the copper layer is 0.1 mm; The thickness of the second interlayer adhesive plate is 0.2 mm; The thickness of the first core board is 1.0 mm; The thickness of the first interlayer bonding plate is 0.2 mm; The thickness of the second core board is 0.1 mm.

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