Semiconductor device and method for forming interconnect structure using VFM and tcb

Abstract

A semiconductor device has a first substrate and a second substrate or an interconnect substrate, where an interconnect structure is formed between the first substrate and the second substrate or the interconnect substrate using a VFM signal in conjunction with heat and / or pressure. The interconnect structure may be a bump or a bump with a conductive pillar. A microwave source disposed near the first and second substrates generates a VFM signal. Heat and pressure may be applied to the interconnect structure while using the VFM signal. Heat or pressure may be applied to the interconnect structure while using the VFM signal. A non-conductive film may be formed around the interconnect structure between the first substrate and the second substrate. An epoxy resin and a flux material may be formed around the interconnect structure between the first substrate and the second substrate.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more specifically to a semiconductor device and method for forming interconnect structures using VFM and TCB. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Multiple semiconductor wafers or individual semiconductor dies can be stacked in a single semiconductor package, a process often referred to as 3D integration. Specifically, products such as integrated logic and memory circuits, sensor packages, and combined microelectromechanical systems (MEMS) utilize 3D integration to reduce form factor, improve performance, reduce power consumption, increase integration capacity, and lower costs.

[0004] Interconnect structures between stacked components in 3D integration (such as bumps and conductive pillars) are typically achieved through thermocompression bonding (TCB). TCB bonding utilizes heat and pressure to bond materials, typically thin films or layers. Heat softens the materials, and pressure forces them into close contact, allowing bonding to occur. However, interconnect structures can fail if heat and pressure are not distributed uniformly (potentially due to structural limitations). Heat and pressure can become uneven, especially for interconnect structures furthest from the heat source. Interconnect failure can cause stacked wafers or dies to tilt, slip, or warp, resulting in defects and reduced reliability. Attached Figure Description

[0005] Figures 1a-1f A semiconductor wafer with multiple semiconductor dies separated by saw marks is shown;

[0006] Figure 2a-2m The process of bonding a semiconductor wafer to an interconnect substrate using VFM and TCB is illustrated.

[0007] Figures 3a-3d This demonstrates another process for bonding semiconductor wafers to interconnect substrates using VFM and TCB;

[0008] Figures 4a-4d The process of bonding a first semiconductor wafer to a second semiconductor wafer using VFM and TCB is illustrated.

[0009] Figures 5a-5cThe process of combining multiple stacked semiconductor wafers using VFM and TCB is shown;

[0010] Figures 6a-6c This demonstrates another process that combines multiple stacked semiconductor wafers using VFM and TCB;

[0011] Figures 7a-7g This demonstrates another process for bonding multiple electrical components to an interconnect substrate using VFM and TCB;

[0012] Figures 8a-8e This demonstrates another process for integrating multiple electrical components onto a semiconductor wafer using VFM and TCB;

[0013] Figures 9a-9d This demonstrates another process for bonding electrical components to an interconnect substrate using VFM and TCB;

[0014] Figures 10a-10d This demonstrates another process for bonding an electrical component to another electrical component using VFM and TCB;

[0015] Figures 11a-11c The process of combining multiple stacked electrical components using VFM and TCB is shown;

[0016] Figures 12a-12c This demonstrates another process that combines multiple stacked electrical components using VFM and TCB;

[0017] Figure 13 A non-conductive film deposited between multiple stacked semiconductor wafers is shown;

[0018] Figure 14 The illustration shows an epoxy resin material deposited around an interconnect structure between multiple stacked semiconductor wafers; and

[0019] Figure 15 A printed circuit board (PCB) is shown, in which different types of packages are arranged on the surface of the PCB. Detailed Implementation

[0020] In the following description with reference to the figures, the invention is described by way of one or more embodiments, wherein the same numerals denote the same or similar elements. While the invention has been described in the best mode for carrying out its objectives, those skilled in the art will appreciate that the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, supported by the following disclosure and the accompanying drawings. The term “semiconductor die” as used herein refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0021] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components (such as transistors and diodes) have the ability to control the flow of current. Passive electrical components (such as capacitors, inductors, and resistors) create a relationship between the voltage and current necessary to perform the circuit function.

[0022] Back-end manufacturing refers to the process of dicing or singulating a completed wafer into individual semiconductor dies and packaging those dies for structural support, electrical interconnection, and environmental isolation. To singulate a semiconductor die, the wafer is scribed and broken along non-functional regions (called "scribing" or "cutting lines"). This dicing is done using laser cutting tools or saw blades. After singulation, the individual semiconductor dies are placed on a packaging substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to contact pads within the package. Electrical connections can be achieved using conductive layers, bumps, column bumps, conductive paste, or wire bonding. A sealant or other molding material is deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the functionality of the semiconductor device available to other system components.

[0023] Figure 1a A semiconductor wafer 100 with a base substrate material 102 is shown, which is, for example, silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials used for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by non-active inter-die regions or saw tracks 106. The saw tracks 106 provide dicing areas for monomerizing the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 is circular with a diameter of 100-450 millimeters (mm). The semiconductor wafer 100 may be rectangular (e.g.,...). Figure 1b (as shown in the image) or any other geometry.

[0024] Figure 1cA cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuitry. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0025] A conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as a contact pad for electrical connections to circuitry on the active surface 110.

[0026] exist Figure 1d In this process, conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, droplet plating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. Suitable attachment or bonding processes are used to bond the bump material to conductive layer 112. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 114. In one embodiment, bumps 114 are formed on under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Bumps 114 can also be compression bonded or thermo-pressed bonded to conductive layer 112. Bumps 114 represent an interconnect structure that can be formed on conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, columnar bumps, microbumps, or other electrical interconnects.

[0027] exist Figure 1e In this process, a saw blade or laser cutting tool 118 is used to monomerize a semiconductor wafer 100 into individual semiconductor dies 104 through a saw path 106. Individual semiconductor dies 104 can be inspected and electrically tested to identify dies or cells (KGD / KGU) that are known to be in good condition after monomerization.

[0028] In an alternative embodiment, the conductive layer 112 may extend through the substrate material 102 to the surface 108, such as Figure 1fAs shown. From Figure 1f The semiconductor chip 100 can be like Figure 1e It is monolithized like that.

[0029] Figure 2a-2m The process of bonding a semiconductor wafer to an interconnect substrate using VFM and TCB is shown. Figure 2a A cross-sectional view of an interconnect substrate or interposer 120 is shown, which includes one or more conductive layers 122 and one or more insulating layers 124. The conductive layers 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layers 122 may be formed using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. The conductive layers 122 provide horizontal electrical interconnects across the substrate 120 and vertical electrical interconnects between the top surface 126 and the bottom surface 128 of the substrate 120. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layers 122 may be electrically shared or electrically isolated. The insulating layer 124 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer 124 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. The insulating layer 124 provides isolation between the conductive layers 122. Multiple conductive layers, such as 122, separated by the insulating layer 124 may exist.

[0030] exist Figure 2b In the middle, using pick and place operations will bring from Figure 1d A semiconductor wafer 100 is disposed on surface 126 of interconnect substrate 120. As described herein, semiconductor wafer 100 may be a first substrate, and interconnect substrate 120 may be a second substrate. Similarly, as described herein, semiconductor wafer 100 may be a first electrical component, and interconnect substrate 120 may be a second electrical component. Flux material 130 is deposited on surface 126. Alternatively, flux 131 is deposited on bump 114, such as... Figure 2c As shown in the diagram, a semiconductor wafer 100 is attached to a heat press 132, and an interconnect substrate 120 is attached to a heat block 134. The heat press 132 applies heat and pressure to the semiconductor wafer 100. The heat block 134 applies heat to the interconnect substrate 120. The semiconductor wafer 100 and the interconnect substrate 120 are preheated by the heat press 132 and the heat block 134, respectively. Preheating activates the bumps 114 and the conductive layers 112 and 122.

[0031] exist Figure 2dIn this diagram, the semiconductor wafer 100 is aligned and in contact with the surface 126 of the substrate 120, as indicated by bonding assembly 135. The electrical and mechanical bonding process of bump 114 with conductive layers 112 and 122 may utilize three simultaneous operations. A hot press block 132 applies heat and pressure to the semiconductor wafer 100 to heat and compress bump 114, as indicated by indicator arrow 136. A hot block 134 applies heat to the interconnect substrate 120 to provide additional heat, as indicated by indicator arrow 138.

[0032] Importantly, heat and pressure are kept uniform across bump 114 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 114 and conductive layers 112 and 122. For this purpose, bonding assembly 135 is disposed within microwave source 140 to transmit variable frequency microwave (VFM) signals 142 to bump 114 and conductive layers 112 and 122, such as... Figure 2e As shown in the diagram. Microwave source 140 includes a magnetron 141 to generate and emit a VFM signal 142. In one embodiment, microwave source 140 may be a microwave oven capable of emitting heat-generating microwaves. In another embodiment, microwave source 140 is disposed on opposite sides of the coupling assembly 135. Microwave source 140 may be disposed on one side of the coupling assembly 135 or above or below the coupling assembly 135.

[0033] Microwave source 140 emits VFM signal 142 toward bump 114 and conductive layers 112 and 122. Figure 2f Further details are shown of the thermocompression indicator 136, thermal indicator 138, and VFM signal 142 surrounding the bump 114 and conductive layers 112 and 122. The thermocompression indicator 136 is used to conform materials to each other and adapt to any roughness or surface. The combination of heat and pressure promotes the diffusion of atoms or molecules across the interface, forming a strong bond. In the case of solder or adhesive layers, heat melts and flows these layers, filling gaps and creating a strong bond upon cooling. The thermal indicator 138 provides uniform heating (i.e., from the opposite direction) and precise temperature control.

[0034] The VFM signal 142 from microwave source 140 comprises electromagnetic radiation in a frequency range of 300 MHz to 300 GHz. In one embodiment, the frequency range is 4.0 GHz to 8.0 GHz, or preferably 5.7 GHz to 7.0 GHz. The VFM signal 142 changes frequency at 25 ms intervals to achieve a desired uniform thermo-pressure energy distribution. More specifically, the VFM signal 142 causes molecules to rotate without breaking their bonds. An electric field causes the electron cloud around the positively charged atomic nucleus to twist in the opposite direction to the field. The molecules with electrons then rotate in the direction of the electric field. When these rotating molecules collide with neighboring molecules, the energy from these collisions is converted into heat energy through friction. Flux 130, as a polar material, can be heated by the VFM signal 142. Similarly, bump 114 is heated and melted by the VFM signal 142. The temperature of flux 130 rises above the bump melting temperature and effectively dissolves and mixes with the molten bump material. It is worth noting that the semiconductor wafer 100 and the interconnect substrate 120 are not polar materials and remain unaffected by the VFM signal 142. Therefore, the temperature levels across the bumps 114 and the conductive layers 112 and 122 become uniform, and there is typically no metal arcing between the bumps and conductive layers. The VFM signal 142 enables a more efficient and uniform bonding between the bumps 114 and the conductive layers 112 and 122 in the presence of heat and / or pressure.

[0035] Figure 2g Another embodiment of a VFM signal 142 with a hot-press indicator 136 but without a heat indicator 138 is shown. In this embodiment, the hot-press block 132 and the VFM signal 142 are sources of heat and pressure that bind the bump 114 to the conductive layers 112 and 122.

[0036] Figure 2h Another embodiment of a VFM signal 142 with a thermal indicator 138 but without a thermal pressure indicator 136 is shown. In this embodiment, the hot spot 134 and the VFM signal 142 are heat sources that bind the bump 114 to the conductive layers 112 and 122.

[0037] Figure 2i Another embodiment of the VFM signal 142 is shown without the hot-press indicator 136 and without the heat indicator 138. In this embodiment, the VFM signal 142 is a horizontal heat source that bonds the bump 114 to the conductive layers 112 and 122. The hot-press indicator 136 and the heat indicator 138 are used to preheat the bonding assembly 135.

[0038] Figure 2jAnother embodiment of the VFM signal 143 without the hot-press indicator 136 and the heat indicator 138 is shown. In this embodiment, the VFM signal 143 is a vertical heat source that bonds the bump 114 to the conductive layers 112 and 122. The hot-press indicator 136 and the heat indicator 138 are used to preheat the bonding assembly 135.

[0039] Figure 2k Another embodiment of the VFM signal without the hot-press indicator 136 and the heat indicator 138 is shown. In this embodiment, magnetron 141 generates VFM signal 142, and magnetron 145 generates VFM signal 147 of a different frequency and / or out of phase with respect to VFM signal 142. VFM signals 142 and 147 are heat sources for bonding bump 114 to conductive layers 112 and 122. The hot-press indicator 136 and the heat indicator 138 are used to preheat the bonding assembly 135.

[0040] in any case, Figure 2l A semiconductor wafer 100 is shown bonded to an interconnect substrate 120 as a semiconductor package 148, wherein a combination of a hot press block 132, a hot block 134 and a microwave source 140, or a microwave source 140 having a hot press block 132 or a hot block 134, or a microwave source 140 without a hot press block 132 and a hot block 134, is used to electrically and mechanically connect bumps 114 between conductive layers 112 and 122 to achieve a uniform hot press distribution. Figure 2m A semiconductor package 148 is shown outside the assembly 135, in which bumps 114 are electrically and mechanically connected between conductive layers 112 and 122.

[0041] The combination of semiconductor wafer 100 and interconnect substrate 120 represents semiconductor package 148. Semiconductor wafer 100 and interconnect substrate 120 have improved interconnect bonding, wherein bumps 114 are electrically and mechanically connected between conductive layers 112 using a combination of thermopressors 132, heat blocks 134, and microwave sources 140, or microwave sources 140 having either thermopressors 132 or heat blocks 134, or microwave sources 140 without either thermopressors 132 or heat blocks 134, to achieve uniform thermopressed distribution and avoid tilting, slippage, and warping as mentioned in the prior art. The heat-generated VFM signal 142 does not heat semiconductor wafer 100 or interconnect substrate 120, therefore these structures do not warp. Volumetric heating characteristics enable efficient control of heat distribution.

[0042] In another embodiment, such as Figure 3a As shown, using pick and place operations will bring from Figure 1cA semiconductor wafer 100 is disposed on surface 126 of interconnect substrate 120. Components with similar functions are assigned the same reference numerals. A plurality of conductive pillars or bases 150 are formed on conductive layer 112. Similarly, a plurality of conductive pillars or bases 152 are formed on conductive layer 122. The conductive pillars 150 and 152 can be formed using photoresist layers deposited on semiconductor wafer 100 and interconnect substrate 120, respectively. The photoresist layers are patterned and etched according to the intended positions of the conductive pillars 150 and 152. Openings in the photoresist layers are filled with a conductive material, such as Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials, to form conductive pillars 150 and 152. Flux material 154 is deposited on conductive pillars 150 and 152.

[0043] From Figure 1c A semiconductor wafer 100 is attached to a heat press 132, and an interconnect substrate 120 is attached to a heat block 134. The heat press 132 applies heat and pressure to the semiconductor wafer 100. The heat block 134 applies heat to the interconnect substrate 120. The semiconductor wafer 100 and the interconnect substrate 120 are preheated by the heat press 132 and the heat block 134, respectively. Preheating activates the conductive pillars 150 and 152 and the conductive layers 112 and 122.

[0044] exist Figure 3b In this configuration, semiconductor wafer 100 is aligned with and brought toward interconnect substrate 120, with intermediate bump 156 contacting conductive posts 150 and 152, designated as bonding assembly 158. The electrical and mechanical bonding process of bump 156 with conductive posts 150 and 152 may utilize three simultaneous operations. A thermal block 132 applies heat and pressure to semiconductor wafer 100 to heat and compress bump 156, indicated by indicator arrow 136. A thermal block 134 applies heat to interconnect substrate 120 to provide additional heat, indicated by indicator arrow 138.

[0045] Importantly, heat and pressure are kept uniform across bump 156 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 156 and conductive posts 150 and 152. For this purpose, bonding assembly 158 is disposed within microwave source 140 to transmit VFM signal 142 to bump 156 and conductive posts 150 and 152. Figure 2e-2f After the discussion, Figure 3c More details are shown of the thermo-pressure indicator 136, the thermal indicator 138, and the VFM signal 142 around the bump 156 and the conductive posts 150 and 152.

[0046] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot indicator 138, or without either the hot pressure indicator 136 or the hot indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 3d The semiconductor wafer 100, which is incorporated into the interconnect substrate 120, is shown as a semiconductor package 159, wherein a combination of a hot press block 132, a hot block 134 and a microwave source 140, or a microwave source 140 having a hot press block 132 or a hot block 134, or a microwave source 140 without a hot press indicator 136 and a hot indicator 138, is used to electrically and mechanically connect bumps 156 between conductive posts 150 and 152, thereby achieving a uniform hot press distribution.

[0047] In another embodiment, such as Figure 4a As shown, a pick-and-place operation is used to place semiconductor wafer 160a onto semiconductor wafer 160b. This makes semiconductor wafer 160a similar to that from... Figure 1c The semiconductor wafer 100. This also makes the semiconductor wafer 160b similar to those from... Figure 1c The semiconductor wafer 100. As described herein, semiconductor wafer 160a may be a first substrate and semiconductor wafer 160b may be a second substrate. Similarly, as described herein, semiconductor wafer 160a may be a first electrical component and semiconductor wafer 160b may be a second electrical component.

[0048] A plurality of conductive pillars or bases 162 are formed on conductive layer 112a. Similarly, a plurality of conductive pillars or bases 164 are formed on conductive layer 112b. The conductive pillars 162 and 164 may be formed using photoresist layers deposited on semiconductor wafers 160a and 160b, respectively. The photoresist layers are patterned and etched according to the intended positions of the conductive pillars 162 and 164. Openings in the photoresist layers are filled with a conductive material, such as Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials, to form the conductive pillars 162 and 164. Flux material 165 is deposited on the conductive pillars 162 and 164.

[0049] Semiconductor wafer 160a is attached to hot press block 132, and semiconductor wafer 160b is attached to hot press block 134. Hot press block 132 applies heat and pressure to semiconductor wafer 160a. Hot press block 134 applies heat to semiconductor wafer 160b. Semiconductor wafers 160a and 160b are preheated by hot press block 132 and hot press block 134, respectively. Preheating activates conductive pillars 162 and 164 and conductive layers 112a and 112b.

[0050] exist Figure 4bIn this configuration, semiconductor wafer 160a is aligned with and brought toward semiconductor wafer 160b, with intermediate bump 166 contacting conductive posts 162 and 164, designated as bonding assembly 167. The electrical and mechanical bonding process of bump 166 to conductive posts 162 and 164 may utilize three simultaneous operations. A hot press block 132 applies heat and pressure to semiconductor wafer 160a to heat and compress bump 166, indicated by indicator arrow 136. A hot press block 134 applies heat to semiconductor wafer 160b to provide additional heat, indicated by indicator arrow 138.

[0051] Importantly, heat and pressure are kept uniform across bump 166 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 166 and conductive posts 162 and 164. For this purpose, bonding assembly 167 is disposed within microwave source 140 to transmit VFM signal 142 to bump 166 and conductive posts 162 and 164. Figure 2e-2f After the discussion, Figure 4c More details are shown of the hot pressure indicator 136, the thermal indicator 138, and the VFM signal 142 around the bump 166 and the conductive posts 162 and 164.

[0052] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot indicator 138, or without either the hot pressure indicator 136 or the hot indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 4d A semiconductor wafer 160a is shown incorporated into a semiconductor wafer 160b as a semiconductor package 168, wherein a combination of a hot press block 132, a hot block 134 and a microwave source 140, or a microwave source 140 having a hot press block 132 or a hot block 134, or a microwave source 140 without a hot press indicator 136 and a hot indicator 138, is used to electrically and mechanically connect bumps 166 between conductive posts 162 and 164, thereby achieving a uniform hot press distribution.

[0053] In another embodiment where multiple semiconductor wafers are stacked, such as Figure 5a As shown, pick-and-place operations are used to align and place semiconductor wafer 170a onto semiconductor wafer 170b, align and place semiconductor wafer 170b onto semiconductor wafer 170c, and align and place semiconductor wafer 170c onto semiconductor wafer 170d. This makes each of semiconductor wafers 170a, 170b, 170c, and 170d similar to those from... Figure 1fThe semiconductor wafer 100. Any number of semiconductor wafers 170 can be stacked, as shown. For example, 4 to 12 semiconductor wafers 170 can be stacked. As described herein, one of the semiconductor wafers 170a-170d can be a first substrate, and one of the semiconductor wafers 170a-170d can be a second substrate. Similarly, as described herein, one of the semiconductor wafers 170a-170d can be a first electrical component, and one of the semiconductor wafers 170a-170d can be a second electrical component.

[0054] Multiple bumps 172 are disposed between semiconductor wafers 170a and 170b, and between semiconductor wafers 170b and 170c, and between semiconductor wafers 170c and 170d, on a conductive layer such as 112. Flux material is deposited on the bumps 172, similar to... Figure 2c .

[0055] Semiconductor wafer 170a is attached to hot press block 132, and semiconductor wafer 170d is attached to hot block 134. Hot press block 132 applies heat and pressure to semiconductor wafers 170a-170d. Hot block 134 applies heat to semiconductor wafers 170a-170d. Semiconductor wafers 170a-170d are preheated by hot press block 132 and hot block 134.

[0056] Semiconductor wafers 170a-170d are disposed between a hot press block 132 and a hot block 134, with bump 172 contacting the conductive layer 112, designated as bonding assembly 174. The electrical and mechanical bonding process of bump 172 to the conductive layer 112 may utilize three simultaneous operations. The hot press block 132 applies heat and pressure to the semiconductor wafers 170a-170d to heat and compress the bump 172, indicated by indicator arrow 136. The hot block 134 applies heat to the semiconductor wafers 170a-170d to provide additional heat, indicated by indicator arrow 138.

[0057] Importantly, heat and pressure are kept uniform across bump 172 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 172 and conductive layer 112. For this purpose, bonding assembly 174 is disposed within microwave source 140 to transmit VFM signal 142 to bump 172 and conductive layer 112. Figure 2e-2f After the discussion, Figure 5b More details are shown of the hot pressure indicator 136, the thermal indicator 138, and the VFM signal 142 around the bump 166 and the conductive posts 162 and 164.

[0058] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot indicator 138, or without either the hot pressure indicator 136 or the hot indicator 138. Figure 2e-2kAs described in [the text]. In any case, Figure 5c The combined semiconductor wafers 170a-170d are shown, wherein a combination of hot press block 132, hot block 134 and microwave source 140, or microwave source 140 having hot press block 132 or hot block 134, or microwave source 140 without hot press indicator 136 and without hot indicator 138, is used to electrically and mechanically connect bump 172 between conductive layers 112, thereby achieving uniform hot press distribution.

[0059] Sealant or molding compound 176 is deposited on and around semiconductor wafers 170a-170d using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. Sealant 176 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers. Sealant 176 is non-conductive, provides structural support, and protects the semiconductor device from external components and contaminants in the environment.

[0060] Conductive bump material is deposited on the conductive layer 112 of the semiconductor wafer 170d using evaporation, electrolytic plating, electroless plating, droplet deposition, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 178. In one embodiment, bumps 178 are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. Bumps 178 can also be compression bonded or thermo-pressed bonded to the conductive layer 112. Bumps 178 represent an interconnect structure that can be formed on the conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, columnar bumps, microbumps, or other electrical interconnects.

[0061] The stacked semiconductor wafers 170a-170d, combined with sealant 176 and bumps 178, represent a semiconductor package 180. Semiconductor package 180 is particularly useful for high-bandwidth memory (HBM). The stacked semiconductor wafers 170a-170d have improved interconnect bonding, wherein bumps 172 are electrically and mechanically connected between conductive layers 112 using a combination of thermoplastic blocks 132, hot blocks 134, and microwave sources 140, or microwave sources 140 having either thermoplastic blocks 132 or hot blocks 134, or microwave sources 140 without thermoplastic blocks 132 or hot blocks 134, thereby achieving uniform thermoplastic distribution and avoiding tilting, slippage, and warping as mentioned in the background art. The heat-generated VFM signal 142 neither heats the semiconductor wafer 100 nor the interconnect substrate 120, so these structures do not melt. Volumetric heating characteristics enable efficient control of heat distribution.

[0062] In another embodiment where multiple semiconductor wafers are stacked, such as Figure 6a As shown, semiconductor wafer 190a is placed on semiconductor wafer 190b, semiconductor wafer 190b is placed on semiconductor wafer 190c, and semiconductor wafer 190c is placed on semiconductor wafer 190d using pick-and-place operations. This makes each of semiconductor wafers 190a, 190b, 190c, and 190d similar to those from... Figure 1f The semiconductor wafer 100. Any number of semiconductor wafers 190 can be stacked, as shown. For example, four to twelve semiconductor wafers 170 can be stacked. As described herein, one of the semiconductor wafers 190a-190d can be a first substrate, and one of the semiconductor wafers 190a-190d can be a second substrate. Similarly, as described herein, one of the semiconductor wafers 190a-190d can be a first electrical component, and one of the semiconductor wafers 190a-190d can be a second electrical component.

[0063] A plurality of conductive pillars or bases 192 are formed on the conductive layer 112 of semiconductor wafer 190a. Similarly, a plurality of conductive pillars or bases 194 are formed on the conductive layer 112 of semiconductor wafer 190b. The conductive pillars 192 and 194 can be formed using photoresist layers deposited on semiconductor wafers 190a and 190b, respectively. The photoresist layers are patterned and etched according to the intended positions of the conductive pillars 192 and 194. Openings in the photoresist layers are filled with a conductive material, such as Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials, to form the conductive pillars 192 and 194. Similar to... Figure 4a Flux material is deposited on conductive pillars 192 and 194.

[0064] Semiconductor wafer 190a is attached to hot press block 132, and semiconductor wafer 190d is attached to hot block 134. Hot press block 132 applies heat and pressure to semiconductor wafers 190a-190d. Hot block 134 applies heat to semiconductor wafers 190a-190d. Semiconductor wafers 190a-190d are preheated by hot press block 132 and hot block 134.

[0065] The semiconductor wafers 190a-190d disposed between the hot press block 132 and the hot block 134, and the bump 196 contacting the conductive layer 112, are represented as bonding assembly 198. The electrical and mechanical bonding process of the bump 196 to the conductive layer 112 may utilize three simultaneous operations. The hot press block 132 applies heat and pressure to the semiconductor wafers 190a-190d to heat and compress the bump 196, as indicated by indicator arrow 136. The hot block 134 applies heat to the semiconductor wafers 190a-190d to provide additional heat, as indicated by indicator arrow 138.

[0066] Importantly, the heat and pressure from the hot press blocks 132 and 134 are kept uniform across the bump 196 with minimal stress to maximize or at least enhance the molecular and atomic bonding between the bump 196 and the conductive posts 192 and 194. For this purpose, a bonding assembly 198 is disposed within the microwave source 140 to transmit the VFM signal 142 to the bump 196 and the conductive posts 192 and 194. Figure 2e-2f After the discussion, Figure 6b More details are shown of the thermo-pressure indicator 136, the thermal indicator 138, and the VFM signal 142 around the bump 196 and the conductive posts 192 and 194.

[0067] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot pressure indicator 138, or without either the hot pressure indicator 136 or the hot pressure indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 6c The combined semiconductor wafers 190a-190d are shown, wherein a combination of a hot press block 132, a hot block 134 and a microwave source 140, or a microwave source 140 having a hot press block 132 or a hot block 134, or a microwave source 140 without a hot press block 132 and a hot block 134, is used to electrically and mechanically connect bumps 196 between conductive posts 192 and 194 to achieve a uniform hot press distribution.

[0068] Sealant or molding compound 200 is deposited on and around semiconductor wafers 190a-190d using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. Sealant 200 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers. Sealant 200 is non-conductive, provides structural support, and protects the semiconductor device from external components and contaminants in the environment.

[0069] Conductive bump material is deposited on the conductive layer 112 of the semiconductor wafer 190d using evaporation, electrolytic plating, electroless plating, droplet coating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 204. In one embodiment, bumps 204 are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. Bumps 204 can also be compression bonded or thermo-pressed bonded to the conductive layer 112. Bumps 204 represent an interconnect structure that can be formed on the conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, columnar bumps, microbumps, or other electrical interconnects.

[0070] The stacked semiconductor wafers 190a-190d, combined with sealant 200 and bumps 204, represent a semiconductor package 210. Semiconductor package 210 is particularly useful for HBM. The stacked semiconductor wafers 190a-190d have improved interconnect bonding, wherein bumps 196 are electrically and mechanically connected between conductive posts 192 and 194 using a combination of thermopressors 132, heat blocks 134, and a microwave source 140, or a microwave source 140 having either thermopressors 132 or heat blocks 134, or a microwave source 140 without thermopressors 132 or heat blocks 134, to achieve uniform thermopressor distribution and avoid tilting, slippage, and warping as mentioned in the background art.

[0071] In another embodiment, such as Figure 7a As shown, a plurality of electrical components 220a-220c are disposed on surface 126 of interconnect substrate 120 using pick-and-place operations. In one embodiment, the electrical components 220a-220c can be made similar to those from... Figure 1eThe semiconductor die 104. Alternatively, electrical components 220a-220c may include other semiconductor dies, semiconductor packages, surface-mount devices, discrete electrical components, interconnect structures, or IPDs. As described herein, any of electrical components 220a-220c may be a first substrate, and interconnect substrate 120 may be a second substrate. Similarly, as described herein, any of electrical components 220a-220c may be a first electrical component, and interconnect substrate 120 may be a second electrical component. Flux material 130 is deposited on surface 126. Alternatively, flux 131 is deposited on bump 114, as in Figure 7b Electrical components 220a-220c are attached to a heat-pressing block 132, and an interconnect substrate 120 is attached to a heat-pressing block 134. The heat-pressing block 132 applies heat and pressure to the electrical components 220a-220c. The heat-pressing block 134 applies heat to the interconnect substrate 120. The electrical components 220a-220c and the interconnect substrate 120 are preheated by the heat-pressing block 132 and the heat-pressing block 134, respectively. Preheating activates the bump 114 and the conductive layers 112 and 122.

[0072] exist Figure 7c In this configuration, electrical components 220a-220c are aligned and in contact with surface 126 of substrate 120, designated as bonding assembly 219. The electrical and mechanical bonding process of bump 114 to conductive layers 112 and 122 may utilize three simultaneous operations. A hot press block 132 applies heat and pressure to electrical components 220a-220c to heat and compress bump 114, indicated by indicator arrow 136. A hot block 134 applies heat to interconnect substrate 120 to provide additional heat, indicated by indicator arrow 138.

[0073] Importantly, heat and pressure are kept uniform across bump 114 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 114 and conductive layers 112 and 122. For this purpose, bonding assembly 219 is disposed within microwave source 140 to transmit VFM signal 142 to bump 114 and conductive layers 112 and 122. Figure 2e-2f After the discussion, Figure 7d More details are shown of the bump 114 and the thermo-press indicator 136, thermal indicator 138 and VFM signal 142 around the conductive layers 112 and 122.

[0074] VFM signal 142 can be operated using a hot pressure indicator 136 or a hot indicator 138, or without either a hot pressure indicator 136 or a hot indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 7eElectrical components 220a-220c incorporated into interconnect substrate 120 are shown, wherein bumps 114 are electrically and mechanically connected between conductive layers 112 and 122 to achieve uniform hot-pressing distribution by using a combination of hot-pressing blocks 132, hot blocks 134 and microwave sources 140, or microwave sources 140 having hot-pressing blocks 132 or hot blocks 134, or microwave sources 140 having neither hot-pressing blocks 132 nor hot blocks 134. Figure 7f Electrical components 220a-220c and interconnect substrate 120 are shown outside the bonding assembly 219, wherein bumps 114 are electrically and mechanically connected between conductive layers 112 and 122.

[0075] Using a saw blade or laser cutting tool 221, the electrical components 220a-220c and the interconnect substrate 120 are monomerized into a single semiconductor package 222. Figure 7g A semiconductor package 222 with improved interconnect bonding is shown, wherein bumps 114 are electrically and mechanically connected between conductive layers 112 using a combination of hot press blocks 132, hot blocks 134 and microwave sources 140, or microwave sources 140 having hot press blocks 132 or hot blocks 134, or microwave sources 140 without hot press blocks 132 and without hot blocks 134, to achieve uniform hot press distribution and avoid tilting, slippage and warping mentioned in the background art.

[0076] In another embodiment, such as Figure 8a As shown, a plurality of electrical components 223a-223c are disposed on semiconductor wafer 224. In one embodiment, the electrical components 223a-223c may be made similar to those from... Figure 1e The semiconductor die 104. Alternatively, electrical components 223a-223c may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical components, interconnect structures, or IPDs. This makes semiconductor wafer 224 similar to semiconductor wafer 100. As described herein, any of electrical components 223a-223c may be a first substrate, and semiconductor wafer 224 may be a second substrate. Similarly, as described herein, any of electrical components 223a-223c may be a first electrical component, and semiconductor wafer 224 may be a second electrical component. Figure 4aSimilarly, conductive pillars 162 and 164 are formed on electrical components 223a-223c and semiconductor wafer 224, respectively. Components with similar functions are assigned the same reference numerals. Flux material 165 is deposited on conductive pillars 162 and 164. Electrical components 223a-223c are attached to a hot press block 132, and semiconductor wafer 224 is attached to a hot block 134. The hot press block 132 applies heat and pressure to the electrical components 223a-223c. The hot block 134 applies heat to the semiconductor wafer 224. Electrical components 223a-223c and semiconductor wafer 224 are preheated by the hot press block 132 and the hot block 134, respectively.

[0077] exist Figure 8b In this configuration, conductive post 162 is aligned and in contact with conductive post 164 and intermediate bump material 166, and is represented as bonding assembly 225. The electrical and mechanical bonding process of bump 166 to conductive posts 162 and 164 may utilize three simultaneous operations. A hot press block 132 applies heat and pressure to electrical components 223a-223c to heat and compress bump 166, as indicated by indicator arrow 136. A hot press block 134 applies heat to semiconductor wafer 224 to provide additional heat, as indicated by indicator arrow 138.

[0078] Importantly, heat and pressure are kept uniform across bump 166 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 166 and conductive posts 162 and 164. For this purpose, bonding assembly 225 is disposed within microwave source 140 to transmit VFM signal 142 to bump 166 and conductive posts 162 and 164. Figure 2e-2f After the discussion, Figure 8c More details are shown of the hot pressure indicator 136, the thermal indicator 138, and the VFM signal 142 around the bump 166 and the conductive posts 162 and 164.

[0079] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot indicator 138, or without either the hot pressure indicator 136 or the hot indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 8d The electrical components 223a-223c incorporated into the semiconductor wafer 224 are shown, wherein a combination of a heat press block 132, a heat block 134 and a microwave source 140, or a microwave source 140 having a heat press block 132 or a heat block 134, or a microwave source 140 without a heat press block 132 and a heat block 134, are used to electrically and mechanically connect bumps 166 between conductive posts 162 and 164 to achieve a uniform heat press distribution.

[0080] The electrical components 223a-223c and the semiconductor wafer 224 are individualized into a single semiconductor package 228 using a saw blade or laser cutting tool 226. Figure 8eA semiconductor package 228 with improved interconnect bonding is shown, wherein a combination of a thermoplastic block 132, a heat block 134 and a microwave source 140, or a microwave source 140 having a thermoplastic block 132 or a heat block 134, or a microwave source 140 without a thermoplastic block 132 and a heat block 134, is used to electrically and mechanically connect bumps 166 between conductive posts 162 and 164 to achieve uniform thermoplastic distribution and avoid tilting, slippage and warping as mentioned in the background art.

[0081] In another embodiment, the electrical component 230 is disposed on a die-sized portion of the interconnect substrate 120, such as Figure 9a As shown in the figure. In one embodiment, the electrical component 230 can be made similar to that from Figure 1e The semiconductor die 104. Alternatively, the electrical component 230 may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical components, interconnect structures, or IPDs. As described herein, the electrical component 230 may be a first substrate, and the die-sized portion of the interconnect substrate 120 may be a second substrate. Similarly, as described herein, the electrical component 230 may be a first electrical component, and the die-sized portion of the interconnect substrate 120 may be a second electrical component. Conductive pillars 150 and 152 are formed on the electrical component 230 and the interconnect substrate 120, respectively, similar to... Figure 3a Flux material 154 is deposited on conductive pillars 150 and 152. Electrical component 230 is attached to hot press block 132, and a die-sized portion of interconnect substrate 120 is attached to hot press block 134. Hot press block 132 applies heat and pressure to electrical component 230. Hot press block 134 applies heat to interconnect substrate 120. Electrical component 230 and interconnect substrate 120 are preheated by hot press block 132 and hot press block 134, respectively.

[0082] exist Figure 9b In this configuration, conductive post 150 is aligned and in contact with conductive post 152 and intermediate bump material 156, and is represented as bonding assembly 232. The electrical and mechanical bonding process of bump 156 to conductive posts 150 and 152 may utilize three simultaneous operations. A hot press block 132 applies heat and pressure to the electrical component 230 to heat and compress bump 156, as indicated by indicator arrow 136. A hot block 134 applies heat to the interconnect substrate 120 to provide additional heat, as indicated by indicator arrow 138.

[0083] Importantly, heat and pressure are kept uniform across bump 156 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 156 and conductive posts 150 and 152. For this purpose, bonding assembly 232 is disposed within microwave source 140 to transmit VFM signal 142 to bump 156 and conductive posts 150 and 152. Figure 2e-2f After the discussion, Figure 9cMore details are shown of the bump 156 and the thermo-pressure indicator 136, the thermal indicator 138, and the VFM signal 142 around the conductive posts 150 and 152.

[0084] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot indicator 138, or without either the hot pressure indicator 136 or the hot indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 9d An electrical component 230 is shown incorporated into a die-sized portion of an interconnect substrate 120, wherein a combination of a thermoplastic block 132, a heat block 134, and a microwave source 140, or a microwave source 140 having either a thermoplastic block 132 or a heat block 134, or a microwave source 140 without either a thermoplastic block 132 or a heat block 134, is used to electrically and mechanically connect bumps 156 between conductive pillars 150 and 152 as a semiconductor package 236 to achieve uniform thermoplastic distribution.

[0085] In another embodiment, such as Figure 10a As shown, electrical component 240a is disposed on electrical component 240b. In one embodiment, electrical components 240a and 240b can be made similar to those from... Figure 1e The semiconductor die 104. Alternatively, electrical components 240a and 240b may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical components, interconnect structures, or IPDs. As described herein, electrical component 240a may be a first electrical component, and electrical component 240b may be a second electrical component. Similarly, as described herein, electrical component 240a may be a first substrate, and electrical component 240b may be a second substrate. Conductive pillars 162 and 164 are formed on electrical components 240a and 240b, respectively, similar to... Figure 4a Flux material 165 is deposited on conductive pillars 162 and 164. Electrical component 240a is attached to hot press block 132, and electrical component 240b is attached to hot block 134. Hot press block 132 applies heat and pressure to electrical component 240a. Hot block 134 applies heat to electrical component 240b. Electrical components 240a and 240b are preheated by hot press block 132 and hot block 134, respectively.

[0086] exist Figure 10b In this configuration, conductive post 162 is aligned and in contact with conductive post 164 and intermediate bump material 166, and is represented as bonding assembly 242. The electrical and mechanical bonding process of bump 166 to conductive posts 162 and 164 may utilize three simultaneous operations. A hot press block 132 applies heat and pressure to electrical component 240a to heat and compress bump 166, as indicated by indicator arrow 136. A hot press block 134 applies heat to electrical component 240b to provide additional heat, as indicated by indicator arrow 138.

[0087] Importantly, heat and pressure are kept uniform across bump 166 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 166 and conductive posts 162 and 164. For this purpose, bonding assembly 242 is disposed within microwave source 140 to transmit VFM signal 142 to bump 166 and conductive posts 162 and 164. Figure 2e-2f After the discussion, Figure 10c More details are shown of the hot pressure indicator 136, the thermal indicator 138, and the VFM signal 142 around the bump 166 and the conductive posts 162 and 164.

[0088] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot indicator 138, or without either the hot pressure indicator 136 or the hot indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 10d An electrical component 240a is shown incorporated into an electrical component 240b, wherein a combination of a thermoplastic block 132, a heat block 134 and a microwave source 140, or a microwave source 140 having a thermoplastic block 132 or a heat block 134, or a microwave source 140 without a thermoplastic block 132 and a heat block 134, is used to electrically and mechanically connect bumps 166 between conductive posts 162 and 164 as a semiconductor package 246 to achieve uniform thermoplastic distribution.

[0089] In another embodiment, such as Figure 11a As shown, multiple electrical components 250a-250d are stacked. In one embodiment, the electrical components 250a-250d can be made similar to those from... Figure 1e The semiconductor die 104. Alternatively, electrical components 250a-250d may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical components, interconnect structures, or IPDs. As described herein, one of the electrical components 250a-250d may be a first substrate, and one of the electrical components 250a-250d may be a second substrate. Similarly, as described herein, one of the electrical components 250a-250d may be a first electrical component, and one of the electrical components 250a-250d may be a second electrical component. Flux material is deposited on conductive layer 112, similar to... Figures 2b-2c Electrical component 250a is attached to hot press block 132, and electrical component 250d is attached to hot block 134. Hot press block 132 applies heat and pressure to electrical components 250a-250d. Hot block 134 applies heat to electrical components 250a-250d. Electrical components 250a-250d are preheated by hot press block 132 and hot block 134, respectively.

[0090] exist Figure 11bIn this configuration, electrical components 250a-250d are aligned and in contact with the intermediate bump material 252, designated as bonding assembly 253. The electrical and mechanical bonding process of bump 252 to conductive layer 112 may utilize three simultaneous operations. A hot press block 132 applies heat and pressure to electrical components 250a-250d to heat and compress bump 252, indicated by indicator arrow 136. A hot block 134 applies heat to electrical components 250a-250d to provide additional heat, indicated by indicator arrow 138.

[0091] Importantly, heat and pressure are kept uniform across bump 252 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 166 and conductive pillars 162 and 164. For this purpose, bonding assembly 253 is disposed within microwave source 140 to transmit VFM signal 142 to bump 252 and conductive layer 112. Figure 2e-2f After the discussion, Figure 11b More details are shown of the thermo-pressure indicator 136, the thermal indicator 138, and the VFM signal 142 surrounding the bump 252 and the conductive layer 112.

[0092] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot indicator 138, or without either the hot pressure indicator 136 or the hot indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 11c The electrical components 250a-250d are shown together, wherein a combination of a hot press block 132, a hot block 134 and a microwave source 140, or a microwave source 140 having a hot press block 132 or a hot block 134, or a microwave source 140 without a hot press block 132 and a hot block 134, is used to electrically and mechanically connect bumps 252 between conductive layers 112 to achieve uniform hot press distribution.

[0093] Sealant or molding compound 254 is deposited on and around the stacked electrical components 250a-25d using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. Sealant 254 can be a polymer composite, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers. Sealant 254 is non-conductive, provides structural support, and protects the semiconductor device from external components and contaminants in the environment.

[0094] Conductive bump material is deposited on the conductive layer 112 of the electrical component 250d using evaporation, electrolytic plating, electroless plating, droplet coating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 258. In one embodiment, bumps 258 are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. Bumps 258 can also be compression bonded or thermo-pressed bonded to the conductive layer 112. Bumps 258 represent an interconnect structure that can be formed on the conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, column bumps, microbumps, or other electrical interconnects.

[0095] The stacked electrical components 250a-250d, combined with sealant 254 and bumps 258, represent a semiconductor package 260. The semiconductor package 260 is particularly useful for HBM. The stacked electrical components 250a-250d have improved interconnect bonding, wherein bumps 252 are electrically and mechanically connected between conductive layers 112 using a combination of hot press blocks 132, hot blocks 134, and microwave sources 140, or microwave sources 140 having either hot press blocks 132 or hot blocks 134, or microwave sources 140 without either hot press blocks 132 or hot blocks 134, to achieve uniform hot press distribution and avoid tilting, slippage, and warping as mentioned in the background art.

[0096] In another embodiment, such as Figure 12a As shown, multiple electrical components 270a-270d are stacked. In one embodiment, the electrical components 270a-270d can be made similar to those from... Figure 1e The semiconductor die 104. Alternatively, electrical components 270a-270d may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical components, interconnect structures, or IPDs. As described herein, one of electrical components 270a-270d may be a first substrate, and one of electrical components 270a-270d may be a second substrate. Similarly, as described herein, one of electrical components 270a-270d may be a first electrical component, and one of electrical components 270a-270d may be a second electrical component. Conductive pillars 272 and 274 are formed on electrical components 270a-270d, and flux material is deposited on the conductive pillars, similar to... Figure 4aElectrical component 270a is attached to hot press block 132, and electrical component 270d is attached to hot block 134. Hot press block 132 applies heat and pressure to electrical components 270a-270d. Hot block 134 applies heat to electrical components 270a-270d. Electrical components 270a-270d are preheated by hot press block 132 and hot block 134.

[0097] Conductive post 272 is aligned and in contact with conductive post 274 and intermediate bump material 276, represented as bonding assembly 277. The electrical and mechanical bonding process of bump 276 to conductive posts 272 and 274 may utilize three simultaneous operations. A hot press block 132 applies heat and pressure to electrical components 270a-270d to heat and compress bump 276, indicated by indicator arrow 136. A hot block 134 applies heat to electrical components 270a-270d to provide additional heat, indicated by indicator arrow 138.

[0098] Importantly, heat and pressure are kept uniform across bump 276 with minimal stress to maximize or at least enhance the molecular and atomic bonding between bump 276 and conductive posts 272 and 274. For this purpose, bonding assembly 277 is disposed within microwave source 140 to transmit VFM signal 142 to bump 276 and conductive posts 272 and 274. Figure 2e-2f After the discussion, Figure 12b More details are shown of the hot pressure indicator 136, the heat indicator 138, and the VFM signal 142 around the bump 276 and the conductive posts 272 and 274.

[0099] VFM signal 142 can be operated using either the hot pressure indicator 136 or the hot indicator 138, or without either the hot pressure indicator 136 or the hot indicator 138. Figure 2e-2k As described in [the text]. In any case, Figure 12c The electrical components 270a-270d are shown together, wherein a combination of a heat-pressing block 132, a heat block 134 and a microwave source 140, or a microwave source 140 having a heat-pressing block 132 or a heat block 134, or a microwave source 140 without a heat-pressing block 132 and a heat block 134, is used to electrically and mechanically connect a bump 276 between conductive posts 272 and 274 to achieve a uniform heat-pressing distribution.

[0100] Sealant or molding compound 282 is deposited on and around the stacked electrical components 270a-27d using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. Sealant 282 can be a polymer composite, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers. Sealant 282 is non-conductive, provides structural support, and protects the semiconductor device from external components and contaminants in the environment.

[0101] Conductive bump material is deposited on the conductive layer 112 of the electrical component 270d using evaporation, electrolytic plating, electroless plating, droplet plating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 284. In one embodiment, bumps 284 are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. Bumps 284 can also be compression bonded or thermo-pressed bonded to the conductive layer 112. Bumps 284 represent an interconnect structure that can be formed on the conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, columnar bumps, microbumps, or other electrical interconnects.

[0102] The stacked electrical components 270a-270d, combined with sealant 282 and bumps 284, represent a semiconductor package 290. The semiconductor package 290 is particularly useful for HBM. The stacked electrical components 270a-270d have improved interconnect bonding, wherein bumps 276 are electrically and mechanically connected between conductive posts 272 and 274 using a combination of thermopressors 132, heat blocks 134, and a microwave source 140, or a microwave source 140 having either thermopressors 132 or heat blocks 134, or a microwave source 140 without thermopressors 132 or heat blocks 134, to achieve uniform thermopressor distribution and avoid tilting, slippage, and warping as mentioned in the background art.

[0103] Figure 13 It shows the relationship with Figures 12a-12c In a similar embodiment, a non-conductive film (NCF) 296 (including a polar material) is deposited around bumps 276 and conductive pillars 272 and 274.

[0104] Figure 14 Showing with Figures 12a-12c In a similar embodiment, epoxy resin and flux material 298 are deposited around bumps 276 and conductive pillars 272 and 274 to protect the interconnect structure.

[0105] Figure 15 An electrical device 400 with a chip carrier substrate or PCB 402 is shown, wherein multiple semiconductor packages are disposed on the surface of the PCB 402, including semiconductor packages 148, 159, 168, 180, 210, 222, 228, 236, 246, 260, and 290. Depending on the application, the electrical device 400 may have one type of semiconductor package or multiple types of semiconductor packages.

[0106] Electrical device 400 can be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electrical device 400 can be a sub-component of a larger system. For example, electrical device 400 can be part of a tablet computer, mobile phone, digital camera, communication system, or other electrical device. Alternatively, electrical device 400 can be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density.

[0107] exist Figure 15 In this PCB 402, a general-purpose substrate is provided for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 404 are formed on or within the surface of the PCB 402 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each semiconductor package, mounting component, and other external system components. Trace 404 also provides power and ground connections to each semiconductor package.

[0108] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first-level package in which the die's mechanical and electrical grounds are directly disposed on the PCB. For illustrative purposes, several types of first-level packages are shown on PCB 402, including a wire bond package 406 and a flip chip 408. Furthermore, several types of second-level packages, including a ball grid array (BGA) 410, a bump chip carrier (BCC) 412, a pad grid array (LGA) 416, a multi-chip module (MCM) or SIP module 418, a quad flat no-leads package (QFN) 420, a quad flat package 422, an embedded wafer-level ball grid array (eWLB) 424, and a wafer-level chip-scale package (WLCSP) 426, are shown disposed on PCB 402. In one embodiment, eWLB 424 is a fan-out wafer-level package (Fo-WLP), and WLCSP426 is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages configured with any combination of first and second-level package styles, along with other electrical components, can be connected to PCB 402. In some embodiments, electrical device 400 comprises a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can integrate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, resulting in lower costs for consumers.

[0109] While one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide a first substrate; Provide a second substrate; as well as Interconnect structures are formed between the first and second substrates using variable frequency microwaves.

2. The method of claim 1 further includes applying heat and pressure to the interconnect structure while using variable frequency microwaves.

3. The method of claim 1 further includes applying heat or pressure to the interconnect structure while using variable frequency microwaves.

4. The method of claim 1 further comprises forming a non-conductive film around the interconnect structure between the first substrate and the second substrate.

5. The method of claim 1, further comprising forming an epoxy resin and a flux material around the interconnect structure between the first substrate and the second substrate.

6. A method for manufacturing a semiconductor device, comprising: Provide the first electrical component; Provide a second electrical component; as well as An interconnect structure is formed between the first and second electrical components using variable frequency microwaves.

7. The method of claim 6, wherein the first electrical component comprises a semiconductor wafer.

8. The method of claim 6, wherein the first electrical component comprises an interconnect substrate.

9. The method of claim 6, further comprising forming a non-conductive film around the interconnect structure between the first electrical component and the second electrical component.

10. The method of claim 6, further comprising forming an epoxy resin and a flux material around the interconnect structure between the first electrical component and the second electrical component.

11. A semiconductor device, comprising: First substrate; Second substrate; as well as An interconnect structure is formed between a first substrate and a second substrate using variable frequency microwaves.

12. The semiconductor device of claim 11, further comprising a hot press block, wherein the first substrate is attached to the hot press block.

13. The semiconductor device of claim 11, further comprising a heat block, wherein the second substrate is attached to the heat block.

14. The semiconductor device of claim 11, further comprising a non-conductive film formed around the interconnect structure between the first substrate and the second substrate.

15. The semiconductor device of claim 11, further comprising an epoxy resin and a flux material formed around the interconnect structure between the first substrate and the second substrate.

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