An acoustic doppler received signal processing method and apparatus

Abstract

This application discloses an acoustic Doppler receiving signal processing method and apparatus. The method includes: performing a first-stage analog coarse-tuning filtering on the received underwater acoustic signal using a low-noise tunable amplifier circuit; performing bandwidth compression filtering on the signal after the first-stage analog coarse-tuning filtering using a fully differential amplifier circuit; performing a second-stage analog fine-tuning filtering on the signal after the bandwidth compression filtering using a programmable bandpass filter; converting the analog signal after the second-stage analog fine-tuning filtering into a digital signal using a fully differential analog-to-digital converter circuit; and performing a third-stage digital fine-locking filtering on the digital signal in the digital domain using an FPGA processing circuit. Using the scheme of this application, a signal processing architecture with deep integration of analog and digital domains, step-by-step focusing, and adaptive tracking is constructed, significantly improving the efficiency and performance of capturing and accurately analyzing weak Doppler signals in complex underwater acoustic environments.

Description

Technical Field

[0001] This application generally relates to the field of underwater acoustic signal processing technology. More specifically, this application relates to an acoustic Doppler receiving signal processing method and apparatus. Background Technology

[0002] The Acoustic Doppler Current Profiler (ADCP) is a key device in modern underwater navigation and velocity measurement. Its basic working principle involves emitting sound waves and receiving the echoes from scattering bodies (such as suspended particles) in the water. By analyzing the Doppler frequency shift of the echo signal relative to the emitted signal, the relative velocity of the carrier to the water flow is accurately calculated. This technology is crucial for the navigation, positioning, and marine environmental surveying of ships, submersibles, and other underwater vehicles.

[0003] To improve measurement accuracy, existing technologies typically employ phased array transducers, using beamforming technology to construct a specific Janus configuration (usually four oblique acoustic beams). This four-beam configuration theoretically can effectively eliminate the influence of changes in sound velocity in water caused by environmental factors such as temperature and salinity on the final velocity measurement results. Furthermore, the receiving signal processing circuit plays a crucial role in the entire system. After the signal is received from the transducer, it sequentially passes through a series of complex analog circuit processing stages, including pre-amplification, beamforming, variable gain control, and bandpass filtering. The aim is to amplify the weak echo signal and filter out environmental noise and other interference to the greatest extent possible, ensuring the accuracy and stability of the velocity measurement.

[0004] However, traditional acoustic Doppler velocimeters suffer from the following design and implementation problems: First, they require high precision and consistency of components: the performance of analog circuits is highly susceptible to the influence of the parameters of electronic components themselves (such as precision, temperature drift, and consistency). This not only increases the difficulty and cost of production and debugging but also limits the long-term stability and reliability of the equipment in harsh environments. Third, they lack compatibility and versatility: traditional processing circuits are usually designed for transducers with specific center frequencies and bandwidths. When it is necessary to adapt to transducers of different frequency bands, it is often necessary to redesign and replace the entire hardware circuit, making adaptive processing impossible and lacking versatility and flexibility.

[0005] In view of this, there is an urgent need to provide an acoustic Doppler receiving signal processing scheme that can overcome the shortcomings of traditional technology and achieve adaptive processing of received signals in different frequency bands. Summary of the Invention

[0006] In order to at least solve one or more of the technical problems mentioned above, this application proposes an acoustic Doppler receiving signal processing scheme in several aspects.

[0007] In a first aspect, this application provides an acoustic Doppler received signal processing method, comprising: performing a first-stage analog coarse-tuning filtering on a received underwater acoustic signal through a low-noise tunable amplifier circuit; performing bandwidth compression filtering on the signal after the first-stage analog coarse-tuning filtering through a fully differential amplifier circuit; performing a second-stage analog fine-tuning filtering on the signal after the bandwidth compression filtering through a programmable bandpass filter; converting the analog signal after the second-stage analog fine-tuning filtering into a digital signal through a fully differential analog-to-digital converter circuit; and performing a third-stage digital fine-locking filtering on the digital signal in the digital domain through an FPGA processing circuit.

[0008] In some embodiments, the low-noise tunable amplifier circuit includes a coupling capacitor, a tunable bandpass filter, an amplifier, and a first feedback capacitor; the first-stage analog coarse-tuning filtering process includes: controlling the center frequency and bandwidth of the tunable bandpass filter through a field-programmable gate array, so that the center frequency of the tunable bandpass filter matches the center frequency of the acoustic transducer operating frequency band receiving the underwater acoustic signal, and making the bandwidth of the tunable bandpass filter a first preset multiple of the operating bandwidth of the acoustic transducer receiving the underwater acoustic signal.

[0009] In some embodiments, the first-stage analog coarse-tuning filtering process further includes: applying a cutoff frequency f to the received underwater acoustic signal. H1 First-order high-pass filtering and cutoff frequency f L1 The first-order low-pass filter is used to obtain the first filtered signal; the first filtered signal is amplified by an amplifier and sent to a fully differential amplifier circuit; wherein, the received underwater acoustic signal is cut off at a frequency of f through a coupling capacitor and the input impedance of a tunable bandpass filter. H1 First-order high-pass filtering; the received underwater acoustic signal is cut off at a frequency of f through the first feedback capacitor and the feedback resistor of the amplifier. L1 First-order low-pass filtering.

[0010] In some embodiments, the fully differential amplifier circuit includes an input capacitor, a fully differential amplifier, and a second feedback capacitor; performing bandwidth compression filtering includes: applying a cutoff frequency of f to the signal that has undergone the first-stage analog coarse-tuning filtering. H2 First-order high-pass filtering and cutoff frequency f L2 The first-order low-pass filter process yields the second filtered signal; this second filtered signal is amplified by a fully differential amplifier and then sent to a programmable bandpass filter circuit; wherein, the signal after the first-stage analog coarse-tuning filter is cut off at a frequency of f through the input capacitor and the input resistor of the fully differential amplifier. H2The signal undergoes first-order high-pass filtering; the signal, after passing through the second feedback capacitor and the feedback resistor of the fully differential amplifier and undergoing first-stage analog coarse-tuning filtering, is cut off at a frequency of f. L2 First-order low-pass filtering.

[0011] In some embodiments, the bandwidth of the second filtered signal ranges from f. L3 -f H3 ,in, , f o1 BW1 is the center frequency of the tunable bandpass filter, and BW1 is the bandwidth of the tunable bandpass filter.

[0012] In some embodiments, performing the second-level analog fine-tuning filtering process includes: setting the center frequency of the programmable bandpass filter to follow the center frequency of the tunable bandpass filter, and setting the bandwidth of the programmable bandpass filter to a second preset multiple of the bandwidth of the signal after bandwidth compression filtering; and filtering the signal after the first-level analog coarse-tuning filtering process using the configured programmable bandpass filter to obtain a third filtered signal.

[0013] In some embodiments, the FPGA processing circuit includes a digital FIR filter and a digital phase-locked loop phase shifter; performing the third-level digital fine-locked filtering process includes: initially setting the center frequency of the digital FIR filter to follow the center frequency of the tunable bandpass filter; performing a scan within a frequency sweep range defined by the center frequency of the tunable bandpass filter to obtain the final center frequency of the digital FIR filter; setting the bandwidth of the digital FIR filter to a third preset multiple of the final center frequency of the digital FIR filter; and using the configured digital FIR filter to filter the digital signal to obtain a fourth filtered signal.

[0014] In some embodiments, the frequency sweep range is [f o1 -2BW2, f o1 +2BW2],f o1 BW2 is the center frequency of the tunable bandpass filter, and BW2 is the bandwidth of the signal after the second stage of analog fine-tuning filtering.

[0015] In some embodiments, after performing the third-level digital fine-locked filtering, the signal that has undergone the third-level digital fine-locked filtering is processed by the digital phase-locked loop phase shifter to generate a signal orthogonal to the signal that has undergone the third-level digital fine-locked filtering.

[0016] In a second aspect, this application provides an acoustic Doppler receiving signal processing apparatus, which performs acoustic Doppler receiving signal processing using the acoustic Doppler receiving signal processing method as described in any embodiment of the first aspect. The apparatus includes: a low-noise tunable amplifier circuit for performing a first-stage analog coarse-tuning filtering on the received underwater acoustic signal; a fully differential amplifier circuit for performing bandwidth compression filtering on the signal after the first-stage analog coarse-tuning filtering; a programmable bandpass filter for performing a second-stage analog fine-tuning filtering on the signal after the bandwidth compression filtering; a fully differential analog-to-digital converter circuit for converting the analog signal after the second-stage analog fine-tuning filtering into a digital signal; and an FPGA processing circuit for performing a third-stage digital fine-locked filtering on the digital signal in the digital domain.

[0017] Using the acoustic Doppler receiver signal processing scheme provided above, this embodiment performs initial analog coarse-tuning filtering on the received underwater acoustic signal through a low-noise tunable amplifier circuit. This effectively suppresses initial noise and preliminarily matches the acoustic transducer characteristics, laying a high-quality foundation for subsequent processing. Next, a fully differential amplifier circuit, with its bandwidth compression capability, further optimizes the signal frequency band while ensuring signal integrity. The subsequent programmable bandpass filter implements the second-stage analog fine-tuning filtering, possessing frequency tracking and adaptive adjustment capabilities, further focusing the target signal in the analog domain and improving the signal-to-noise ratio. Through a fully differential analog-to-digital converter circuit, the analog signal is converted into a digital signal with high precision and without distortion, creating favorable conditions for in-depth processing in the digital domain. Finally, the FPGA processing circuit undertakes the core task of the third-stage digital fine-locked filtering in the digital domain. Leveraging its powerful parallel computing capabilities and programmability, it achieves precise extraction and purification of weak Doppler signals. The collaborative work of this series of devices has created a signal processing architecture that deeply integrates analog and digital domains, focuses progressively, and tracks adaptively, significantly improving the efficiency and performance of capturing and accurately analyzing weak Doppler signals in complex underwater acoustic environments.

[0018] Furthermore, in some embodiments, by precisely controlling the center frequency and bandwidth of the tunable bandpass filter through the FPGA, the filter's center frequency can adaptively match the operating center frequency of the acoustic transducer, and its bandwidth can be limited to a preset multiple of the acoustic transducer's operating bandwidth. This ensures that the main energy of the target signal can be efficiently captured at the very beginning of the signal chain, and out-of-band noise can be initially filtered out. The high-pass filter formed by the coupling capacitor and the input impedance of the tunable bandpass filter, and the low-pass filter formed by the first feedback capacitor and the amplifier feedback resistor, together construct an effective bandpass filter window. This not only removes low-frequency noise and high-frequency interference but also precisely defines the frequency band range of the target signal.

[0019] Furthermore, in some embodiments, a fully differential amplifier circuit is used to purify and enhance the signal after the first-stage coarse-tuning filter. Firstly, by cleverly utilizing the combination of input capacitors and resistors, and second feedback capacitors and resistors, the circuit amplifies the signal while simultaneously implementing another stage of bandpass filtering, further narrowing the signal bandwidth. This bandwidth compression operation allows for more precise focusing on the target frequency band and filters out out-of-band noise remaining after the first-stage coarse tuning. Furthermore, in some embodiments, the powerful real-time computing capabilities of the FPGA are utilized to perform final precise locking and purification of the signal in the digital domain. It employs a highly efficient two-step search strategy of "coarse tuning guidance, fine scanning": First, it does not search blindly but cleverly inherits the results of the previous stage analog filtering, initially setting the center frequency of the digital FIR filter near the center frequency already determined by the analog circuit, which greatly narrows the search range and improves efficiency. Subsequently, it performs a fine scan within a reasonable range limited by the analog bandwidth. This scanning capability enables it to accurately capture the true signal frequency that is frequency-biased due to the Doppler effect, achieving true locking. Once the final center frequency is locked, the system adaptively sets the filter bandwidth to a specific multiple of that frequency, forming an extremely narrow filtering window that perfectly matches the target signal, thereby accurately filtering out all residual sideband noise and maximizing the signal-to-noise ratio. Attached Figure Description

[0020] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein:

[0021] Figure 1 An exemplary flowchart of an acoustic Doppler received signal processing method according to an embodiment of this application is shown;

[0022] Figure 2 An exemplary flowchart illustrating the execution of third-level digital fine-locked filtering according to an embodiment of this application is shown;

[0023] Figure 3 A signal frequency band variation diagram of an embodiment of this application is shown;

[0024] Figure 4 A first exemplary structural block diagram of an acoustic Doppler receiving signal processing apparatus according to an embodiment of this application is shown;

[0025] Figure 5 A second exemplary structural block diagram of an acoustic Doppler receiving signal processing apparatus according to an embodiment of this application is shown. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] It should be understood that the terms "comprising" and "including" used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0028] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0029] Figure 1 An exemplary flowchart of an acoustic Doppler received signal processing method 100 according to an embodiment of this application is shown.

[0030] like Figure 1 As shown, in step S110, the received underwater acoustic signal is subjected to the first stage of analog coarse-tuning filtering through a low-noise tunable amplifier circuit.

[0031] In embodiments of this application, the low-noise tunable amplifier circuit includes a coupling capacitor, a tunable bandpass filter, an amplifier, and a first feedback capacitor.

[0032] In the embodiments of this application, during the first-stage analog coarse-tuning filtering process, firstly, the center frequency and bandwidth of the tunable bandpass filter are controlled by a field-programmable gate array (FPGA) to match the center frequency of the tunable bandpass filter to the center frequency of the acoustic transducer operating band receiving the underwater acoustic signal, and the bandwidth of the tunable bandpass filter is a first preset multiple of the operating bandwidth of the acoustic transducer receiving the underwater acoustic signal. Next, the received underwater acoustic signal is cut off at a frequency of f. H1 First-order high-pass filtering and cutoff frequency f L1 The signal is first filtered by a first-order low-pass filter. Then, the first filtered signal is amplified by an amplifier and sent to a fully differential amplifier circuit.

[0033] In the embodiments of this application, the tunable bandpass filter consists of an inductor and a varactor diode, and the formula for calculating the center frequency of the tunable bandpass filter is: L is the inductance value that makes up the tunable bandpass filter, and C is... D-tri This refers to the adjustable capacitance value of a varactor diode.

[0034] By adjusting the tunable bandpass filter, which consists of an inductor and a varactor diode, in real time, its center frequency is precisely matched to the center frequency of the acoustic transducer currently in use, thus achieving self-adaptation to different hardware.

[0035] In the embodiments of this application, the bandwidth of the tunable bandpass filter is 1.5 times the operating bandwidth of the acoustic transducer.

[0036] By setting the bandwidth of the tunable bandpass filter to 1.5 times the transducer's operating bandwidth, a capture window slightly wider than the original signal bandwidth was created. This effectively filters out a significant amount of noise far from the target frequency band while ensuring that the target signal, which deviates from the center frequency due to Doppler shift, is not accidentally filtered out, thus balancing noise reduction and signal integrity.

[0037] Specifically, the received underwater acoustic signal is cut off at a frequency of f by using a coupling capacitor and the input impedance of a tunable bandpass filter. H1 First-order high-pass filtering processing.

[0038] Specifically, C i R is the capacitance value of the coupling capacitor. L R is the input impedance of the tunable bandpass filter. i This is the input impedance value inside the amplifier.

[0039] Specifically, the received underwater acoustic signal is cut off at a frequency of f using the first feedback capacitor and the feedback resistor of the amplifier. L1 First-order low-pass filtering.

[0040] Specifically, C FB R is the capacitance value of the first feedback capacitor. FB This is the value of the amplifier's feedback resistor.

[0041] After step S110 is completed, in step S120, the signal that has undergone the first stage of analog coarse-tuning filtering is subjected to bandwidth compression filtering through a fully differential amplifier circuit.

[0042] In the embodiments of this application, the fully differential amplifier circuit includes an input capacitor, a fully differential amplifier, and a second feedback capacitor.

[0043] In the embodiments of this application, during the bandwidth compression filtering process, firstly, the signal that has undergone the first-stage analog coarse-tuning filtering process is cut off at a frequency of f. H2 First-order high-pass filtering and cutoff frequency f L2 The signal is first-order low-pass filtered to obtain a second filtered signal. Then, the second filtered signal is amplified by a fully differential amplifier and sent to a programmable bandpass filter circuit.

[0044] Specifically, the fully differential amplifier circuit amplifies the two signals output from the first-stage analog coarse-tuning filter in a fully differential manner.

[0045] Specifically, the signal after the first-stage analog coarse-tuning filter is cut off at a frequency of f by the input capacitor and the input resistor of the fully differential amplifier. H2 First-order high-pass filtering processing.

[0046] The signal, after undergoing the first stage of analog coarse filtering, is cut off at a frequency of f. H2 First-order high-pass filtering and cutoff frequency f L2 The first-order low-pass filtering further limits the bandwidth, thus achieving bandwidth reduction.

[0047] Specifically, the signal processed by the first-stage analog coarse-tuning filter through the second feedback capacitor and the feedback resistor of the fully differential amplifier is cut off at a frequency of f. L2 First-order low-pass filtering.

[0048] In the embodiments of this application, C i1 R is the capacitance value of the input capacitor. i1 R is the input resistance value of the fully differential amplifier. OP_DIFF This is the input impedance value inside the fully differential amplifier.

[0049] In the embodiments of this application, C FB1 FB1 is the value of the feedback capacitor of the fully differential amplifier, and FB2 is the value of the feedback resistor of the fully differential amplifier.

[0050] In the embodiments of this application, the bandwidth of the second filtered signal ranges from f. L3 -f H3 ,in, , f o1 BW1 is the center frequency of the tunable bandpass filter, and BW1 is the bandwidth of the tunable bandpass filter.

[0051] After step S120 is completed, in step S130, a second-stage analog fine-tuning filter is performed on the signal that has undergone bandwidth compression filtering through a programmable bandpass filter.

[0052] In the embodiments of this application, during the second-stage analog fine-tuning filtering process, firstly, the center frequency of the programmable bandpass filter is set to follow the center frequency of the tunable bandpass filter, and the bandwidth of the programmable bandpass filter is set to a second preset multiple of the bandwidth of the signal after bandwidth compression filtering. Then, the signal after the first-stage analog coarse-tuning filtering process is filtered by the configured programmable bandpass filter to obtain the third filtered signal.

[0053] In the embodiments of this application, the second preset multiple is 1.2, meaning the bandwidth of the programmable bandpass filter is... .

[0054] By setting the bandwidth of the programmable bandpass filter to a smaller multiple, it imposes a more stringent constraint on the signal bandwidth based on the previous stage of filtering. This operation can accurately remove residual noise adjacent to the target signal that was not filtered out in the first stage of coarse tuning, thereby significantly improving the signal-to-noise ratio.

[0055] Through steps S110 and S120, a two-step analog filtering process from coarse to fine adjustment is achieved, improving the signal quality to a very high level in a more stable and reliable manner before entering the final digital processing. This provides a higher-quality signal for subsequent digital lock-in filtering, significantly reducing the difficulty and computational burden of digital processing.

[0056] After step S130 is completed, in step S140, the analog signal that has undergone the second-stage analog fine-tuning filtering process is converted into a digital signal through a fully differential analog-to-digital converter circuit.

[0057] In the embodiments of this application, the sampling rate f sample =5Msps oversampling of analog signals prevents frequency aliasing and converts analog signals with limited bandwidth from the analog domain to the digital domain.

[0058] After step S140 is completed, in step S150, in the digital domain, the digital signal is subjected to a third-level digital fine-locked filtering process by the FPGA processing circuit.

[0059] In embodiments of this application, the FPGA processing circuit includes a digital FIR filter and a digital phase-locked loop phase shifter.

[0060] The specific process involved in performing the third-level digital fine-locked filtering in the embodiments of this application can be found in [reference needed]. Figure 2.

[0061] Figure 2 An exemplary flowchart illustrating the execution of third-level digital fine-locked filtering processing according to an embodiment of this application is shown.

[0062] like Figure 2 As shown, in step S210, the center frequency of the digital FIR filter is initially set to follow the center frequency of the tunable bandpass filter. In step S220, a sweep is performed within the frequency range defined by the center frequency of the tunable bandpass filter to obtain the final center frequency of the digital FIR filter. In step S230, the bandwidth of the digital FIR filter is set to a third preset multiple of the final center frequency of the digital FIR filter. In step S240, the digital signal is filtered using the configured digital FIR filter to obtain a fourth filtered signal.

[0063] In the embodiments of this application, the frequency sweep range is [f o1 -2BW2, f o1 +2BW2],f o1 BW2 is the center frequency of the tunable bandpass filter, and BW2 is the bandwidth of the signal after the second stage of analog fine-tuning filtering.

[0064] In the embodiments of this application, the third preset multiple is 0.1, that is, the bandwidth of the digital FIR filter is 0.1 times the final center frequency.

[0065] Once the final center frequency of the signal is accurately located through scanning, the bandwidth of the digital FIR filter is adaptively set to 0.1 times the final frequency. This is equivalent to creating a filtering window with a width of only 10% of the signal frequency, which is far more accurate than any analog filter. This extremely narrow bandwidth filtering can filter out all stubborn noise that is right next to the target signal and cannot be removed in the first two stages of filtering, pushing the signal-to-noise ratio to its limit.

[0066] In the embodiments of this application, after performing the third-level digital fine-locked filtering process, the signal that has undergone the third-level digital fine-locked filtering process is processed by a digital phase-locked loop phase shifter to generate a signal orthogonal to the signal that has undergone the third-level digital fine-locked filtering process. That is, the signal that has undergone the third-level digital fine-locked filtering process is phase-shifted by 90 degrees by the digital phase-locked loop phase shifter, thereby further realizing beamforming.

[0067] Using a digital phase-locked loop to achieve phase shift ensures accurate 90-degree phase shift and is completely unaffected by common problems of analog devices such as ambient temperature and component aging, thus ensuring the stability and reliability of signal processing.

[0068] The generated pair of orthogonal signals (i.e., I / Q signals) is a fundamental prerequisite for digital beamforming. With I / Q data, the system can overcome physical limitations, achieve spatial filtering, focus only on target signals from a specific direction, and actively suppress interference noise from other directions.

[0069] In one embodiment of this application, the process of achieving adaptive signal adjustment through steps S110-S150 can be found in [reference needed]. Figure 3 .

[0070] In summary, through the acoustic Doppler receiver signal processing scheme provided above, this embodiment uses a low-noise tunable amplifier circuit to perform initial analog coarse-tuning filtering on the received underwater acoustic signal, effectively suppressing initial noise and initially matching the acoustic transducer characteristics, laying a high-quality foundation for subsequent processing. Next, a fully differential amplifier circuit, with its bandwidth compression capability, further optimizes the signal frequency band while ensuring signal integrity. The subsequent programmable bandpass filter implements the second-stage analog fine-tuning filtering, possessing frequency tracking and adaptive adjustment capabilities, further focusing the target signal in the analog domain and improving the signal-to-noise ratio. Through a fully differential analog-to-digital converter circuit, the analog signal is converted into a digital signal with high precision and without distortion, creating favorable conditions for in-depth processing in the digital domain. Finally, the FPGA processing circuit undertakes the core task of the third-stage digital fine-locked filtering in the digital domain, leveraging its powerful parallel computing capabilities and programmability to achieve precise extraction and purification of weak Doppler signals. The collaborative work of this series of devices has created a signal processing architecture that deeply integrates analog and digital domains, focuses progressively, and tracks adaptively, significantly improving the efficiency and performance of capturing and accurately analyzing weak Doppler signals in complex underwater acoustic environments.

[0071] Furthermore, in some embodiments, by precisely controlling the center frequency and bandwidth of the tunable bandpass filter through the FPGA, the filter's center frequency can adaptively match the operating center frequency of the acoustic transducer, and its bandwidth can be limited to a preset multiple of the acoustic transducer's operating bandwidth. This ensures that the main energy of the target signal can be efficiently captured at the very beginning of the signal chain, and out-of-band noise can be initially filtered out. The high-pass filter formed by the coupling capacitor and the input impedance of the tunable bandpass filter, and the low-pass filter formed by the first feedback capacitor and the amplifier feedback resistor, together construct an effective bandpass filter window. This not only removes low-frequency noise and high-frequency interference but also precisely defines the frequency band range of the target signal.

[0072] Furthermore, in some embodiments, a fully differential amplifier circuit is used to purify and enhance the signal after the first-stage coarse-tuning filter. Firstly, by cleverly utilizing a combination of input capacitors and resistors, and a second feedback capacitor and resistor, the circuit simultaneously amplifies the signal and performs another stage of bandpass filtering, further narrowing the signal bandwidth. This bandwidth compression operation allows for more precise focusing on the target frequency band and filters out out-of-band noise remaining after the first-stage coarse-tuning.

[0073] Furthermore, in some embodiments, the powerful real-time computing capabilities of the FPGA are utilized to perform final, precise signal locking and purification in the digital domain. It employs a highly efficient two-step search strategy of "coarse-tuning guidance and fine-tuning scanning": First, instead of blindly searching, it cleverly inherits the results of the preceding analog filtering, initially setting the center frequency of the digital FIR filter near the center frequency already determined by the analog circuit. This significantly narrows the search range and improves efficiency. Subsequently, it performs a fine scan within a reasonable range limited by the analog bandwidth. This scanning capability allows it to accurately capture the true signal frequency that is frequency-biased due to the Doppler effect, achieving true locking. Once the final center frequency is locked, the system adaptively sets the filter bandwidth to a specific multiple of that frequency, forming an extremely narrow, perfectly matched filtering window for the target signal, thereby accurately filtering out all residual sideband noise and maximizing the signal-to-noise ratio.

[0074] This application also provides an acoustic Doppler receiving signal processing device, which can perform acoustic Doppler receiving signal processing using the aforementioned acoustic Doppler receiving signal processing method 100, or other methods, which are not limited herein.

[0075] Figure 4 A first exemplary structural block diagram of an acoustic Doppler receiving signal processing apparatus according to an embodiment of this application is shown.

[0076] like Figure 4 As shown, the device 400 includes a low-noise tunable amplifier circuit 410, a fully differential amplifier circuit 420, a programmable bandpass filter 430, a fully differential analog-to-digital converter circuit 440, and an FPGA processing circuit 450.

[0077] Specifically, the low-noise tunable amplifier circuit 410 is used to perform a first-stage analog coarse-tuning filter on the received underwater acoustic signal.

[0078] Specifically, the fully differential amplifier circuit 420 is used to perform bandwidth compression filtering on the signal that has undergone the first stage of analog coarse-tuning filtering.

[0079] Specifically, the programmable bandpass filter 430 is used to perform a second-stage analog fine-tuning filter on the signal that has undergone bandwidth compression filtering.

[0080] Specifically, the fully differential analog-to-digital converter circuit 440 is used to convert the analog signal, which has undergone a second-stage analog fine-tuning filter, into a digital signal.

[0081] Specifically, the FPGA processing circuit 450 is used to perform a third-level digital fine-locked filtering process on the digital signal in the digital domain.

[0082] Figure 5 A second exemplary structural block diagram of an acoustic Doppler receiving signal processing apparatus according to an embodiment of this application is shown.

[0083] like Figure 5 As shown, the low-noise tunable amplifier circuit 410 includes a coupling capacitor 411, a tunable bandpass filter 412, an amplifier 413, and a first feedback capacitor 414. The fully differential amplifier circuit 420 includes an input capacitor 421, a fully differential amplifier 422, and a second feedback capacitor 423. The FPGA processing circuit 450 includes a digital FIR filter 451 and a digital phase-locked loop phase shifter 452.

[0084] Specifically, the coupling capacitor 411 and the input impedance of the tunable bandpass filter 412 form a first-order high-pass filter. The weak signal output by the acoustic transducer is filtered out by the first-order high-pass filter to remove low-frequency interference. The first feedback capacitor 414 and the feedback resistor of the amplifier 413 form a first-order low-pass filter to remove high-frequency interference. The tunable bandpass filter 412 is composed of an inductor and a varactor diode. Its filtering frequency is adaptively controlled by the FPGA. The amplifier 413 amplifies the signal with limited bandwidth after filtering out low-frequency and high-frequency interference and sends it to the fully differential amplifier circuit 420.

[0085] Specifically, the input capacitor 421 and the input resistor of the fully differential amplifier 422 form a first-order high-pass filter. The signal output by the low-noise tunable amplifier circuit 410 is filtered out for low-frequency interference by the first-order high-pass filter. The second feedback capacitor 423 and the feedback resistor of the fully differential amplifier 422 form a first-order low-pass filter to filter high-frequency interference. The fully differential amplifier 422 amplifies the signal after filtering out low-frequency and high-frequency interference and sends it to the programmable bandpass filter 430.

[0086] Specifically, the programmable bandpass filter 430 is a digital programmable bandpass filter with an SPI interface. Its center frequency and bandwidth can be controlled by FPGA circuitry to achieve second-stage analog fine-tuning filtering.

[0087] Specifically, the fully differential analog-to-digital converter circuit 440 performs high-speed oversampling on the limited bandwidth analog signal output by the programmable bandpass filter 430, and transmits the sampled data to the FPGA processing circuit 450 via the LVDS signal.

[0088] Specifically, the FPGA processing circuit 450 acquires the data output by the fully differential analog-to-digital converter circuit 440 through LVDS communication, and first performs third-stage adaptive bandpass filtering using a digital FIR filter 451 inside the FPGA. After bandpass filtering, the signal is phase-shifted by 90 degrees using a digital phase-locked loop phase shifter 452 inside the FPGA, thereby further realizing beamforming.

[0089] When the device 400 performs acoustic Doppler signal processing using the aforementioned acoustic Doppler receiving signal processing method 100, the aforementioned step S110 is executed by the low-noise tunable amplifier circuit 410, the aforementioned step S120 is executed by the fully differential amplifier circuit 420, the aforementioned step S130 is executed by the programmable bandpass filter 430, the aforementioned step S140 is executed by the fully differential analog-to-digital converter circuit 440, and the aforementioned step S150 is executed by the FPGA processing circuit 450. The specific execution process can be referred to above and will not be repeated here. Although several embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives can be conceived by those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein can be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. An acoustic Doppler received signal processing method, characterized by, The method comprises: performing first-stage analog coarse adjustment filtering processing on the received underwater acoustic signal through a low-noise tunable amplification circuit; performing bandwidth compression filtering processing on the signal subjected to the first-stage analog coarse adjustment filtering processing through a fully differential amplification circuit; performing second-stage analog fine adjustment filtering processing on the signal subjected to the bandwidth compression filtering processing through a programmable band-pass filter; converting the analog signal subjected to the second-stage analog fine adjustment filtering processing into a digital signal through a fully differential analog-to-digital conversion circuit; in the digital domain, performing third-stage digital fine locking filtering processing on the digital signal through an FPGA processing circuit.

2. The acoustic Doppler received signal processing method of claim 1, wherein, The low-noise tunable amplification circuit comprises a coupling capacitor, a tunable band-pass filter, an amplifier, and a first feedback capacitor; The first-stage analog coarse adjustment filtering processing comprises: controlling the center frequency and the bandwidth of the tunable band-pass filter through an FPGA, so that the center frequency of the tunable band-pass filter matches the center frequency of the working frequency band of the acoustic transducer receiving the underwater acoustic signal, and the bandwidth of the tunable band-pass filter is a first preset multiple of the working bandwidth of the acoustic transducer receiving the underwater acoustic signal.

3. The acoustic Doppler received signal processing method of claim 2, wherein, The first-stage analog coarse adjustment filtering processing further comprises: The received underwater acoustic signal is subjected to first-order high-pass filtering with a cutoff frequency of f H1 and first-order low-pass filtering with a cutoff frequency of f L1 , to obtain a first filtered signal; amplifying the first filtered signal through the amplifier and sending it to the fully differential amplification circuit; Wherein, the received underwater acoustic signal is processed by the first-order high-pass filtering with the cut-off frequency f H1 which is determined by the coupling capacitance and the input impedance of the tunable band-pass filter. The received underwater acoustic signal is subjected to a first-order low-pass filtering process with a cutoff frequency of f L1 by the first feedback capacitor and the feedback resistor of the amplifier.

4. The acoustic Doppler received signal processing method of claim 2, wherein, The fully differential amplification circuit comprises an input capacitor, a fully differential amplifier, and a second feedback capacitor; The bandwidth compression filtering processing comprises: The signal processed by the first-stage analog rough adjustment filtering is subjected to first-order high-pass filtering with a cutoff frequency of f H2 and first-order low-pass filtering with a cutoff frequency of f L2 , to obtain a second filtered signal. amplifying the second filtered signal through the fully differential amplifier and sending it to the programmable band-pass filter circuit; Wherein, the signal which has passed the first-stage analog coarse adjustment filtering processing is processed by the input capacitor and the input resistance of the full differential amplifier to be a first-order high-pass filtering processing with the cut-off frequency f H2 . The signal processed by the first-stage analog coarse adjustment filter is subjected to a first-order low-pass filter processing with a cutoff frequency of f L2 by the second feedback capacitor and the feedback resistor of the fully differential amplifier.

5. The acoustic Doppler received signal processing method of claim 4, wherein, The bandwidth of the second filtered signal ranges from f L3 -f H3 wherein, , , f o1 is the center frequency of the tunable bandpass filter and BW1 is the bandwidth of the tunable bandpass filter.

6. The acoustic Doppler received signal processing method of claim 2, wherein, The second-stage analog fine adjustment filtering processing comprises: setting the center frequency of the programmable band-pass filter to follow the center frequency of the tunable band-pass filter, and setting the bandwidth of the programmable band-pass filter to be a second preset multiple of the bandwidth of the signal subjected to the bandwidth compression filtering processing; filtering the signal subjected to the first-stage analog coarse adjustment filtering processing through the programmable band-pass filter with the settings completed to obtain a third filtered signal.

7. The acoustic Doppler received signal processing method of claim 2, wherein, The FPGA processing circuit comprises a digital FIR filter and a digital phase-locked loop phase shifter; The third-stage digital fine locking filtering processing comprises: preliminarily setting the center frequency of the digital FIR filter to follow the center frequency of the tunable band-pass filter; performing scanning within a frequency scanning range defined by the center frequency of the tunable band-pass filter to obtain a final center frequency of the digital FIR filter; setting the bandwidth of the digital FIR filter to be a third preset multiple of the final center frequency of the digital FIR filter; filtering the digital signal through the digital FIR filter with the settings completed to obtain a fourth filtered signal.

8. The acoustic Doppler received signal processing method of claim 7, wherein, the sweep range is [f o1 -2BW2,f o1 +2BW2]f o1 is the center frequency of the tunable bandpass filter, and BW2 is the bandwidth of the signal processed through the second stage of analog fine tuning filtering.

9. The acoustic Doppler received signal processing method of claim 7, wherein, After the third-stage digital fine locking filtering processing is performed, the signal subjected to the third-stage digital fine locking filtering processing is processed through the digital phase-locked loop phase shifter to generate a signal orthogonal to the signal subjected to the third-stage digital fine locking filtering processing.

10. An acoustic Doppler received signal processing apparatus, characterized by, The acoustic Doppler received signal processing method is used for acoustic Doppler received signal processing, and the device comprises: A low-noise tunable amplification circuit is used to perform a first-stage analog coarse adjustment filtering process on a received underwater acoustic signal; A fully differential amplification circuit is used to perform a bandwidth compression filtering process on the signal after the first-stage analog coarse adjustment filtering process; A programmable band-pass filter is used to perform a second-stage analog fine adjustment filtering process on the signal after the bandwidth compression filtering process; A fully differential analog-to-digital conversion circuit is used to convert the analog signal after the second-stage analog fine adjustment filtering process into a digital signal; An FPGA processing circuit is used to perform a third-stage digital fine locking filtering process on the digital signal in the digital domain.

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