Interrupt resource control method and device, processor, equipment, medium and product

Abstract

The invention relates to an interrupt resource control method and device, a processor, equipment, a medium and a product. The method is applied to an interrupt control center in a processor, and comprises the following steps: when it is detected that a starting moment of a new time window arrives, obtaining a statistical number of interrupt requests from the starting moment of the new time window to a current moment; according to the statistical number of the interrupt requests and a configured interrupt number threshold value, determining the delay duration of credit return; according to the delay duration of credit return, the credit of the target processing module is returned, and the target processing module is a processing module which sends an interrupt request to the interrupt control center and does not return the credit. By adopting the method, the interruption request loss caused by the overflow of the interruption request of the annular buffer area can be prevented, and the transmission reliability of the interruption request is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an interrupt resource control method, apparatus, processor, device, medium and product. Background Technology

[0002] In computer systems, interrupt mechanisms ensure overall system performance and responsiveness. Taking a GPU chip as an example, some of its internal processing modules, such as the GPU subsystem, need to report interrupt requests to provide feedback on their task completion status, error messages, and state changes when exceptions occur.

[0003] In related technologies, GPU chips do not have a central processing unit. Instead, an interrupt control center typically stores interrupt requests. When a processing module generates an interrupt request, it is written to the interrupt control center's circular buffer via a bus protocol. However, the interrupt control center deals with a large number of processing modules, and the number of interrupt requests acquired in a short period may exceed the storage capacity of the circular buffer. This can lead to interrupt request overflow in the circular buffer, resulting in interrupt requests being lost and causing malfunctions in the entire GPU chip.

[0004] Therefore, how to prevent interrupt request overflow from the circular buffer and thus interrupt request loss is a problem that urgently needs to be solved in this field. Summary of the Invention

[0005] Based on this, this application provides an interrupt resource control method, apparatus, processor, device, medium, and product that can prevent interrupt request overflow from the circular buffer and thus prevent interrupt request loss, thereby improving the reliability of interrupt request transmission.

[0006] Firstly, this application provides an interrupt resource control method, which is applied to the interrupt control center inside the processor, and the method includes:

[0007] If the start time of the new time window is detected, obtain the number of interruption requests from the start time of the new time window to the current time.

[0008] Based on the number of interrupt requests and the configured interrupt number threshold, the delay time for credit return is determined; the credit characterization processor sends the credentials required to the interrupt control center to send the interrupt request.

[0009] Based on the delay time of the credit return, the credit of the target processing module is returned. The target processing module is the processing module that issued an interrupt request to the interrupt control center but did not return the credit.

[0010] In some embodiments, the method further includes:

[0011] Get the end time of the previous time window;

[0012] If the time interval between the end of the previous time window and the current time reaches a preset time interval, then the start time of the new time window is determined; the end time of the new time window is the time interval between the start time of the new time window and the preset time interval.

[0013] In some embodiments, obtaining the number of interruption requests from the start time of the new time window to the current time includes:

[0014] Get the number of interruption requests received from the start time of the new time window to the current time;

[0015] The number of interrupt requests received is defined as the number of interrupt request statistics.

[0016] In some embodiments, the delay duration for credit return is determined based on the number of interruption requests and a configured interruption number threshold, including:

[0017] If the number of interruption requests is greater than or equal to the interruption number threshold, the delay time for credit return is determined to be a preset value; the preset value is greater than 0.

[0018] If the number of interruption requests is less than the interruption number threshold, the delay time for credit return is determined to be 0.

[0019] In some embodiments, the credit of the target processing module is returned based on the delay duration of the credit return, including:

[0020] Obtain the transmission time of the interrupt request sent by the interrupt control center to the target processing module;

[0021] Determine the target time based on the sending time and the delay duration of the credit return;

[0022] If the target time is reached, return the credit of the target processing module.

[0023] In some embodiments, determining the target time based on the sending time and the delay duration of the credit return includes:

[0024] If the number of interrupt requests at the time of transmission is less than the interruption threshold, the time of transmission will be determined as the target time.

[0025] If the number of interrupt requests at the time of transmission is greater than or equal to the interruption threshold, the target time is determined based on a set time with a delay duration greater than 0 starting from the time of transmission.

[0026] In some embodiments, determining the target time based on a set time with a delay duration greater than 0 starting from the transmission time includes:

[0027] If the set time is greater than or equal to the end time of the new time window, the end time of the new time window is determined as the target time.

[0028] If the set time is less than the end time of the new time window, the set time will be set as the target time.

[0029] In some embodiments, determining the target time based on a set time with a delay duration greater than 0 starting from the transmission time includes:

[0030] During the pending time between the sending time and the setting time, if the threshold mechanism enters the disabled state, the pending time will be determined as the target time.

[0031] In some embodiments, the method further includes:

[0032] At the end of the new time window, the interruption request count is reset to 0.

[0033] In some embodiments, the method further includes:

[0034] When the threshold mechanism is enabled, a default number of credits is allocated to each processing module in the processor; the default number is greater than 0.

[0035] In this system, a credit count greater than 0 for each processing module indicates that an interrupt request is allowed to be sent, while a credit count of 0 for each processing module indicates that an interrupt request is not allowed to be sent. Each processing module must decrement its own credit count by 1 for each interrupt request sent, and the interrupt control center must increment the credit count of at least one processing module by 1 for each interrupt request sent by at least one processing module.

[0036] In some embodiments, the method further includes:

[0037] When the threshold mechanism is enabled, the processor's internal threshold register, interval register, and count register are configured. The threshold register stores the interrupt count threshold, the interval register stores the delay duration, and the count register stores the interrupt request statistics.

[0038] Secondly, this application provides an interruption resource control device, which includes:

[0039] The acquisition module is used to acquire the statistical number of interruption requests from the start time of the new time window to the current time, when the start time of the new time window is detected.

[0040] The determination module is used to determine the delay time for credit return based on the number of interrupt requests and the configured interrupt number threshold; the processing module in the credit characterization processor sends the credentials required for the interrupt request to the interrupt control center.

[0041] The credit processing module is used to return the credit to the target processing module based on the delay time of the credit return. The target processing module is the processing module that issued an interrupt request to the interrupt control center but did not return the credit.

[0042] Thirdly, this application provides a processor including a memory, an interrupt control center, and multiple processing modules. The memory stores a computer program, and the multiple processing modules are communicatively connected to the interrupt control center. When the interrupt control center executes the computer program, it implements the steps of the method in any of the first aspects.

[0043] Fourthly, this application provides a computer device including the processor described above.

[0044] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method of any one of the first aspects.

[0045] In a sixth aspect, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method in any of the first aspects.

[0046] In the technical solution provided in this application embodiment, the delay time for credit return is determined based on the number of interrupt request statistics and the configured interrupt number threshold. The credit of the target processing module is returned based on the credit return delay time. Thus, the interrupt control center flexibly adjusts the time for returning credit to the processing module based on the current number of interrupt request statistics. This allows the reporting rate of interrupt requests from the processing module to be flexibly adjusted according to the number of interrupt request statistics, preventing interrupt requests from exceeding the storage capacity of the circular buffer. It effectively controls the interrupt resources used to store interrupt requests, preventing interrupt request overflow from the circular buffer and subsequent interrupt request loss, thereby improving the reliability of interrupt request transmission. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A schematic diagram of a data stream for an interruption request provided for some embodiments;

[0049] Figure 2 A flowchart illustrating an interruption resource control method provided in the first embodiment;

[0050] Figure 3 A flowchart illustrating an interruption resource control method provided in the second embodiment;

[0051] Figure 4 A flowchart illustrating an interruption resource control method provided in the third embodiment;

[0052] Figure 5 A flowchart illustrating an interruption resource control method provided in the fourth embodiment;

[0053] Figure 6 A flowchart illustrating an interruption resource control method provided in the fifth embodiment;

[0054] Figure 7 A flowchart illustrating an interruption resource control method provided in the sixth embodiment;

[0055] Figure 8 A flowchart illustrating an interruption resource control method provided in the seventh embodiment;

[0056] Figure 9 A schematic diagram illustrating the credit mechanism of the processing module and the interrupt control center provided in some embodiments;

[0057] Figure 10 A schematic diagram of the structure of an interrupt resource control device provided for some embodiments;

[0058] Figure 11 A schematic diagram of the processor structure provided for some embodiments;

[0059] Figure 12 A schematic diagram of the structure of a computer device provided for some embodiments. Detailed Implementation

[0060] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0062] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined. In the description of the embodiments of this application, "each" means each of the multiple options, unless otherwise explicitly defined.

[0063] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0064] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0065] The core of a System-on-Chip (SoC) is a system-level microchip that carries the modular circuitry required for a complete functional system. The Central Processing Unit (CPU), GPU, internal memory, input / output ports, and application-specific circuit blocks are all designed and integrated onto the same SoC. To achieve higher data transfer speeds, these modules typically use a high-speed Peripheral Component Interconnect express (PCIe) bus for end-to-end connectivity.

[0066] Interrupt requests (also known as interrupt messages or interrupt packets) are a self-reporting mechanism of processing modules (such as the GPU subsystem) designed to inform the host (such as the CPU) of their task completion status, error messages, and state changes. In one scenario, the GPU does not have a central processing unit internally. This means that when an exception occurs in the processing module, the error message is reported through the Message Signaled Interrupt (MSI) mechanism of the PCIe module. The process of the interrupt request traveling from the processing module to the PCIe module requires the interrupt control center to complete.

[0067] The interrupt control center plays the role of storing interrupt requests. When a processing module generates an interrupt request, it writes it to the circular buffer in the interrupt control center via a bus protocol. However, the interrupt control center deals with a large number of processing modules, and there may be situations where the number of interrupt requests exceeds the storage capacity of the circular buffer. If a critical interrupt request is lost, it may cause the entire GPU chip to malfunction. Therefore, preventing the circular buffer from overflowing is of paramount importance to the interrupt control center.

[0068] A circular buffer is divided into three modules: information input, information storage, and information output. Some technologies use a waterline to backpressure or discard interrupt requests during the storage phase. While this prevents circular buffer overflow, it can result in process termination or data loss.

[0069] The interrupt resource control method provided in this application places the operation means at the front end of the entire data flow. Therefore, this scheme anchors the input perspective and, together with the credit mechanism, precisely controls the write rate of interrupt requests, thereby realizing dynamic management of the circular buffer space.

[0070] Figure 1 A schematic diagram of a data stream for an interruption request is provided for some embodiments, such as Figure 1As shown, the interrupt reporting process consists of three stages: information input, information storage, and information output. When a processing module needs to report an interrupt request, it writes it to the circular buffer of the interrupt control center via Bus 1. To ensure the orderliness of interrupt request reporting, the process of each processing module sending an interrupt request is constrained. The interrupt control center pre-allocates a certain number of credits to each processing module. When a processing module sends a complete interrupt request to the interrupt control center, its credits are decremented by 1; as long as the processing module's credits are not zero, it does not affect the normal transmission of the next interrupt request. After the interrupt request arrives at the interrupt control center, it is stored in the circular buffer. When the number of interrupt requests accumulates to a certain value, the host is informed by updating the write pointer that the interrupt vectors in these interrupt requests need to be processed. Then, the interrupt requests in the circular buffer are written to the system memory via Bus 2 and the PCIe module. In this way, the host can process these interrupt vectors in the system memory through the interrupt routine. Thus, the process of interrupt request generation and processing forms a perfect closed loop.

[0071] Figure 2 A flowchart illustrating an interruption resource control method provided in the first embodiment is shown below. Figure 2 As shown, the method includes an interrupt control center applied within the processor, and the method includes the following steps:

[0072] S201. If the start time of the new time window is detected, obtain the number of interruption requests from the start time of the new time window to the current time.

[0073] The interrupt control center can store received interrupt requests in a circular buffer.

[0074] Unless otherwise specified, the processor in the embodiments of this application may include one or a combination of at least two of the following: GPU, CPU, Neural Network Processing Unit (NPU), Data Processing Unit (DPU), Tensor Processing Unit (TPU), Microcontroller Unit (MCU), Microprocessor Unit (MPU), etc. For example, the processor is a GPU, which may include multiple processing modules, each of which may be a GPU subsystem.

[0075] In some embodiments, the interrupt control center may be included within the GPU. In other embodiments, the interrupt control center may be located outside the GPU. The interrupt control center in the embodiments of this application may also be referred to as an interrupt controller, interrupt handling module, or interrupt handling unit, etc.

[0076] A circular buffer is a special type of buffer data structure used in GPUs to temporarily store data, enabling the GPU's processing units to efficiently acquire and process data. Data is sequentially placed into the circular buffer; when the circular buffer is full, new data overwrites the oldest data, forming a circular storage structure.

[0077] For example, the time windows are consecutive on the timeline, and the end time (also called the end time) of the current time window is the start time of the new time window. In some embodiments, a new time window with a duration equal to the preset time interval can be obtained at preset time intervals. For example, the preset time interval can be a pre-configured interval.

[0078] In some embodiments, detecting the start time of a new time window may include: detecting that the current time has reached the start time of the new time window. For example, the end time of the current time window may be determined as the start time of the new time window.

[0079] In some embodiments, obtaining the interrupt request statistics from the start time of the new time window to the current time may include: obtaining the number of interrupt requests received from the start time of the new time window to the current time, and determining the number of interrupt requests received as the interrupt request statistics. In other embodiments, obtaining the interrupt request statistics from the start time of the new time window to the current time may include: obtaining the number of interrupt requests received between the start time of the new time window and the current time; obtaining the number of interrupt requests sent from the interrupt control center among the interrupt requests received between the start time of the new time window and the current time; and determining the difference between the number of interrupt requests received and the number of interrupt requests sent as the interrupt request statistics at the current time. For example, the number of interrupt requests sent may be the number of interrupt requests sent out by the interrupt control center from the circular buffer via the bus.

[0080] The processor includes multiple processing modules. For example, each processing module can send an interrupt request to the interrupt control center, which stores the interrupt request in its circular buffer.

[0081] The interrupt request count changes dynamically over time. In some embodiments, a counter can be used to count the interrupt requests at the current moment. The counter can be pre-configured by the interrupt control center. In some embodiments, the counter can count the interrupt requests once per clock cycle of a new time window. For example, if the current counter value is 9, and 2 new interrupt requests are stored in the circular buffer in the next clock cycle, the counter value will change to 11 regardless of whether the interrupt control center issues an interrupt request in the next clock cycle.

[0082] S202. Determine the delay duration for credit return based on the number of interruption requests and the configured interruption threshold.

[0083] The credit representation processor sends the credentials required to the interrupt control center to send an interrupt request.

[0084] For example, the interrupt count threshold can be a pre-configured value. For example, the interrupt count threshold can be stored in a pre-configured threshold register.

[0085] In some embodiments, the interruption number threshold may be less than the maximum number of interruption requests that the circular buffer can cache. Exemplarily, the interruption number threshold can be determined based on the maximum number of interruption requests that the circular buffer can cache. For example, the interruption number threshold can be the maximum number of interruption requests that the circular buffer can cache multiplied by the rounded value of a preset coefficient, for example, the preset coefficient can be a real number greater than 0 and less than 1. For example, the preset coefficient is between 0.2 and 0.8. For example, the preset coefficient can be 0.2, 0.4, 0.6, or 0.8.

[0086] In some embodiments, the delay duration for credit return can be determined based on whether the number of interruption requests is greater than or equal to a configured interruption number threshold. For example, if the number of interruption requests is greater than or equal to the configured interruption number threshold, the delay duration for credit return is determined as a first delay duration; if the number of interruption requests is less than the configured interruption number threshold, the delay duration for credit return is determined as a second delay duration, where the first delay duration is greater than the second delay duration. For example, the second delay duration can be 0.

[0087] In some embodiments, different processing modules maintain different credit registers, each credit register storing the credits of its respective processing module. In other embodiments, at least two processing modules may maintain the same credit register, which stores the total credits of the at least two processing modules. Each processing module is eligible to send an interrupt request to the circular buffer only if the number of credits in its corresponding credit register is greater than 0; if the number of credits in its corresponding credit register is 0, it is not eligible to send an interrupt request to the circular buffer. If a processing module is eligible to send an interrupt request to the circular buffer, the interrupt request can be sent from that processing module to the interrupt control center. If a processing module is not eligible to send an interrupt request to the circular buffer, the interrupt request cannot be sent from that processing module to the interrupt control center.

[0088] Sending an interrupt request from the processing module to the circular buffer may include: sending the interrupt request to the interrupt control center so that the interrupt control center writes the interrupt request to the circular buffer.

[0089] For any processing module, if it sends an interrupt request to the circular buffer, the credit count corresponding to that processing module is reduced by one.

[0090] For the interrupt control center, for each interrupt request issued from the circular buffer, the credit count corresponding to the target processing module that sent the interrupt request is incremented by one.

[0091] S203. Based on the delay time of the credit return, return the credit of the target processing module.

[0092] The target processing module is the module that processes interrupt requests issued by the interrupt control center but has not returned a response.

[0093] In some embodiments, returning the credit of the target processing module based on the credit return delay may include: returning the credit of the target processing module after an interval of the credit return delay. In other embodiments, returning the credit of the target processing module based on the credit return delay may include: determining a target time (e.g., a target clock cycle) based on the credit return delay, and returning the credit of the target processing module based on the target time. Exemplarily, returning the credit of the target processing module based on the target time may include returning the credit of the target processing module at the target time, or returning the credit of the target processing module at the next moment after the target time (e.g., the next clock cycle of the target clock cycle).

[0094] For example, the target processing module may include the processing module to which the interrupt request issued by the interrupt control center after the current moment belongs. The target processing module may be one processing module or at least two processing modules.

[0095] In some embodiments, the method may further include: setting the credit count of all processing modules to zero when the number of interrupt requests stored in the circular buffer reaches the maximum number of interrupt requests that the circular buffer can store, in order to avoid losing interrupt requests.

[0096] In the technical solution provided in this application embodiment, the delay time for credit return is determined based on the number of interrupt request statistics and the configured interrupt number threshold. The credit of the target processing module is returned based on the credit return delay time. Thus, the interrupt control center flexibly adjusts the time for returning credit to the processing module based on the current number of interrupt request statistics. This allows the reporting rate of interrupt requests from the processing module to be flexibly adjusted according to the number of interrupt request statistics, preventing interrupt requests from exceeding the storage capacity of the circular buffer. It effectively controls the interrupt resources used to store interrupt requests, preventing interrupt request overflow from the circular buffer and subsequent interrupt request loss, thereby improving the reliability of interrupt request transmission.

[0097] In some embodiments, the method may further include: obtaining the end time of the previous time window; if the duration between the end time and the current time reaches a preset time interval, then determining the start time of the current arrival at the new time window.

[0098] In other embodiments, the method may further include: obtaining the end time of the current time window and determining the end time of the current time window as the start time of a new time window.

[0099] In some embodiments, the end time of the new time window is the time interval between the start time of the new time window and a preset time interval.

[0100] In the technical solution provided by this application embodiment, a new time window is reached at a preset time interval, and the interrupt request statistics are re-counted at the start of each new window. In this way, at least at the start of the new time window, the interrupt request statistics are less than the configured interrupt number threshold, thereby avoiding the interrupt control center from being in a state of delayed return of credit. Therefore, this application embodiment can improve the effectiveness of interrupt reporting.

[0101] Figure 3 A flowchart illustrating an interruption resource control method provided in the second embodiment is shown below. Figure 3 As shown, the method includes an interrupt control center applied within the processor. Figure 3 Compared to the example Figure 2 The difference in the embodiments is that S201 may include the following steps S2011 to S2012:

[0102] S2011. If the start time of the new time window is detected, obtain the number of interrupt requests received from the start time of the new time window to the current time.

[0103] In this embodiment of the application, at the start of the new time window, the circular buffer may still store interrupt requests. However, this embodiment of the application does not count the number of interrupt requests that have been stored since the start of the new time window. Instead, it counts the number of interrupt requests received and written to the circular buffer starting from 0.

[0104] For example, at the start time t0 of the new time window, the circular buffer still stores 5 interrupt requests. However, the number of these 5 interrupt requests is not counted in the new time window, and the counter value (including the interrupt request count) should be 0. At time t1, 3 interrupt requests are written to the circular buffer, so the number of interrupt requests received from the start time t0 of the new time window to time t1 is determined to be 3. At time t2, 2 interrupt requests are written to the circular buffer, so the number of interrupt requests received from the start time t0 of the new time window to time t2 is determined to be 5.

[0105] For example, if a processing module successfully sends an interrupt message to the interrupt control center, it raises a flag. The interrupt control center samples the flag at each rising edge of the clock. For instance, if a flag is sampled, the counter is incremented by 1 to obtain the number of interrupt requests received from the start of the new time window to the current time.

[0106] S2012. The number of interrupt requests received is determined as the number of interrupt request statistics.

[0107] In the technical solution provided in this application embodiment, by obtaining the number of interrupt request receptions from the start time of the new time window to the current time, the number of interrupt request receptions is determined as the number of interrupt request statistics, so that the transmission of interrupt requests is no longer affected by the high latency of the return to the target processing module in the previous time window of the new time window.

[0108] Figure 4 A flowchart illustrating an interruption resource control method provided in the third embodiment is shown below. Figure 4 As shown, the method includes an interrupt control center applied within the processor. Figure 4 Compared to the example Figure 2 The difference in the embodiments is that S202 may include the following steps S2021 and S2022:

[0109] S2021. If the number of interruption requests is greater than or equal to the interruption number threshold, the delay time for credit return is determined to be a preset value; the preset value is greater than 0.

[0110] In some embodiments, the preset values ​​corresponding to different processing modules may be the same. In other embodiments, the preset values ​​corresponding to different processing modules may be the same. For example, the preset value corresponding to a high-priority processing module may be lower than the preset value corresponding to a low-priority processing module.

[0111] For example, the preset value can be greater than or equal to 1 clock cycle. For example, the preset value can range from 1 clock cycle to 50 clock cycles. For instance, the preset value can be 1 clock cycle, 2 clock cycles, 5 clock cycles, 10 clock cycles, 20 clock cycles, or 50 clock cycles, etc. In some embodiments, the preset value should be less than or equal to the interval of the new time window.

[0112] For example, when the credit return delay is a preset value, returning the credit of the target processing module based on the credit return delay may include: obtaining the sending time of the interrupt request from the interrupt control center; determining the target time based on the sending time and the credit return delay; and returning the credit of the target processing module based on the target time. For example, returning the credit of the target processing module based on the target time may include: returning the credit of the target processing module at the target time. Yet another example, returning the credit of the target processing module based on the target time may include: returning the credit of the target processing module at the time following the target time.

[0113] S2022. If the number of interruption requests is less than the interruption number threshold, determine that the delay time for credit return is 0.

[0114] For example, when the credit return delay is 0, returning the credit of the target processing module according to the credit return delay may include: returning the credit of the target processing module at the current moment (e.g., the current clock cycle), or returning the credit of the target processing module at the next moment (e.g., the next clock cycle).

[0115] In the technical solution provided in this application embodiment, the delay time for credit return is determined by judging whether the number of interrupt request statistics is greater than or equal to the interrupt number threshold. The delay time for returning credit to the target processing module is either greater than 0 or equal to 0. This improves the effectiveness of interrupt resource control by flexibly determining the delay time for returning credit to the target processing module based on the number of interrupt request statistics.

[0116] Figure 5A flowchart illustrating an interruption resource control method provided in the fourth embodiment is shown below. Figure 5 As shown, the method includes an interrupt control center applied within the processor. Figure 5 Compared to the example Figure 2 The difference in the embodiments is that S203 may include the following steps S2031 and S2033:

[0117] S2031. Obtain the sending time of the interrupt request from the interrupt control center to the target processing module.

[0118] For example, when the target clock cycle interrupt control center issues an interrupt request to the target processing module, the transmission time is the target clock cycle.

[0119] S2032. Determine the target time based on the sending time and the delay duration of the credit return.

[0120] For example, when the delay duration is greater than 0, the target time is determined by setting a time with a delay duration greater than 0 starting from the transmission time. For example, when the delay duration is 0, the current time or the next time after the current time is determined as the target time.

[0121] S2033. If the target time is reached, return the credit of the target processing module.

[0122] In the technical solution provided in this application embodiment, the target time is determined based on the sending time of the interrupt request sent by the interrupt control center to the target processing module and the delay time of credit return. The credit of the target processing module is returned at the target time, thereby enabling the credit of the target processing module to be returned at a precise time point, which improves the accuracy and precision of data processing.

[0123] In some embodiments, determining the target time based on the sending time and the delay duration of credit return includes: determining the sending time as the target time if the number of interruption requests at the sending time is less than the interruption number threshold.

[0124] In some embodiments, determining the target time based on the sending time and the delay duration of credit return includes: if the number of interruption requests at the sending time is greater than or equal to the interruption number threshold, determining the target time based on a set time with a delay duration greater than 0 starting from the sending time.

[0125] In the technical solution provided in this application embodiment, when the number of interrupt requests at the sending time is less than the interrupt number threshold, the sending time is determined as the target time. When the number of interrupt requests at the sending time is greater than or equal to the interrupt number threshold, the target time is determined according to a set time with a delay duration greater than 0 starting from the sending time. The target time can be flexibly determined based on the number of interrupt requests at the sending time, so that the determination of the target time matches the reporting rate of interrupt requests reported by the processing module, thereby improving the utilization rate of interrupt resources.

[0126] In some embodiments, determining the target time based on a set time with a delay duration greater than 0 starting from the transmission time includes: if the set time is greater than or equal to the end time of the new time window, determining the end time of the new time window as the target time.

[0127] In some embodiments, determining the target time based on a set time with a delay duration greater than 0 starting from the transmission time includes: determining the set time as the target time if the set time is less than the end time of the new time window.

[0128] The technical solution provided in this application embodiment enables the target time to always be within the current new time window, thereby avoiding the impact of the target time on the number of interruption requests counted in the next time window, avoiding cross-window interference, and improving the accuracy of the interruption request count.

[0129] In some embodiments, determining the target time based on a set time with a delay duration greater than 0 starting from the transmission time includes: determining the undetermined time as the target time when the threshold mechanism enters a disabled state during an undetermined time between the transmission time and the set time.

[0130] In the technical solution provided in this application embodiment, a threshold mechanism is used to enable interrupt control center so that it no longer returns credit with a delay time greater than 0, thereby improving the efficiency of the processing module in reporting interrupt requests.

[0131] Figure 6 A flowchart illustrating an interruption resource control method provided in the fifth embodiment is shown below. Figure 6 As shown, the method includes an interrupt control center applied within the processor. Figure 6 Compared to the example Figure 2 The difference in the embodiments is that S204 may be included after S203:

[0132] S204. At the end of the detection period of the new time window, reset the interruption request count to 0.

[0133] For example, the counter's count value is reset to 0.

[0134] In the technical solution provided in this application embodiment, when the end of the new time window is detected, the interrupt request statistics are reset to 0, so that the processing module whose interrupt request reporting rate is restricted is no longer constrained, and all processing modules can send interrupt requests in a normal manner. That is, after the interrupt control center receives the interrupt request, it will immediately return a credit. In the next time window after the new time window, the interrupt request statistics will be recounted from 0, and the cycle will continue, thereby realizing dynamic management of the circular buffer space.

[0135] Figure 7 A flowchart illustrating an interruption resource control method provided in the sixth embodiment is shown below. Figure 7 As shown, the method includes an interrupt control center applied within the processor. Figure 7 Compared to the example Figure 2 The difference in the embodiments is that S205 may be included before S201:

[0136] S205. When the threshold mechanism is enabled, allocate a default number of credits to each processing module in the processor; the default number is greater than 0.

[0137] In this system, a credit count greater than 0 for each processing module indicates that an interrupt request is allowed to be sent, while a credit count of 0 for each processing module indicates that an interrupt request is not allowed to be sent. Each processing module must decrement its own credit count by 1 for each interrupt request sent, and the interrupt control center must increment the credit count of at least one processing module by 1 for each interrupt request sent by at least one processing module.

[0138] In some embodiments, the same amount of credits is allocated to different processing modules. In other embodiments, the amount of credits can be allocated to each processing module according to its processing priority, so that different amounts of credits are allocated to processing modules with different processing priorities.

[0139] In the technical solution provided in this application embodiment, when the threshold mechanism is enabled, a default number of credits are allocated to each processing module in the processor, so that each processing module is qualified to report an interrupt request to the interrupt control center.

[0140] In some embodiments, the method further includes configuring the threshold register, interval register, and quantity register inside the processor when the threshold mechanism is enabled; wherein the threshold register is used to store the interrupt quantity threshold, the interval register is used to store the delay duration, and the quantity register is used to store the interrupt request statistics.

[0141] This application's embodiments can address the problem of circular buffer overflow caused by interrupt storms. Some embodiments propose a scheme to set an interrupt quantity threshold before interrupt request input, which can reduce the reporting rate of interrupt requests during write operations. An interrupt storm refers to a phenomenon where the interrupt control center receives a large number of interrupt requests in a short period, causing it to be busy processing these interrupts and unable to perform other tasks normally, resulting in a significant decrease in system performance or even system paralysis.

[0142] By advancing the operation implementation phase to before the interrupt request input, the space left for subsequent operations is very small once the circular buffer has stored the interrupt request, which can easily lead to the loss of some critical information. Therefore, this application embodiment brings a certain degree of security to the entire system by handling the interrupt storm problem as early as possible.

[0143] This application's embodiment optimizes the credit mechanism. Traditional solutions typically use a halt to return credits to pressure the processing module, preventing corresponding interrupt requests from being written to the circular buffer and causing process blocking. This application's embodiment, however, slows down the rate at which specific processing modules send interrupt requests by increasing the credit return time, thus ensuring the continuous existence of the interrupt reporting path for the processing module.

[0144] In some embodiments, this application provides a loop with multiple time intervals. When a time window ends, the mechanism automatically resets the counter value and enters the next time window, restarting the count from 0. During this process, the host may resolve the interrupt storm problem in the processing module, without affecting the inflow of subsequent interrupt requests, thus ensuring the orderly progress of the overall process.

[0145] The interrupt resource control method provided in this application is a threshold-based interrupt resource management method, comprising three modules: a register configuration module, a counting module, and a delay module. The register configuration module is used to configure relevant registers, the counting module is used to obtain the number of interrupt requests in the circular buffer at the current time (e.g., the counting module can be a counter), and the delay module can be used to control the delay duration.

[0146] Figure 8 A flowchart illustrating an interruption resource control method provided in the seventh embodiment is shown below. Figure 8 As shown, the method includes the following steps:

[0147] S801, Configure threshold enable.

[0148] S802, Configure Time Window.

[0149] S803, Configure the threshold for the number of interrupts.

[0150] S804. Count the number of interrupt requests within the current time window.

[0151] S805. Determine whether the number of interrupt requests is greater than or equal to the interrupt number threshold.

[0152] If S805 is true, execute S806; if S805 is false, execute S808.

[0153] S806. Immediately increase the credit return time to slow down the rate at which subsequent processing modules send interruption requests within the current time window.

[0154] S807. The current time window has ended, and the next time window will begin.

[0155] S808: Do not increase credit return time so as not to affect the normal sending of interruption requests by the processing module.

[0156] After S808, execution restarts from S804.

[0157] When the threshold mechanism is enabled, the interrupt control center enters the register configuration phase. First, it configures the interval used to form the time window. Based on the interval, the entire timeline is divided into multiple intervals, the size of which is configured based on multiple SOC clock cycles. Within this interval, this embodiment focuses specifically on two values: the number of interrupt requests sent by the processing module (count) and the interrupt count threshold configured in the register (max_value). Each time the processing module writes an interrupt request, the counter increments the count by 1. When the counter reaches the interrupt count threshold (max_value), the delay module is activated.

[0158] Normally, when the interrupt control center receives an interrupt request from a processing module, it immediately returns a credit to that module. However, in some exceptional cases, a particular processing module generates a large number of interrupt requests within a short period. This embodiment of the application requires a delay in the credit return time to prevent the processing module from sending interrupt requests smoothly. This delay is pre-set during the register configuration phase. This obstacle will not persist indefinitely. For example, upon recognizing the end of an interval, regardless of whether the set interrupt quantity threshold was reached within that time window or whether a credit return delay occurred, the interrupt request count recorded by the aforementioned counter will immediately be reset to zero. Then, the next interval will begin, at which point the processing module can send interrupt requests normally, and the above process will be repeated. Of course, all parameters in the entire scheme are configurable and will be matched to specific scenarios.

[0159] In this embodiment, the information transmission rate can be controlled during the interrupt request input stage to prevent adjustment at the storage stage, thus avoiding the loss of important interrupt requests due to ring buffer overflow. All required parameters in this embodiment are configured using registers, allowing for dynamic adjustment for different application scenarios to achieve both security and performance guarantees. This embodiment effectively reduces the amount of information flowing into the ring buffer per unit time, significantly alleviating the storage operation pressure on the ring buffer. The process in this embodiment is simple, implemented through three steps: counting, judgment, and delay.

[0160] This application focuses on limiting the inflow rate of interrupt requests during the interrupt request input phase, and the main part of this is accomplished through a credit mechanism.

[0161] Figure 9 A schematic diagram illustrating the credit mechanism of the processing module and interrupt control center provided in some embodiments, such as... Figure 9As shown, the interrupt control center allocates n credits (where n is an integer greater than or equal to 1) to each processing module. These credits can be viewed as keys; a processing module needs credits to be eligible to write an interrupt request to the ring buffer. Before a processing module sends an interrupt request to the ring buffer, the interrupt control center suspends a credit check to determine if the module has enough credits to support a valid interrupt request inflow. If the module doesn't have enough, it is disqualified from sending an interrupt request; this can be considered a reverse-push. Typically, the interrupt control center allocates two credits to each processing module, meaning each module can continuously send two interrupt requests to the ring buffer. Once the interrupt control center issues an interrupt request from a processing module, it returns one credit to that module, thus granting it the right to send another interrupt request. This embodiment of the application precisely controls the timing and speed of interrupt request sending by changing the delay duration of the credit return.

[0162] against Figure 9 The processing module shown consumes one credit for each terminal request it sends. The interrupt control center returns one credit after a delay or immediately for each interrupt request it issues. The processing module can determine its own credit count n; if n is greater than or equal to 1, it can send an interrupt request; if n equals 0, it cannot report an interrupt request.

[0163] The interrupt control center maintains a credit queue for each processing module. This credit queue can be First Input First Output (FIFO) and stores credits. Each time a processing module sends an interrupt request to the interrupt control center, it retrieves one credit from the credit FIFO. Whenever the interrupt control center outputs an interrupt request from a processing module in a circular buffer, it returns one credit to that processing module's credit FIFO. In some embodiments, a credit may be returned to the processing module's credit FIFO immediately or with a delay.

[0164] In other embodiments, the interrupt control center maintains a credit value for each processing module. Each time a processing module sends an interrupt request to the interrupt control center, its credit value is decremented by one. Each time the interrupt control center outputs an interrupt request from a processing module's circular buffer, its credit value is incremented by one. In some embodiments, the credit value of a processing module may be incremented immediately or with a delay.

[0165] In some embodiments, the interrupt control center maintains a credit FIFO or credit value internally. In other embodiments, the credit FIFO or credit value may be stored in a register outside the interrupt control center.

[0166] For example, each interrupt request sent by a processing module consists of 8 packets, and each interrupt request is 256 bits in size. For example, a total of 64 processing modules can send interrupt requests to the interrupt control center. Inside the interrupt control center, there are generally two types of buffers. The first is a circular buffer that stores interrupt requests, with a width of 256 bits, corresponding to the size of one interrupt request. To prevent overflow, its depth is generally set to 16 to 65536 bytes. The second is a credit buffer that stores credits, corresponding to the 64 processing modules, with each processing module having 2 credits, for a total of 128 credits. For example, the credit buffer has a width of 6 bits and a depth of 128 bits.

[0167] For example, the interrupt control center can determine the credit return method based on the interrupt request sent by the processing module. The specific operation is as follows:

[0168] When the interrupt number threshold mechanism enable register of the interrupt control center is configured to 1, this scheme configures the interrupt number threshold and the size of the time window through the max_value and interval registers. For example, the interrupt number threshold is set to A.

[0169] When the interrupt control center is running, it divides the total timeline into time windows of size interval. For example, if the interval register value is 8, the actual size of each time window is considered to be 3 (log28) clock cycles. As another example, if the interval register value is 8, the actual size of each time window is considered to be 8 clock cycles. Simultaneously, a counter begins counting the number of interrupt requests, and the results are written to the count register. This embodiment assumes the number of interrupt requests is B.

[0170] Taking the third time window as an example, starting from the beginning of the third time window, as time progresses, the number of interrupt requests (B) sent by the processing module within the third time window exceeds the interrupt number threshold (A). At this point, a delay phase is required. Credits are no longer returned immediately; the interrupt control center returns them to the processing module after a delay of the specified value. When a specific processing module (e.g., the module with 0 credits) does not receive any credits, it will not initiate the next interrupt until the delay ends. This process avoids a circular buffer overflow caused by an interrupt storm generated by a processing module within a unit of time. This mechanism applies to all exception handling modules; as long as the number of interrupt requests sent by a processing module exceeds the interrupt number threshold, the interrupt write rate of that processing module will be limited.

[0171] At the end of the third time window, the above statistical result, count, will be immediately cleared to zero, and the process will enter the next configured time window. At this time, the processing modules whose rates are limited are no longer constrained and can send interrupt requests in a normal manner. That is, the circular buffer will immediately return a credit after receiving the interrupt request, and the subsequent process will repeat the above steps.

[0172] Based on the same inventive concept, this application also provides an interrupt resource control device for implementing the interrupt resource control method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more interrupt resource control device embodiments provided below can be found in the limitations of the interrupt resource control method described above, and will not be repeated here.

[0173] In one exemplary embodiment, Figure 10 A schematic diagram of the structure of the interrupt resource control device provided in some embodiments, such as Figure 10 As shown, the interruption resource control device includes:

[0174] The acquisition module is used to acquire the statistical number of interruption requests from the start time of the new time window to the current time, when the start time of the new time window is detected.

[0175] The determination module is used to determine the delay time for credit return based on the number of interrupt requests and the configured interrupt number threshold; the processing module in the credit characterization processor sends the credentials required for the interrupt request to the interrupt control center.

[0176] The credit processing module is used to return the credit to the target processing module based on the delay time of the credit return. The target processing module is the processing module that issued an interrupt request to the interrupt control center but did not return the credit.

[0177] In some embodiments, the acquisition module is further configured to acquire the end time of the previous time window; the determination module is further configured to determine the start time of the new time window if the duration between the end time of the previous time window and the current time reaches a preset time interval; the end time of the new time window is the time interval between the start time of the new time window and the preset time interval.

[0178] In some embodiments, the acquisition module includes an acquisition unit and a determination unit. The acquisition unit is used to acquire the number of interrupt requests received from the start time of the new time window to the current time. The determination unit is used to determine the number of interrupt requests received as the number of interrupt requests counted.

[0179] In some embodiments, the determining module includes a determining unit, which is configured to determine the delay time of credit return as a preset value when the number of interruption requests is greater than or equal to the interruption number threshold; the preset value is greater than 0; and to determine the delay time of credit return as 0 when the number of interruption requests is less than the interruption number threshold.

[0180] In some embodiments, the credit processing module includes an acquisition unit, a determination unit, and a credit processing unit; the acquisition unit is used to acquire the transmission time of the interrupt request sent by the interrupt control center to the target processing module; the determination unit is used to determine the target time based on the transmission time and the delay duration of the credit return; the credit processing unit is used to return the credit of the target processing module when the target time is reached.

[0181] In some embodiments, the determining unit is further configured to determine the sending time as the target time when the number of interrupt requests at the sending time is less than the interrupt number threshold; and to determine the target time based on a set time with a delay duration greater than 0 starting from the sending time when the number of interrupt requests at the sending time is greater than or equal to the interrupt number threshold.

[0182] In some embodiments, the determining unit is further configured to determine the end time of the new time window as the target time when the set time is greater than or equal to the end time of the new time window; and to determine the set time as the target time when the set time is less than the end time of the new time window.

[0183] In some embodiments, the determining unit is further configured to determine the pending time as the target time when the threshold mechanism enters a disabled state during the pending time between the sending time and the setting time.

[0184] In some embodiments, the interruption resource control device further includes a reset module for resetting the interruption request count to 0 at the time when the end of the new time window is detected.

[0185] In some embodiments, the interrupt resource control device further includes a credit allocation module for allocating a default number of credits to each processing module in the processor when the threshold mechanism is enabled; the default number is greater than 0.

[0186] In this system, a credit count greater than 0 for each processing module indicates that an interrupt request is allowed to be sent, while a credit count of 0 for each processing module indicates that an interrupt request is not allowed to be sent. Each processing module must decrement its own credit count by 1 for each interrupt request sent, and the interrupt control center must increment the credit count of at least one processing module by 1 for each interrupt request sent by at least one processing module.

[0187] In some embodiments, the interrupt resource control device further includes a configuration module for configuring the threshold register, interval register, and quantity register inside the processor when the threshold mechanism is enabled; wherein the threshold register is used to store the interrupt quantity threshold, the interval register is used to store the delay duration, and the quantity register is used to store the interrupt request statistics.

[0188] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0189] Each module in the aforementioned interrupt resource control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0190] Figure 11 A schematic diagram of the processor structure provided for some embodiments, such as Figure 11 As shown, the processor includes an interrupt control center and multiple processing modules. The multiple processing modules are communicatively connected to the interrupt control center. When the interrupt control center executes a computer program, it implements the steps of the method provided in any of the above embodiments.

[0191] For example, when the interrupt control center executes a computer program, it performs the following: upon detecting the arrival of the start time of a new time window, it obtains the statistical number of interrupt requests from the start time of the new time window to the current time; based on the statistical number of interrupt requests and a configured interrupt number threshold, it determines the delay duration for credit return; the credit characterizes the credentials required for the processing module in the processor to send an interrupt request to the interrupt control center; and based on the delay duration for credit return, it returns the credit of the target processing module, which is the processing module that issued the interrupt request to the interrupt control center but did not return the credit.

[0192] In one exemplary embodiment, Figure 12This is a schematic diagram of a computer device provided for some embodiments. The computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for wired or wireless communication with external terminals. Wireless communication can be implemented through Wireless Fidelity (WIFI), mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements an interrupt resource control method. The display unit of the computer device is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0193] Those skilled in the art will understand that Figure 12 The structures shown are merely block diagrams of some structures related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements. For example, a computer device may include the processor described above.

[0194] In one embodiment, a computer-readable storage medium is provided, wherein a computer program, when executed by a processor, implements the steps of the method provided in any of the above embodiments.

[0195] For example, in one exemplary embodiment, a computer-readable storage medium is provided having a computer program stored thereon. When executed by a processor, the computer program performs the following steps: upon detecting the arrival of the start time of a new time window, obtaining the number of interrupt requests from the start time of the new time window to the current time; determining the delay duration for credit return based on the number of interrupt requests and a configured interrupt number threshold; the credit characterizes the credentials required for a processing module in the processor to send an interrupt request to the interrupt control center; and, based on the delay duration for credit return, returning the credit of a target processing module, which is a processing module that issued an interrupt request to the interrupt control center but did not return a credit.

[0196] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method provided in any of the above embodiments.

[0197] For example, in one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps: upon detecting the arrival of the start time of a new time window, obtaining the number of interrupt request statistics from the start time of the new time window to the current time; determining the delay duration for credit return based on the number of interrupt request statistics and a configured interrupt number threshold; the credit characterizes the credentials required for a processing module in the processor to send an interrupt request to the interrupt control center; and, based on the delay duration for credit return, returning the credit of a target processing module, which is a processing module that issued an interrupt request to the interrupt control center but did not return credit.

[0198] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the methods described above.

[0199] The processor, functional modules, or functional units in any embodiment of this application may include an integration of one or more of the following: a general-purpose processor, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field-programmable gate array (FPGA), a CPU, a GPU, an NPU, a controller, a microcontroller, a microprocessor, a programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, a quantum computing-based data processing logic unit, an artificial intelligence (AI) processor, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0200] The memory or computer-readable storage medium in any embodiment of this application may include at least one of non-volatile memory and volatile memory. Non-volatile memory includes integration of one or more of the following: Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory, Optical Disc, Compact Disc Read-Only Memory (CD-ROM), Magnetic Tape, Floppy Disk, Flash Memory, Optical Memory, High-Density Embedded Non-Volatile Memory, Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Graphene Memory, Volatile Memory, etc. Volatile memory includes one or more of the following: Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0201] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0202] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application's patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for controlling interrupted resources, characterized in that, An interrupt control center applied within a processor, the method comprising: If the start time of a new time window is detected, the number of interruption requests from the start time of the new time window to the current time is obtained. The delay time for credit return is determined based on the number of interrupt requests and the configured interrupt number threshold; the credit represents the credentials required for the processing module in the processor to send an interrupt request to the interrupt control center. Based on the delay time of the credit return, the credit of the target processing module is returned. The target processing module is the processing module that issued an interrupt request to the interrupt control center but did not return the credit.

2. The method according to claim 1, characterized in that, The method further includes: Get the end time of the previous time window; If the time interval between the end of the previous time window and the current time reaches a preset time interval, then the start time of the new time window is determined; the end time of the new time window is the time interval between the start time of the new time window and the preset time interval.

3. The method according to claim 1 or 2, characterized in that, The step of obtaining the number of interruption requests from the start time of the new time window to the current time includes: Get the number of interruption requests received from the start time of the new time window to the current time; The number of interrupt requests received is determined as the number of interrupt requests counted.

4. The method according to claim 1 or 2, characterized in that, The step of determining the delay duration for credit return based on the statistical number of interruption requests and the configured interruption number threshold includes: If the number of interruption requests is greater than or equal to the interruption number threshold, the delay time for credit return is determined to be a preset value; the preset value is greater than 0. If the number of interruption requests is less than the interruption number threshold, the delay time for credit return is determined to be 0.

5. The method according to claim 1 or 2, characterized in that, The step of returning the credit of the target processing module based on the delay duration returned by the credit includes: Obtain the sending time of the interrupt request sent by the interrupt control center to the target processing module; The target time is determined based on the sending time and the delay duration of the credit return. Upon reaching the target time, the credit of the target processing module is returned.

6. The method according to claim 5, characterized in that, Determining the target time based on the sending time and the delay duration of the credit return includes: If the number of interruption requests at the specified transmission time is less than the interruption number threshold, the transmission time is determined as the target time. If the number of interruption requests at the transmission time is greater than or equal to the interruption number threshold, the target time is determined based on a set time with a delay duration greater than 0 starting from the transmission time.

7. The method according to claim 6, characterized in that, Determining the target time based on a set time with a delay duration greater than 0, starting from the transmission time, includes: If the set time is greater than or equal to the end time of the new time window, the end time of the new time window is determined as the target time. If the set time is less than the end time of the new time window, the set time is determined as the target time.

8. The method according to claim 6, characterized in that, Determining the target time based on a set time with a delay duration greater than 0, starting from the transmission time, includes: If the threshold mechanism enters a disabled state during a pending time between the sending time and the set time, the pending time is determined as the target time.

9. The method according to claim 1 or 2, characterized in that, The method further includes: At the end of the new time window, the interruption request count is reset to 0.

10. The method according to claim 1 or 2, characterized in that, The method further includes: When the threshold mechanism is enabled, a default number of credits is allocated to each processing module in the processor; the default number is greater than 0. Wherein, a credit count greater than 0 for each processing module indicates that sending an interrupt request is allowed, and a credit count of 0 for each processing module indicates that sending an interrupt request is not allowed; each processing module needs to decrement its own credit count by 1 for each interrupt request sent, and the interrupt control center needs to increment the credit count of at least one processing module by 1 for each interrupt request issued by at least one processing module.

11. The method according to claim 1 or 2, characterized in that, The method further includes: When the threshold mechanism is enabled, the threshold register, interval register, and quantity register inside the processor are configured; wherein, the threshold register is used to store the interrupt quantity threshold, the interval register is used to store the delay duration, and the quantity register is used to store the interrupt request statistics.

12. An interruption resource control device, characterized in that, The interruption resource control device includes: The acquisition module is used to acquire the statistical number of interruption requests from the start time of the new time window to the current time when the start time of the new time window is detected. The determination module is used to determine the delay time for credit return based on the number of interrupt requests and the configured interrupt number threshold; the processing module in the credit characterization processor sends the credentials required for the interrupt request to the interrupt control center. The credit processing module is used to return the credit of the target processing module based on the delay time of the credit return. The target processing module is the processing module that issued an interrupt request to the interrupt control center but did not return the credit.

13. A processor, characterized in that, It includes an interrupt control center and multiple processing modules, which are communicatively connected to the interrupt control center. When the interrupt control center executes a computer program, it implements the steps of the method according to any one of claims 1 to 11.

14. A computer device, characterized in that, The computer device includes the processor of claim 13.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 11.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 11.

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