Memory layout method during calculation of fHog characteristics by using FPGA (Field Programmable Gate Array)

Abstract

The invention provides a memory layout method for calculating fHog characteristics by using an FPGA (Field Programmable Gate Array), which comprises the following steps of: constructing a hierarchical memory structure matched with a calculation process according to the calculation process of the fHog characteristics in the FPGA; the calculation process comprises image zooming, pixel gradient calculation, eigenvector generation based on Ceil and eigenvector dimension reduction; the construction of the hierarchical memory structure comprises the following steps: configuring a double-buffer structure based on a block memory for a calculation process of image scaling, configuring a row buffer structure based on a distributed memory for a calculation process of pixel gradient calculation, and configuring a Ceil buffer structure and a histogram buffer structure based on the distributed memory for a calculation process generated based on a Ceil feature vector; a feature vector storage structure based on a block memory is configured for the calculation process of feature vector dimension reduction, and is used for storing the final fHog feature vector after dimension reduction; through a layered memory structure, the calculation process of fHog features is executed in parallel on the FPGA in an assembly line mode, so that the bottleneck of FPGA storage resources is solved, and the calculation efficiency is maximized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA programmable technology, in particular to a memory layout method for calculating fHog features using FPGA. BACKGROUND

[0002] The fHog (Felzenszwalb's HOG variant) feature is a high-efficiency feature descriptor in the field of computer vision target recognition and tracking. It represents the edge and shape information of the target by calculating the gradient direction histogram of the local region of the image, and has a certain robustness to light and deformation. However, the calculation process of the fHog feature involves image scaling, gradient calculation, interpolation, histogram statistics, normalization and dimension reduction, etc., which contains a large number of floating point operations and has high computational complexity. In the software (such as CPU / GPU) based implementation, this has become the performance bottleneck of the entire automatic tracking algorithm, which is difficult to meet the needs of high real-time application scenarios.

[0003] Field programmable gate array (FPGA) is very suitable for accelerating such computationally intensive tasks due to its parallel processing and customizable hardware circuit capabilities. However, the storage resources (mainly including distributed memory and block memory) inside the FPGA chip are relatively limited and have different structures, which are the core scarce resources that need to be optimized in the design. The existing technology often lacks deep optimization of the overall calculation process and data flow when implementing fHog feature calculation on FPGA, and fails to finely plan the memory type and layout according to the data volume, life cycle and access characteristics of each calculation step (such as image scaling, gradient calculation, Ceil-based feature generation, feature dimension reduction). This easily leads to low utilization efficiency of storage resources, data path congestion, and idle computing units, etc., so that the parallel pipeline advantage of a single FPGA chip cannot be fully utilized to realize real-time and efficient calculation of fHog features. SUMMARY

[0004] In view of the above defects or deficiencies in the prior art, the present application aims to provide a memory layout method for calculating fHog features using FPGA, comprising the following steps: In the FPGA, a hierarchical memory structure matching the calculation process of the fHog feature is constructed according to the calculation process of the fHog feature; the calculation process includes image scaling, pixel gradient calculation, Ceil-based feature vector generation, and feature vector dimension reduction; The construction of the hierarchical memory structure includes: A double-buffered structure based on block memory is configured for the calculation process of image scaling, which is used to read in the original image row data and output the scaled whole frame image in a pipelined manner; The computing flow for the pixel gradient calculation is configured with a distributed memory-based row buffer structure for buffering at least two rows of scaled image data to support parallel computation of the pixel gradient. The computing flow for the Ceil-based feature vector generation is configured with a distributed memory-based Ceil buffer structure and a histogram buffer structure; the Ceil buffer structure is composed of multiple parallel memory banks for buffering intermediate gradient data of multiple rows of Ceils in an odd-even interleaved manner to support single-cycle gradient interpolation and histogram statistics; and the histogram buffer structure is used for temporarily storing histogram summation results of the Ceils to support subsequent vector normalization computation. The computing flow for the feature vector dimension reduction is configured with a block memory-based feature vector storage structure for storing the final fHog feature vector after dimension reduction. Through the hierarchical memory structure, the computing flow of the fHog feature is executed in a pipelined manner on the FPGA in parallel.

[0005] According to the technical scheme provided in the embodiments of the present application, the computing flow for the image scaling is configured with a block memory-based double buffering structure, including the following steps: Two memory blocks are used as row buffers to buffer row data of the input image in an alternating manner; When one of the memory blocks buffers current row data, the other memory block reads previous row data to perform bilinear interpolation computation in combination with the current row data to complete image scaling; The scaled whole frame of image is written into the block memory for storage.

[0006] According to the technical scheme provided in the embodiments of the present application, the computing flow for the pixel gradient calculation is configured with a distributed memory-based row buffer structure, including the following steps: Two rows of image data are buffered using a distributed memory; When the third row of image data is input, the two rows of buffered image data are synchronously read, and the gradient of the current pixel in the horizontal direction and the vertical direction is calculated in parallel to further obtain the gradient amplitude and the direction angle.

[0007] According to the technical scheme provided in the embodiments of the present application, the computing flow for the Ceil-based feature vector generation is configured with a distributed memory-based Ceil buffer structure, including the following steps: At least four memory blocks are set to buffer gradient data of two rows of Ceils in an odd-even interleaved manner, so that the gradient value of each input pixel can be mapped to the adjacent four Ceils in one cycle; Another memory block is set to buffer Ceil data of subsequent rows to support pipelined execution of histogram summation and vector normalization computation.

[0008] According to the technical solution provided in the embodiments of this application, the histogram cache structure is coupled with the Ceil cache structure and is used to store the cumulative sum of each bin of the gradient histogram of each Ceil. Its capacity is matched with the number of Ceil and the histogram dimension.

[0009] According to the technical solution provided in the embodiments of this application, the gradients of the current pixel in the horizontal and vertical directions are calculated in parallel to obtain the gradient magnitude and direction angle, including the following steps: Based on the pixel gradient signs in the horizontal and vertical directions, floating-point multiplication and comparison operations with multiple predetermined angles are performed in parallel to simplify the arctangent calculation. Specifically, the orientation angle required to obtain the 18-dimensional feature vector is calculated first, and the orientation angle required to obtain the 9-dimensional feature vector is calculated in real time from the orientation angle of the 18-dimensional feature vector.

[0010] According to the technical solution provided in the embodiments of this application, in the calculation process of generating feature vectors based on Ceil, the calculations of vector normalization and vector truncation are performed in a pipeline manner, including: After completing the histogram summation of the 3 rows of Ceil, immediately start the vector normalization calculation of Ceil in the 3x3 neighborhood centered on the current Ceil; During the normalization calculation, the obtained feature vector is simultaneously compared with a preset threshold to achieve vector truncation.

[0011] According to the technical solution provided in the embodiments of this application, the calculation process for feature vector dimensionality reduction includes: For each Ceil, the 108-dimensional feature vector is summed along the column direction to obtain a 27-dimensional feature vector; Summing the 27-dimensional feature vector along the row direction yields a 4-dimensional feature vector; The 27-dimensional feature vector is concatenated with the 4-dimensional feature vector to generate the final 31-dimensional fHog feature vector.

[0012] According to the technical solution provided in the embodiments of this application, the default calculation parameters used in the method include: the scaled image size is 64*64 pixels; the Ceil size is 4*4 pixels; and the image data quantization bit depth is 16 bits.

[0013] According to the technical solution provided in the embodiments of this application, the FPGA storage resources consumed to implement the hierarchical memory structure include: using a specific number of block memory to store the scaled image and the dimension-reduced feature vector; and using a specific size of distributed memory to implement row cache, Ceil cache and histogram cache.

[0014] Compared with the prior art, the beneficial effects of this application are as follows: I. Achieving Refined and Efficient Utilization of Storage Resources: This invention constructs a hierarchical memory structure that matches the fHog computation process. Instead of simply and uniformly allocating the limited storage resources of the FPGA, this method deeply analyzes the differentiated requirements for data cache capacity, bandwidth, and access speed at different stages, such as image scaling, gradient calculation, feature generation, and dimensionality reduction. By configuring block RAM for image scaling and final features, and distributed RAM for intermediate gradient data and Ceil histograms, "on-demand allocation" and "maximizing the use" of heterogeneous FPGA storage resources are achieved, fundamentally alleviating the resource bottleneck problem.

[0015] Second, it significantly improves computational parallelism and pipeline efficiency: By tailoring memory structures for different computational stages (such as double buffering for image scaling, row buffering for gradient calculation, and alternating Ceil buffering for feature generation), tightly coupled computational steps are decoupled. These structures ensure that data is supplied to subsequent computational units in the most efficient way, enabling multiple operations such as pixel gradient calculation, gradient interpolation, and histogram statistics to be completed in parallel within a single cycle, and forming an efficient pipeline between stages. This greatly reduces processing latency and improves overall data throughput.

[0016] Third, it ensures complete and efficient implementation on a single FPGA chip: Through the optimized memory layout described above, this invention enables the entire complex fHog feature calculation process to run smoothly on a single FPGA chip. This method reduces the reliance on frequent access to off-chip memory during implementation and also reduces the computing power requirements of other computing units in the system (such as DSPs), thus providing a feasible hardware foundation for building miniaturized, low-power, and high real-time embedded vision processing systems. Attached Figure Description

[0017] Figure 1 A flowchart illustrating the steps of a memory layout method for calculating fHog features using an FPGA, as provided in an embodiment of this application. Figure 2 This is a schematic diagram of the bilinear interpolation cyclic double-buffered memory structure provided in the embodiments of this application; Figure 3 This is a schematic diagram of the memory structure for calculating pixel gradient magnitude and orientation angle provided in an embodiment of this application; Figure 4 This is a schematic diagram of the memory structure for calculating feature vectors provided in an embodiment of this application; Figure 5 This is a schematic diagram of the memory structure for feature vector summation provided in an embodiment of this application; Figure 6This is a schematic diagram of the structure for calculating the memory requirements of the fHog feature using an FPGA, as provided in an embodiment of this application. Detailed Implementation

[0018] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] Example 1 As mentioned in the background section, to address the problems in the prior art, this application proposes a memory layout method for calculating fHog features using an FPGA, such as... Figure 1 As shown, it includes the following steps: S1. Within the FPGA, a hierarchical memory structure matching the calculation process of the fHog feature is constructed; the calculation process includes image scaling, pixel gradient calculation, Ceil-based feature vector generation, and feature vector dimensionality reduction. S2. The construction of the hierarchical memory structure includes: S21. Configure a block memory-based double buffer structure for the image scaling calculation process, which is used to pipeline the reading of the original image row data and output the scaled whole frame image. S22. Configure a row cache structure based on distributed memory for the pixel gradient calculation process to cache at least two rows of scaled image data to support parallel calculation of pixel gradients. S23. Configure a Ceil cache structure and a histogram cache structure based on distributed memory for the calculation process of Ceil feature vector generation; the Ceil cache structure consists of multiple parallel storage volumes, which are used to cache intermediate gradient data of multiple rows of Ceil in an odd-even alternating manner to support single-cycle gradient interpolation and histogram statistics; the histogram cache structure is used to temporarily store the histogram summation results of Ceil to support subsequent vector normalization calculations. S24. Configure a block memory-based feature vector storage structure for the feature vector dimensionality reduction calculation process to store the final fHog feature vector after dimensionality reduction. S3. Through the layered memory structure, the calculation process of the fHog feature is executed in parallel in a pipeline manner on the FPGA.

[0021] like Figure 2As shown, in a preferred embodiment, configuring a block memory-based double-buffered structure for the image scaling calculation process includes the following steps: Two memory blocks are used as row buffers to cache the row data of the input image in an alternating manner; While caching the current row of data in one memory block, the previous row of data is read from another memory block, and bilinear interpolation is performed in combination with the current row of data to complete the image scaling. The scaled full-frame image is written to block memory for storage.

[0022] like Figures 3-6 As shown, in a preferred embodiment, configuring a distributed memory-based row cache structure for the pixel gradient calculation process includes the following steps: Use a distributed memory cache to cache two consecutive rows of image data; When the third row of image data is input, the cached two rows of image data are read synchronously, and the gradient of the current pixel in the horizontal and vertical directions is calculated in parallel to obtain the gradient magnitude and direction angle.

[0023] In a preferred embodiment, configuring a Ceil cache structure based on distributed memory for the computation process of generating Ceil feature vectors includes the following steps: Set up at least four memory blocks to cache the gradient data of two rows of Ceil in an odd-even interleaved manner, so that the gradient value of each input pixel can be interpolated to the four adjacent Ceil in one cycle. An additional memory block is allocated to cache Ceil data for subsequent rows to support pipelined execution of histogram summation and vector normalization calculations.

[0024] In a preferred embodiment, the histogram cache structure is coupled to the Ceil cache structure to store the cumulative sum of each bin of the gradient histogram of each Ceil, and its capacity is matched with the number of Ceil and the histogram dimension.

[0025] In a preferred embodiment, the gradients of the current pixel in the horizontal and vertical directions are calculated in parallel to obtain the gradient magnitude and orientation angle, including the following steps: Based on the pixel gradient signs in the horizontal and vertical directions, floating-point multiplication and comparison operations with multiple predetermined angles are performed in parallel to simplify the arctangent calculation. Specifically, the orientation angle required to obtain the 18-dimensional feature vector is calculated first, and the orientation angle required to obtain the 9-dimensional feature vector is calculated in real time from the orientation angle of the 18-dimensional feature vector.

[0026] In a preferred embodiment, in the Ceil-based feature vector generation computation process, vector normalization and vector truncation are performed in a pipelined manner, including: After completing the histogram summation of the 3 rows of Ceil, immediately start the vector normalization calculation of Ceil in the 3x3 neighborhood centered on the current Ceil; During the normalization calculation, the obtained feature vector is simultaneously compared with a preset threshold to achieve vector truncation.

[0027] In a preferred embodiment, the calculation process for feature vector dimensionality reduction includes: For each Ceil, the 108-dimensional feature vector is summed along the column direction to obtain a 27-dimensional feature vector; Summing the 27-dimensional feature vector along the row direction yields a 4-dimensional feature vector; The 27-dimensional feature vector is concatenated with the 4-dimensional feature vector to generate the final 31-dimensional fHog feature vector.

[0028] In a preferred embodiment, the default calculation parameters used by the method include: the scaled image size is 64*64 pixels; the Ceil size is 4*4 pixels; and the image data quantization bit depth is 16 bits.

[0029] In a preferred embodiment, the FPGA storage resources consumed in implementing the hierarchical memory structure include: using a specific number of block memory blocks to store the scaled image and the dimensionality-reduced feature vectors; and using a specific size of distributed memory to implement row cache, Ceil cache, and histogram cache.

[0030] Specifically, considering the characteristics of fHog features and their application in automatic tracking algorithms, this scheme uses the memory layout of FPGA for calculating fHog features, including the following steps: The calculation steps for fHog features are: image scaling, pixel gradient magnitude, pixel gradient direction angle, feature vector generation, and feature vector dimensionality reduction. The feature vector generation calculation steps are further divided into: gradient interpolation, vector histogram, histogram summation, vector normalization, and vector truncation.

[0031] Image scaling specifically includes: Image scaling is performed using a bilinear interpolation algorithm, calculating one pixel from four pixels in the original image. Before scaling, a scaling factor is calculated based on the original and scaled image sizes. Then, using the scaling factor and the center point of the original image, the pixel coordinates at the start and end of scaling are calculated to control image data caching. A circular double-buffered memory structure is used to store image data. Each row of image data is stored alternately between two memory blocks. After each row of image data stops being stored, the address of the memory block is generated, the image data is read twice, and the interpolation calculation is completed, as shown in the attached diagram.Figure 1 As shown. One pixel is calculated in two clock cycles. Image scaling can be achieved using this memory structure if the original image has more than 128 pixels per row, or by increasing the clock frequency for reading and calculation. The scaled image data is 64*64*16 bits in size and is stored in the FPGA block memory. Taking an AMD FPGA as an example, it requires four (64*64*16bit / 16Kbit) memory blocks.

[0032] Specifically, the pixel gradient magnitude includes: The pixel gradient is calculated by subtracting the pixels before and after the current pixel, and the pixels above and below it. The magnitude is the square root of the sum of the squares of the pixel gradients in both directions. A distributed memory circular buffer using an FPGA is employed to buffer two rows of image data, each row being 64*16 bits in size. When the third row of data is output, the pixel gradient magnitude is calculated, and the data for the third row is simultaneously stored in the circular buffer, as shown in the attached diagram. Figure 2 As shown, the calculated pixel gradient magnitude is directly output to the subsequent gradient interpolation module.

[0033] Specifically, the pixel gradient direction angle includes: Simultaneously calculate the pixel gradient and its orientation angle. Calculating the orientation angle requires calculating the arctangent value. To simplify the calculation, this can be achieved by using the sign of the pixel gradient, performing four floating-point multiplications (20º, 40º, 60º, 80º), and comparing these four floating-point numbers in parallel, all within a single cycle. The calculation result only outputs the orientation angle of the 18-dimensional feature vector; the orientation angle of the 9-dimensional feature vector is calculated in real-time from the orientation angle of the 18-dimensional feature vector.

[0034] The feature vector generation specifically includes: The feature vector generation calculation steps are: gradient interpolation, vector histogram, histogram summation, vector normalization, and vector truncation.

[0035] The gradient magnitude of each pixel is mapped to four ceils based on interpolation coefficients, defined as gradient interpolation. Within each ceil, the gradient magnitudes are summed based on the gradient direction angle and arranged sequentially, defined as a vector histogram. The summation of the squared magnitudes of each histogram within each ceil is defined as histogram summation. In a 3x3 ceil, the histograms of the four ceils at each corner are summed again, and the square root is defined as vector normalization. Each gradient magnitude in the vector histogram of each ceil is divided by the normalized vector to obtain a feature vector. Each feature vector is compared to a threshold; feature vectors smaller than the threshold remain unchanged, while those larger are truncated using the threshold value, defined as vector truncation.

[0036] Feature vector generation calculations use the same data cache. To achieve single-period gradient interpolation, two rows of Ceil need to be cached, with each row arranged in odd and even order, thus requiring four memory blocks. To achieve single-period histogram statistics, distributed memory within the FPGA is required. After the first two rows of image data in each Ceil have completed interpolation calculations, the histogram summation for the previous Ceil begins. Vector normalization calculations can only be performed after the histogram summation for three Ceil rows has been completed. Vector truncation is calculated simultaneously during the normalization process.

[0037] Ceil's cache is designed with 8 blocks, as shown in the attached image. Figure 3 As shown, Ram0 stores Ceil00, Ceil02, ...; Ram1 stores Ceil01, Ceil03, ..., and so on.

[0038] For example, in Ceil11, there are 16 pixels. Each pixel has 4 components, resulting in 64 components mapped to 9 Ceils. The top four pixels (pixel coordinates: [4, 4]; [4, 5]; [5, 4]; [5, 5]) are mapped to Ceil00, Ceil01, Ceil10, and Ceil11 respectively, and so on for other pixels. After the calculation of the pixels in the 5th row of the image is completed, the interpolation calculation of Ceil00, Ceil01, Ceil02, and Ceil03 is completed, and the histogram summation calculation can begin. The vector normalization of Ceil11 is to calculate the sum of 9 Ceils in a 3*3 grid centered on Ceil11, with 4 Ceils at each corner, such as Ceil00 + Ceil01 + Ceil10 + Ceil11 for the top left corner.

[0039] The cache required for feature vector generation is the distributed memory of the FPGA, with a size of: 8 (number of RAM) * 8 (number of Ceil) * (9 + 18) (vector dimension) * 32 bits (floating point) = 55296 bits.

[0040] Histogram summation requires storing the summation result of each Ceil histogram, which is 8*8*32bit=4096bit in size. Due to the small capacity, the distributed memory of the FPGA is also used, and the layout structure is the same as that of the vector histogram.

[0041] After the image data interpolation calculation for row 13 is completed, the histogram summation for row 2 (Ceil) begins. The required number of calculation cycles is: 9 (using 9-dimensional feature vector summation) * 8 (16 Ceil divided into two Rams) = 72. After the histogram summation is completed, the feature vector generation for row 2 (Ceil) begins. The 9-dimensional and 18-dimensional feature vectors are calculated in parallel, requiring: 18 * 8 (16 Ceil divided into two Rams) = 144 calculation cycles. The total number of calculation cycles is 72 + 144 = 216. Before the pixel interpolation calculation for row 17 (corresponding to row 0 (Ceil)) ends, there are 4 rows of pixels and 256 cycles, which is greater than 216, so the vector generation calculation can be completed.

[0042] Each Ceil generates a (9+18)*4=108-dimensional feature vector. The generated feature vector is directly output to the feature vector dimensionality reduction module and does not require caching.

[0043] Specifically, feature vector dimensionality reduction includes: Each Ceil contains 108 dimensional feature vectors. Summation along the column direction yields a 27 dimensional feature vector, and summation along the row direction yields a 4 dimensional feature vector, generating a 31 dimensional feature vector, as shown in the appendix. Figure 4 As shown, the generated feature vectors are stored in the FPGA's block memory, with a size of 14*14*9*32bit + 14*14*18*32bit + 14*14*4*32bit, requiring a total of 4+7+2=13 blocks of memory.

[0044] The memory size and type required for FPGA calculation of fHog features are attached. Figure 5 As shown. Taking AMD's K7 series FPGA as an example, the block memory requires 19 blocks of memory, and the distributed memory requires a total of 59392 bits.

[0045] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A memory layout method for calculating fHog features using an FPGA, characterized in that, Includes the following steps: Within the FPGA, a hierarchical memory structure matching the calculation process of the fHog feature is constructed; the calculation process includes image scaling, pixel gradient calculation, Ceil-based feature vector generation, and feature vector dimensionality reduction. The construction of the hierarchical memory structure includes: Configure a block memory-based double buffer structure for the image scaling calculation process, which is used to pipeline the reading of the original image row data and output the scaled whole frame image. Configure a row cache structure based on distributed memory for the pixel gradient calculation process to cache at least two rows of scaled image data to support parallel calculation of pixel gradients; The computational process for generating feature vectors based on Ceil is configured with a Ceil cache structure and a histogram cache structure based on distributed memory. The Ceil cache structure consists of multiple parallel storage volumes, which are used to cache intermediate gradient data of multiple rows of Ceil in an odd-even alternating manner to support single-cycle gradient interpolation and histogram statistics. The histogram cache structure is used to temporarily store the histogram summation results of Ceil to support subsequent vector normalization calculations. Configure a block-memory-based feature vector storage structure for the feature vector dimensionality reduction calculation process, which is used to store the final fHog feature vector after dimensionality reduction; The layered memory structure enables the parallel execution of fHog feature calculations in a pipelined manner on the FPGA.

2. The memory layout method for calculating fHog features using FPGA according to claim 1, characterized in that: Configuring a block-memory-based double-buffered structure for the image scaling calculation process includes the following steps: Two memory blocks are used as row buffers to cache the row data of the input image in an alternating manner; While caching the current row of data in one memory block, the previous row of data is read from another memory block, and bilinear interpolation is performed in combination with the current row of data to complete the image scaling. The scaled full-frame image is written to block memory for storage.

3. The memory layout method for calculating fHog features using FPGA according to claim 1, characterized in that: The configuration of the pixel gradient calculation process using a distributed memory-based row cache structure includes the following steps: Use a distributed memory cache to cache two consecutive rows of image data; When the third row of image data is input, the cached two rows of image data are read synchronously, and the gradient of the current pixel in the horizontal and vertical directions is calculated in parallel to obtain the gradient magnitude and direction angle.

4. The memory layout method for calculating fHog features using FPGA according to claim 1, characterized in that: The configuration of the Ceil cache structure based on distributed memory for the calculation process of generating Ceil feature vectors includes the following steps: Set up at least four memory blocks to cache the gradient data of two rows of Ceil in an odd-even interleaved manner, so that the gradient value of each input pixel can be interpolated to the four adjacent Ceil in one cycle. An additional memory block is allocated to cache Ceil data for subsequent rows to support pipelined execution of histogram summation and vector normalization calculations.

5. The memory layout method for calculating fHog features using FPGA according to claim 4, characterized in that: The histogram cache structure is coupled with the Ceil cache structure and is used to store the cumulative sum of each bin of the gradient histogram of each Ceil. Its capacity is matched with the number of Ceil and the histogram dimension.

6. The memory layout method for calculating fHog features using FPGA according to claim 3, characterized in that: The gradients of the current pixel in the horizontal and vertical directions are calculated in parallel to obtain the gradient magnitude and direction angle, including the following steps: Based on the pixel gradient signs in the horizontal and vertical directions, floating-point multiplication and comparison operations with multiple predetermined angles are performed in parallel to simplify the arctangent calculation. Specifically, the orientation angle required to obtain the 18-dimensional feature vector is calculated first, and the orientation angle required to obtain the 9-dimensional feature vector is calculated in real time from the orientation angle of the 18-dimensional feature vector.

7. The memory layout method for calculating fHog features using FPGA according to claim 1, characterized in that: In the Ceil-based feature vector generation computation process, vector normalization and vector truncation are performed in a pipelined manner, including: After completing the histogram summation of the 3 rows of Ceil, immediately start the vector normalization calculation of Ceil in the 3x3 neighborhood centered on the current Ceil; During the normalization calculation, the obtained feature vector is simultaneously compared with a preset threshold to achieve vector truncation.

8. The memory layout method for calculating fHog features using FPGA according to claim 1, characterized in that: The calculation process for eigenvector dimensionality reduction includes: For each Ceil, the 108-dimensional feature vector is summed along the column direction to obtain a 27-dimensional feature vector; Summing the 27-dimensional feature vector along the row direction yields a 4-dimensional feature vector; The 27-dimensional feature vector is concatenated with the 4-dimensional feature vector to generate the final 31-dimensional fHog feature vector.

9. The memory layout method for calculating fHog features using FPGA according to claim 1, characterized in that: The default calculation parameters used in the method include: the scaled image size is 64*64 pixels; the Ceil size is 4*4 pixels; and the image data quantization bit depth is 16 bits.

10. The memory layout method for calculating fHog features using FPGA according to claim 1, characterized in that: The FPGA storage resources consumed in implementing the hierarchical memory structure include: using a specific number of block memory blocks to store the scaled image and the dimensionality-reduced feature vectors; and using a specific size of distributed memory to implement row cache, Ceil cache, and histogram cache.

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