RF analog front end

Abstract

The invention relates to an RF analog front end. In one embodiment, an electronic circuit includes: an amplifier (310) having first and second outputs, first and second inputs, and first and second terminals; a high pass filter (304) coupled between the first terminal and the second terminal of the amplifier (310); and a configurable output network (312) coupled between the first output and the second output of the amplifier (310).

Description

[0001] Cross-reference to related applications

[0002] This patent application claims the benefit and priority of Indian Provisional Patent Application No. 202441053403, filed on July 12, 2024, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to an electronic system and method, and in certain embodiments, to a radio frequency (RF) analog front end. Background Technology

[0004] In electronics, an analog-to-digital converter (ADC) is a circuit that converts analog signals into digital signals. A digital-to-analog converter (DAC) is a circuit that converts digital signals into analog signals. ADCs and DACs are used in a wide variety of applications, such as audio, video, control, instrumentation, data acquisition, communications, imaging, automotive and aerospace applications, and others. In communications applications, for example, an ADC is used to convert analog radio frequency (RF) signals received via wired or wireless communication media into digital signals for further processing. Many architectures exist, and the implementation of an ADC can vary depending on the application. For instance, the suitability of an ADC architecture for a particular application is determined by performance characteristics such as bandwidth and signal-to-noise ratio (SNDR). Summary of the Invention

[0005] According to an embodiment, an electronic circuit includes: an amplifier having a first output and a second output, a first input and a second input, and a first terminal and a second terminal; a high-pass filter coupled between the first terminal and the second terminal of the amplifier; and a configurable output network coupled between the first output and the second output of the amplifier.

[0006] According to an embodiment, an integrated circuit includes: a semiconductor substrate; a first metal layer disposed over the semiconductor substrate; a second metal layer disposed over the semiconductor substrate; a first switch having a first terminal and a second terminal; a first connector disposed in the first metal layer and coupled to the first terminal of the first switch; a second connector disposed in the first metal layer and coupled to the second terminal of the first switch, the first connector and the second connector being arranged in a first shape; a second switch having a first terminal and a second terminal; a third connector disposed in the second metal layer and coupled to the first terminal of the second switch and the second terminal of the first switch; and a fourth connector disposed in the second metal layer and coupled to the second terminal of the second switch and the first terminal of the first switch, the third connector and the fourth connector being arranged in a second shape concentric with the first shape and substantially aligned with the first shape.

[0007] According to an embodiment, a method includes: operating a configurable output network of a digital signal attenuator (DSA) of a transceiver in a first operating mode at a first time; operating the DSA in the first operating mode; operating the configurable output network of the DSA of the transceiver in a second operating mode at a second time; and operating the DSA in the second operating mode. Attached Figure Description

[0008] To more fully understand this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0009] Figure 1 This is a block diagram of an example radio frequency (RF) circuit;

[0010] Figure 2 It is feasible. Figure 1 A block diagram of one or more of the receivers;

[0011] Figure 3 yes Figure 2 A schematic diagram of an example implementation of a digital signal attenuator (DSA);

[0012] Figure 4 When constructed in a bandpass (e.g., narrow) operating mode Figure 3 A schematic diagram of DSA;

[0013] Figure 5 When constructed in wideband operating mode Figure 3 A schematic diagram of DSA;

[0014] Figure 6A It is feasible. Figure 3 A schematic diagram of a first example inductor, which is at least one of the inductors;

[0015] Figure 6BIt is a cross-sectional view illustrating how the switch is coupled to the connector of the first metal layer of the semiconductor;

[0016] Figure 7A It is feasible. Figure 3 A schematic diagram of a second example inductor, which is at least one of the inductors;

[0017] Figure 7B It is a cross-sectional view illustrating how the switch is coupled to the connector of the first metal layer of the semiconductor;

[0018] Figure 7C This is a cross-sectional view illustrating how the switch is coupled to the connector in the second metal layer of the semiconductor; and

[0019] Figure 8 Description of the operation according to embodiments of the present disclosure Figure 3 A flowchart of an embodiment of DSA method 800.

[0020] Unless otherwise indicated, corresponding reference numerals and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments, and the figures are not necessarily drawn to scale. Detailed Implementation

[0021] The following describes in detail the making and use of the disclosed embodiments. However, it should be understood that this disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using this disclosure and do not limit the scope of this disclosure.

[0022] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments based on the description. Embodiments may be obtained without one or more of the specific details or with other methods, components, materials, etc. In some cases, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" in this specification indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment," which may appear in different places in this specification, do not necessarily refer entirely to the same embodiment. Furthermore, specific forms, structures, or features may be combined in any suitable manner in one or more embodiments.

[0023] Several aspects of this disclosure are described below with reference to illustrative examples. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the described order of actions or events, as some actions may occur in a different order and / or simultaneously with other actions or events.

[0024] Some embodiments relate generally to analog-to-digital converters, and more particularly to methods and apparatus for attenuating signals used in radio frequency sampling analog-to-digital converters.

[0025] Modern radio frequency (RF) applications encompass communications and radar applications. Other RF applications include motor control feedback, network and vector analyzers, communications test equipment, non-destructive testing, microwave receivers, software-defined radios, orthogonal and diversity radio receivers, and handheld radios and instruments. In example communications applications, RF circuitry can be implemented in any of the following: macro radio remote units (RRUs), active antenna systems (AAS) for massive MIMO (mMIMO), base stations (small cells or large areas), distributed antenna systems (DAS), or repeaters.

[0026] In modern applications, RF circuits operate across a wide range of frequencies. Even within specific applications, the operating frequency of an RF circuit can vary. For example, while RF circuits in communication applications typically operate between 20 kHz and 300 GHz, those in satellite communication applications operate between 2 GHz and 30 GHz. Furthermore, in multi-carrier, multi-mode cellular communication applications, RF circuits can support multiple frequency bands, such as dual-band, tri-band, and quad-band, with a center frequency range of 800 MHz to 2.1 GHz. In smart antenna communication applications, RF circuits can support fourth-generation (4G) communication (600 MHz to 2.6 GHz), fifth-generation (5G) communication (<1 GHz to 40 GHz), and sixth-generation (6G) communication (7 GHz to 300 GHz).

[0027] In modern communications applications, service providers (also known as carriers) utilize higher frequency ranges (e.g., 5G and 6G frequency ranges) to support higher data rates. Furthermore, in modern communications applications, different carriers operate at various center frequencies. For example, a first carrier communicates in a frequency band centered on a first center frequency, and a second carrier communicates in a frequency band centered on a second center frequency. In some examples, a carrier simultaneously supports multiple operating frequency bands.

[0028] To support operation in higher frequency ranges, the use of various carriers operating at various center frequencies, and operation in multiple frequency bands, the ADC in the RF circuitry will support a wide bandwidth of input frequencies. For example, the ADC can provide both wideband and narrowband support. Example wideband support includes support for operation in frequency bands ranging from 100 MHz to 6 GHz or from 3.1 GHz to 10.6 GHz. Example narrowband support includes support for a frequency band approximately 400 MHz wide, with center frequencies anywhere from 1.8 GHz to 7.2 GHz. Wideband support of the ADC in the RF circuitry allows the RF circuitry to support scenarios where carriers operate simultaneously in multiple frequency bands. Furthermore, wideband support provided by the ADC in the RF circuitry allows the RF circuitry to implement feedback channels that can improve the performance of the RF circuitry. Narrowband support of the ADC in the RF circuitry allows the RF circuitry to achieve a better noise figure (e.g., compared to wideband operation).

[0029] Supporting both narrowband and broadband operation can be beneficial. For example, a device can support multiple protocols, one or more of which can be narrowband (e.g., WiFi, BLE, etc.), and one or more of which can be broadband (e.g., UWB, etc.).

[0030] To support both wideband and narrowband operation, the ADC's input reflection coefficient (S11) parameter and input bandwidth will support frequencies up to 6 GHz. The ADC's S11 parameter and input bandwidth can depend on the ADC's digital signal attenuator (DSA). For example, in a receiver, the DSA can be positioned between the matching network and the ADC. Therefore, since the same matching network will be used across frequency bands, the DSA's input capacitance will be low to maintain the ADC's low S11 parameter.

[0031] In the examples described herein, a DSA can be understood as a circuit that adjusts the magnitude of the input signal to an ADC to ensure that the magnitude is within the threshold range of the ADC (e.g., within the operating voltage range of the ADC) regardless of the received signal strength of the input signal. For example, a DSA may have variable gain to (1) amplify the analog signal received by the base station when the amplitude of the analog signal is small (e.g., when the analog signal originates from a device far from the base station), and (2) attenuate the analog signal received by the base station when the amplitude of the analog signal is large (e.g., when the analog signal originates from a device close to the base station).

[0032] The DSA can be a programmable circuit, for example, to allow tuning of the S11 parameter. Furthermore, the DSA can be a passive or active circuit. For example, a passive DSA applies a negative gain to the input signal and attenuates input signals having a value exceeding a threshold range to within the threshold range. Conversely, an active DSA, for example, applies a positive gain to the input signal having a value below a threshold range and attenuates input signals having a value exceeding the threshold range to within the threshold range.

[0033] Passive DSAs are useful, for example, in base stations supporting small cells (small coverage areas) and can handle larger input signal values ​​than active DSAs. However, passive DSAs have a large noise figure. The noise figure (NF) quantifies the degradation of the signal-to-noise ratio (SNR) caused by the components, with a lower NF value indicating better performance. Active DSAs are useful, for example, in base stations supporting large and small cells (large coverage areas). However, active DSAs do not incorporate noise cancellation techniques and, as a result of low-pass filtering at the output, introduce noise aliasing, which increases the NF of the active DSA. To mitigate amplified noise, active DSAs can be tuned. However, tuning an active DSA can be complex and may require adjusting many of its components.

[0034] In some embodiments, to support both wideband and narrowband operation, the S11 parameters and input bandwidth of the ADC will support frequencies, for example, up to 6 GHz, depending on the ADC's DSA. However, the DSA may only support a narrow bandwidth of the input frequency (e.g., a specific band for a particular carrier). Thus, a single fixed-design DSA may not be able to support multiple carriers or multiple bands. Advantageously, some embodiments described herein include a highly configurable DSA having: (1) a reconfigurable output network that supports both bandpass (e.g., narrow) and wideband operating modes; (2) cross-coupled transistors for improving the S11 parameters across frequencies of the ADC coupled to the DSA; and (3) a high-pass filter (HPF) for preventing frequency aliasing when the DSA is constructed in wideband operating mode. In some embodiments, when constructed in narrowband operating mode, the reconfigurable output network achieves a lower NF and allows for a wide tuning range. For example, the reconfigurable output network may include a tunable area-effective inductor that allows configuration of the bandpass filter (BPF) implemented by the reconfigurable output network. In some embodiments, when constructed in a wideband operating mode, the reconfigurable output network supports operation in a frequency band ranging from 100 MHz to 6 GHz. Furthermore, the reconfigurable output network can consume three to four times less on-chip area than other methods.

[0035] Figure 1 This is a block diagram of a radio frequency (RF) circuit 100 according to an embodiment of the present disclosure. Figure 1 In the example, RF circuit 100 includes digital signal generation circuit 102 and transmitters 1041 to 1042. N Local oscillator circuit 106, transmitting antennas 1081 to 108 N Receiving antennas 1101 to 110 M Receiver 1121 to 112 M and processor circuit 114. Furthermore, in Figure 1 In the example, transmitters 1041 to 104 N Each includes a digital-to-analog converter (DAC) 1161 to 116. N Mixers 1181 to 118 N Phase shifters 1201 to 120 N and example power amplifiers (PA) 1221 to 122 N .

[0036] In some embodiments, circuit 100 may be implemented using a single IC comprising elements 102, 104, 106, 112, 114, and 136. In other embodiments, circuit 100 may be implemented using multiple discrete components, in contrast to integration within a single IC. Other implementations are also possible.

[0037] In some embodiments, the digital signal generation circuit 102 is implemented as part of the processor circuit 114. In other embodiments, the digital signal generation circuit 102 and the processor circuit 114 are implemented separately.

[0038] exist Figure 1 In the example described, receivers 1121 to 112 M Each circuit includes a balun circuit (1241 to 124). M Matching network 1261 to 126 M Digital signal attenuator (DSA) 1281 to 128 M Sampling circuits 1301 to 130 M and analog-to-digital converters (ADCs) 1321 to 132 M .exist Figure 1 In the example, RF circuit 100 includes feedback receiver 112 FB Example feedback switches 1341 to 134 N And feedback circuit 136. In Figure 1 In the example, feedback receiver 112 FB Includes 124 balun circuits FB Matching Network 126 FB DSA 128 FB Sampling circuit 130FB and ADC 132 FB .

[0039] exist Figure 1 In the illustrated example, RF circuit 100 includes transmitters 1041 to 1042. N and transmitting antennas 1081 to 108 N Sixteen of each of the following. For example, N equals sixteen. In Figure 1 In the example, RF circuit 100 includes components for transmitters 1041 to 104 N 112 of the four feedback receivers FB One example. Therefore, for example, although Figure 1 The description of feedback receiver 112 is as follows. FB One example, but in some embodiments, Figure 1 The RF circuit 100 includes a feedback receiver 112 FB Four examples. In Figure 1 In the example, RF circuit 100 includes receiving antennas 1101 to 110. M and receivers 1121 to 112 M Sixteen of each of the three. For example, M equals sixteen. In some examples, the RF circuit 100 contains different numbers of transmitters 1041 to 104. N Transmitting antennas 1081 to 108 N Receiving antennas 1101 to 110 M Feedback receiver 112 FB Or receiver 1121 to 112 M Any one of them.

[0040] In some examples, the RF circuit 100 and the processor circuit 114 are implemented separately and may be coupled together. Alternatively, the RF circuit 100 may be implemented with the processor circuit 114, for example, in a single-chip package or on a system-on-a-chip (SoC) (e.g., a single IC). In the example where the RF circuit 100 is implemented with the processor circuit 114 on the SoC, the RF circuit 100 may correspond to a sub-circuit of the IC that forms the SoC.

[0041] exist Figure 1 In the examples described, DACs 1161 to 116 N Each of them has a first input, a second input, a first output, and a second output. Figure 1 In the example, the balun circuits 1241 to 124 M Balanced-unbalanced converter circuit 124 FB Each of them has an input, a first output, and a second output. Figure 1PA 1221 to 122 N Each of them, ADC 1321 to 132 M Each of them and ADC 132 FB It has a first input, a second input, and an output. Furthermore, in Figure 1 In the example, phase shifters 1201 to 120 N Each of them, matching network 1261 to 126 M Each of the 126 matching networks FB DSA1281 to 128 M Each of them, DSA 128 FB Sampling circuits 1301 to 130 M Each of the 130 sampling circuits FB It has a first input, a second input, a first output, and a second output.

[0042] exist Figure 1 In the illustrated example, mixers 1181 to 118 N Each of them has a first input, a second input, a third input, a fourth input, a first output, and a second output. Figure 1 In the example, the digital signal generation circuit 102 has an output. Figure 1 Each of the processor circuit 114 and the feedback circuit 136 has an input and an output. Figure 1 In the example, the local oscillator circuit 106 has a first output and a second output. Additionally, feedback switches 1341 to 134... N Each of them has a control terminal, a first current path terminal, and a second current path terminal.

[0043] exist Figure 1 In the illustrated example, the digital signal generation circuit 102 is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In the example, digital signal generation circuit 102 is coupled to transmitters 1041 to 104. N For example, the output of the digital signal generation circuit 102 is coupled to transmitters 1041 to 1044. N DAC 1161 to 116 N The corresponding first input. In some examples, the digital signal generation circuit 102 is coupled to the processor circuit 114.

[0044] exist Figure 1 In the examples described, DACs 1161 to 116 N Each of these is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In the examples, DAC 1161 to 116N Coupled to the digital signal generation circuit 102. For example, the first input of the corresponding DAC is coupled to the output of the digital signal generation circuit 102. Figure 1 In the examples, DAC 1161 to 116 N Coupled to processor circuitry 114. For example, the second input of the corresponding DAC is coupled to the output of feedback circuitry 136. Furthermore, in Figure 1 In the examples, DAC 1161 to 116 N Coupled to mixers 1181 to 118 N For example, the first and second outputs of the corresponding DAC are coupled to the first and second inputs of the corresponding mixer, respectively.

[0045] exist Figure 1 In the illustrated example, mixers 1181 to 118 N Each of these is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In the example, mixers 1181 to 118 N Coupled to DAC 1161 to 116 N For example, the first and second inputs of the corresponding mixer are coupled to the first and second outputs of the corresponding DAC, respectively. Furthermore, in Figure 1 In the example, mixers 1181 to 118 N Coupled to local oscillator circuit 106. For example, the third and fourth inputs of the corresponding mixer are coupled to the first and second outputs of local oscillator circuit 106, respectively. Figure 1 In the example, mixers 1181 to 118 N Coupled to phase shifters 1201 to 120 N For example, the first and second outputs of the corresponding mixer are coupled to the first and second inputs of the corresponding phase shifter, respectively.

[0046] exist Figure 1 In the illustrated example, the local oscillator circuit 106 is implemented by at least one of an analog circuit system or a digital circuit system. For example, the local oscillator circuit 106 includes a phase-locked loop (PLL) oscillator with a voltage-controlled oscillator (VCO). In additional or alternative examples, the local oscillator circuit 106 includes a crystal oscillator. Figure 1 In the example, local oscillator circuit 106 is coupled to mixers 1181 to 118. N For example, the first and second outputs of the local oscillator circuit 106 are coupled to mixers 1181 to 1182, respectively. N The third and fourth inputs of the responders.

[0047] exist Figure 1 In the illustrated example, phase shifters 1201 to 120 N Each of these is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In the example, phase shifters 1201 to 120 N Coupled to mixers 1181 to 118 N For example, the first and second inputs of the corresponding phase shifter are coupled to the first and second outputs of the corresponding mixer, respectively. Furthermore, in Figure 1 In the example, phase shifters 1201 to 120 N Coupled to PA 1221 to 122 N For example, the first and second outputs of the corresponding phase shifter are coupled to the first and second inputs of the corresponding PA, respectively.

[0048] exist Figure 1 In the examples described, PA 1221 to 122 N Each of these is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In the examples, PA 1221 to 122 N Coupled to phase shifters 1201 to 120 N For example, the first and second inputs of the corresponding PA are coupled to the first and second outputs of the corresponding phase shifter, respectively. Furthermore, in Figure 1 In the examples, PA 1221 to 122 N Coupled to transmitting antennas 1081 to 108 N For example, the output of the corresponding PA is coupled to the corresponding transmitting antenna. Figure 1 In the examples, PA 1221 to 122 N Coupled to feedback switches 1341 to 134 N For example, the output of the corresponding PA is coupled to the first current path terminal of the corresponding feedback switch.

[0049] exist Figure 1 In the illustrated example, digital signal generation circuitry 102 includes the functionality to receive signal parameter values ​​(e.g., from processor circuitry 114) of signals (e.g., data signals to be modulated on a carrier signal, chirp sequences in radar frames, etc.). In some examples, the signal parameters are defined by the system architecture and may include, for example, indications of which transmitters 1041 to 104 should be enabled. N The transmitter enable parameters, signal frequency, ADC sampling time, and transmitter start time, etc., are specified. Figure 1In the example, the digital signal generation circuit 102 also includes the function of generating a signal for transmission (e.g., a data signal to be modulated on a carrier signal, a chirp, etc.) in response to signal parameter values ​​(e.g., received from the processor circuit 114). For example, the digital signal generation circuit 102 generates signals for applications implementing the RF circuit 100 (e.g., communication applications, radar applications, etc.). Example applications that can implement the RF circuit 100 include ultra-wideband (UWB) applications, Wi-Fi applications, etc. Low-power (BLE) applications, sub-1GHz applications, and applications based on IEEE standards (e.g., IEEE 802.15.4).

[0050] exist Figure 1 In the examples described, DACs 1161 to 116 N Each of them samples the signal generated by the digital signal generation circuit 102. Figure 1 In the example, the local oscillator circuit 106 generates a carrier signal, and the data signal (e.g., generated by the digital signal generation circuit 102) is modulated onto the carrier signal. Furthermore, in... Figure 1 In the example, mixers 1181 to 118 N The local oscillator (LO) signal is compared with that from DAC 1161 to 116. N Each sampled data signal is mixed. Therefore, mixers 1181 to 118... N Each of them generates a modulated signal.

[0051] exist Figure 1 In the illustrated example, phase shifters 1201 to 120 N Each of them receives from mixers 1181 to 118 N The modulated signal provided by the responder in the circuit is shifted accordingly for use in applications utilizing RF circuit 100. Figure 1 In the example, phase shifters 1221 to 122 N Each of the amplifications is from phase shifter 1201 to 120. N The receiver receives the modulated (and possibly phase-shifted) signal and provides the amplified signal to the transmitting antennas 1081 to 108. N The corresponding entity in [the context]. Furthermore, in [the context of the previous sentence]... Figure 1 In the example, transmitters 1041 to 104 N via transmitting antennas 1081 to 108 N Transmit the amplified signal.

[0052] exist Figure 1 In the illustrated example, the balun circuits 1241 to 124 MEach of these is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In the example, the balun circuits 1241 to 124 M Coupled to receiving antennas 1101 to 110 M For example, the input of the corresponding balun circuit is coupled to receiving antennas 1101 to 110. M The corresponding entity in [the context]. Furthermore, in [the context of the previous sentence]... Figure 1 In the example, the balun circuits 1241 to 124 M Coupled to matching network 1261 to 126 M For example, the first and second outputs of the corresponding balanced-unbalanced converter circuit are coupled to the first and second inputs of the corresponding matching network, respectively.

[0053] exist Figure 1 In the example described, matching networks 1261 to 126 M Each of these is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In the example, the matching network is from 1261 to 126. M Coupled to balun circuits 1241 to 124 M For example, the first and second inputs of the corresponding matching network are coupled to the first and second outputs of the corresponding balun circuit, respectively. Furthermore, matching networks 1261 to 126... M Coupled to DSA 1281 to 128 M For example, the first and second outputs of the corresponding matching network are coupled to the corresponding DSAs 1281 to 128. M The first and second inputs.

[0054] exist Figure 1 In the examples described, DSA 1281 to 128 M Each of these is implemented by at least one of an analog circuit system or a digital circuit system. (Combined) Figure 3 The instructions and descriptions can be implemented according to DSA 1281 to 128. M Example electronic circuits of any of them. In Figure 1 In the examples, DSA 1281 to 128 M Coupled to matching network 1261 to 126 M For example, the first and second inputs of the corresponding DSA are coupled to the first and second outputs of the corresponding matching network, respectively. Figure 1 In the examples, DSA1281 to 128 M Coupled to sampling circuits 1301 to 130 MFor example, the first and second outputs of the corresponding DSA are coupled to the first and second inputs of the corresponding sampling circuit, respectively.

[0055] exist Figure 1 In the example described, sampling circuits 1301 to 130 M Each of these is implemented by at least one of an analog circuit system or a digital circuit system. (Combined) Figure 2 The description and specifications can be used to implement sampling circuits 1301 to 130. M Example implementation of the sampling circuit for any of them. Figure 1 In the example, sampling circuits 1301 to 130 M Coupled to DSA 1281 to 128 M For example, the first and second inputs of the corresponding sampling circuit are coupled to the first and second outputs of the corresponding DSA, respectively. Furthermore, in Figure 1 In the example, sampling circuits 1301 to 130 M Coupled to ADC 1321 to 132 M For example, the first and second outputs of the corresponding sampling circuit are coupled to the first and second inputs of the corresponding ADC, respectively.

[0056] exist Figure 1 In the example described, ADC 1321 to 132 M Each of these is implemented by at least one of an analog circuit system or a digital circuit system. Figure 1 In the example, ADC 1321 to 132 M Coupled to sampling circuits 1301 to 130 M For example, the first and second inputs of the corresponding ADC are coupled to the first and second outputs of the corresponding sampling circuit, respectively. Furthermore, in Figure 1 In the example, ADC 1321 to 132 M Coupled to processor circuit 114. For example, the output of the corresponding ADC is coupled to the input of processor circuit 114.

[0057] exist Figure 1 In the illustrated examples, processor circuitry 114 may be implemented using analog and / or digital circuitry systems. For example, in some embodiments, processor circuitry 114 may be implemented as a general-purpose or custom processor or controller coupled to memory and configured to execute instructions from this memory. In some embodiments, processor circuitry 114 may be implemented using a general-purpose or custom DSP, a general-purpose or custom microcontroller, an FFT engine, a combined DSP and microcontroller processor, an FPGA, or an application-specific integrated circuit (ASIC). Figure 1In the example, the input of processor circuit 114 is coupled to ADCs 1321 to 132. M The output of the corresponding entity in [the context]. Furthermore, in [the context]... Figure 1 In the example, processor circuit 114 is coupled to feedback switches 1341 to 134. N For example, the output of processor circuit 114 is coupled to the control terminal of the corresponding feedback switch. Although in Figure 1 In the example, the output of processor circuit 114 is described as a single terminal, but in some embodiments, the output may be provided by corresponding feedback switches 1341 to 1342. N One or more outputs are implemented. In some examples, processor circuitry 114 is coupled to digital signal generation circuitry 102.

[0058] exist Figure 1 In the example described, receiving antennas 1101 to 110 M Each of these receives signals from the environment within the field of view of the RF circuit 100. For example, receiving antennas 1101 to 110... M Each of these receives cell signals from the environment. In additional or alternative examples, receiving antennas 1101 to 110... M Each of them receives radar frames from the environment. Figure 1 In the example, the balun circuits 1241 to 124 M Each of them converts the single-ended received signal into a differential received signal and forwards the differential received signal to matching networks 1261 to 126. M .exist Figure 1 In the example, the matching network is from 1261 to 126. M Receivers 1121 to 112 M The input impedance of the receiving antenna is 1101 to 110. M Impedance matching.

[0059] exist Figure 1 In the example described, matching networks 1261 to 126 M Provide the differential received signal to DSA 1281 to 128 M .exist Figure 1 In the examples, DSA 1281 to 128 M Each of them adjusts the gain of the differential received signal to be between ADC1321 and 132. M Within the threshold range. Figure 1 In the example, sampling circuits 1301 to 130 M Each of the components samples the differential received signal and provides one or more samples to ADCs 1321 to 1322. M Furthermore, in Figure 1In the example, ADC 1321 to 132 M Each of them converts the differential received signal from the analog domain to the digital domain.

[0060] In some examples, RF circuit 100 includes ADCs 1321 to 132. M The digital front-end (DFE) circuitry system between the processor circuitry 114 and the receiver 1121. For example, the DFE circuitry system extends from receiver 1121 to 112... M The system receives digital signals and performs decimation filtering or other processing operations on them, for example, to adjust the data transmission rate of the digital signals. Alternatively, the DFE circuitry can perform other operations on the digital signals, such as those performed by receivers 1121 to 112. M DC offset removal or compensation (e.g., digital compensation) for non-ideals in the receiver (e.g., inter-receiver gain imbalance non-ideal, inter-receiver phase imbalance non-ideal, etc.).

[0061] exist Figure 1 In the illustrated examples, processor circuitry 114 is used to perform at least a portion of signal processing on a digital signal generated from a received analog signal. In some examples, processor circuitry 114 is used to transmit the result of signal processing. For example, processor circuitry 114 transmits the result of signal processing to a processing unit. In some examples, processor circuitry 114 interfaces with another device via a high-speed interface or a Serial Peripheral Interface (SPI). Figure 1 In one example, processor circuit 114 performs an FFT on each received signal. In some examples, processor circuit 114 receives control information (e.g., signal timing, power level, triggering of monitoring functions, etc.) via SPI. For example, in response to control information, processor circuit 114 provides data parameters to digital signal generation circuit 102 or provides control signals to said digital signal generation circuit.

[0062] In some examples, the processor circuit 114 is triggered by PAs 1221 to 122. N Transmitted to transmitting antennas 1081 to 108 N Sampling of one or more of the analog signals. For example, by feeding feedback switches 1341 to 134... N One of them sends a control signal to trigger the sampling of the analog signal. Figure 1 In the example, feedback switches 1341 to 134 N The control terminals of each of these are coupled to the output of processor circuit 114. Additionally, feedback switches 1341 to 134... N The first current path terminals of each of them are respectively coupled to PA 1221 to 122 NThe output, and feedback switches 1341 to 134 N The second current path terminal of each of them is coupled to the balun circuit 124. FB Input. In Figure 1 In the example, feedback switches 1341 to 134 N Each of these is implemented by a transistor, such as a field-effect transistor (FET).

[0063] exist Figure 1 In the illustrated example, unless otherwise described, feedback receiver 112 FB Regarding receivers 1121 to 112 M The implementation and coupling are similarly described. As described above, in Figure 1 In the example, the balun circuit 124 FB The input is coupled to feedback switches 1341 to 134. N The second current path terminal of each of them. Additionally, ADC 132 FB The output is coupled to the input of feedback circuit 136. Figure 1 In the example, the feedback circuit 136 is implemented by at least one of an analog circuit system or a digital circuit system. Furthermore, in... Figure 1 In the example, the input of feedback circuit 136 is coupled to ADC 132. FB The output of the feedback circuit 136 is coupled to DAC 1161 to 116. N The second input of the responder. Although in Figure 1 In the example, the output of feedback circuit 136 is described as a single terminal, but in some embodiments, the output may be provided by terminals corresponding to DACs 1161 to 116. N One or more outputs are implemented.

[0064] exist Figure 1 In the illustrated example, feedback circuit 136 is transmitted via feedback receiver 112 FB For PA 1221 to 122 N One of them is transmitted to the transmitting antennas 1081 to 108. N The analog signal of one of them is sampled. For example, feedback circuit 136 determines PA 1221 to 122. N The nonlinearity in one of the components is corrected by determining one or more digital predistortion (DPD) coefficients. Based on the one or more DPD coefficients, the feedback circuit 136 adjusts the circuit corresponding to the nonlinearity obtained by the feedback receiver 112. FB Sampled PA 1221 to 122 N One of the DACs is 1161 to 116. NOne of them. In this way, the feedback circuit 136 can improve the transmitters 1041 to 104 of the RF circuit 100. N The adjacent channel power ratio (ACPR) between them.

[0065] Figure 2 This is a block diagram of a receiver 200 according to an embodiment of the present disclosure. Figure 1 Receiver 1121 to 112 M Either of these can be implemented as receiver 200. Figure 2 In the example, receiver 200 includes a receiving antenna 202, a balun circuit 204, a matching network 206, a DSA 208, a sampling circuit 210, and an ADC 212. In some embodiments, the receiving antenna 202, the balun circuit 204, and the matching network 206 are external to the chip (e.g., SoC, IC, etc.), while the DSA 208, the sampling circuit 210, and the ADC 212 are internal to the chip (e.g., SoC, IC, etc.). Other embodiments are also possible.

[0066] exist Figure 2 In the example, the balun circuit 204 has an input, a first output, and a second output, and the ADC has a first input, a second input, and an output. Figure 2 In the example, each of the matching network 206, DSA 208, and sampling circuit 210 has a first input, a second input, a first output, and a second output.

[0067] exist Figure 2 In the illustrated example, the balun circuit 204 includes a transformer 214 and a ground terminal 216. For example, the ground terminal 216 is at a voltage of zero volts (V). Figure 2 In the example, transformer 214 includes a first input, a second input, a first output, a second output, and a center tap. Figure 2 In the example, the input of the balun circuit 204 is coupled to the receiving antenna 202. For example, the first input of the transformer 214 is coupled to the receiving antenna 202, and therefore to the input of the balun circuit 204. Furthermore, for example, the second input of the transformer 214 is coupled to the ground terminal 216.

[0068] exist Figure 2In the illustrated example, the first and second outputs of the balun circuit 204 are coupled to the first and second inputs of the matching network 206, respectively. For example, the first output of the transformer 214 is coupled to the first input of the matching network 206, and therefore to the first output of the balun circuit 204. Furthermore, for example, the second output of the transformer 214 is coupled to the second input of the matching network 206, and therefore, the second output of the transformer 214 is coupled to the second output of the balun circuit 204. Figure 2 In the example, the center tap of transformer 214 is coupled to ground terminal 216.

[0069] exist Figure 2 In the illustrated example, the matching network 206 can be implemented by analog circuit systems and / or digital circuit systems. Figure 2 In the example, the first and second inputs of the matching network 206 are coupled to the first and second outputs of the balun circuit 204, respectively. For instance, the first and second inputs of the matching network 206 are coupled to the first and second outputs of the transformer 214, respectively. Figure 2 In the example, the first and second outputs of the matching network 206 are coupled to the first and second inputs of the DSA 208.

[0070] exist Figure 2 In the illustrated example, the DSA 208 can be implemented by analog circuitry and / or digital circuitry. Figure 3 Possible implementations of the DSA 208 according to embodiments of the present disclosure are shown.

[0071] exist Figure 2 In the example, the first and second inputs of DSA 208 are coupled to the first and second outputs of matching network 206, respectively. Furthermore, in Figure 2 In the example, the first and second outputs of DSA 208 are coupled to the first and second inputs of sampling circuit 210, respectively.

[0072] exist Figure 2 In the illustrated example, the sampling circuit 210 includes a first buffer 218, a second buffer 220, a first sampling switch 222, a second sampling switch 224, a first sampling capacitor 226, a second sampling capacitor 228, and a control circuit system 230. Figure 2 In the example, each of buffers 218 and 220 has an input and an output. Furthermore, in... Figure 2 In the example, each of buffers 218 and 220 is implemented by an analog circuit system and / or a digital circuit system.

[0073] exist Figure 2In the illustrated example, each of sampling switches 222 and 224 has a control terminal, a first current path terminal, and a second current path terminal. For example, each of sampling switches 222 and 224 is implemented using a transistor, such as a field-effect transistor (FET). Figure 2 In the example, each of sampling capacitors 226 and 228 has a first terminal and a second terminal. Furthermore, each of sampling capacitors 226 and 228 has a capacitance of C. Figure 2 In the example, the control circuit system 230 has a first output and a second output. For example, the control circuit system 230 is implemented by at least one of an analog circuit system or a digital circuit system.

[0074] exist Figure 2 In the illustrated example, the first input of sampling circuit 210 is coupled to the first output of DSA 208. For example, the input of buffer 218 is coupled to the first output of DSA 208, and therefore to the first input of sampling circuit 210. Furthermore, the output of buffer 218 is coupled to the second current path terminal of sampling switch 222. Figure 2 In the example, the second input of sampling circuit 210 is coupled to the second output of DSA 208. For example, the input of buffer 220 is coupled to the second output of DSA 208, and therefore to the second input of sampling circuit 210. Furthermore, the output of buffer 220 is coupled to the second current path terminal of sampling switch 224.

[0075] exist Figure 2 In the illustrated example, the first current path terminal of the sampling switch 222 is coupled to the first terminal of the sampling capacitor 226, and the second current path terminal of the sampling switch 222 is coupled to the output of the buffer 218. Furthermore, the control terminal of the sampling switch 222 is coupled to the first output of the control circuit system 230. Figure 2 In the example, the first current path terminal of the sampling switch 224 is coupled to the first terminal of the sampling capacitor 228, and the second current path terminal of the sampling switch 224 is coupled to the output of the buffer 220. Furthermore, the control terminal of the sampling switch 224 is coupled to the second output of the control circuit system 230.

[0076] exist Figure 2 In the illustrated example, the first output of sampling circuit 210 is coupled to the first input of ADC 212. For example, the first terminal of sampling capacitor 226 is coupled to the first current path terminal of sampling switch 222 and the first input of ADC 212. Therefore, the first terminal of sampling capacitor 226 is coupled to the first output of sampling circuit 210. Furthermore, the second terminal of sampling capacitor 226 is coupled to ground terminal 216. Figure 2In the example, the second output of sampling circuit 210 is coupled to the second input of ADC 212. For instance, the first terminal of sampling capacitor 228 is coupled to the first current path terminal of sampling switch 224 and the second input of ADC 212. Therefore, the first terminal of sampling capacitor 228 is coupled to the second output of sampling circuit 210. Furthermore, the second terminal of sampling capacitor 228 is coupled to ground terminal 216.

[0077] exist Figure 2 In the illustrated example, buffers 218 and 220 buffer the differential analog signal provided by DSA 208. Based on control signals from control circuitry 230, sampling switches 222 and 224 are activated (conducting current) to charge sampling capacitors 226 and 228, respectively. Consequently, sampling circuit 210 samples the differential analog signal provided by DSA 208.

[0078] exist Figure 2 In the illustrated example, the ADC 212 is implemented by at least one of an analog circuit system or a digital circuit system. Figure 2 In the example, the first and second inputs of ADC 212 are coupled to the first and second outputs of sampling circuit 210, respectively. For instance, the first input of ADC 212 is coupled to the first terminal of sampling capacitor 226, and the second input of ADC 212 is coupled to the first terminal of sampling capacitor 228. Figure 2 In the example, the output of ADC 212 is coupled to the input of the processor circuit. For instance, the output of ADC 212 is coupled to the input of processor circuit 114.

[0079] Figure 3 yes Figure 2 A schematic diagram of an example implementation of the DSA 208. Figure 3 In the example, the DSA 208 includes a configurable input network 302, a high-pass filter 304, a first common-mode resistor 306, a second common-mode resistor 308, a low-noise amplifier (LNA) 310, a configurable output network 312, and a control circuitry 314. Figure 3 In the example, the configurable input network 302 has a first input, a second input, a first output, a second output, a third output, and a fourth output. Figure 3 In the example, each of the high-pass filter 304, common-mode resistor 306, and common-mode resistor 308 has a first terminal and a second terminal.

[0080] exist Figure 3 In the illustrated example, the LNA 310 has a first input, a second input, a third input, a fourth input, a first output, a second output, a first terminal, and a second terminal. Figure 3 In the example, the configurable output network 312 has a first terminal, a second terminal, a first control terminal, a second control terminal, a third control terminal, a fourth control terminal, a fifth control terminal, and a sixth control terminal. Although in Figure 3 In the example, the first, second, third, fourth, fifth, and sixth control terminals of the configurable output network 312 are described as a single terminal, but in some embodiments, one or more of the first, second, third, fourth, fifth, or sixth control terminals may be implemented by one or more terminals. Figure 3 In the example, the control circuit system 314 has a first output, a second output, a third output, a fourth output, a fifth output, and a sixth output. Although in Figure 3 In the example, the first output, second output, third output, fourth output, fifth output and sixth output of the control circuit system 314 are described as a single output, but in some embodiments, one or more of the first output, second output, third output, fourth output, fifth output or sixth output may be implemented by one or more outputs.

[0081] exist Figure 3 In the illustrated example, a first input of the configurable input network 302 is coupled to a first input of the DSA 208, and a second input of the configurable input network 302 is coupled to a second input of the DSA 208. Figure 3 In the example, the first output of the configurable input network 302 is coupled to the fourth input of the LNA 310, and the second output of the configurable input network 302 is coupled to the third input of the LNA 310. Furthermore, in Figure 3 In the example, the third output of the configurable input network 302 is coupled to the first input of the LNA 310, and the fourth output of the configurable input network 302 is coupled to the second input of the LNA 310.

[0082] exist Figure 3 In the illustrated example, the first terminal of the high-pass filter 304 is coupled to the first terminal of the LNA 310 and the first terminal of the common-mode resistor 308. Furthermore, the second terminal of the high-pass filter 304 is coupled to the second terminal of the LNA 310 and the first terminal of the common-mode resistor 306. Therefore, the high-pass filter 304 is coupled between the first and second terminals of the LNA 310. Figure 3 In the example, common-mode resistor 306 has R CM The resistor. Furthermore, the first terminal of the common-mode resistor 306 is coupled to the second terminal of the LNA 310 and the second terminal of the high-pass filter 304. Figure 3In the example, the second terminal of the common-mode resistor 306 is coupled to the example ground terminal 316 (also referred to as ground). For example, in some embodiments, the ground terminal 316 is at a voltage of zero V. In some examples, the ground terminal 316 is implemented by ground terminal 216. Figure 3 In the illustrated example, common-mode resistor 308 has R CM The resistance. In Figure 3 In the example, the first terminal of the common-mode resistor 308 is coupled to the first terminal of the LNA 310 and the first terminal of the high-pass filter 304. Furthermore, the second terminal of the common-mode resistor 308 is coupled to the ground terminal 316 (coupled to ground).

[0083] exist Figure 3 In the illustrated example, the first input of the LNA 310 is coupled to the third output of the configurable input network 302. Furthermore, in Figure 3 In the example, the second input of the LNA 310 is coupled to the fourth output of the configurable input network 302. Figure 3 In the example, the third input of the LNA 310 is coupled to the second output of the configurable input network 302. Furthermore, in Figure 3 In the example, the fourth input of LNA 310 is coupled to the first output of configurable input network 302.

[0084] exist Figure 3 In the illustrated example, the first output of LNA 310 is coupled to the first terminal of configurable output network 312. Figure 3 In the example, the first output of the LNA 310 is coupled to the first output of the DSA 208. Furthermore, in Figure 3 In the example, the second output of LNA 310 is coupled to the second terminal of configurable output network 312. Figure 3 In the example, the second output of the LNA 310 is coupled to the second output of the DSA 208. Furthermore, in Figure 3 In the example, the first terminal of LNA 310 is coupled to the first terminal of high-pass filter 304 and the first terminal of common-mode resistor 308. Figure 3 In the example, the second terminal of LNA 310 is coupled to the second terminal of high-pass filter 304 and the first terminal of common-mode resistor 306.

[0085] exist Figure 3 In the illustrated example, the first terminal of the configurable output network 312 is coupled to the first output of the LNA 310. Figure 3 In the example, the second terminal of the configurable output network 312 is coupled to the second output of the LNA 310. Furthermore, in Figure 3In the example, the first control terminal of the configurable output network 312 is coupled to the first output of the control circuit system 314. Figure 3 In the example, the second control terminal of the configurable output network 312 is coupled to the second output of the control circuit system 314.

[0086] exist Figure 3 In the illustrated example, the third control terminal of the configurable output network 312 is coupled to the third output of the control circuit system 314. Figure 3 In the example, the fourth control terminal of the configurable output network 312 is coupled to the fourth output of the control circuit system 314. Furthermore, in Figure 3 In the example, the fifth control terminal of the configurable output network 312 is coupled to the fifth output of the control circuit system 314. Figure 3 In the example, the sixth control terminal of the configurable output network 312 is coupled to the sixth output of the control circuit system 314.

[0087] exist Figure 3 In the illustrated example, the configurable input network 302 includes a first example input resistor 318, a first example input capacitor 320, a second example input resistor 322, and a second example input capacitor 324. Figure 3 In the example, each of the input resistor 318, input capacitor 320, input resistor 322, and input capacitor 324 has a first terminal and a second terminal. Furthermore, in... Figure 3 In the example, the input resistor 318 has a high R value. IN A resistor with a resistance of ohms (Ω). For example, the input resistor 318 has a resistance of zero ohms and R. IN A variable resistor with an adjustable resistance (configurable resistance) between Ω. Figure 3 In the example, the first terminal of input resistor 318 is coupled to the second terminal of input capacitor 320. Furthermore, the second terminal of input resistor 318 is coupled to the first output of configurable input network 302. For example, the second terminal of input resistor 318 is coupled to the fourth input of LNA 310.

[0088] exist Figure 3 In the illustrated example, the input capacitor 320 has a capacitance of up to C. IN The capacitance is a farad (F). For example, the input capacitor 320 has a capacitance between zero F and C. IN A variable capacitor with an adjustable capacitance (configurable capacitance) between F. Figure 3In this example, the first terminal of the input capacitor 320 will operate as the fourth output of the configurable input network 302. For example, the first terminal of the input capacitor 320 is coupled to the second input of the LNA 310. Furthermore, the second terminal of the input capacitor 320 is coupled to the first terminal of the input resistor 318. Thus, the first terminal of the input resistor 318 and the second terminal of the input capacitor 320 are coupled to the first input of the configurable input network 302.

[0089] exist Figure 3 In the illustrated example, the input resistor 322 has a resistance as high as R. IN A resistor with a resistance of Ω. For example, the input resistor 322 has a resistance of zero Ω and R. IN A variable resistor with an adjustable resistance between Ω. Figure 3 In the example, the first terminal of input resistor 322 is coupled to the second terminal of input capacitor 324. Furthermore, the second terminal of input resistor 322 is coupled to the second output of configurable input network 302. For example, the second terminal of input resistor 322 is coupled to the third input of LNA 310.

[0090] exist Figure 3 In the illustrated example, the input capacitor 324 has a capacitance of up to C. IN The capacitance is F. For example, the input capacitor 324 has a capacitance between zero F and C. IN A variable capacitor with an adjustable capacitance between F. Figure 3 In the example, the first terminal of the input capacitor 324 is coupled to the third output of the configurable input network 302. For example, the first terminal of the input capacitor 324 is coupled to the first input of the LNA 310. Furthermore, the second terminal of the input capacitor 324 is coupled to the first terminal of the input resistor 322. Therefore, the first terminal of the input resistor 322 and the second terminal of the input capacitor 324 are coupled to the second input of the configurable input network 302.

[0091] exist Figure 3In the illustrated example, each of input resistor 318, input capacitor 320, input resistor 322, and input capacitor 324 is described as a two-terminal assembly. In some embodiments, each of input resistor 318, input capacitor 320, input resistor 322, and input capacitor 324 includes at least one control terminal to allow tuning of the component's impedance. For example, as a variable component, input resistor 318 is implemented by two or more resistors connected in parallel, wherein at least one of the two or more resistors is coupled in series with a switch to allow a control signal to tune the resistance of input resistor 318. Thus, each of input resistor 318, input capacitor 320, input resistor 322, and input capacitor 324 includes at least one control terminal coupled to a controller, such as control circuitry system 314.

[0092] exist Figure 3 In the illustrated example, the high-pass filter 304 includes a first resistor 326, a high-pass capacitor 328, and a second resistor 330. Figure 3 Each of the example resistor 326, high-pass capacitor 328, and resistor 330 has a first terminal and a second terminal. Figure 3 In the example, resistor 326 has R DIFF The resistor 326 has a resistance of 326. Furthermore, the first terminal of resistor 326 is coupled to the second terminal of high-pass capacitor 328. Figure 3 In the example, the second terminal of resistor 326 is coupled to the second terminal of LNA 310 and the first terminal of common-mode resistor 306. Therefore, the second terminal of resistor 326 is coupled to the second terminal of high-pass filter 304.

[0093] exist Figure 3 In the illustrated example, the high-pass capacitor 328 has C HP The capacitance. In Figure 3 In the example, the first terminal of the high-pass capacitor 328 is coupled to the second terminal of the resistor 330. Furthermore, the second terminal of the high-pass capacitor 328 is coupled to the first terminal of the resistor 326. Figure 3 In the example, resistor 330 has R DIFF The resistor 330 is coupled to the first terminal of the LNA 310 and the first terminal of the common-mode resistor 308. Therefore, the first terminal of the resistor 330 is coupled to the first terminal of the high-pass filter 304. Figure 3In the example, the second terminal of resistor 330 is coupled to the first terminal of high-pass capacitor 328. As described above, high-pass capacitor 328 is coupled between the first and second terminals of LNA 310, resistor 330 is coupled between the first terminal of LNA 310 and high-pass capacitor 328, and resistor 326 is coupled between the second terminal of LNA 310 and high-pass capacitor 328.

[0094] exist Figure 3 In the illustrated example, LNA 310 includes a first transconductance transistor 332, a second transconductance transistor 334, a third transconductance transistor 336, a fourth transconductance transistor 338, a first cross-coupled capacitor 340, a second cross-coupled capacitor 342, a third cross-coupled capacitor 344, and a fourth cross-coupled capacitor 346. Figure 3 In the example, cross-coupled capacitors 340, 342, 344, and 346 have a first terminal and a second terminal. Furthermore, in... Figure 3 In the example, each of transconductance transistors 332, 334, 336 and 338 has a control terminal (gate terminal), a first current path terminal (drain terminal) and a second current path terminal (source terminal).

[0095] exist Figure 3 In the illustrated example, each of transconductance transistors 332, 334, 336, and 338 is implemented by a transistor such as a negative-channel (N-channel) FET. For example, each of transconductance transistors 332, 334, 336, and 338 is implemented by an N-channel metal-oxide-semiconductor (MOS) FET. Figure 3 In this example, the control terminal of transconductance transistor 332 is coupled to a fourth output of configurable input network 302. For instance, the control terminal of transconductance transistor 332 is coupled to a first terminal of input capacitor 320. Therefore, the control terminal of transconductance transistor 332 is coupled to a fourth input of LNA 310.

[0096] exist Figure 3 In the illustrated example, the first current path terminal of the transconductance transistor 332 is coupled to the second output of the configurable input network 302. For example, the first current path terminal of the transconductance transistor 332 is coupled to the second terminal of the input resistor 322. Therefore, the first current path terminal of the transconductance transistor 332 is coupled to the third input of the LNA 310. Figure 3 In the example, the first current path terminal of transconductance transistor 332 is also coupled to the second current path terminal of transconductance transistor 336 and the second terminal of cross-coupled capacitor 342. Figure 3 In the example, the second current path terminal of the transconductance transistor 332 is coupled to the second terminal of the high-pass filter 304 and the first terminal of the common-mode resistor 306. Therefore, the second current path terminal of the transconductance transistor 332 is coupled to the second terminal of the LNA 310.

[0097] exist Figure 3 In the illustrated example, the control terminal of transconductance transistor 334 is coupled to the third output of configurable input network 302. For example, the control terminal of transconductance transistor 334 is coupled to the first terminal of input capacitor 324. Therefore, the control terminal of transconductance transistor 334 is coupled to the first input of LNA 310. Figure 3 In the example, the first current path terminal of the transconductance transistor 334 is coupled to the first output of the configurable input network 302. For example, the first current path terminal of the transconductance transistor 334 is coupled to the second terminal of the input resistor 318. Therefore, the first current path terminal of the transconductance transistor 334 is coupled to the fourth input of the LNA 310.

[0098] exist Figure 3 In the illustrated example, the first current path terminal of transconductance transistor 334 is also coupled to the second current path terminal of transconductance transistor 338 and the second terminal of cross-coupled capacitor 340. Figure 3 In the example, the second current path terminal of the transconductance transistor 334 is coupled to the first terminal of the high-pass filter 304 and the first terminal of the common-mode resistor 308. Therefore, the second current path terminal of the transconductance transistor 334 is coupled to the first terminal of the LNA 310.

[0099] exist Figure 3 In the illustrated example, the control terminal of transconductance transistor 336 is coupled to the first terminal of cross-coupled capacitor 340 and the first terminal of cross-coupled capacitor 344. Figure 3 In the example, the first current path terminal of transconductance transistor 336 is coupled to the second terminal of configurable output network 312 and the second terminal of cross-coupled capacitor 346. Therefore, the first current path terminal of transconductance transistor 336 is coupled to the second output of LNA 310. Furthermore, the second current path terminal of transconductance transistor 336 is coupled to the first current path terminal of transconductance transistor 332 and the second terminal of cross-coupled capacitor 342.

[0100] exist Figure 3 In the illustrated example, the control terminal of transconductance transistor 338 is coupled to the first terminal of cross-coupled capacitor 342 and the first terminal of cross-coupled capacitor 346. Figure 3In the example, the first current path terminal of the transconductance transistor 338 is coupled to the first terminal of the configurable output network 312 and the second terminal of the cross-coupled capacitor 344. Therefore, the first current path terminal of the transconductance transistor 338 is coupled to the first output of the LNA 310. Furthermore, the second current path terminal of the transconductance transistor 338 is coupled to the first current path terminal of the transconductance transistor 334 and the second terminal of the cross-coupled capacitor 340.

[0101] exist Figure 3 In the illustrated example, the cross-coupled capacitor 340 has a capacitance of 4C. Figure 3 In the example, the first terminal of the cross-coupling capacitor 340 is coupled to the control terminal of the transconductance transistor 336 and the first terminal of the cross-coupling capacitor 344. Furthermore, the second terminal of the cross-coupling capacitor 340 is coupled to the first current path terminal of the transconductance transistor 334 and the second current path terminal of the transconductance transistor 338. Therefore, the cross-coupling capacitor 340 cross-couples the control terminal of the transconductance transistor 336 and the second current path terminal of the transconductance transistor 338.

[0102] exist Figure 3 In the illustrated example, the cross-coupled capacitor 342 has a capacitance of 4C. Figure 3 In the example, the first terminal of the cross-coupling capacitor 342 is coupled to the control terminal of the transconductance transistor 338 and the first terminal of the cross-coupling capacitor 346. Furthermore, the second terminal of the cross-coupling capacitor 342 is coupled to the first current path terminal of the transconductance transistor 332 and the second current path terminal of the transconductance transistor 336. Therefore, the cross-coupling capacitor 342 cross-couples the control terminal of the transconductance transistor 338 and the second current path terminal of the transconductance transistor 336.

[0103] exist Figure 3 In the illustrated example, cross-coupled capacitor 344 has a capacitance of C (one-quarter of the capacitance of cross-coupled capacitor 340). Figure 3 In the example, the first terminal of the cross-coupling capacitor 344 is coupled to the control terminal of the transconductance transistor 336 and the first terminal of the cross-coupling capacitor 340. Furthermore, the second terminal of the cross-coupling capacitor 344 is coupled to the first terminal of the configurable output network 312 and the first current path terminal of the transconductance transistor 338. Thus, the cross-coupling capacitor 344 cross-couples the control terminal of the transconductance transistor 336 and the first current path terminal of the transconductance transistor 338.

[0104] exist Figure 3 In the illustrated example, cross-coupled capacitor 346 has a capacitance of C (one-quarter of the capacitance of cross-coupled capacitor 342). Figure 3In the example, the first terminal of the cross-coupling capacitor 346 is coupled to the control terminal of the transconductance transistor 338 and the first terminal of the cross-coupling capacitor 342. Furthermore, the second terminal of the cross-coupling capacitor 346 is coupled to the second terminal of the configurable output network 312 and the first current path terminal of the transconductance transistor 336. Thus, the cross-coupling capacitor 346 cross-couples the control terminal of the transconductance transistor 338 and the first current path terminal of the transconductance transistor 336.

[0105] As described above, the first current path terminal of transconductance transistor 334 is also coupled to the first output of LNA 310. For example, the first current path terminal of transconductance transistor 334 is coupled to the first output of LNA 310 via cross-coupling capacitors 340 and 344. Furthermore, the first current path terminal of transconductance transistor 332 is coupled to the second output of LNA 310. For example, the first current path terminal of transconductance transistor 332 is coupled to the second output of LNA 310 via cross-coupling capacitors 342 and 346.

[0106] exist Figure 3 In the illustrated example, the configurable output network 312 includes a first inductor 348, a first resistor 350, a first switch 352, a second inductor 354, a second resistor 356, a second switch 358, an example resistor 360, and an example capacitor 362. Figure 3 In the example, each of switches 352 and 358 has a control terminal, a first current path terminal, and a second current path terminal. Furthermore, each of inductors 348, 350, 354, 356, 360, and capacitor 362 has a first terminal and a second terminal. Figure 3 In the example, each of inductor 348, inductor 354, resistor 360, and capacitor 362 has a control terminal. Although in Figure 3 In the example, the control terminal of each of inductor 348, inductor 354, resistor 360 and capacitor 362 is described as a single terminal, but in some embodiments, one or more of the control terminals of inductor 348, inductor 354, resistor 360 and capacitor 362 may be implemented by one or more terminals.

[0107] exist Figure 3 In the illustrated example, inductor 348 has an inductance up to L Henry (H). For example, inductor 348 is a variable inductor having a tunable inductance between zero H and LH. According to some embodiments of this disclosure, in conjunction with... Figures 6A to 6B Examples of inductor implementations that can be used to implement inductor 348 are illustrated and described in sections 7A to 7C. Figure 3In the example, the control terminal of inductor 348 is coupled to the fourth output of control circuitry system 314. Therefore, the control terminal of inductor 348 is coupled to the fourth control terminal of configurable output network 312. Figure 3 In the example, the first terminal of inductor 348 is coupled to the second terminal of resistor 350 and the second current path terminal of switch 352. Furthermore, the second terminal of inductor 348 is coupled to the second terminal of inductor 354 and example supply terminal 364. For example, supply terminal 364 is at voltage V. DD V.

[0108] exist Figure 3 In the illustrated example, resistor 350 has R WB A resistance of Ω. In Figure 3 In the example, the first terminal of resistor 350 is coupled to the first current path terminal of switch 352, the first terminal of resistor 360, the first terminal of capacitor 362, the first current path terminal of transconductance transistor 338, and the second terminal of cross-coupled capacitor 344. Furthermore, the second terminal of resistor 350 is coupled to the first terminal of inductor 348 and the second current path terminal of switch 352.

[0109] exist Figure 3 In the illustrated example, switch 352 is implemented by a transistor, such as a FET. Figure 3 In the example, the control terminal of switch 352 is coupled to the third output of control circuit system 314. Therefore, the control terminal of switch 352 is coupled to the third control terminal of configurable output network 312. Figure 3 In the example, the first current path terminal of switch 352 is coupled to the first terminal of resistor 350, the first terminal of resistor 360, the first terminal of capacitor 362, the first current path terminal of transconductance transistor 338, and the second terminal of cross-coupled capacitor 344. Furthermore, the second current path terminal of switch 352 is coupled to the first terminal of inductor 348 and the second terminal of resistor 350.

[0110] exist Figure 3 In the illustrated example, inductor 354 has an inductance up to LH. For example, inductor 354 is a variable inductor with a tunable inductance between zero H and LH. Combined with... Figures 6A to 6B Examples of implementations of the inductor 354, illustrated in sections 7A to 7C, are described and illustrated. Figure 3 In the example, the control terminal of inductor 354 is coupled to the fifth output of control circuit system 314. Therefore, the control terminal of inductor 354 is coupled to the fifth control terminal of configurable output network 312. Figure 3In the example, the first terminal of inductor 354 is coupled to the second terminal of resistor 356 and the second current path terminal of switch 358. Furthermore, the second terminal of inductor 354 is coupled to the second terminal of inductor 348 and supply terminal 364.

[0111] exist Figure 3 In the illustrated example, resistor 356 has R WB A resistance of Ω. In Figure 3 In the example, the first terminal of resistor 356 is coupled to the first current path terminal of switch 358, the second terminal of resistor 360, the second terminal of capacitor 362, the first current path terminal of transconductance transistor 336, and the second terminal of cross-coupled capacitor 346. Furthermore, the second terminal of resistor 356 is coupled to the first terminal of inductor 354 and the second current path terminal of switch 358.

[0112] exist Figure 3 In the illustrated example, switch 358 is implemented by a transistor, such as a FET. Figure 3 In the example, the control terminal of switch 358 is coupled to the sixth output of control circuit system 314. Therefore, the control terminal of switch 358 is coupled to the sixth control terminal of configurable output network 312. Figure 3 In the example, the first current path terminal of switch 358 is coupled to the first terminal of resistor 356, the second terminal of resistor 360, the second terminal of capacitor 362, the first current path terminal of transconductance transistor 336, and the second terminal of cross-coupled capacitor 346. Furthermore, the second current path terminal of switch 358 is coupled to the first terminal of inductor 354 and the second terminal of resistor 356.

[0113] exist Figure 3 In the illustrated example, resistor 360 has a high R value. BPF The resistance. For example, resistor 360 has a resistance of zero Ω and R. BPF A variable resistor with an adjustable resistance between Ω. Figure 3 In the example, the control terminal of resistor 360 is coupled to the second output of control circuit system 314. Therefore, the control terminal of resistor 360 is coupled to the second control terminal of configurable output network 312. Figure 3In the example, the first terminal of resistor 360 is coupled to the first terminal of resistor 350, the first current path terminal of switch 352, the first terminal of capacitor 362, the first current path terminal of transconductance transistor 338, and the second terminal of cross-coupled capacitor 344. Furthermore, the second terminal of resistor 360 is coupled to the first terminal of resistor 356, the first current path terminal of switch 358, the second terminal of capacitor 362, the first current path terminal of transconductance transistor 336, and the second terminal of cross-coupled capacitor 346.

[0114] exist Figure 3 In the illustrated example, capacitor 362 has a value as high as C. BPF The capacitance. For example, capacitor 362 has a capacitance between zero F and C. BPF A variable capacitor with an adjustable capacitance between F. Figure 3 In the example, the control terminal of capacitor 362 is coupled to the first output of control circuit system 314. Therefore, the control terminal of capacitor 362 is coupled to the first control terminal of configurable output network 312.

[0115] exist Figure 3 In the illustrated example, the first terminal of capacitor 362 is coupled to the first terminal of resistor 350, the first current path terminal of switch 352, the first terminal of resistor 360, the first current path terminal of transconductance transistor 338, and the second terminal of cross-coupled capacitor 344. Therefore, the first terminal of resistor 350, the first current path terminal of switch 352, the first terminal of resistor 360, and the first terminal of capacitor 362 are coupled to the first terminal of configurable output network 312. Figure 3 In the example, the second terminal of capacitor 362 is coupled to the first terminal of resistor 356, the first current path terminal of switch 358, the second terminal of resistor 360, the first current path terminal of transconductance transistor 336, and the second terminal of cross-coupled capacitor 346. Therefore, the first terminal of resistor 356, the first current path terminal of switch 358, the second terminal of resistor 360, and the second terminal of capacitor 362 are coupled to the second terminal of configurable output network 312.

[0116] As described above, inductors 348 and 354 form a composite inductor, with a center tap coupled to supply terminal 364. The composite inductor (inductors 348 and 354) is coupled between the first and second terminals of the configurable output network 312. Furthermore, resistor 350 is coupled between the first terminal of the configurable output network 312 and the composite inductor, and switch 352 is coupled in parallel with resistor 350. As described above, resistor 356 is coupled between the second terminal of the configurable output network 312 and the composite inductor, and switch 358 is coupled in parallel with resistor 356. Additionally, resistor 360 and capacitor 362 are coupled between the first and second terminals of the configurable output network 312.

[0117] exist Figure 3 In the illustrated example, at least one of the configurable input network 302 or the configurable output network 312 facilitates the adjustment or configuration of the DSA 208 by the control circuitry system 314 to operate in a bandpass (e.g., narrow) operating mode or a wideband operating mode. For example, the control circuitry system 314 adjusts or configures at least one of the configurable input network 302 or the configurable output network 312 based on one or more values ​​programmed into one or more registers. Figure 3 In the example, when the DSA 208 is configured to operate in a narrow operating mode, the DSA 208 can target a single frequency band, for example, between 200 and 400 MHz, where the center frequency is adjustable or configurable, for example, between 1.8 GHz and 7.2 GHz. Furthermore, when the DSA 208 is configured to operate in a narrow operating mode, the DSA 208 can advantageously achieve improved non-linearity (NF).

[0118] As further described herein, by implementing a variable inductor in the configurable output network 312, the DSA 208 achieves a wide tuning range in narrow operating modes (e.g., between 1.8 GHz and 7.2 GHz) while consuming less on-chip area than other technologies. Figure 3 In the example, when the DSA 208 is configured to operate in a wideband operating mode, the DSA 208 supports operation in a frequency band ranging from, for example, 100 MHz to 6 GHz. Therefore, the DSA 208 can simultaneously support multiple center frequencies, for example, in scenarios where the carrier operates in multiple frequency bands simultaneously.

[0119] exist Figure 3 In the illustrated example, when the DSA 208 is configured to operate in a wideband operating mode, the high-pass filter 304 can improve the mitigation of noise folding. Figure 3In the example, LNA 310 implements a differential common gate (CG) LNA. As described herein, the control terminal of transconductance transistor 336 is cross-coupled to the second current path terminal of transconductance transistor 338 via cross-coupling capacitor 340, and the control terminal of transconductance transistor 338 is cross-coupled to the second current path terminal of transconductance transistor 336 via cross-coupling capacitor 342.

[0120] This cross-coupling will affect the transconductance (g) of transconductance transistors 336 and 338. m The input bandwidth of DSA 208 can be doubled, but it can also be reduced by loading the second current path terminals (source terminals) of transconductance transistors 336 and 338, which may reduce the S11 parameter of the ADC coupled to DSA 208 at higher frequencies. Advantageously, in some embodiments, the capacitive load at the second current path terminals of transconductance transistors 336 and 338 is reduced by reducing the capacitance of cross-coupling capacitors 340 and 342 from 8C to 4C. Some embodiments also reduce the capacitive load by cross-coupling transconductance transistors 336 and 338 via cross-coupling capacitors 344 and 346, the capacitance of which is one-quarter of the capacitance of cross-coupling capacitors 340 and 342.

[0121] For example, the first current path terminal of transconductance transistor 338 and the control terminal of transconductance transistor 336 are cross-coupled via cross-coupling capacitor 344, and the first current path terminal of transconductance transistor 336 and the control terminal of transconductance transistor 338 are cross-coupled via cross-coupling capacitor 346. By cross-coupling transconductance transistors 336 and 338 via cross-coupling capacitors 344 and 346, a higher voltage amplitude is generated at the first current path terminal (drain terminal) of transconductance transistors 336 and 338 than at the second current path terminal (source terminal).

[0122] Therefore, the transconductance (g) of transconductance transistors 336 and 338 m This increases, while simultaneously improving the input bandwidth and S11 parameters of the ADC coupled to the DSA 208 (e.g., at higher frequencies). For example, combining... Figure 3 The described and illustrated cross-coupling achieves the target S11 parameters for frequencies up to 8 GHz, while the S11 parameters for other methods decrease (to less than -10 dB) at frequencies greater than 4 GHz. Therefore, the cross-coupling of transconductance transistors 336, 338 via cross-coupling capacitors 344, 346 improves the S11 parameters of the ADC (e.g., ADC 212) to which the DSA 208 is coupled.

[0123] Table 1 below illustrates example performance characteristics of the DSA 208 when implemented in narrow operating mode and wide operating mode according to embodiments of the present disclosure.

[0124] Table 1

[0125]

[0126] In Table 1, the bandwidth column identifies the bandwidth supported by the DSA 208 when configured in narrow and wide operating modes. In wide operating mode, the DSA 208 has a bandwidth ranging from 100 MHz to 6 GHz. In narrow operating mode, the DSA 208 has a bandwidth of 400 MHz, with a center frequency ranging from 1.8 GHz to 7.2 GHz. Furthermore, Table 1 identifies the input of the maximum gain setting parameter in narrow and wide operating modes. For example, when the DSA 208's gain setting is at its maximum, the input at the maximum gain setting parameter indicates the input power level in decibels (dB) and milliwatts (dBm).

[0127] Table 1 also lists the NF, noise spectral density (NSD), and example use cases of the DSA 208 when constructed in narrow and wide operating modes. For example, when constructed in narrow operating mode, the DSA 208 can support 5G applications in low- and mid-range frequency bands (e.g., L-band (1 GHz to 2 GHz), S-band (2 GHz to 4 GHz), and C-band (4 GHz to 8 GHz). Furthermore, for example, when constructed in wide operating mode, the DSA 208 can be used to sense spurious artifacts via a feedback channel. When constructed in wide operating mode, the DSA 208 can support multi-band applications where the carrier operates simultaneously in multiple frequency bands.

[0128] In some embodiments, the control circuitry 314 may be implemented as a general-purpose or custom processor, or controlled and coupled to memory and configured to execute instructions in that memory. In some embodiments, the control circuitry 314 may be implemented or include a state machine and / or a hardware accelerator. In some embodiments, the control circuitry 314 may be implemented in an FPGA. In some embodiments, the control circuitry controls the DSA 208 in response to instructions / triggers from the processor circuitry 114. In some embodiments, the control circuitry 314 may not execute instructions from memory. Other embodiments are also possible.

[0129] Figure 4 When constructed in narrow operating mode Figure 3 A schematic diagram of the DSA 208. In Figure 4In the example, control circuitry 314 closes switches 352 and 358 to configure the configurable output network 312, or more generally, the DSA 208, into a narrow operating mode. In the context of describing the state of a switch or transistor, "closed" or "on" refers to the state when the switch or transistor is conducting current. Furthermore, in the context of describing the state of a switch or transistor, "open" or "off" refers to the state when the switch or transistor is not conducting current.

[0130] exist Figure 4 In the illustrated example, by closing switches 352 and 358, control circuitry 314 enables configurable output network 312 to implement a tunable BPF. For example, by closing switch 352, control circuitry 314 couples the first terminal of inductor 348 to the first terminal of resistor 360, the first terminal of capacitor 362, the first current path terminal of transconductance transistor 338, and the second terminal of cross-coupled capacitor 344, thereby bypassing resistor 350. Furthermore, for example, by closing switch 358, control circuitry 314 couples the first terminal of inductor 354 to the second terminal of resistor 360, the second terminal of capacitor 362, the first current path terminal of transconductance transistor 336, and the second terminal of cross-coupled capacitor 346, thereby bypassing resistor 356.

[0131] exist Figure 4 In the illustrated example, by implementing a tunable BPF at the output of the DSA 208, some embodiments advantageously reduce noise aliasing and improve the NF of the DSA 208 (by 4.5 dB). For example, noise can spread across the entire spectrum of an analog signal before it is filtered. When the analog signal is sampled, the noise spreading across the spectrum is folded into the frequency band where the analog signal is sampled. For example, as a result of sampling, the amplitude of noise in the sampled frequency band is amplified by signal artifacts from other frequency bands. Therefore, noise folding or noise aliasing can cause the ADC to incorrectly identify noise as a sample to be converted into a digital value.

[0132] For example, if the analog signal provided by the DSA has a frequency of 3.5 GHz, and the sampling circuit samples the analog signal at 3 giga-samples per second (GSPS), the sampled signal provided to the ADC will appear as a 0.5 GHz signal, with noise folding across the 0.5 GHz, 2.5 GHz, 3.5 GHz, 5.5 GHz, and 6.5 GHz frequency bands. Noise folding can reduce the noise aliasing of the DSA by, for example, 6 dB. To mitigate noise aliasing, some techniques implement a low-pass filter (LPF) at the output of the DSA. An LPF can operate over a wide frequency range, while other filters (e.g., a BPF) operate over a specific frequency band. For example, to support a wide frequency range, a BPF can be implemented based on multiple inductor-capacitor (LC) tank paths multiplexed together, where each LC tank path corresponds to a different frequency range.

[0133] However, implementing a BPF using multiple LC trenches consumes a significant amount of on-chip area and is impractical for modern RF applications (e.g., due to the large bandwidth required for modern RF applications). Furthermore, implementing a BPF using multiple LC trenches links the supported bandwidth and gain of the BPF, resulting in reduced gain at lower frequencies. A BPF based on multiple LC trenches also has limited tunability because only the capacitance of the LC trenches can be adjusted. Therefore, an LPF can be used in applications requiring high bandwidth. In operation, when noise is at frequencies exceeding the LPF's cutoff frequency, the LPF removes noise appearing in the signal's spectrum. Thus, depending on the signal's frequency content, a significant amount of noise is still folded into the signal's sampling band.

[0134] As described in this article, in Figure 4 In the example, the configurable output network 312 is configured to implement a tunable BPF using a variable inductor. In some embodiments, by implementing as Figures 6A to 6B Or the inductors 348 and / or 354 described in 7A to 7C, the BPF implemented by the configurable output network 312 can advantageously consume significantly less area than, for example, a BPF implemented based on multiple LC tank circuits. Furthermore, by implementing such... Figures 6A to 6B The BPF implemented with the inductors 348 and / or 354 described in 7A to 7C, by the configurable output network 312, can advantageously support a greater degree of tuning than, for example, a BPF implemented based on multiple LC tank circuits.

[0135] In some embodiments, control circuitry 314 may (1) configure inductors 348 and / or 354 to shift the frequency band of the BPF implemented by the configurable output network 312, and (2) configure the capacitance of capacitor 362 to shift the center frequency of the BPF implemented by the configurable output network 312. Thus, the BPF implemented by the configurable output network 312 supports a large bandwidth (e.g., 1.8 GHz to 7.2 GHz) in an area-efficient manner. Furthermore, by constructing the configurable output network 312 to implement the BPF at the output of the DSA 208, some embodiments can advantageously reduce the amount of noise folded into the sampling band. For example, only noise present in the BPF band (if present) can be folded into the sampling band. Therefore, when the sampling circuit 210 samples the analog signal provided by the DSA 208, only noise from the BPF band can be folded into the sampling band. Thus, the ADC 212 can appropriately distinguish between noise and samples to be converted into digital values.

[0136] Figure 5 When constructed in broadband operating mode according to an embodiment of this disclosure Figure 3 A schematic diagram of the DSA 208. In Figure 5 In the example, control circuitry 314 disconnects switches 352 and 358, sets the resistance of resistor 360 to zero Ω, and sets the capacitance of capacitor 362 to zero F, thereby configuring the configurable output network 312, or more generally the DSA 208, into a wideband operating mode. Furthermore, in Figure 5 In the example, C P Example parasitic capacitance 502 is formed between the first and second terminals of configurable output network 312.

[0137] exist Figure 5 In the illustrated example, by opening switches 352 and 358, control circuitry 314 effectively adds a shunt peaking load (implemented by resistors 350 and 356) at the output of DSA208. Figure 5 The configurable output network 312 is constructed as described herein, and the control circuitry 314 enables the configurable output network 312 to implement a tunable wideband LPF. Figure 5 In the example, the wideband LPF implemented by the configurable output network 312 can provide a flat frequency band (also known as the passband), for example from 100MHz to 6GHz, where the magnitude of the signal provided by the LNA 310 is kept within 1dB of the upper limit of the passband.

[0138] exist Figure 5In the illustrated example, when the configurable output network 312 is configured in wideband operation mode, the DSA 208 can support multi-band applications where the carrier operates in multiple frequency bands simultaneously. For example, in a dual-band scenario, the RF circuitry may need to support two frequency bands for a specific communication application. Therefore, implementing a wideband LPF at the output of the DSA 208 facilitates support for multi-band applications via the RF circuitry. Furthermore, when the configurable output network 312 is configured in wideband operation mode, the DSA 208 can be used to sense spurious artifacts via a feedback channel.

[0139] For example, in MIMO RF applications, feedback channels are implemented to improve the ACPR between the transmitters of the RF circuit. Therefore, in MIMO RF applications, feedback channels are implemented to facilitate DPD (Distributed Dynamic Processing) to correct nonlinearities in the transmitter's PA (Power Amplifier). For example, the ADC can sense nonlinearities via the feedback channel, and the sampled signal can be used to adjust the coefficients used for the DPD. In such an example, implementing the configurable output network 312 of the DSA 208 as a wideband LPF allows the ADC in the feedback channel to sense spurious artifacts in adjacent frequency bands (e.g., third-order harmonic distortion (HD3) artifacts and third-order intermodulation distortion (IMD3) artifacts).

[0140] As described herein, implementing an LPF at the output of a DSA can increase noise folding in the sampled signal. To mitigate this noise folding, the DSA 208 can implement a high-pass filter 304 as described herein. For example, the high-pass filter 304 filters out signals with frequencies less than 1.6 GHz to reduce overall noise folding during sampling, as well as other low-frequency noise (e.g., flicker noise). Thus, when the DSA 208 is implemented as a wideband LPF, the high-pass filter 304 achieves a 6 dB NF for the DSA 208.

[0141] Furthermore, while implementing the configurable output network 312 as a wideband LPF allows the DSA 208 to support wideband applications, such as for feedback ADCs and multi-band carriers, implementing the configurable output network 312 as a wideband LPF can slightly reduce the gain of the DSA 208 (e.g., from 12.5 dB to 9.5 dB). This degradation of the DSA 208's NF is acceptable in such applications (e.g., in feedback applications where spurious artifacts are sensed but control of the ADC input level may not be necessary). As illustrated in Table 1, the DSA 208 has an NSD of 7 dB when constructed in wideband operating mode and 4 dB when constructed in narrowband operating mode. In wideband applications, the trade-off between the NF degradation (3 dB) and the improved NSD is acceptable.

[0142] exist Figure 3 , 4In the example of 5, transistors 332, 334, 336, and 338 are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, transistors 332, 334, 336, and 338 can be N-channel FETs, N-channel insulated-gate bipolar transistors (IGBTs), N-channel junction field-effect transistors (JFETs), negative-positive-negative (NPN) bipolar junction transistors (BJTs), or slightly modified positive (P-type) equivalent devices. Transistors 332, 334, 336, and 338 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 332, 334, 336, and 338 can be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0143] Figure 6A It is feasible. Figure 3 A schematic diagram of a first example inductor 600, comprising at least one of inductors 348 and 354. Figure 6A In the example, inductor 600 is a four-turn inductor, wherein the center tap of inductor 600 is open, and inductor 600 includes four ports (labeled P1-N1, P2-N2, P3-N3, and P4-N4). Furthermore, the center tap of inductor 600 is located between ports labeled P4-N4. Figure 6A In the example, inductor 600 includes two leads labeled L1 to L2.

[0144] exist Figure 6A In the illustrated example, inductor 600 includes a first switch 602, a first connector 604, a second connector 606, a second switch 608, a third connector 610, a fourth connector 612, a fifth connector 614, a third switch 616, a sixth connector 618, a seventh connector 620, an eighth connector 622, a fourth switch 624, a ninth connector 626, a tenth connector 628, and an eleventh connector 630. Figure 6A In the examples, each of switches 602, 608, 616, and 624 has a control terminal, a first current path terminal, and a second current path terminal. Furthermore, each of connectors 604, 606, 610, 612, 614, 618, 620, 622, 626, 628, and 630 has a first terminal and a second terminal.

[0145] exist Figure 6AIn the illustrated examples, each of switches 602, 608, 616, and 624 is implemented by a transistor, such as a FET. Furthermore, each of connectors 604, 606, 610, 612, 614, 618, 620, 622, 626, 628, and 630 is implemented by a conductor, such as doped polysilicon or a metal (copper, aluminum, etc.). Figure 6A In the example, components of inductor 600 can be implemented in various layers of the semiconductor. For example, connectors 604, 606, 610, 614, 618, 622, and 626, 630 are implemented in a first metal layer of the semiconductor (represented in the first metal layer, located in the first metal layer, etc.). Furthermore, connectors 612, 620, 628 are implemented in a second metal layer of the semiconductor (represented in the second metal layer, located in the second metal layer, etc.). For example, the second metal layer is below the first metal layer. In some examples, the second metal layer is above the first metal layer.

[0146] exist Figure 6A In the illustrated example, ports (P1-N1, P2-N2, P3-N3, and P4-N4) are implemented in the first metal layer of the semiconductor. Furthermore, switches 602, 608, 616, and 624 are implemented directly below the ports (P1-N1, P2-N2, P3-N3, and P4-N4). For example, switches 602, 608, 616, and 624 are implemented in the substrate of the semiconductor. Figure 6A In the example, the control terminal of switch 602 is coupled to control circuitry 314. For instance, the control terminal of switch 602 is connected via a top metal layer to the supply voltage provided by control circuitry 314. Figure 6A In the example, the first current path terminal of switch 602 is coupled to the first terminal (P1) of the first port (P1-N1), and the second current path terminal of switch 602 is coupled to the second terminal (N1) of the first port (P1-N1).

[0147] exist Figure 6A In the illustrated example, the first terminal of connector 604 is coupled to the first terminal (P1) of the first port (P1-N1), and the second terminal of connector 604 is coupled to the first lead (L1) of inductor 600. Figure 6A In the example, the first terminal of connector 606 is coupled to the second lead (L2) of inductor 600, and the second terminal of connector 606 is coupled to the second terminal (N1) of the first port (P1-N1). Therefore, the first current path terminal of switch 602 is coupled to the first terminal of connector 604, and the second current path terminal of switch 602 is coupled to the second terminal of connector 606. Figure 6AIn the example, connectors 604 and 606 are arranged in a first shape. For example, connectors 604 and 606 are arranged in an octagonal shape.

[0148] exist Figure 6A In the illustrated example, the control terminal of switch 608 is coupled to control circuitry 314. For example, the control terminal of switch 608 is connected via a top metal layer to the supply voltage provided by control circuitry 314. Figure 6A In the example, the first current path terminal of switch 608 is coupled to the first terminal (P2) of the second port (P2-N2), and the second current path terminal of switch 608 is coupled to the second terminal (N2) of the second port (P2-N2).

[0149] exist Figure 6A In the illustrated example, the first terminal of connector 610 is coupled to the second terminal of connector 612, and the second terminal of connector 610 is coupled to the first terminal (P2) of the second port (P2-N2). Figure 6A In the example, the first terminal of connector 612 is coupled to the second terminal (N1) of the first port (P1-N1), and the second terminal of connector 612 is coupled to the first terminal of connector 610. Therefore, the first terminal of connector 612 is coupled to the second terminal of connector 606. Figure 6A In the example, the first terminal of connector 614 is coupled to the second terminal (N2) of the second port (P2-N2), and the second terminal of connector 614 is coupled to the first terminal (P1) of the first port (P1-N1). Therefore, the second terminal of connector 614 is coupled to the first terminal of connector 604.

[0150] exist Figure 6A In the illustrated example, the first current path terminal of switch 608 is coupled to the second terminal of connector 610, and the second current path terminal of switch 608 is coupled to the first terminal of connector 614. Figure 6A In the example, connectors 610 and 614 are arranged in a second shape concentric with the first shape. For example, connectors 610 and 614 are arranged in an octagonal shape concentric with the octagonal shape formed by connectors 604 and 606.

[0151] exist Figure 6A In the illustrated example, the control terminal of switch 616 is coupled to control circuitry 314. For example, the control terminal of switch 616 is connected via a top metal layer to the supply voltage provided by control circuitry 314. Figure 6AIn the example, the first current path terminal of switch 616 is coupled to the first terminal (P3) of the third port (P3-N3), and the second current path terminal of switch 616 is coupled to the second terminal (N3) of the third port (P3-N3).

[0152] exist Figure 6A In the illustrated example, the first terminal of connector 618 is coupled to the first terminal (P3) of the third port (P3-N3), and the second terminal of connector 618 is coupled to the first terminal of connector 620. Figure 6A In the example, the first terminal of connector 620 is coupled to the second terminal of connector 618, and the second terminal of connector 620 is coupled to the second terminal (N2) of the second port (P2-N2). Therefore, the second terminal of connector 620 is coupled to the first terminal of connector 614. Figure 6A In the example, the first terminal of connector 622 is coupled to the first terminal (P2) of the second port (P2-N2), and the second terminal of connector 622 is coupled to the second terminal (N3) of the third port (P3-N3).

[0153] exist Figure 6A In the illustrated example, the first current path terminal of switch 616 is coupled to the first terminal of connector 618, and the second current path terminal of switch 616 is coupled to the second terminal of connector 622. Figure 6A In the example, connectors 618 and 622 are arranged in a third shape concentric with the second shape. For example, connectors 618 and 622 are arranged in an octagonal shape concentric with the octagonal shape formed by connectors 610 and 614.

[0154] exist Figure 6A In the illustrated example, the control terminal of switch 624 is coupled to control circuitry 314. For example, the control terminal of switch 624 is connected via a top metal layer to the supply voltage provided by control circuitry 314. Figure 6A In the example, the first current path terminal of switch 624 is coupled to the first terminal (P4) of the fourth port (P4-N4), and the second current path terminal of switch 624 is coupled to the second terminal (N4) of the fourth port (P4-N4).

[0155] exist Figure 6A In the illustrated example, the first terminal of connector 626 is coupled to the second terminal of connector 628, and the second terminal of connector 626 is coupled to the first terminal (P4) of the fourth port (P4-N4). Figure 6AIn the example, the first terminal of connector 628 is coupled to the second terminal (N3) of the third port (P3-N3), and the second terminal of connector 628 is coupled to the first terminal of connector 626. Therefore, the first terminal of connector 628 is coupled to the second terminal of connector 622. Figure 6A In the example, the first terminal of connector 630 is coupled to the second terminal (N4) of the fourth port (P4-N4), and the second terminal of connector 630 is coupled to the first terminal (P3) of the third port (P3-N3). Therefore, the second terminal of connector 630 is coupled to the first terminal of connector 618.

[0156] exist Figure 6A In the illustrated example, the first current path terminal of switch 624 is coupled to the second terminal of connector 626, and the second current path terminal of switch 624 is coupled to the first terminal of connector 630. Figure 6A In the example, connectors 626 and 630 are arranged in a fourth shape concentric with the third shape. For example, connectors 626 and 630 are arranged in an octagonal shape concentric with the octagonal shape formed by connectors 618 and 622.

[0157] exist Figure 6A In the illustrated example, inductor 600 can be arranged in four different configurations with four different inductances. For example, depending on which of switches 602, 608, 616, and 624 is configured to be closed (via control circuitry 314), inductor 600 can be configured in four different configurations. Figure 6A In the examples, four different arrangements have inductances of 0.6 nanohenries (nH), 1.4 nH, 2.5 nH, and 3.6 nH. Therefore, the inductor 600 can be tuned based on the application in which the DSA 208 is implemented.

[0158] For example, when the configurable output network 312 is implemented as a BPF, setting different inductance values ​​for inductor 600 allows the user to tune the center frequency of the passband (e.g., from 1.8 GHz to 7.2 GHz). Furthermore, when the configurable output network 312 is implemented as a wideband LPF, the user can tune the cutoff frequency of the wideband LPF by adjusting the inductance of inductor 600. For example, when the configurable output network 312 is implemented as a wideband LPF, the inductance of inductor 600 (by control circuitry 314) is set to 1.4 nH to achieve a passband from 100 MHz to 6 GHz.

[0159] like Figure 6AAs illustrated in the examples, for a four-turn inductor coil, four different inductance values ​​can be achieved for inductor 600. Therefore, depending on which of switches 602, 608, 616, and 624 is configured to be closed (via control circuitry 314), inductor 600 can be configured in four different arrangements with different inductances. More generally, for an N-turn inductor coil, N different inductance values ​​can be achieved for the inductor. Therefore, the examples described herein include programmable inductors that achieve a tunable passband in a manner that consumes less area than other methods. For example, as described herein, a BPF can be implemented based on multiple LC tank paths multiplexed together, where each LC tank path corresponds to a different frequency range. Implementing a tunable passband using multiple LC tank paths is more efficient than based on... Figure 6A The 600 inductor with tunable passband consumes at least three to four times more area.

[0160] Figure 6B This is a cross-sectional view illustrating how switch 624 is coupled to connectors 626 and 630 of the first metal layer of the semiconductor. For example, in Figure 6B In this example, inductor 600 is implemented in an example semiconductor 632 having ten metal layers, a top metal layer, and a substrate. Figure 6B In the example, connectors 604, 606, 610, 614, 618, 622, 626, and 630 are implemented in the top metal layer of semiconductor 632, and connectors 612, 620, and 628 (not shown) are implemented in a metal layer directly beneath the top metal layer of semiconductor 632. Figure 6B In the example, the fourth port (P4-N4) is implemented in the top layer metal of semiconductor 632.

[0161] exist Figure 6B In the illustrated example, switch 624 is implemented in the substrate of semiconductor 632 and connected to connectors 626 and 630 through a via through a metal layer of semiconductor 632. For example, a first current path terminal of switch 624 is coupled to a first terminal (P4) of the fourth port (P4-N4), and a second current path terminal of switch 624 is coupled to a second terminal (N4) of the fourth port (P4-N4). Figure 6B In the example, the control terminal of switch 624 is connected to the supply voltage provided by control circuit system 314 through a through-hole passing through the top metal of semiconductor 632.

[0162] In the examples described herein, switch 616 is coupled to connectors 618 and 622 in a similar manner to how switch 624 is coupled to connectors 626 and 630. In the examples described herein, switch 608 is coupled to connectors 610 and 614 in a similar manner to how switch 624 is coupled to connectors 626 and 630. In the examples described herein, switch 602 is coupled to connectors 604 and 606 in a similar manner to how switch 624 is coupled to connectors 626 and 630.

[0163] Figure 7A The embodiments of this disclosure are implementable. Figure 3 A schematic diagram of a second example inductor 700, comprising at least one of inductors 348 and 354. Figure 7A In the example, inductor 700 is a four-turn inductor implemented in two semiconductor layers, and inductor 700 includes four ports (labeled P1-N1, P2-N2, P3-N3, and P4-N4). Furthermore, in... Figure 7A In the example, inductor 700 includes two leads labeled L1 to L2.

[0164] exist Figure 7A In the illustrated example, inductor 700 includes a first switch 702, a first connector 704, a second connector 706, a second switch 708, a third connector 710, a fourth connector 712, a fifth connector 714, a third switch 716, a sixth connector 718, a seventh connector 720, an eighth connector 722, a fourth switch 724, a ninth connector 726, and a tenth connector 728. Figure 7A In the examples, each of switches 702, 708, 716, and 724 has a control terminal, a first current path terminal, and a second current path terminal. Furthermore, each of connectors 704, 706, 710, 712, 714, 718, 720, 722, 726, and 728 has a first terminal and a second terminal.

[0165] exist Figure 7A In the illustrated examples, each of switches 702, 708, 716, and 724 is implemented using a transistor, such as a FET. Furthermore, each of connectors 704, 706, 710, 712, 714, 718, 720, 722, 726, and 728 is implemented using a conductor, such as doped polysilicon or a metal (copper, aluminum, etc.). Figure 7AIn the example, the components of inductor 700 can be implemented in various layers of the semiconductor. For example, connectors 704, 706, 710, 714, and 720 are implemented in a first metal layer of the semiconductor (represented in the first metal layer, located in the first metal layer, etc.). Furthermore, connectors 712, 718, 722, and 726, 728 are implemented in a second metal layer of the semiconductor (represented in the second metal layer, located in the second metal layer, etc.). For example, the second metal layer is below the first metal layer. In some examples, the second metal layer is above the first metal layer.

[0166] exist Figure 7A In the illustrated example, ports (P1-N1 and P2-N2) are implemented in the first metal layer of the semiconductor. Furthermore, switches 702 and 708 are implemented below the ports (P1-N1 and P2-N2). For example, switches 702 and 708 are implemented in the substrate of the semiconductor. Figure 7A In the example, the ports (P3-N3 and P4-N4) are implemented in the second metal layer of the semiconductor. Furthermore, switches 716 and 724 are implemented below the ports (P3-N3 and P4-N4). For example, switches 716 and 724 are implemented in the substrate of the semiconductor. Figure 7A In the example, the control terminal of switch 702 is coupled to control circuitry 314. For instance, the control terminal of switch 702 is connected via a top metal layer to the supply voltage provided by control circuitry 314. Figure 7A In the example, the first current path terminal of switch 702 is coupled to the first terminal (P1) of the first port (P1-N1), and the second current path terminal of switch 702 is coupled to the second terminal (N1) of the first port (P1-N1).

[0167] exist Figure 7A In the illustrated example, the first terminal of connector 704 is coupled to the first terminal (P1) of the first port (P1-N1), and the second terminal of connector 704 is coupled to the first lead (L1) of inductor 700. Figure 7A In the example, the first terminal of connector 706 is coupled to the second lead (L2) of inductor 700, and the second terminal of connector 706 is coupled to the second terminal (N1) of the first port (P1-N1). Therefore, the first current path terminal of switch 702 is coupled to the first terminal of connector 704, and the second current path terminal of switch 702 is coupled to the second terminal of connector 706. Figure 7A In the example, connectors 704 and 706 are arranged in a first shape. For example, connectors 704 and 706 are arranged in an octagonal shape.

[0168] exist Figure 7AIn the illustrated example, the control terminal of switch 708 is coupled to control circuitry 314. For example, the control terminal of switch 708 is connected via a top metal layer to the supply voltage provided by control circuitry 314. Figure 7A In the example, the first current path terminal of switch 708 is coupled to the first terminal (P2) of the second port (P2-N2), and the second current path terminal of switch 708 is coupled to the second terminal (N2) of the second port (P2-N2).

[0169] exist Figure 7A In the illustrated example, the first terminal of connector 710 is coupled to the second terminal of connector 712, and the second terminal of connector 710 is coupled to the first terminal (P2) of the second port (P2-N2). Figure 7A In the example, the first terminal of connector 712 is coupled to the second terminal (N1) of the first port (P1-N1), and the second terminal of connector 712 is coupled to the first terminal of connector 710. Therefore, the first terminal of connector 712 is coupled to the second terminal of connector 706. Figure 7A In the example, the first terminal of connector 714 is coupled to the second terminal (N2) of the second port (P2-N2), and the second terminal of connector 714 is coupled to the first terminal (P1) of the first port (P1-N1). Therefore, the second terminal of connector 714 is coupled to the first terminal of connector 704.

[0170] exist Figure 7A In the illustrated example, the first current path terminal of switch 708 is coupled to the second terminal of connector 710, and the second current path terminal of switch 708 is coupled to the first terminal of connector 714. Figure 7A In the example, connectors 710 and 714 are arranged in a second shape concentric with the first shape. For example, connectors 710 and 714 are arranged in an octagonal shape concentric with the octagonal shape formed by connectors 704 and 706.

[0171] exist Figure 7A In the illustrated example, the control terminal of switch 716 is coupled to control circuitry 314. For example, the control terminal of switch 716 is connected via a top metal layer to the supply voltage provided by control circuitry 314. Figure 7A In the example, the first current path terminal of switch 716 is coupled to the first terminal (P3) of the third port (P3-N3), and the second current path terminal of switch 716 is coupled to the second terminal (N3) of the third port (P3-N3).

[0172] exist Figure 7AIn the illustrated example, the first terminal of connector 718 is coupled to the first terminal (P3) of the third port (P3-N3), and the second terminal of connector 718 is coupled to the second terminal (N2) of the second port (P2-N2). For example, the second terminal of connector 718 is coupled to the first terminal of connector 714. Figure 7A In the example, the first terminal of connector 720 is coupled to the second terminal of connector 728, and the second terminal of connector 720 is coupled to the first terminal (P3) of the third port (P3-N3). For example, the second terminal of connector 720 is coupled to the first terminal of connector 718. Figure 7A In the example, the first terminal of connector 722 is coupled to the first terminal (P2) of the second port (P2-N2), and the second terminal of connector 722 is coupled to the second terminal (N3) of the third port (P3-N3). For example, the first terminal of connector 722 is coupled to the second terminal of connector 710.

[0173] exist Figure 7A In the illustrated example, the first current path terminal of switch 716 is coupled to the first terminal of connector 718, and the second current path terminal of switch 716 is coupled to the second terminal of connector 722. Figure 7A In one example, connectors 718 and 722 are arranged in a third shape that is concentric with and substantially aligned with the second shape. For example, connectors 718 and 722 are arranged in an octagonal shape that is concentric with and substantially aligned with the octagonal shape formed by connectors 710 and 714.

[0174] exist Figure 7A In the illustrated example, the control terminal of switch 724 is coupled to control circuitry 314. For example, the control terminal of switch 724 is connected via a top metal layer to the supply voltage provided by control circuitry 314. Figure 7A In the example, the first current path terminal of switch 724 is coupled to the first terminal (P4) of the fourth port (P4-N4), and the second current path terminal of switch 724 is coupled to the second terminal (N4) of the fourth port (P4-N4).

[0175] exist Figure 7A In the illustrated example, the first terminal of connector 726 is coupled to the second terminal (N3) of the third port (P3-N3), and the second terminal of connector 726 is coupled to the first terminal (P4) of the fourth port (P4-N4). For example, the first terminal of connector 726 is coupled to the second terminal of connector 722. Figure 7AIn the example, the first terminal of connector 728 is coupled to the second terminal (N4) of the fourth port (P4-N4), and the second terminal of connector 728 is coupled to the first terminal of connector 720.

[0176] exist Figure 7A In the illustrated example, the first current path terminal of switch 724 is coupled to the second terminal of connector 726, and the second current path terminal of switch 724 is coupled to the first terminal of connector 728. Figure 7A In one example, connectors 726 and 728 are arranged in a fourth shape that is concentric with and substantially aligned with the first shape. For example, connectors 726 and 728 are arranged in an octagonal shape that is concentric with and substantially aligned with the octagonal shape formed by connectors 704 and 706.

[0177] like Figure 7A As described, inductor 700 is a four-turn inductor implemented in two layers. For example, a first turn is formed in the first metal layer of the semiconductor via connectors 704 and 714; a second turn is formed in the second metal layer of the semiconductor via connectors 718 and 728 (connected via connector 720 in the first metal layer); a third turn is formed in the second metal layer via connectors 726 and 722; and a fourth turn is formed in the first metal layer via connectors 710 and 706 (connected via connector 712 in the second metal layer). Therefore, inductor 700 can be arranged in four different configurations with four different inductances, depending on which of the switches 702, 708, 716, and 724 is configured to be closed (via control circuit system 314). Figure 7A In the example, compared to inductor 600, inductor 700 can reduce the area consumed by a four-turn inductor by approximately 62%. For instance, inductor 600 consumes 0.0676 square millimeters (mm²). 2 The area of ​​the inductor is 0.0256 mm², and the inductor 700 consumes 0.0256 mm². 2 The area.

[0178] Figure 7B This is a cross-sectional view illustrating how switch 708 is coupled to connectors 710 and 714 of the first metal layer of the semiconductor. For example, in Figure 7B In this example, inductor 700 is implemented in an example semiconductor 730 having ten metal layers, a top metal layer, and a substrate. Figure 7B In the example, connectors 704, 706, 710, and 714 are implemented in the top metal layer of semiconductor 730, and connectors 718, 722, 726, and 728 are implemented in a metal layer directly beneath the top metal layer of semiconductor 730. Figure 7BIn the example, the second port (P2-N2) is implemented in the top metal of semiconductor 730.

[0179] exist Figure 7B In the illustrated example, switch 708 is implemented in the substrate of semiconductor 730 and connected to connectors 710 and 714 through a via through the metal layer of semiconductor 730. For example, a first current path terminal of switch 708 is coupled to a first terminal (P2) of the second port (P2-N2), and a second current path terminal of switch 708 is coupled to a second terminal (N2) of the second port (P2-N2). Figure 7B In the example, the control terminal of switch 708 is connected to the supply voltage provided by control circuitry system 314 via a through-hole passing through the top metal of semiconductor 730. In the example described herein, switch 702 is coupled to connectors 704 and 706 in a similar manner to how switch 708 is coupled to connectors 710 and 714.

[0180] Figure 7C This is a cross-sectional view illustrating how the switch 716 is coupled to connectors 718, 722 of a second metal layer of a semiconductor according to an embodiment of the present disclosure. For example, in Figure 7C In this embodiment, inductor 700 is implemented within semiconductor 730. Figure 7C In the example, the third port (P3-N3) is implemented in a metal layer directly beneath the top metal of semiconductor 730. Figure 7C In the example, switch 716 is implemented in the substrate of semiconductor 730 and connected to connectors 718 and 722 through a via through the metal layer of semiconductor 730. For example, a first current path terminal of switch 716 is coupled to a first terminal (P3) of the third port (P3-N3), and a second current path terminal of switch 716 is coupled to a second terminal (N3) of the third port (P3-N3). Figure 7C In the example, the control terminal of switch 716 is connected to the supply voltage provided by control circuitry system 314 via a through-hole passing through the top metal of semiconductor 730. In the example described herein, switch 724 is coupled to connectors 726, 728 in a similar manner to how switch 716 is coupled to connectors 718, 722.

[0181] Figure 8 This diagram illustrates an embodiment of a method 800 for operating a DSA, such as DSA 300, according to an embodiment of this disclosure. Method 800 may be implemented, for example, by a control circuitry system 314. Method 800 begins at block 802, where the control circuitry system 314 configures the configurable output network 312 of the DSA 208 to operate in a first operating mode. Figure 8In the example, the first operating mode is a wideband operating mode. For instance, at block 802, control circuitry 314 disconnects switches 352 and 358, sets the corresponding inductances of inductors 348 and 354, and disables resistors 360 and capacitors 362. By disconnecting switches 352 and 358, setting the corresponding inductances of inductors 348 and 354, and disabling resistors 360 and capacitors 362, control circuitry 314 operates the configurable output network 312 of DSA 208 as a low-pass filter in the first operating mode. At block 804, control circuitry 314 operates DSA 208 in the first operating mode.

[0182] exist Figure 8 In the illustrated example, at block 806, the control circuitry 314 configures the configurable output network 312 of the DSA 208 to operate in a second operating mode at a second time. For example, the second time is after the first time. Figure 8 In the example, the second operating mode is a narrowband operating mode. For example, at block 806, control circuitry 314 closes switches 352 and 358, sets the corresponding inductances of inductors 348 and 354, sets the resistance of resistor 360, and sets the capacitance of capacitor 362. By closing switches 352 and 358, setting the corresponding inductances of inductors 348 and 354, setting the resistance of resistor 360, and setting the capacitance of capacitor 362, control circuitry 314 operates the configurable output network 312 of DSA 208 as a bandpass filter in the second operating mode. At block 808, control circuitry 314 operates DSA 208 in the second operating mode.

[0183] In some examples, the first operating mode is a narrowband operating mode. In such examples, control circuitry 314 closes switches 352 and 358, sets the corresponding inductances of inductors 348 and 354, sets the resistance of resistor 360, and sets the capacitance of capacitor 362 to place the configurable output network 312 in narrowband operating mode. Therefore, control circuitry 314 operates the configurable output network 312 of DSA 208 as a bandpass filter in the first operating mode.

[0184] In an example where the first operating mode is a narrowband operating mode, the second operating mode includes a wideband operating mode. In such an example, control circuitry 314 disconnects switches 352 and 358, sets the corresponding inductances of inductors 348 and 354, and disables resistors 360 and capacitors 362. Therefore, control circuitry 314 operates the configurable output network 312 of the DSA 208 as a low-pass filter in the second operating mode.

[0185] Although Figure 3 Implementation instructions Figure 3 The control circuit system 314 is an example of a certain method, but Figure 3 One or more of the elements, processes, or apparatus described herein may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, Figure 3 The example control circuit system 314 can be implemented solely by hardware, or by a combination of hardware, software, and firmware. Therefore, for example, Figure 3 The control circuit system 314 can be implemented by a programmable circuit system in combination with one or more machine-readable instructions (e.g., firmware or software), a processor circuit system, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more ASICs, one or more programmable logic devices (PLDs), or one or more field-programmable logic devices (FPLDs) (e.g., FPGAs). Furthermore, in addition to or replacing... Figure 3 One or more elements, processes or apparatus described herein, Figure 3 The example control circuit system 314 may also include one or more elements, processes or devices, or may include more than one of any or all of the described elements, processes and devices.

[0186] exist Figure 8 The diagram shows one or more flowcharts, which represent functions that can be executed by a programmable circuit system to perform operations on... Figure 3 The control circuit system 314 performs at least one of the steps in its implementation or instantiation, or indicates that it can be executed by a programmable circuit system to control... Figure 3 The control circuitry system 314 performs example operations of at least one of the implementations or instantiations. If the steps are implemented as machine-readable instructions, the machine-readable instructions may be one or more executable programs or portions of one or more executable programs for execution by a programmable circuitry system (e.g., a general-purpose or custom processor). In some embodiments, one or more functions or portions of functions are executed by a programmable circuitry system (e.g., an FPGA).

[0187] As mentioned in this article, Figure 8Example operations can be implemented using executable instructions (e.g., at least one of computer-readable or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device or disk, excluding propagation signals and transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include flash memory, registers and / or triggers, read-only memory (ROM), etc.

[0188] The circuits described herein may be reconfigurable to include replaced components to provide at least partially similar functionality to that available before the component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in at least one of series or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some components in the described examples are included in an integrated circuit and others are outside the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as outside the integrated circuit may be included in the integrated circuit, and some features described as inside the integrated circuit may be incorporated outside the integrated circuit.

[0189] As used herein, “approximately,” “about,” and “substantially” modify their subject / value to identify the potential presence of variation that occurs in real-world applications. For example, “approximately,” “about,” and “substantially” may modify dimensions or locations that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. For example, unless otherwise specified herein, “approximately,” “about,” and “substantially” may indicate that such dimensions or locations are within a tolerance of + / -10%, or, if the value is zero, a reasonable range of values ​​near zero.

[0190] Within the scope of the claims, modifications are possible in the described examples, and other examples are possible as well.

[0191] As should be understood from the foregoing, example systems, apparatuses, articles of art, and methods for highly adjustable, compact DSAs used in RF sampling ADCs have been described. For example, the described systems, apparatuses, articles of art, and methods include programmable inductors that provide a wide tuning range and facilitate the implementation of bandpass and wideband low-pass filters at the DSA output. Thus, the described examples include highly adjustable analog front-ends that can meet a wide range of applications. For example, by implementing bandpass filters at the outputs of the DSA and the noise cancellation LNA, the examples described herein reduce the noise figure of the DSA, for example, from 8 dB to 4 dB.

[0192] Furthermore, for example, by partially cross-coupling the transconductance transistor of the LNA from the drain to the gate, the example described herein significantly improves the S11 parameter of the DSA across frequencies. In dual-band or feedback ADC applications, the example described herein implements an extremely wideband low-pass filter at the output of the DSA. Additionally, by including an HPF at the common source of the configurable input network of the DSA, the example described herein reduces low-frequency noise folding in wideband operating mode and thus improves the noise figure by, for example, another 0.5 dB. In the example described herein, one or more identical inductors are used in both narrow and wideband operating modes. Therefore, the example described herein reduces the amount of area consumed by the tunable DSA.

[0193] As described herein, the example systems, apparatuses, articles, and methods comprise a highly configurable DSA having: (1) a reconfigurable output network supporting both narrow and wide operating modes; (2) cross-coupled transistors for improving the S11 parameters of the DSA across frequencies; and (3) a high-pass filter (HPF) for preventing frequency aliasing when the DSA is constructed in wide operating mode. The described systems, apparatuses, articles, and methods improve the efficiency of using computing devices by reducing the area in which the tunable DSA is implemented, increasing the tuning range of the DSA, and utilizing a single circuit to support both narrow and wide operating modes. The described systems, apparatuses, articles, and methods also relate to one or more improvements in the operation of machines, such as computers or other electronic, electromechanical, or mechanical devices.

[0194] Exemplary embodiments of this disclosure are summarized herein. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0195] Example 1. An electronic circuit comprising: an amplifier having a first output and a second output, a first input and a second input, and a first terminal and a second terminal; a high-pass filter coupled between the first terminal and the second terminal of the amplifier; and a configurable output network coupled between the first output and the second output of the amplifier.

[0196] Example 2. An electronic circuit according to Example 1, wherein the amplifier comprises: a first transistor having a control terminal coupled to a first input of the amplifier, a first current path terminal coupled to a first output of the amplifier, and a second current path terminal coupled to the first terminal of the amplifier; a second transistor having a control terminal coupled to a second input of the amplifier, a first current path terminal coupled to a second output of the amplifier, and a second current path terminal coupled to the second terminal of the amplifier; a third transistor having a first current path terminal coupled to the first output of the amplifier and a second current path terminal coupled to the first current path terminal of the first transistor; and a fourth transistor having a first current path terminal coupled to the second output of the amplifier and a second current path terminal coupled to the first current path terminal of the second transistor.

[0197] Example 3. An electronic circuit according to one of Examples 1 or 2, further comprising: a first capacitor coupled between a control terminal of the third transistor and a first current path terminal of the fourth transistor; a second capacitor coupled between the control terminal of the third transistor and a second current path terminal of the fourth transistor; a third capacitor coupled between the control terminal of the fourth transistor and the first current path terminal of the third transistor; and a fourth capacitor coupled between the control terminal of the fourth transistor and the second current path terminal of the third transistor.

[0198] Example 4. An electronic circuit according to one of Examples 1 to 3, wherein the high-pass filter comprises: a first capacitor coupled between a first terminal of the amplifier and a second terminal of the amplifier; a first resistor coupled between the first terminal of the amplifier and the first capacitor; and a second resistor coupled between the second terminal of the amplifier and the first capacitor.

[0199] Example 5. An electronic circuit according to one of Examples 1 to 4, further comprising: a first resistor coupled between the first terminal of the amplifier and ground; and a second resistor coupled between the second terminal of the amplifier and ground.

[0200] Example 6. An electronic circuit according to any one of Examples 1 to 5, further comprising a configurable input network having: a first output coupled to the second current path terminal of the third transistor; a second output coupled to the second current path terminal of the fourth transistor; a third output coupled to the control terminal of the first transistor; and a fourth output coupled to the control terminal of the second transistor.

[0201] Example 7. An electronic circuit according to any one of Examples 1 to 6, wherein the configurable input network comprises: a first input and a second input; a first resistor coupled between the first input of the configurable input network and a second current path terminal of the third transistor; a first capacitor coupled between the first input of the configurable input network and a control terminal of the second transistor; a second resistor coupled between the second input of the configurable input network and a second current path terminal of the fourth transistor; and a second capacitor coupled between the second input of the configurable input network and the control terminal of the first transistor.

[0202] Example 8. An electronic circuit according to one of Examples 1 to 7, wherein each of the first resistor and the second resistor has a configurable resistance, and each of the first capacitor and the second capacitor has a configurable capacitance.

[0203] Example 9. An electronic circuit according to one of Examples 1 to 8, wherein the configurable output network includes an inductor coupled between the first output and the second output of the amplifier.

[0204] Example 10. An electronic circuit according to any one of Examples 1 to 9, wherein the inductor comprises: a first metal layer disposed over a semiconductor substrate; a second metal layer disposed over the semiconductor substrate; a third switch having a first terminal and a second terminal; a first connector disposed in the first metal layer and coupled to the first terminal of the third switch; a second connector disposed in the first metal layer and coupled to the second terminal of the third switch, the first connector and the second connector being arranged in a first shape; a fourth switch having a first terminal and a second terminal; a third connector disposed in the first metal layer and coupled to the first terminal of the fourth switch; a fourth connector disposed in the second metal layer and coupled to the third connector and the second terminal of the third switch; and a fifth connector disposed in the first metal layer and coupled to the second terminal of the fourth switch and the first terminal of the third switch, the third connector and the fifth connector being arranged in a second shape concentric with the first shape.

[0205] Example 11. An electronic circuit according to any one of Examples 1 to 10, wherein the inductor comprises: a first metal layer disposed over a semiconductor substrate; a second metal layer disposed over the semiconductor substrate; a third switch having a first terminal and a second terminal; a first connector disposed in the first metal layer and coupled to the first terminal of the third switch; a second connector disposed in the first metal layer and coupled to the second terminal of the third switch, the first connector and the second connector being arranged in a first shape; a fourth switch having a first terminal and a second terminal; a third connector disposed in the second metal layer and coupled to the first terminal of the fourth switch and the second terminal of the third switch; and a fourth connector disposed in the second metal layer and coupled to the second terminal of the fourth switch and the first terminal of the third switch, the third connector and the fourth connector being arranged in a second shape concentric with and substantially aligned with the first shape.

[0206] Example 12. An electronic circuit according to one of Examples 1 to 11, wherein the configurable output network comprises: a first resistor coupled between the first output of the amplifier and the inductor; and a second resistor coupled between the second output of the amplifier and the inductor.

[0207] Example 13. An electronic circuit according to one of Examples 1 to 12, wherein the configurable output network comprises: a first switch coupled in parallel with the first resistor; and a second switch coupled in parallel with the second resistor.

[0208] Example 14. An electronic circuit according to one of Examples 1 to 13, wherein the configurable output network comprises: a variable resistor coupled between the first output and the second output of the amplifier; and a variable capacitor coupled between the first output and the second output of the amplifier.

[0209] Example 15. An electronic circuit according to any one of Examples 1 to 14, wherein the configurable output network comprises: a first variable inductor having a first terminal and a second terminal, the second terminal of the first variable inductor being coupled to a supply terminal; a first resistor having a first terminal coupled to a first output of the amplifier and a second terminal coupled to the first terminal of the first variable inductor; a first switch coupled in parallel with the first resistor; a second variable inductor having a first terminal and a second terminal, the second terminal of the second variable inductor being coupled to the supply terminal; a second resistor having a first terminal coupled to a second output of the amplifier and a second terminal coupled to the first terminal of the second variable inductor; a second switch coupled in parallel with the second resistor; a variable resistor coupled between the first output and the second output of the amplifier; and a variable capacitor coupled between the first output and the second output of the amplifier.

[0210] Example 16. An electronic circuit according to any one of Examples 1 to 15, comprising a control circuit system configured to: in a first mode, close the first switch and the second switch; and in a second mode, open the first switch and the second switch.

[0211] Example 17. An electronic circuit according to any one of Examples 1 to 16, wherein the configurable input network, the amplifier, the high-pass filter, and the configurable output network form a digital signal attenuator (DSA) having a first output and a second output, and a first input and a second input, the electronic circuit comprising: a balun circuit having a first output, a second output, and an input; a matching network having a first output and a second output coupled to the first input and the second input of the DSA, respectively, and a first input and a second input coupled to the first output and the second output of the balun circuit, respectively; a sampling circuit having a first output and a second output, and a first input and a second input coupled to the first output and the second output of the DSA, respectively; and an analog-to-digital converter (ADC) having a first input and a second input coupled to the first output and the second output of the sampling circuit, respectively.

[0212] Example 18. An integrated circuit comprising: a semiconductor substrate; a first metal layer disposed over the semiconductor substrate; a second metal layer disposed over the semiconductor substrate; a first switch having a first terminal and a second terminal; a first connector disposed in the first metal layer and coupled to the first terminal of the first switch; a second connector disposed in the first metal layer and coupled to the second terminal of the first switch, the first connector and the second connector being arranged in a first shape; a second switch having a first terminal and a second terminal; a third connector disposed in the second metal layer and coupled to the first terminal of the second switch and the second terminal of the first switch; and a fourth connector disposed in the second metal layer and coupled to the second terminal of the second switch and the first terminal of the first switch, the third connector and the fourth connector being arranged in a second shape concentric with and substantially aligned with the first shape.

[0213] Example 19. An integrated circuit according to Example 18, wherein the first switch, the first connector, the second connector, the third connector, and the fourth connector form a first variable inductor or a second variable inductor, at least one of the first variable inductor or the second variable inductor comprising: a third switch having a first terminal and a second terminal, the first terminal being coupled to the second connector; a fifth connector disposed in the second metal layer and coupled to the second terminal of the third switch and the first connector; a sixth connector disposed in the first metal layer and coupled to the first terminal of the third switch; and a seventh connector disposed in the first metal layer and coupled to the second terminal of the third switch, the sixth connector and the seventh connector being arranged in a third shape concentric with the first shape.

[0214] Example 20. An integrated circuit according to one of Examples 18 or 19, wherein at least one of the first variable inductor or the second variable inductor comprises: a fourth switch having a first terminal and a second terminal; an eighth connector disposed in the second metal layer and coupled to the first terminal of the fourth switch and the second terminal of the second switch; a ninth connector disposed in the first metal layer and coupled to the first terminal of the second switch; and a tenth connector disposed in the second metal layer and coupled to the second terminal of the fourth switch and the ninth connector, wherein the eighth connector and the tenth connector are arranged in a fourth shape concentric with and substantially aligned with the third shape.

[0215] Example 21. An integrated circuit according to any one of Examples 18 to 20, wherein the first switch, the first connector, the second connector, the second switch, the third connector, and the fourth connector form at least one of a first variable inductor or a second variable inductor, and the integrated circuit comprises: the first variable inductor having a first terminal and a second terminal coupled to a supply terminal; a first resistor having a first terminal and a second terminal coupled to the first terminal of the first variable inductor; a third switch having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the first terminal of the first variable inductor; the second... A variable inductor, the second variable inductor having a first terminal and a second terminal coupled to the supply terminal; a second resistor having a first terminal and a second terminal coupled to the first terminal of the second variable inductor; a fourth switch having a first terminal coupled to the first terminal of the second resistor and a second terminal coupled to the first terminal of the second variable inductor; a variable resistor having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the first terminal of the second resistor; and a variable capacitor having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the first terminal of the second resistor.

[0216] Example 22. An integrated circuit according to one of Examples 18 to 21, comprising: a first transistor having a control terminal, a first current path terminal, and a second current path terminal; a second transistor having a control terminal, a first current path terminal, and a second current path terminal; a third transistor having a control terminal, a first current path terminal, and a second terminal, the first terminal being coupled to a first terminal of a first resistor; a fourth transistor having a control terminal, a first current path terminal, and a second current path terminal, the first current path terminal being coupled to a first terminal of a second resistor; a first capacitor coupled between the control terminal of the third transistor and the first current path terminal of the fourth transistor; a second capacitor coupled between the control terminal of the third transistor and the second current path terminal of the fourth transistor; a third capacitor coupled between the control terminal of the fourth transistor and the first current path terminal of the third transistor; and a fourth capacitor coupled between the control terminal of the fourth transistor and the second current path terminal of the third transistor.

[0217] Example 23. An integrated circuit according to one of Examples 18 to 22, wherein the variable resistor is a first variable resistor, the variable capacitor is a first variable capacitor, and the integrated circuit comprises: a second variable resistor having a first terminal and a second terminal coupled to a second current path terminal of the third transistor; a second variable capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal coupled to the first terminal of the second variable resistor; a third variable resistor having a first terminal and a second terminal coupled to the second current path terminal of the fourth transistor; and a third variable capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal coupled to the first terminal of the third variable resistor.

[0218] Example 24. An integrated circuit according to one of Examples 18 to 23, comprising: a third resistor having a first terminal and a second terminal coupled to a second current path terminal of a second transistor; a fifth capacitor having a first terminal and a second terminal coupled to the first terminal of the third resistor; a fourth resistor having a first terminal coupled to the second current path terminal of the first transistor and a second terminal coupled to the first terminal of the fifth capacitor; a fifth resistor having a first terminal coupled to the second current path terminal of the second transistor and a second terminal coupled to ground; and a sixth resistor having a first terminal coupled to the second current path terminal of the first transistor and a second terminal coupled to ground.

[0219] Example 25. A method comprising: operating a configurable output network of a digital signal attenuator (DSA) of a transceiver in a first operating mode at a first time; operating the DSA in the first operating mode; operating the configurable output network of the DSA of the transceiver in a second operating mode at a second time; and operating the DSA in the second operating mode.

[0220] Example 26. The method according to Example 25, wherein the first operating mode is a wideband operating mode and the second operating mode is a narrowband operating mode.

[0221] Example 27. A method according to one of Examples 25 or 26, wherein the first operating mode includes operating the configurable output network of the DSA as a low-pass filter, and the second operating mode includes operating the configurable output network as a band-pass filter.

[0222] Example 28. A method according to one of Examples 25 to 27, wherein the configurable output network comprises a first switch, a second switch, a first variable inductor, a second variable inductor, a variable resistor, and a variable capacitor, and the method comprises: operating the configurable output network in a first operating mode by: disconnecting the first switch and the second switch; setting the respective inductances of the first variable inductor and the second variable inductor; and disabling the variable resistor and the variable capacitor; and operating the configurable output network in a second operating mode by: closing the first switch and the second switch; setting the respective inductances of the first variable inductor and the second variable inductor; setting the resistance of the variable resistor; and setting the capacitance of the variable capacitor.

[0223] Example 29. A method according to one of Examples 25 to 28, wherein the configurable output network comprises a first switch, a second switch, a first variable inductor, a second variable inductor, a variable resistor, and a variable capacitor, and the method comprises: operating the configurable output network in a first operating mode by: closing the first switch and the second switch; setting the respective inductances of the first variable inductor and the second variable inductor; setting the resistance of the variable resistor; and setting the capacitance of the variable capacitor; and operating the configurable output network in a second operating mode by: opening the first switch and the second switch; setting the respective inductances of the first variable inductor and the second variable inductor; and disabling the variable resistor and the variable capacitor.

[0224] Although this disclosure has been described with reference to illustrative embodiments, this specification is not intended to be limiting. Those skilled in the art will understand, upon referring to this specification, various modifications and combinations of the illustrative embodiments and other embodiments.

Claims

1. An electronic circuit comprising: An amplifier having a first output and a second output, a first input and a second input, and a first terminal and a second terminal; A high-pass filter coupled between the first and second terminals of the amplifier; and A configurable output network is coupled between the first output and the second output of the amplifier.

2. The electronic circuit according to claim 1, wherein the amplifier comprises: A first transistor has a control terminal coupled to the first input of the amplifier, a first current path terminal coupled to the first output of the amplifier, and a second current path terminal coupled to the first terminal of the amplifier. The second transistor has a control terminal coupled to the second input of the amplifier, a first current path terminal coupled to the second output of the amplifier, and a second current path terminal coupled to the second terminal of the amplifier. The third transistor has a first current path terminal coupled to the first output of the amplifier and a second current path terminal coupled to the first current path terminal of the first transistor. and A fourth transistor having a first current path terminal coupled to the second output of the amplifier and a second current path terminal coupled to the first current path terminal of the second transistor.

3. The electronic circuit according to claim 2, further comprising: A first capacitor is coupled between the control terminal of the third transistor and the first current path terminal of the fourth transistor; The second capacitor, coupled to the control terminal of the third transistor and the fourth transistor... Between the terminals of the second current path; A third capacitor is coupled between the control terminal of the fourth transistor and the first current path terminal of the third transistor; and A fourth capacitor is coupled between the control terminal of the fourth transistor and the second current path terminal of the third transistor.

4. The electronic circuit according to claim 2, wherein the high-pass filter comprises: A first capacitor is coupled between the first terminal and the second terminal of the amplifier; A first resistor is coupled between the first terminal of the amplifier and the first capacitor; and A second resistor is coupled between the second terminal of the amplifier and the first capacitor.

5. The electronic circuit according to claim 2, further comprising: A first resistor is coupled between the first terminal of the amplifier and ground; and A second resistor is coupled between the second terminal of the amplifier and ground.

6. The electronic circuit of claim 2, further comprising a configurable input network, the configurable input network having: A first output is coupled to the second current path terminal of the third transistor; A second output is coupled to the second current path terminal of the fourth transistor; A third output is coupled to the control terminal of the first transistor; and A fourth output is coupled to the control terminal of the second transistor.

7. The electronic circuit of claim 6, wherein the configurable input network comprises: First input and second input; A first resistor is coupled between the first input of the configurable input network and the second current path terminal of the third transistor; A first capacitor is coupled between the first input of the configurable input network and the control terminal of the second transistor; A second resistor is coupled between the second input of the configurable input network and the second current path terminal of the fourth transistor; and A second capacitor is coupled between the second input of the configurable input network and the control terminal of the first transistor.

8. The electronic circuit of claim 7, wherein each of the first resistor and the second resistor has a configurable resistance, and each of the first capacitor and the second capacitor has a configurable capacitance.

9. The electronic circuit of claim 1, wherein the configurable output network includes an inductor coupled between the first output and the second output of the amplifier.

10. The electronic circuit of claim 9, wherein the inductor comprises: A first metal layer is disposed above a semiconductor substrate; A second metal layer is disposed above the semiconductor substrate; The third switch has a first terminal and a second terminal; A first connector is disposed in the first metal layer and coupled to the first terminal of the third switch; A second connector, which is disposed in the first metal layer and coupled to the second terminal of the third switch, wherein the first connector and the second connector are arranged in a first shape; The fourth switch has a first terminal and a second terminal; A third connector is disposed in the first metal layer and coupled to the first terminal of the fourth switch; A fourth connector is disposed in the second metal layer and coupled to the second terminal of the third connector and the third switch; and A fifth connector, which is disposed in the first metal layer and coupled to the second terminal of the fourth switch and the first terminal of the third switch, wherein the third connector and the fifth connector are arranged in a second shape concentric with the first shape.

11. The electronic circuit of claim 9, wherein the inductor comprises: A first metal layer is disposed above a semiconductor substrate; A second metal layer is disposed above the semiconductor substrate; The third switch has a first terminal and a second terminal; A first connector is disposed in the first metal layer and coupled to the first terminal of the third switch; A second connector, which is disposed in the first metal layer and coupled to the second terminal of the third switch, wherein the first connector and the second connector are arranged in a first shape; The fourth switch has a first terminal and a second terminal; A third connector is disposed in the second metal layer and coupled to the first terminal of the fourth switch and the second terminal of the third switch; and A fourth connector, disposed in the second metal layer and coupled to the second terminal of the fourth switch and the first terminal of the third switch, wherein the third connector and the fourth connector are arranged in a second shape concentric with and substantially aligned with the first shape.

12. The electronic circuit of claim 9, wherein the configurable output network comprises: A first resistor is coupled between the first output of the amplifier and the inductor; and A second resistor is coupled between the second output of the amplifier and the inductor.

13. The electronic circuit of claim 12, wherein the configurable output network comprises: A first switch is coupled in parallel with the first resistor; and The second switch is coupled in parallel with the second resistor.

14. The electronic circuit of claim 1, wherein the configurable output network comprises: A variable resistor coupled between the first output and the second output of the amplifier; and A variable capacitor coupled between the first output and the second output of the amplifier.

15. The electronic circuit of claim 1, wherein the configurable output network comprises: A first variable inductor having a first terminal and a second terminal, wherein the second terminal of the first variable inductor is coupled to a supply terminal; A first resistor having a first terminal coupled to the first output of the amplifier and a second terminal coupled to the first output of the amplifier. The second terminal of the first terminal of the first variable inductor; A first switch is coupled in parallel with the first resistor; A second variable inductor having a first terminal and a second terminal, wherein the second terminal of the second variable inductor is coupled to the supply terminal; The second resistor has a first terminal coupled to the second output of the amplifier and a second terminal coupled to the first terminal of the second variable inductor; The second switch is coupled in parallel with the second resistor; A variable resistor coupled between the first output and the second output of the amplifier; and A variable capacitor coupled between the first output and the second output of the amplifier.

16. The electronic circuit of claim 15, further comprising a control circuit system configured to: In the first mode, the first switch and the second switch are closed; and In the second mode, the first switch and the second switch are disconnected.

17. The electronic circuit of claim 6, wherein the configurable input network, the amplifier, the high-pass filter, and the configurable output network form a digital signal attenuator (DSA) having a first output and a second output, and a first input and a second input, the electronic circuit comprising: A balanced-unbalanced converter circuit having a first output, a second output, and an input; and A matching network having a first output and a second output coupled to the first input and the second input of the DSA, respectively, and a first input and a second input coupled to the first output and the second output of the balun circuit, respectively; A sampling circuit having a first output and a second output, and a first input and a second input respectively coupled to the first output and the second output of the DSA; and An analog-to-digital converter (ADC) having a first input and a second input respectively coupled to the first output and the second output of the sampling circuit.

18. An integrated circuit, comprising: Semiconductor substrate; A first metal layer is disposed above the semiconductor substrate; A second metal layer is disposed above the semiconductor substrate; A first switch having a first terminal and a second terminal; A first connector is disposed in the first metal layer and coupled to the first terminal of the first switch; A second connector is disposed in the first metal layer and coupled to the second terminal of the first switch, the first connector and the second connector being arranged in a first shape; The second switch has a first terminal and a second terminal; A third connector is disposed in the second metal layer and coupled to the first terminal of the second switch and the second terminal of the first switch; and A fourth connector, which is disposed in the second metal layer and coupled to the second terminal of the second switch and the first terminal of the first switch, wherein the third connector and the fourth connector are arranged in a second shape that is concentric with the first shape and substantially aligned with the first shape.

19. The integrated circuit of claim 18, wherein the first switch, the first connector, the second connector, the third connector, and the fourth connector form a first variable inductor or a second variable inductor, at least one of the first variable inductor or the second variable inductor comprising: A third switch has a first terminal and a second terminal, the first terminal being coupled to the second connector; A fifth connector, which is disposed in the second metal layer and coupled to the second terminal of the third switch and the first connector; A sixth connector is disposed in the first metal layer and coupled to the first terminal of the third switch; and A seventh connector, which is disposed in the first metal layer and coupled to the second terminal of the third switch, wherein the sixth connector and the seventh connector are arranged in a third shape concentric with the first shape.

20. The integrated circuit of claim 19, wherein at least one of the first variable inductor or the second variable inductor comprises: The fourth switch has a first terminal and a second terminal; An eighth connector, which is disposed in the second metal layer and coupled to the first terminal of the fourth switch and the second terminal of the second switch; A ninth connector, which is disposed in the first metal layer and coupled to the first terminal of the second switch; and A tenth connector, which is disposed in the second metal layer and coupled to the second terminal of the fourth switch and the ninth connector, wherein the eighth connector and the tenth connector are arranged in a fourth shape that is concentric with and substantially aligned with the third shape.

21. The integrated circuit of claim 18, wherein the first switch, the first connector, the second connector, the second switch, the third connector, and the fourth connector form at least one of a first variable inductor or a second variable inductor, and the integrated circuit comprises: The first variable inductor has a first terminal and a second terminal coupled to a supply terminal; A first resistor having a first terminal and a second terminal coupled to the first terminal of the first variable inductor; A third switch has a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the first terminal of the first variable inductor; The second variable inductor has a first terminal and a second terminal coupled to the supply terminal; The second resistor has a first terminal and a second terminal coupled to the first terminal of the second variable inductor; A fourth switch having a first terminal coupled to the first terminal of the second resistor and a second terminal coupled to the first terminal of the second variable inductor; A variable resistor having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the first terminal of the second resistor; and A variable capacitor having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the first terminal of the second resistor.

22. The integrated circuit of claim 21, comprising: The first transistor has a control terminal, a first current path terminal, and a second current path terminal. The second transistor has a control terminal, a first current path terminal, and a second current path terminal. The third transistor has a control terminal, a first current path terminal, and a second terminal, the first terminal being coupled to the first terminal of the first resistor; The fourth transistor has a control terminal, a first current path terminal and a second current path terminal, the first current path terminal being coupled to the first terminal of the second resistor; A first capacitor, coupled to the control terminal of the third transistor and the fourth transistor. Between the terminals of the first current path; The second capacitor, coupled to the control terminal of the third transistor and the fourth transistor... Between the terminals of the second current path; A third capacitor is coupled between the control terminal of the fourth transistor and the first current path terminal of the third transistor; and A fourth capacitor is coupled between the control terminal of the fourth transistor and the second current path terminal of the third transistor.

23. The integrated circuit of claim 22, wherein the variable resistor is a first variable resistor, the variable capacitor is a first variable capacitor, and the integrated circuit comprises: The second variable resistor has a first terminal and a second terminal coupled to the second current path terminal of the third transistor; The second variable capacitor has a first terminal coupled to the control terminal of the second transistor and a second terminal coupled to the first terminal of the second variable resistor; A third variable resistor has a first terminal and a second terminal coupled to the second current path terminal of the fourth transistor; and A third variable capacitor has a first terminal coupled to the control terminal of the first transistor and a second terminal coupled to the first terminal of the third variable resistor.

24. The integrated circuit of claim 23, comprising: A third resistor has a first terminal and a second terminal coupled to the second current path terminal of the second transistor; A fifth capacitor has a first terminal and a second terminal coupled to the first terminal of the third resistor; A fourth resistor has a first terminal coupled to the second current path terminal of the first transistor and a second terminal coupled to the first terminal of the fifth capacitor; The fifth resistor has a first terminal coupled to the second current path terminal of the second transistor and a second terminal coupled to ground; and The sixth resistor has a first terminal coupled to the second current path terminal of the first transistor and a second terminal coupled to ground.

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