Node for a communication bus system

Abstract

The invention relates to a node for a ternary modulation communication bus system. The node comprises a controller; a receiver; and a signal driver: a first dominant state; a second dominant state; or an implicit state; wherein, during an enumeration process, the controller is configured to: receive, via the receiver, an enumeration signal from the communication bus; in response to the enumeration signal, the signal driver is controlled to apply a sequence of ternary modulation states at a respective time slot sequence to the communication bus to represent a unique identifier of the node according to an enumeration coding scheme, where the enumeration coding scheme includes one or more ternary coding rules, including: at each time slot, a sequence of ternary modulation states at a respective time slot sequence; the signal driver applies only the recessive state or a predetermined one of the first dominant state and the second dominant state specific to the time slot.

Description

Technical Field

[0001] This disclosure relates to nodes for communication bus systems, communication bus systems, and battery management systems. Background Technology

[0002] Some battery management systems use the daisy-chain converter protocol layer (TPL) for communication. Larger battery packs increase the requirements for the communication system. Summary of the Invention

[0003] According to a first aspect of this disclosure, a node for a ternary modulation communication bus system is provided, the node comprising:

[0004] Controller;

[0005] The receiver is configured to detect the ternary modulation state on the communication bus; and

[0006] A signal driver configured to apply a ternary modulation state to a communication bus, wherein the ternary modulation state includes one of the following:

[0007] First dominant state;

[0008] Second dominant state; or

[0009] Hidden state;

[0010] During the enumeration process, the controller is configured to:

[0011] The enumeration signal is received from the communication bus via the receiver;

[0012] In response to the enumeration signal, the signal driver is controlled to apply the ternary modulation state sequence for the corresponding time slot sequence to the communication bus according to the enumeration coding scheme to represent the unique identifier of the node.

[0013] The enumeration encoding scheme includes one or more ternary encoding rules, including:

[0014] In each time slot, the signal driver applies only the recessive state or a predetermined one of the first and second dominant states specific to the time slot.

[0015] In one or more embodiments, each ternary modulation state may include a sequence of symbols. The rule may include that each slot / symbol / ternary modulation state of the ternary modulation state sequence may have only a predetermined one of a first dominant state and a second dominant state. An enumeration coding scheme may map a first number of symbols to a second number of bits. Each symbol in the first number of symbols may have only a symbol-specific recessive state or a predetermined one of a first dominant state and a second dominant state.

[0016] In one or more embodiments, one or more ternary coding rules may include: the signal driver applying the same number of first dominant states as the second dominant state on the time slot sequence.

[0017] In one or more embodiments, one or more ternary encoding rules may include one or more of the following:

[0018] Imbalances in sequences of two first dominant states or two second dominant states are prohibited; and

[0019] Temporary imbalances in a sequence of first dominant states or second dominant states do not last more than three time slots.

[0020] In one or more embodiments, one or more ternary encoding rules may include one or more of the following:

[0021] The maximum run length of the same ternary modulation state at the beginning of the ternary modulation state sequence is one time slot;

[0022] The maximum run length of the same ternary modulation state (specifically, the recessive state) within a ternary modulation state sequence is three time slots; and

[0023] The maximum run length of the same ternary modulation state (specifically, the recessive state) at the end of the ternary modulation state sequence is two time slots.

[0024] In one or more embodiments, the signal driver may include:

[0025] A dominant state driver, comprising a push-pull driver configured to selectively:

[0026] Pull the first bus connection terminal up to the power supply voltage and pull the second bus connection terminal down to the reference voltage to provide the first dominant state; and

[0027] Pull the second bus connection terminal up to the power supply voltage and pull the first bus connection terminal down to the reference voltage to provide the second dominant state; and

[0028] A reference state driver includes a buffered common-mode reference circuit configured to apply the recessive state to the first and second bus connection terminals.

[0029] In one or more embodiments, the dominant state driver can be configured to:

[0030] Selectively enable a first state switch and selectively disable a second state switch to apply the first dominant state to the communication bus;

[0031] Selectively enabling the second state switch and selectively deactivating the first state switch applies the second dominant state to the communication bus; and

[0032] The first state switch is selectively disabled and the second state switch is selectively disabled to apply the latent state to the communication bus.

[0033] In one or more embodiments, the enumeration encoding scheme may include encoding six three-level symbols to provide three-bit enumeration data.

[0034] In one or more embodiments, the enumeration encoding scheme can be defined by a six-level symbol-to-three-bit data mapping, which is based on:

[0035]

[0036] Or based on:

[0037]

[0038] In one or more embodiments, the controller can be configured to:

[0039] For each time slot, a continuous ternary modulation state is received from the receiver, the continuous ternary modulation state being sustained on the communication bus within the time slot;

[0040] If, for each time slot in the time slot sequence, the ternary modulation state applied to the communication bus matches the continuous ternary modulation state on the bus within the time slot, then the node is determined to have won the arbitration process; and

[0041] If, for any time slot in the time slot sequence, the ternary modulation state applied to the communication bus differs from the continuous ternary modulation state on the bus within the time slot, then the node is determined to have lost the arbitration process.

[0042] In one or more embodiments, the receiver may be configured to detect a synchronization signal on the communication bus to indicate the start of each time slot.

[0043] In one or more embodiments, the controller can be configured to respond to the synchronization signal in the following manner:

[0044] Waiting period for protection; and

[0045] After the protection period, the ternary modulation state in the ternary modulation state sequence corresponding to the time slot is applied during the transmission period.

[0046] In one or more embodiments, the controller can be configured to detect whether the ternary modulation state applied to the communication bus during a fixed time window of the transmission period matches the continuous ternary modulation state on the bus.

[0047] According to a second aspect of this disclosure, a ternary modulation communication bus system is provided, comprising:

[0048] Main control unit;

[0049] Communication bus; and

[0050] The multiple nodes disclosed in this article,

[0051] The master control unit is configured to apply the enumeration signal to the communication bus.

[0052] According to a third aspect of this disclosure, a battery management system is provided, which includes any node or ternary modulation communication bus system disclosed herein.

[0053] According to a fourth aspect of this disclosure, a method for enumerating nodes on a ternary modulation communication bus system is provided, the method comprising:

[0054] At the node, an enumeration signal is received from the communication bus of the ternary modulation communication bus system;

[0055] The sequence of ternary modulation states representing the unique identifier of the node is encoded according to an enumeration encoding scheme, wherein each ternary modulation state includes one of the following:

[0056] First dominant state;

[0057] Second dominant state; or

[0058] Hidden state;

[0059] Each ternary modulation state is applied to the communication bus in the corresponding time slot of the corresponding time slot sequence;

[0060] If, for each time slot in the time slot sequence, the ternary modulation state applied to the communication bus matches a continuous ternary modulation state persisting on the bus within that time slot, then the node is determined to have won the arbitration process; and

[0061] If, for any time slot in the time slot sequence, the ternary modulation state applied to the communication bus is different from the continuous ternary modulation state that persists on the bus within the time slot, then the node is determined to have lost the arbitration process.

[0062] The enumeration encoding scheme includes one or more ternary encoding rules, including:

[0063] In each time slot, the node applies only the latent state or the predetermined one of the first and second dominant states specific to the time slot.

[0064] While this disclosure allows for various modifications and alternatives, its details have been illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described may also exist. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0065] The foregoing discussion is not intended to present every exemplary embodiment or implementation within the scope of the present or future claims. Various exemplary embodiments are further illustrated in the accompanying drawings and the following detailed description. A more complete understanding of these various exemplary embodiments can be achieved by considering the following detailed description in conjunction with the accompanying drawings. Attached Figure Description

[0066] One or more embodiments will now be described with reference to the accompanying drawings, by way of example only, in which:

[0067] Figure 1 A communication bus system according to an embodiment of the present disclosure is shown;

[0068] Figure 2 A node for a ternary modulation communication bus system according to an embodiment of the present disclosure is shown;

[0069] Figure 3A and 3B A circuit system for a signal driver for a node is shown according to an embodiment of the present disclosure;

[0070] Figure 3C This shows a 3-level signal with PAM-3 encoding;

[0071] Figure 4 Two enumeration encoding schemes for an enumeration process according to embodiments of the present disclosure are shown;

[0072] Figure 5 An enumeration process according to an embodiment of this disclosure is illustrated;

[0073] Figure 6 Example signal encoding for providing aligned time slots according to embodiments of the present disclosure is shown; and

[0074] Figure 7 Another node is shown according to an embodiment of this disclosure. Detailed Implementation

[0075] Some battery management systems use the daisy-chain TPL protocol for communication. Traffic on these lines is increasing due to the larger number of units used (e.g., 800V packs), the large amount of sensing required for synchronization, and EIS timestamping. Communication systems may also require a dedicated master controller unit (MCU) core.

[0076] The solution is to improve the speed of TPL by using 3-state pulse amplitude modulation (PAM-3). In this regard, Fast TPL (FTPL) has been created that allows for faster communication. However, daisy-chain topologies may not always be the optimal solution for applications. This disclosure provides a bus topology for PAM-3 with an address resolution protocol (enumeration). The address resolution protocol requires an "arbitration" mechanism at the physical layer. The arbitration mechanism is applicable when several nodes are communicating simultaneously on the bus.

[0077] Existing arbitration mechanisms are based on 2-state communication lines. For example, I 2 C has a strong / dominant low level driven by an internal pull-down of the node, i.e., logic 0. A weak / recessive high level is driven by an external pull-up, i.e., logic 1. For the CAN bus, the dominant state is when both the high and low lines are at their respective high and low voltage levels (logic 0). The recessive state is when both lines are at the intermediate voltage level (logic 1).

[0078] However, FTPL uses 3-level / 3-state pulse amplitude modulation (PAM-3) instead of methods such as I 2 Binary modulation of C or CAN. CAN or SMBus (I 2 The arbitration mechanism of a superset of C cannot be transposed to PAM-3. This paper discloses an innovative arbitration solution for the PAM-3 bus.

[0079] Figure 1 A communication bus system 100 according to an embodiment of the present disclosure is shown. In this example, system 100 is a ternary modulation system implementing PAM-3.

[0080] System 100 includes a master control unit (MCU) 102 connected to a gateway 104. Gateway 104 is connected to a communication bus 106. In this example, the communication bus 106 includes twisted-pair cables, and each end of each wire is connected to the gateway 104. System 100 further includes a plurality of nodes 108-1…108-N, which may be slave nodes. Each node 108-1…108-N may include battery management circuitry from a battery management system. Each node 108-1…108-N is distributed along the length of the communication bus 106 and connected to two wires.

[0081] All nodes 108-1…108-N in the bus topology must be identified by gateway 104. This identification process is called enumeration or address resolution protocol and is managed by the network layer. The enumeration mechanism can be based on the unique device identifier (UID) of each node 108-1…108-N. In many cases, this UID will have a high-order count, such as a 48-bit UID. The enumeration process can also assign simpler node addresses (e.g., 3-bit or 6-bit) to each node 108-1…108-N.

[0082] The node addresses assigned to specific nodes 108-1...108-N during the enumeration process can then be added to the protocol header at the data link layer for subsequent communication between MCU 102 and nodes 108-1...108-N.

[0083] During the enumeration process, when no nodes 108-1...108-N of bus 106 are being enumerated, each node 108-1...108-N can respond to broadcast / global commands from MCU 102 / Gateway 104. All nodes 108-1...108-N can respond simultaneously. If arbitration is not performed at the physical layer, high-level, medium-level, and low-level symbols may be superimposed and compromise communication because system 100 is using PAM-3 modulation. The disclosed nodes, systems, and methods implement an arbitration mechanism at the physical layer to avoid such conflicts.

[0084] Figure 2 A node 208 for a ternary modulation communication bus system according to an embodiment of the present disclosure is shown.

[0085] The node includes a controller 210, a receiver 212, and a signal driver 214. The receiver 212 is configured to detect the ternary modulation state on the communication bus 206. The signal driver 214 is configured to attempt to apply the ternary modulation state to the communication bus 206. The ternary modulation state includes one of the following: a first dominant state (+1); a second dominant state (-1); and a recessive state (0).

[0086] A dominant state is a state that will dominate the recessive state if two states are simultaneously applied to the communication bus 206 by different nodes 208. For example, if a first node applies a first dominant state to bus 206, and a second node simultaneously applies a recessive state to bus 206, then the first dominant state will dominate the recessive state and will persist on bus 206. In this way, the first node "wins" the communication race. An arbitration process is performed at the physical layer to determine which node wins, and this arbitration process can be used in an enumeration process, as discussed further below.

[0087] During the enumeration process, controller 210 is configured to receive an enumeration signal from receiver 212, which detects the corresponding enumeration sequence of ternary modulation states on communication bus 206. This enumeration signal can be applied to communication bus 206 as a global signal from the MCU / gateway for all nodes to respond to.

[0088] In response to the enumeration signal, controller 210 controls signal driver 214 to apply a ternary modulation state sequence to communication bus 206. The ternary modulation state sequence represents the UID of node 208. Each ternary modulation state in the sequence can be called a chip or symbol and is applied to communication bus 206 in the corresponding time slot of the time slot sequence. Controller 210 controls signal driver 214 to apply the ternary modulation state sequence according to an enumeration coding scheme (also referred to as an enumeration coding protocol, enumeration coding mapping, enumeration coding rule set, or enumeration coding conversion). The enumeration coding scheme includes a set of ternary coding rules to avoid conflicts where different dominant states are applied to communication bus 206 simultaneously.

[0089] The rules of the enumeration coding scheme include that, in each time slot, the signal driver may apply only one of the following: (a) a recessive state; or (b) a predefined first dominant state and a second dominant state specific to the time slot. The rules may also include that the signal driver applies the same number of first dominant states (chips) as the second dominant states (chips) over the time slot sequence. The enumeration coding scheme is discussed in more detail below.

[0090] Figure 3A and 3B A circuit system for a signal driver 314 for a node is shown according to an embodiment of the present disclosure.

[0091] The circuit system is configured to attempt to apply one of the following: a first dominant state; a second dominant state; and a recessive state to the communication bus. The resulting 3-level signal with PAM-3 encoding is... Figure 3C As shown in Figure 3, the first dominant state is provided as a high level (voltage) or +1. The second dominant state is provided as a low level (voltage) or -1. The recessive state is provided as a middle level (voltage) or 0. Figure 3 shows six chips, each corresponding to a specific time slot and including a ternary modulation state of +1, -1, or 0.

[0092] Return to Figure 3A and 3BThe circuit system includes a dominant state driver 316 and a recessive state driver 318. Each of the dominant state driver 316 and the recessive state driver 318 is coupled to: a first bus connection terminal 320 (labeled TXP), which is configured to be coupled to a first wire of the communication bus; and a second bus connection terminal 322 (labeled TXN), which is configured to be coupled to a second wire of the communication bus.

[0093] The dominant state driver 316 is configured to selectively provide one or neither of the first and second dominant states. In this example, the dominant state driver 316 includes a push-pull driver. The push-pull driver is configured to either pull down the second bus connection 322 to a reference voltage and pull up the first bus connection to a supply voltage, or vice versa.

[0094] The dominant state driver includes a pair of first state switches 324-1 and 324-2 and a pair of second state switches 326-1 and 326-2.

[0095] The first switch 324-1 of the first state switches 324-1 and 324-2 is coupled between a power supply voltage terminal (labeled V5_ANA_TX) and a first bus connection terminal 320. The second switch 324-2 of the first state switches 324-1 and 324-2 is coupled between a reference voltage terminal (e.g., ground) and a second bus connection terminal 322. In this way, the first state switches 324-1 and 324-2 can selectively couple the first bus connection terminal 320 to the power supply voltage terminal and the second bus connection terminal 322 to the reference voltage terminal to apply a first dominant state (high-level voltage) across the first bus connection terminal 320 and the second bus connection terminal 322. The controller can enable the first state switches 324-1 and 324-2 to control the signal driver circuitry to apply the first dominant state to the communication bus.

[0096] The first switch 326-1 of the second state switches 326-1 and 326-2 is coupled between the power supply voltage terminal and the second bus connection terminal 322. The second switch 326-2 of the first state switches 326-1 and 326-2 is coupled between the reference voltage terminal and the first bus connection terminal 320. In this way, the second state switches 326-1 and 326-2 can selectively couple the first bus connection terminal 320 to the reference voltage terminal and the second bus connection terminal 322 to the power supply voltage terminal to apply a second dominant state (low-level voltage) across the first bus connection terminal 320 and the second bus connection terminal 322. The controller can enable the second state switches 326-1 and 326-2 to control the signal driver circuit to apply the second dominant state to the communication bus.

[0097] The recessive state driver 318 includes a weakly buffered common-mode reference circuit based on a resistor ladder. The recessive state driver is configured to attempt to apply the intermediate level voltage of the recessive state to both the first bus connection 320 and the second bus connection 322.

[0098] The recessive state driver 318 can continuously attempt to apply an intermediate level voltage to the first bus connection 320 and the second bus connection 322. If the dominant state driver 316 attempts to apply either a first dominant state or a second dominant state to the first bus connection 320 and the second bus connection 322, then the dominant state driver 316 will overpower the weak buffer common-mode reference circuit, and the dominant state signal level (high or low) will dominate the recessive state signal level (intermediate). Therefore, the controller can control the signal driver circuit to attempt to apply the recessive state to the communication bus by disabling both the first state switches 324-1, 324-2 and the second state switches 326-1, 326-2 of the dominant state driver 316. In this way, the dominant state driver will not attempt to apply either the first dominant state or the second dominant state, thereby allowing the recessive state driver 318 to attempt to apply the recessive state to the communication bus via bus connections 320, 322.

[0099] The dominance of the dominant state driver 316 relative to the recessive state driver 318 applies within a single node and between nodes on the communication bus. For example, if a first node is applying a first or second dominant mode (using the dominant driver circuitry), this first dominant mode will dominate the recessive state driver of any node attempting to apply a recessive state to the communication bus. Thus, as expected by the arbitration process, the dominant state dominates the recessive state and persists on the bus (becoming a persistent ternary modulation state for the current time slot).

[0100] The ability of the signal driver to provide one of a first dominant mode, a second dominant mode, or a recessive mode to the communication bus enables arbitration during the enumeration process. However, conflicts between the first and second dominant modes on the communication bus should be avoided.

[0101] An examination of the dominant driver circuit 316 reveals a potential conflict in cases where different nodes on the communication bus attempt to apply different of the first and second dominant states on the bus. For example, if the first node attempts to apply the first dominant state to the communication bus and the second node attempts to apply the second dominant state to the communication bus, current can flow from the power supply voltage terminal of the first node to the first communication bus terminal 320 of the first node, to the first communication bus terminal 320 of the second node, and to the reference terminal of the second node. This will draw a large amount of current and potentially damage the integrated circuit. Therefore, such conflicts in dominant states should be avoided.

[0102] Return to Figure 2 As described above, controller 210 controls signal driver 214 to apply a ternary modulation state sequence for the corresponding time slot sequence to communication bus 206 to represent the UID of the node according to an enumeration coding scheme. The enumeration coding scheme prevents conflicts between the first and second dominant states on communication bus 206.

[0103] Figure 4 An example enumeration encoding scheme for an enumeration encoding process according to an embodiment of the present disclosure is shown. The encoding scheme is shown as a table. The encoding scheme includes encoding 6 chips (symbols) having 3 levels to provide 3 bits of enumeration data. A first dominant state is represented as +1, a second dominant state is represented as -1, and a recessive state is represented as 0.

[0104] An enumeration coding scheme includes one or more ternary coding rules. It represents two different enumeration coding schemes that satisfy the ternary coding rules. Enumeration coding schemes enable multiple nodes to attempt to apply ternary modulation states to the communication bus simultaneously (during the enumeration and arbitration processes) without the risk of explicit state conflicts.

[0105] Enumerated encoding schemes include one or more ternary encoding rules, including:

[0106] (i) In each time slot, the signal driver may apply only one of the following: (a) a recessive state; or (b) a predefined first and second dominant state specific to the time slot. In other words, different nodes cannot apply different dominant states to the communication bus in the same time slot. This rule can be applied in... Figure 4 As seen in the diagram, each column contains only +1 or -1, but not both. Each chip / slot may contain only one of two pairs: {-1, 0} and {0, 1}.

[0107] (ii) The signal driver should apply the same number of first dominant states as the second dominant state on the time-slot sequence. In other words, the ternary modulation state sequence must be balanced. This reduces unwanted capacitance in the driver circuitry. This rule can be applied in... Figure 4 As seen in the image, the sum of the six symbols in each row is zero.

[0108] (iii) The imbalance of dominant states does not exceed ±1. In other words, when a chip in the sequence includes a first dominant state, another first dominant state is prohibited in a subsequent time slot until after the time slot that includes a second dominant state. In other words, dominant states in the sequence must alternate between the first and second dominant states (although recessive states are allowed in between).

[0109] (iv) A temporary imbalance in the first or second dominant state sequence without a subsequent other imbalance in the first or second dominant state (i.e., a temporary imbalance of ±1 (and associated capacitance) persisting in the sequence) must not last more than 3 chips. This rule can be applied to... Figure 4 As seen in the table, for symbol option 1, for the first three chips of 101, the temporary imbalance of -1 persists.

[0110] (v) The maximum run length at the beginning of the sequence should be 1. In other words, the second chip in the sequence is different from the first chip in the sequence. This can be achieved by... Figure 4 As can be seen, the second chip [1] is always different from the first chip [0].

[0111] (vi) The maximum internal run length within a sequence should be 3. In other words, a sequence cannot contain more than three consecutive chips with the same state. This can include concatenation of sequences. For example, 001 followed by 110 would be a sequence with three recessive states (chips [4] and [5] are 001 and chip [1] is 110).

[0112] (vii) The maximum run length at the end of the sequence should be 2. In other words, the sequence cannot include more than two consecutive chips with the same state at the end of the sequence. Figure 4 The chips [3], [4] and [5] in the code cannot be the same.

[0113] In the above rules, imbalance refers to the cumulative total number of modulation states in the sequence. Run length refers to the consecutive modulation states of the same type in the sequence. For example, a sequence with consecutive chips of -1, 0, 0 has an imbalance of -1 for three chips / slots, a run length of 1 for the second dominant state, and a run length of 2 for the recessive state.

[0114] During the enumeration process, each node on the communication bus encodes its UID according to the enumeration encoding scheme. Then, each node can simultaneously attempt to apply a ternary modulation state sequence representing its UID to the communication bus. Two dominant states and one recessive state are pre-defined to provide an arbitration process at the physical layer, allowing each node to be enumerated sequentially according to the increasing order of its UID. In other words, the node with the lowest UID wins the arbitration. This can be achieved... Figure 4 As can be seen, the lower enumeration bit values ​​contain more explicit states.

[0115] Figure 5 An enumeration process according to an embodiment of this disclosure is illustrated. This process can be performed by any node or communication bus system disclosed herein. Further reference will continue. Figure 4 Describe the process.

[0116] At step 528, all nodes connected to the bus can be in listen-only mode. Each node connected to the communication bus receives an enumeration signal from the communication bus. The MCU can assert the enumeration signal on the communication bus (e.g., via a gateway) as a global signal for all nodes that will initiate the enumeration process. The enumeration signal may include a start enumeration command instructing all nodes to clear their node addresses (if any). This can set the node address of each node to 0. The enumeration signal may include a return UID command instructing all nodes connected to the bus to return their UID.

[0117] In the second step 530, the node encodes the sequence of ternary modulation states representing the node's UID according to the enumeration encoding scheme. Each ternary modulation state includes one of the following: a first dominant state; a second dominant state; or a recessive state.

[0118] The enumeration coding scheme includes one or more ternary coding rules as described above, including: in each time slot of the time slot sequence corresponding to the corresponding ternary modulation state sequence, the node may apply only: (i) a recessive state; or (ii) a predetermined one of the first and second dominant states specific to the time slot to the communication bus.

[0119] At step 532, during the first time slot, the node applies the first ternary modulation state in the ternary modulation state sequence to the communication bus.

[0120] At the fourth decision step 534, the node detects the continuous ternary modulation state that persists on the communication bus during the first time slot and determines whether the first ternary modulation state applied by the node to the communication bus matches the continuous ternary modulation state.

[0121] When a node attempts to apply a recessive state to the bus while a dominant state persists on the bus, a state mismatch occurs. In this way, the node has lost the arbitration process against another node on the bus, indicating that it will not be assigned an address at this time. If the states do not match, the method proceeds to step 536, and the node waits for another global signal on the bus indicating that another phase of the enumeration process will begin (i.e., assigning the node address to another node).

[0122] If the states do match, the method proceeds to the sixth decision step 538 and determines whether the current ternary modulation state is the last ternary modulation state in the sequence of ternary modulation states. During the first time slot, this will not be the case, and the node returns to step 532 to apply the next ternary modulation state in the sequence to the bus.

[0123] If the ternary modulation state applied to the bus continues to match the continuous modulation state used for the entire ternary modulation state sequence, then the node has won the arbitration process and will be assigned a node address by the MCU. The method then proceeds to step 540 and waits for node address assignment from the MCU.

[0124] The entire process is then repeated for all unlisted nodes (nodes without node addresses) until all nodes on the bus have been assigned node addresses. After the enumeration process and the assignment of all node addresses, the MCU can then address the individual nodes on the bus by including the simple node address in the header field. Therefore, nodes will not respond simultaneously, reducing the risk of collisions between different dominance states. Thus, after the enumeration process, the MCU and each node can switch to a standard ternary encoding scheme with a higher bit rate, such as a six-level symbol to six-bit encoding scheme.

[0125] refer to Figure 4 We can consider the following encoding schemes. Figure 5 The process involves two different nodes attaching to the bus. For simplicity, we'll assume the first node's UID is 010 (third row of the table) and the second node's UID is 100 (fifth row of the table), using symbol option 1. In reality, the UID will be a much higher value, such as a 48-bit ID, which can be obtained through... Figure 4 It is encoded by concatenating (and optionally padding) three-dimensional codes and their corresponding six-symbol sequences.

[0126] Jumping to step 532, in the first time slot, both the first node and the second node will apply the first symbol (marked as [0]) corresponding to their enumerated UIDs. Both the first node and the second node will apply the second dominant state -1 to the communication bus. This second dominant state will persist on the bus, resulting in a positive result for the match check between the first and second nodes at step 534. The process will proceed to step 538 and return to step 532 to apply the next symbol (symbol [1]). Both the first and second nodes will apply the first dominant state +1 to the bus, resulting in a positive match between the two nodes at step 534 and further looping back to step 532. In the next iteration at step 532, the first and second nodes will apply the next symbol (symbol [2]). The first node will apply the second dominant state -1 to the bus and the second node will attempt to apply the recessive state 0. The second dominant state will dominate the recessive state, and the second dominant state will persist on the bus (persistent ternary modulation state). Therefore, the first node will determine a positive match at step 534 and proceed to step 538 and loop back to step 532. However, the second node will determine the mismatch in step 534 and proceed to step 536 and wait for another global signal from the bus. At step 534, the first node will continue through the remaining symbols in its ternary modulation state sequence and will continue to have a successful match. When the first node completes step 534 for the last symbol (symbol [5]), the determination at step 538 will be positive, and the node will proceed to step 540 and receive a node address assignment from the MCU / bus, such as address 001. Then, the first node will no longer participate in the enumeration process and may wait for another global signal indicating the completion of the enumeration process, or wait for a specific node addressing signal from the MCU.

[0127] The entire process is then repeated using only the second node. Since the second node is the only remaining node to be enumerated, it will automatically determine the positive match for each symbol in step 534 and eventually proceed to step 540 to receive the node address assignment, such as address 002.

[0128] More generally, the process is repeated until every node connected to the bus has been assigned a node address. This is because the MCU may initially not know how many nodes are connected to the bus. After the enumeration process, the MCU knows how many nodes are connected to the bus and the UID and node address of each node.

[0129] After assigning each node address, the MCU can use an enumeration encoding scheme to request each node to return its node address. If no node address is enumerated, then node address 0 will win the arbitration process (see [link]). Figure 4 The first row of the table), and the MCU knows to run another node address assignment loop ( Figure 5(The process). If a non-zero address wins the arbitration, the MCU knows that all nodes have been assigned node addresses.

[0130] All nodes must respond synchronously to ensure that each node's time slots are aligned. In other words, nodes respond with their first symbol, second symbol, nth symbol, etc., during the same response time slot.

[0131] In some examples, the communication bus system can have a master clock that ensures this alignment of time slots. In other examples, each node can have its own clock. In such examples, the MCU can use a synchronization signal to ensure the alignment of time slots.

[0132] Figure 6 An example signal encoding for providing aligned time slots according to an embodiment of the present disclosure is shown.

[0133] All nodes on the bus operate on their own clocks, with a variability of ±5%. In this example, to provide aligned time slots, nodes send their PAM-3 signaling within a specific time window surrounded by two protection release periods and triggered by the master synchronization signal.

[0134] In this example, the time slot corresponds to 1000ns. The diagram shows:

[0135] 1. Output from MCU or gateway (labeled "Main Output");

[0136] 2. Inputs received at the MCU or gateway (labeled "Main Inputs");

[0137] 3. The response of the first node (minimum propagation distance) located closest to the MCU on the bus, the first node having a fast clock (+5%) (labeled "slave near fast"); and

[0138] 4. The response (maximum propagation distance) of the second node located far from the MCU on the bus, the second node having a slow clock (-5%) (marked as "slave far slow");

[0139] The first and second nodes illustrate the worst-case scenario—a combination of a first node with a fast clock and positioned close to the MCU, and a second node with a slow clock and positioned far from the MCU.

[0140] At the start of a time slot, the MCU asserts a synchronization signal on the bus for 250 ns to signal the start of the time slot. Each slave node is configured to respond to the synchronization signal with a 250 ns guard period (protection release), during which the node does not apply any modulation state to the bus. Following the guard period is a 250 ns transmission period, during which the node asserts the ternary modulation state (symbol) corresponding to the current time slot. This transmission period is followed by another 250 ns protection release.

[0141] Due to the negligible propagation distance and the 5% fast clock of the first node, the first node begins symbol transmission (transmission period start) ahead of schedule at 487.5 ns (instead of 500 ns, if the clock is accurate). Because of the negligible propagation distance, the MCU receives the signal from the first node at 487.5 ns. Due to the fast clock, the first node completes signal transmission (transmission period end) at 725 ns, and the main output receives the signal from the first node at 725 ns.

[0142] Conversely, due to the 50ns propagation delay, the second node only receives the end of the synchronization signal at 300ns. The slow clock composite delay means the second node only starts signal transmission at 562.5ns and completes it at 825ns. The 50ns propagation delay also applies to the signal returning to the MCU. Therefore, the MCU receives the signal from the second node at 612.5ns and 875ns.

[0143] The MCU receives signals from both the first and second nodes within a fixed time window from 612.5ns (starting signal reception from the second node) to 725ns (stopping signal reception from the first node). Since the first and second nodes represent the worst-case scenario, the fixed time window from 612.5ns to 725ns represents the time window during which signals will be received from all nodes on the bus and enumeration and arbitration processes can occur. In this example, the optimal sampling time is 669ns; other examples may use time slots, synchronization signals, guard periods, transmission periods, and / or transmission windows of varying durations.

[0144] Figure 7 Another node is shown according to an embodiment of this disclosure. Also included is... Figure 2 In Figure 7 The characteristics have already been given in the corresponding numbers in the 700 series, and will not need to be described again here.

[0145] Node 708 includes a controller 710, a transmission formatter 742, a transmission encoder 744, a transmission timer 746, a receiver resynchronization unit 748, a receiver decoder 750, and a receiver formatter 752. It should be understood that each of these modules and / or their functions can be configured as appropriate. Figure 2It is part of the controller, signal driver, and / or receiver.

[0146] The new functionality required for the three-level enumeration process is shown in dashed outline.

[0147] The transfer formatter 742 is configured to receive data bytes from the controller 710 and determine the FTPL code—a sequence of ternary modulation states (symbols)—according to a ternary encoding scheme. During the enumeration process, the transfer formatter 742 uses the enumeration formatter 754 to apply an enumeration encoding scheme, such as the six three-level symbols to three-bit scheme described above. The enumeration scheme determines the sequence of ternary modulation states representing the UID received from the controller 710. After the enumeration process, the transfer formatter 742 can use a standard ternary encoding scheme (e.g., a six three-level symbols to six-bit scheme) to determine the FTPL code of the data bytes received from the controller 710.

[0148] The transmission encoder 744 encodes the bit stream determined by the transmission formatter 742 into a ternary modulated state stream.

[0149] Transmission timer 746 includes arbitration timer 756, which is configured to receive a synchronization signal from synchronization detector 758 of receiver resynchronization 748 and add a protection period in response to the synchronization signal. Transmission timer 746 drives a control signal driver to apply a ternary modulation state to bus 706 within a specific time slot after the end of the protection period.

[0150] Synchronization detector 758 detects the synchronization signal for each time slot on communication bus 706 and provides the synchronization signal to arbitration timer 756.

[0151] The receiver resynchronization 748 also includes a loss detector 760 to detect whether the continuous ternary modulation state on the bus matches the ternary modulation state applied by the signal driver of node 708. The loss detector 760 can detect a match during a fixed time window within a transmission period, as described above. Figure 6 As described.

[0152] The receiver decoder 750 and receiver formatter 752 convert the ternary modulation state (symbol) detected on bus 706 back into data for controller 710. Controller 710 includes arbitration control 762 to detect whether a node has lost the arbitration process for the current node address assignment phase of the enumeration process.

[0153] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above diagrams may be performed in any order. Furthermore, those skilled in the art will recognize that while an example set of instructions / methods has been discussed, the material in this specification can be combined in various ways to produce other examples, and should be understood within the context of the detailed description provided herein.

[0154] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed and controlled by the executable instructions. Such instructions are loaded to execute on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0155] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transitory machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any single or multiple components manufactured. Non-transitory machine- or computer-usable media as defined herein does not include signals, but such media may be capable of receiving and processing information from signals and / or other transient media.

[0156] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via networks, computers, or data-based devices and / or services. These may include cloud, internet, intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0157] In one example, one or more instructions or steps discussed in this article are automated. The terms automated or automatic (and similar variations) mean using computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without human intervention, observation, effort, and / or decision-making.

[0158] It should be understood that any components that are to be coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, another component can be positioned between two components that are said to be coupled.

[0159] In this specification, exemplary embodiments have been presented according to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of details, can be practiced. It is intended that the appended claims cover all possible exemplary embodiments.

Claims

1. A node for a ternary modulation communication bus system, characterized in that, The nodes include: Controller; The receiver is configured to detect the ternary modulation state on the communication bus; and A signal driver configured to apply a ternary modulation state to a communication bus, wherein the ternary modulation state includes one of the following: First dominant state; Second dominant state; or Hidden state; During the enumeration process, the controller is configured to: The enumeration signal is received from the communication bus via the receiver; In response to the enumeration signal, the signal driver is controlled to apply the ternary modulation state sequence for the corresponding time slot sequence to the communication bus according to the enumeration coding scheme to represent the unique identifier of the node. The enumeration encoding scheme includes one or more ternary encoding rules, including: In each time slot, the signal driver applies only the recessive state or a predetermined one of the first and second dominant states specific to the time slot.

2. The node according to claim 1, characterized in that, The one or more ternary encoding rules include: The signal driver applies the same number of first dominant states as the second dominant state to the time slot sequence.

3. The node according to claim 1 or claim 2, characterized in that, The one or more ternary encoding rules include one or more of the following: Imbalances in sequences of two first dominant states or two second dominant states are prohibited. as well as Temporary imbalances in a sequence of first dominant states or second dominant states do not last more than three time slots.

4. The node according to any one of the preceding claims, characterized in that, The one or more ternary encoding rules include one or more of the following: The maximum run length of the same ternary modulation state at the beginning of the ternary modulation state sequence is one time slot; The maximum run length of the same ternary modulation state within the ternary modulation state sequence is three time slots; and The maximum run length of the same ternary modulation state at the end of the ternary modulation state sequence is two time slots.

5. The node according to any one of the preceding claims, characterized in that, The signal driver includes: A dominant state driver, comprising a push-pull driver configured to selectively: Pull the first bus connection terminal up to the power supply voltage and pull the second bus connection terminal down to the reference voltage to provide the first dominant state; and Pull the second bus connection terminal up to the power supply voltage and pull the first bus connection terminal down to the reference voltage to provide the second dominant state; and A reference state driver includes a buffered common-mode reference circuit configured to apply the recessive state to the first and second bus connection terminals.

6. The node according to claim 5, characterized in that, The dominant state driver is configured to: Selectively enable a first state switch and selectively disable a second state switch to apply the first dominant state to the communication bus; The second state switch is selectively enabled and the first state switch is selectively disabled to apply the second dominant state to the communication bus; and The first state switch is selectively disabled and the second state switch is selectively disabled to apply the latent state to the communication bus.

7. The node according to any one of the preceding claims, characterized in that, The enumeration encoding scheme includes encoding six three-level symbols to provide three-bit enumeration data.

8. A ternary modulation communication bus system, characterized in that, include: Main control unit; Communication bus; as well as Multiple nodes according to any one of the preceding claims, The master control unit is configured to apply the enumeration signal to the communication bus.

9. A battery management system, characterized in that, Includes the node according to any one of claims 1 to 7 or the ternary modulation communication bus system according to claim 8.

10. A method for enumerating nodes on a ternary modulation communication bus system, characterized in that, The method includes: At the node, an enumeration signal is received from the communication bus of the ternary modulation communication bus system; The sequence of ternary modulation states representing the unique identifier of the node is encoded according to an enumeration encoding scheme, wherein each ternary modulation state includes one of the following: First dominant state; Second dominant state; or Hidden state; Each ternary modulation state is applied to the communication bus in the corresponding time slot of the corresponding time slot sequence; If, for each time slot in the time slot sequence, the ternary modulation state applied to the communication bus matches a continuous ternary modulation state persisting on the bus within that time slot, then the node is determined to have won the arbitration process; and If, for any time slot in the time slot sequence, the ternary modulation state applied to the communication bus is different from the continuous ternary modulation state that persists on the bus within the time slot, then the node is determined to have lost the arbitration process. The enumeration encoding scheme includes one or more ternary encoding rules, including: In each time slot, the node applies only the latent state or the predetermined one of the first and second dominant states specific to the time slot.

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