Flash memory device and manufacturing method thereof
By etching the gate stack and forming grooves in the NOR Flash memory cell, the crosstalk problem caused by the reduction of floating gate distance is solved, improving the reliability of the device and reducing the channel resistance.
Patent Information
- Application Number
- CN202511429804.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-01-13
AI Technical Summary
In NOR Flash memory cells, as the floating gate distance decreases, crosstalk problems become more severe, especially when programming a selected row. The adjacent rows are subjected to more severe crosstalk, affecting device reliability.
By etching a portion of the substrate while etching the gate stack, a groove is formed, and metal silicide contact vias are formed within the substrate. This adjusts the ion implantation angle of the lightly doped source/drain regions, improves programming crosstalk between adjacent rows of co-located contact vias, and reduces channel resistance.
It effectively improves programming crosstalk between adjacent rows of co-located contact holes, reduces channel resistance, and improves device reliability.
Smart Images
Figure CN121335100A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and particularly relates to a flash memory device and a manufacturing method thereof. BACKGROUND
[0002] Flash memory is a kind of non-volatile memory which can keep data for a long time even without power supply, that is, the data will not be lost after power-off. Flash memory is mainly divided into NOR and NAND types, commonly known as NOR flash and NAND flash. Among them, NOR flash, also known as code type flash memory, has the characteristics of direct code execution, strong reliability and fast reading speed, and thus becomes the mainstream non-volatile memory in flash memory technology.
[0003] With the continuous shrinkage of NOR flash memory cells, the floating gate (FG) and the floating gate distance are getting closer and closer, and the crosstalk (Disturb) becomes a key problem affecting the reliability of NOR flash. It is found in the test process that a new crosstalk (Disturb) mode is introduced, that is, when programming the selected row (Row Program), other rows compared with the most adjacent row will suffer more serious crosstalk. It is suspected that the PGM current electrons during programming cause secondary electrons at the junction, which are injected into the adjacent floating gate, causing crosstalk. SUMMARY
[0004] The purpose of the present application is to provide a flash memory device and a manufacturing method thereof to solve the programming crosstalk problem of adjacent rows of co-line contact holes.
[0005] To achieve the above purpose, the present application provides a manufacturing method of a flash memory device, comprising:
[0006] A semiconductor structure is provided, which comprises a substrate, a gate stack layer on the substrate, and a word line polysilicon between the gate stack layer, the gate stack layer comprises a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top, a hard mask layer is formed on the control gate polysilicon layer, and a word line side wall is formed on the sidewall of the hard mask layer;
[0007] The hard mask layer is removed, and a first side wall is formed on the sidewall of the word line side wall;
[0008] The gate stack layer and part of the thickness of the substrate are etched in sequence with the word line side wall and the first side wall as a mask, and a groove is formed in the substrate;
[0009] A second side wall is formed on the sidewall of the etched gate stack layer and the groove;
[0010] etching part of the second side wall to form a side wall opening in the recess; and
[0011] forming a metal silicide in the side wall opening and forming a contact via connecting the metal silicide.
[0012] Optionally, the etching thickness of the substrate is 50-200 angstroms.
[0013] Optionally, after forming the recess and before forming the second side wall, the method further comprises performing a first ion implantation on the substrate to form a lightly doped source / drain region.
[0014] Optionally, the first ion implantation is performed through the recess at an angle of 7-15 degrees.
[0015] Optionally, after forming the side wall opening and before forming the metal silicide, the method further comprises performing a second ion implantation on the substrate to form a heavily doped source / drain region.
[0016] Optionally, before removing the hard mask layer, the method further comprises performing chemical mechanical polishing and etching back on the word line polysilicon and forming a word line oxide layer on the word line polysilicon after etching back.
[0017] Optionally, forming a metal silicide in the side wall opening and forming a contact via connecting the metal silicide comprises:
[0018] forming an interlayer dielectric layer on the substrate surface;
[0019] etching the interlayer dielectric layer to expose the metal silicide in the side wall opening.
[0020] Optionally, a gate oxide layer is formed on the substrate, and the gate stack and the word line polysilicon are located on the gate oxide layer.
[0021] Optionally, a tunneling oxide layer is arranged between the word line polysilicon and the gate stack, and a first dielectric layer and a second dielectric layer are formed on the side of the tunneling oxide layer close to the gate stack.
[0022] Optionally, the word line side wall is an oxide layer, the first side wall is a nitride layer, the first dielectric layer is an oxide layer, and the second dielectric layer is a nitride layer.
[0023] Optionally, the second side wall comprises an oxide layer and a nitride layer, and the oxide layer is arranged close to the gate stack.
[0024] Optionally, the inter-gate dielectric layer is composed of stacked oxide layers, nitride layers and oxide layers.
[0025] Correspondingly, the application also provides a flash memory device, which is manufactured by the manufacturing method of the flash memory device.
[0026] A semiconductor structure, comprising a substrate, a gate stack on the substrate, and a word line polysilicon between the gate stack, the gate stack comprising, from bottom to top, a floating gate polysilicon layer, an inter-gate dielectric layer, and a control gate polysilicon layer.
[0027] A recess, which is deep into the substrate, is between the semiconductor structures.
[0028] A first side wall and a word line side wall are on the control gate polysilicon layer, and the word line side wall is close to the word line polysilicon.
[0029] A second side wall covers the sidewall of the first side wall, the sidewall of the gate stack, and part of the recess.
[0030] A metal silicide is in the recess not covered by the second side wall.
[0031] A contact via connects the metal silicide.
[0032] Optionally, the recess is deep into the substrate by 50-200 angstroms.
[0033] Optionally, a tunneling oxide layer is between the word line polysilicon and the gate stack, and a first dielectric layer and a second dielectric layer are formed on the side of the tunneling oxide layer close to the gate stack.
[0034] Optionally, a gate oxide layer is formed on the substrate, and the gate stack is on the gate oxide layer.
[0035] In summary, the manufacturing method of the flash memory device provided by the application etches the gate stack to form the floating gate and the control gate, and continues to etch part of the thickness of the substrate, so as to ensure that the source / drain region is lower than the channel surface in the subsequent process, improve the programming crosstalk of the adjacent rows of the common bit line contact via, and reduce the channel resistance by adjusting the ion implantation angle of the lightly doped source / drain region to connect the channel and the source / drain vertically. BRIEF DESCRIPTION OF DRAWINGS
[0036] Figure 1 The flowchart of the manufacturing method of the flash memory device provided by the embodiment of the application is shown.
[0037] Figures 2A-2H The structure diagram of the structure formed by the corresponding steps of the manufacturing method of the flash memory device is shown. DETAILED DESCRIPTION
[0038] For the purpose of making the content of the present application more clear and easy to understand, the content of the present application is further explained in the following in combination with the drawings of the specification. Of course, the present application is not limited to this specific embodiment, and general substitutions well known to those skilled in the art are also covered in the protection scope of the present application.
[0039] Secondly, the present application is described in detail by using a schematic diagram. In the detailed description of the present application, the schematic diagram is not enlarged in part according to the general proportion for the convenience of description, and this should not be taken as a limitation of the present application.
[0040] For the convenience of description, some embodiments of the present application can use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the drawings of the embodiments. It should be understood that, in addition to the orientation described in the drawings, the spatial relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element or component described as "below" or "under" other elements or components will then be positioned "above" or "over" the other elements or components. The terms "first", "second", etc. in the following are used to distinguish between similar elements, and do not necessarily describe a specific order or time sequence.
[0041] Figure 1 A flowchart of a manufacturing method of a flash memory device provided by an embodiment of the present application is shown in FIG. 1. The manufacturing method of the flash memory device provided by the embodiment includes the following steps: Figure 1
[0042] Step S01: providing a semiconductor structure, the semiconductor structure including a substrate, a gate stack on the substrate, and a word line polysilicon between the gate stack, the gate stack including, from bottom to top, a floating gate polysilicon layer, an inter-gate dielectric layer, and a control gate polysilicon layer, a hard mask layer formed on the control gate polysilicon layer, and a word line side wall formed on the sidewall of the hard mask layer;
[0043] Step S02: removing the hard mask layer, and forming a first side wall on the sidewall of the word line side wall;
[0044] Step S03: taking the word line side wall and the first side wall as a mask, etching the gate stack and part of the thickness of the substrate in sequence, and forming a groove in the substrate;
[0045] Step S04: forming a second side wall on the sidewall of the etched gate stack and the groove;
[0046] Step S05: etching part of the second side wall to form a side wall opening in the groove; and,
[0047] Step S06: A metal silicide is formed inside the sidewall opening, and a contact via is formed to connect the metal silicide.
[0048] Figures 2A-2H This is a schematic diagram illustrating the structural steps of a flash memory device fabrication method according to an embodiment of the present invention. Please refer to... Figure 1 As shown, and in combination Figures 2A-2H The present invention provides a detailed description of the method for manufacturing the flash memory device.
[0049] First, refer to Figures 2A-2B As shown, step S01 is performed to provide a semiconductor structure, which includes a substrate 100, a gate stack on the substrate 100, and word line polysilicon 110 located between the gate stacks. The gate stack includes a floating gate polysilicon layer 102, an inter-gate dielectric layer, and a control gate polysilicon layer 104 from bottom to top. A hard mask layer 105 is formed on the control gate polysilicon layer 104. The hard mask layer 105 exposes a portion of the control gate polysilicon layer 104 on the side near the word line polysilicon 110, and word line sidewalls 106 are formed on the sidewalls of the hard mask layer 105.
[0050] Specifically, the substrate 100 can be a silicon substrate, the inter-gate dielectric layer is composed of stacked oxide layer 103a, nitride layer 103b, and oxide layer 103c, and the hard mask layer 105 is made of at least one of silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbide nitride, and silicon oxynitride.
[0051] A gate oxide layer 101 is formed on the substrate 100, and the gate stack is located on the gate oxide layer 101. The gate oxide layer 101 can be formed by methods such as low-pressure chemical vapor deposition, atomic layer deposition, thermal oxidation, or molecular beam epitaxy. The material of the gate oxide layer 101 is silicon oxide to enhance the interfacial adhesion between layers.
[0052] A tunneling oxide layer 111 is disposed between the word line polysilicon 100 and the gate stack. A first dielectric layer 112 and a second dielectric layer 113 are formed on the side of the tunneling oxide layer 111 near the gate stack. The first dielectric layer 112 is an oxide layer and the second dielectric layer 113 is a nitride layer, such as the first dielectric layer 112 being a silicon oxide layer and the second dielectric layer 113 being a silicon nitride layer.
[0053] In step S01, after the semiconductor structure is formed, the process further includes chemical mechanical polishing and etching back of the word line polysilicon 110, forming a word line oxide layer 114 on the etched word line polysilicon 110, and performing chemical mechanical polishing (CMP) after forming the word line oxide layer 114. The word line oxide layer 114 is located above the tunnel oxide layer 111, the first dielectric layer 112, and the second dielectric layer 113.
[0054] Next, refer to Figure 2C and Figure 2D Step S02 is executed to remove the hard mask layer 105 and form a first sidewall 107 on the sidewall of the word line sidewall 106.
[0055] Next, refer to Figure 2E In step S03, using the word line sidewall 106 and the first sidewall 107 as masks, the gate stack and a portion of the substrate 100 are sequentially etched to form a groove 120 in the substrate 100. The etching thickness of the substrate 100 is 50 angstroms to 200 angstroms, for example, 100 angstroms.
[0056] Furthermore, after etching to form the groove 120, the substrate is further subjected to a first ion implantation (CellLDDIMP) to form a lightly doped source / drain region. The first ion implantation is performed by tilting the groove, and the tilt angle of the first ion implantation is 7 degrees to 15 degrees, for example, 10 degrees. The implanted ion is arsenic ion (As).
[0057] In this embodiment, while etching the gate stack to form the floating gate and control gate, a portion of the substrate thickness is etched to ensure that the subsequent source / drain regions are below the channel surface, thus improving programming crosstalk between adjacent rows of the co-located contact holes (BL CT). Furthermore, this fabrication process eliminates the need for additional masks. By adjusting the Cell LDDIMP injection angle, the channel and source / drain are vertically connected, thereby reducing the channel resistance.
[0058] Next, refer to Figure 2F In step S04, a second sidewall is formed on the sidewalls of the etched gate stack and the groove 120. The second sidewall includes an isolation oxide layer 108a and an isolation nitride layer 108b, with the isolation oxide layer 108a disposed close to the gate stack.
[0059] Next, continue to refer to Figure 2FStep S05 involves etching a portion of the second sidewall within the groove 120 until the substrate 100 is exposed, forming a sidewall opening 121. After forming the sidewall opening 121, a second ion implantation (Cell NPLUS IMP) is performed on the substrate 100 to form heavily doped source / drain regions.
[0060] Next, refer to Figure 2G and Figure 2H In step S06, a metal silicide 122 is formed in the sidewall opening 121, and a contact through hole 124 is formed to connect the metal silicide 122.
[0061] Specifically, after forming a metal silicide 122 within the sidewall opening 121, an interlayer dielectric layer 123 is formed on the surface of the substrate 100. The interlayer dielectric layer 123 is then etched to expose the metal silicide 122 located in the sidewall opening 121, forming a connecting contact via 124. The metal silicide 122 includes nickel metal silicide, cobalt metal silicide, or titanium metal silicide; for example, in this embodiment, it is nickel metal silicide. In other embodiments of the present invention, a metal silicide is formed on the word line polysilicon, and a contact via connecting thereto is formed.
[0062] Accordingly, the present invention also provides a flash memory device, manufactured using the flash memory device manufacturing method described above. Referring to other figures, the flash memory device includes:
[0063] A semiconductor structure includes a substrate 100, a gate stack on the substrate 100, and word line polysilicon 110 between the gate stacks. The gate stack includes, from bottom to top, a floating gate polysilicon layer 102, an inter-gate dielectric layer, and a control gate polysilicon layer 104.
[0064] The groove 120 extends into the substrate 100 and is located between the semiconductor structures.
[0065] The first sidewall 108 and the word line sidewall 107 are located on the control gate polysilicon layer 104, with the word line sidewall 107 disposed close to the word line polysilicon 110.
[0066] The second sidewall covers the sidewall of the first sidewall 107, the sidewall of the gate stack, and part of the groove 120;
[0067] Metal silicide 122 is located within the groove 120 not covered by the second sidewall;
[0068] Contact through-hole 123 connects to the metal silicide 122.
[0069] Specifically, a gate oxide layer 101 is formed on the substrate 100, and the gate stack and the word line polysilicon 110 are located on the gate oxide layer 101. The trench 120 extends into the substrate to a thickness of 50 angstroms to 200 angstroms. Ion implantation is performed on the substrate through the trench 120 to form lightly doped source / drain regions and heavily doped source / drain regions. A tunneling oxide layer 111 is disposed between the word line polysilicon 110 and the gate stack, and a first dielectric layer 112 and a second dielectric layer 113 are formed on the side of the tunneling oxide layer 111 closest to the gate stack.
[0070] In summary, the present invention provides a flash memory device and its fabrication method in which, while etching the gate stack to form the floating gate and control gate, a portion of the substrate thickness is etched to ensure that the subsequent source / drain regions are below the channel surface, thereby improving programming crosstalk between adjacent rows of co-located contact holes. Furthermore, this fabrication process does not require additional masks, and the channel and source / drain can be vertically connected by adjusting the ion implantation angle of the lightly doped source / drain regions, thereby reducing the channel resistance.
[0071] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing a flash memory device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a substrate, a gate stack on the substrate and word line polysilicon located between the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top, a hard mask layer and word line sidewalls formed on the control gate polysilicon layer. Remove the hard mask layer and form a first sidewall on the sidewall of the word line sidewall; Using the word line sidewall and the first sidewall as masks, the gate stack and a portion of the substrate are etched sequentially to form a groove on the substrate; A second sidewall is formed on the sidewall of the etched gate stack and the groove; The second sidewall is etched to form a sidewall opening within the groove; as well as, Metal silicide is formed within the sidewall opening, and a contact via is formed to connect the metal silicide.
2. The method for manufacturing a flash memory device according to claim 1, characterized in that, The etching thickness of the substrate is 50 angstroms to 200 angstroms.
3. The method for manufacturing a flash memory device according to claim 1, characterized in that, After the formation of the groove and before the formation of the second sidewall, the substrate is further subjected to a first ion implantation to form a lightly doped source / drain region.
4. The method for manufacturing a flash memory device according to claim 3, characterized in that, The first ion implantation is performed by tilting the ion through the groove, and the tilt angle of the first ion implantation is 7 degrees to 15 degrees.
5. The method for manufacturing a flash memory device according to claim 1, characterized in that, After forming the sidewall openings and before forming the metal silicide, a second ion implantation is performed on the substrate to form heavily doped source / drain regions.
6. The method for manufacturing a flash memory device according to claim 1, characterized in that, Before removing the hard mask layer, the process further includes: chemically mechanically polishing and re-etching the word line polysilicon, and forming a word line oxide layer on the re-etched word line polysilicon.
7. The method for manufacturing a flash memory device according to claim 1, characterized in that, The process of forming a metal silicide within the sidewall opening and forming a connection between the metal silicide includes: contact vias comprising: An interlayer dielectric layer is formed on the surface of the substrate; The interlayer dielectric layer is etched to expose the metal silicide located at the sidewall opening.
8. The method for manufacturing a flash memory device according to claim 1, characterized in that, A gate oxide layer is formed on the substrate, and the gate stack is formed on the gate oxide layer.
9. The method for manufacturing a flash memory device according to claim 1, characterized in that, A tunneling oxide layer is disposed between the word line polysilicon and the gate stack, and a first dielectric layer and a second dielectric layer are formed on the side of the tunneling oxide layer near the gate stack.
10. The method for manufacturing a flash memory device according to claim 11, characterized in that, The sidewall of the letter line is an oxide layer, the first sidewall is a nitrided layer, the first dielectric layer is an oxide layer, and the second dielectric layer is a nitrided layer.
11. The method for manufacturing a flash memory device according to claim 1, characterized in that, The second sidewall includes an oxide layer and a nitride layer, with the oxide layer disposed close to the gate stack.
12. The method for manufacturing a flash memory device according to claim 1, characterized in that, The inter-gate dielectric layer is composed of stacked oxide, nitride, and oxide layers.
13. A flash memory device, comprising a flash memory device manufactured using the method of manufacturing a flash memory device according to any one of claims 1 to 12, wherein the flash memory device comprises: A semiconductor structure includes a substrate, a gate stack on the substrate, and word line polysilicon located between the gate stacks, wherein the gate stack includes, from bottom to top, a floating gate polysilicon layer, an inter-gate dielectric layer, and a control gate polysilicon layer. Grooves, extending into the substrate, are located between the semiconductor structures; The first sidewall and the word line sidewall are located on the control gate polysilicon layer, with the word line sidewall disposed close to the word line polysilicon layer. The second sidewall covers the sidewall of the first sidewall, the sidewall of the gate stack, and part of the groove; Metal silicide is located within the groove not covered by the second sidewall; Contact vias connect the metal silicide.
14. The flash memory device according to claim 13, characterized in that, The groove extends into the substrate to a depth of 50 to 200 angstroms.
15. The flash memory device according to claim 13, characterized in that, A tunneling oxide layer is disposed between the word line polysilicon and the gate stack, and a first dielectric layer and a second dielectric layer are formed on the side of the tunneling oxide layer near the gate stack.
16. The flash memory device according to claim 13, characterized in that, A gate oxide layer is formed on the substrate, and the gate stack is located on the gate oxide layer.