Negative capacitance tunneling field effect transistor and preparation method thereof

Abstract

The invention relates to a negative capacitance tunneling field effect transistor and a preparation method thereof, belongs to the technical field of field effect transistors, and solves the technical problems of limited tunneling area and small on-state current of an existing tunneling field effect transistor. The transistor comprises a source region, an intrinsic region, a drain region, a gate oxide layer, a metal gate, a drain electrode, a source electrode and an HfO2 ferroelectric layer. And the lengths of the HfO2 ferroelectric layer and the metal gate are smaller than the length of the gate oxide layer. And the doping type of the intrinsic region is the same as that of the drain region and is opposite to that of the source region. The preparation method comprises the steps of sample wafer pretreatment, photoetching, etching, ion implantation, photoresist removal, activation, implantation and doping, gate oxide layer deposition, HfO2 ferroelectric layer preparation, metal gate preparation, oxide layer removal, and source electrode and drain electrode deposition. The invention is used for the tunneling field effect transistor with the short gate structure based on the negative capacitance effect.

Description

Technical Field

[0001] This invention belongs to the field of field-effect transistor technology, specifically relating to a negative capacitance tunneling field-effect transistor with the function of suppressing bipolar current and its fabrication method. Background Technology

[0002] As integrated circuit dimensions continue to shrink, the overall power of circuits is constantly increasing. Fabricating field-effect transistors (FETs) with large on / off ratios and steep subthreshold swings (SS) is crucial for improving device response speed and reducing power consumption. Tunneling field-effect transistors (TFETs), based on the band-to-band tunneling principle, can effectively reduce the device's SS. When a voltage is applied to the gate of a TFET, the intrinsic band decreases. When the valence band of the source region is higher than the conduction band of the intrinsic region, and the potential barrier becomes thinner, valence band electrons from the source region can tunnel into the conduction band of the intrinsic region, generating a tunneling current. At this point, the TFET is in the ON state.

[0003] A typical tunneling field-effect transistor is a gate-controlled PIN diode, also known as a lateral tunneling field-effect transistor, whose device structure is as follows: Figure 1 As shown, the structure includes source region 2, intrinsic region 3, drain region 4, gate oxide layer 5, metal gate 6, drain electrode 7, and semiconductor substrate 8. In this structure, tunneling breakdown occurs at the interface between source region 2 and intrinsic region 3, in the gate-controlled surface region. The area where tunneling occurs is limited, resulting in a relatively small on-state current. This is a major reason why tunneling field-effect transistors (TFTSs) cannot yet replace MOSFETs. Furthermore, since the working principle of TFTSs is to generate current through band-to-band tunneling, band-to-band tunneling also occurs at the junction of the channel and drain regions, generating bipolar current. This affects the power consumption and operating performance of the device. Overcoming the problem of small on-state current and reducing the bipolar current in the drain region has become the focus of TFTS research.

[0004] Regarding the negative capacitance effect, compared to traditional MOSFETs, negative capacitance transistors have an additional layer of ferroelectric material in the gate dielectric. Due to the residual polarization of the ferroelectric material, the voltage acting on the gate dielectric is greater than the actual applied gate voltage, thus increasing the channel surface potential. Compared to ordinary tunneling transistors (TFETs), the on-state current is improved to some extent.

[0005] By incorporating ferroelectric material into the gate stack of a TFET, the ion current is enhanced, while simultaneously making the subthreshold swing (SS) very steep. Therefore, by adding ferroelectric material to the gate stack of a TFET, faster switching and enhanced ion current can be achieved. Consequently, negative capacitance TFETs (NC-TFETs) hold great potential for low-power applications in the field of very large-scale integration (VLSI).

[0006] Due to its high dielectric constant, wide band gap, and good compatibility with CMOS processes, HfO2 binary oxide is widely used in field-effect transistors. Compared with traditional ferroelectric thin films, the polycrystalline structure of HfO2 ferroelectric thin films reduces the requirements for the substrate. In addition, thanks to the mature process of combining with silicon-based materials, the reliability and stability of the devices are guaranteed, and the smaller thickness limit makes the miniaturization of ferroelectric devices possible.

[0007] Preparation of ferroelectric layer

[0008] There are four main methods for preparing ferroelectric oxide thin films: sol-gel method, magnetron sputtering method, pulsed laser deposition (PLD) method, and metal-organic chemical vapor deposition (MOCVD). Among them, the sol-gel method has the advantages of simple equipment, easy operation, easy doping of thin films, and ability to prepare thin films on a large area. Summary of the Invention

[0009] To overcome the shortcomings of existing tunneling field-effect transistors, such as limited tunneling area and small on-state current, this invention proposes a negative capacitance tunneling field-effect transistor and its fabrication method.

[0010] The technical solution adopted by this invention to solve its technical problem is:

[0011] A negative capacitance tunneling field-effect transistor includes a source region, an intrinsic region, a drain region, a gate oxide layer, a metal gate, a drain electrode, a source electrode, and an HfO2 ferroelectric layer.

[0012] The drain electrode, drain region, intrinsic region, source region, and source electrode are connected sequentially along the length direction, have equal thickness, and are aligned in the thickness direction.

[0013] The intrinsic region, gate oxide layer, HfO2 ferroelectric layer, and metal gate are sequentially connected from the inside to the outside along the thickness direction; the gate oxide layer and the intrinsic region are of equal length and aligned in the length direction; the HfO2 ferroelectric layer and the metal gate are of equal length and aligned in the length direction, one end of the HfO2 ferroelectric layer is flush with the end where the drain region and the intrinsic region meet, and the length of the HfO2 ferroelectric layer is less than the length of the gate oxide layer.

[0014] The doping types of the source region and the intrinsic region and the drain region are opposite, while the doping types of the intrinsic region and the drain region are the same.

[0015] In the aforementioned negative capacitance tunneling field-effect transistor, the source region, intrinsic region, and drain region are made of Si.

[0016] In the aforementioned negative capacitance tunneling field-effect transistor, the metal gate is metal and the gate oxide layer is SiO2.

[0017] The aforementioned negative capacitance tunneling field-effect transistor has a P-type doping type in its source region, with a doping dose of 1×10⁻⁶. 20 cm -3 The drain region is N-type doped with a doping dose of 5 × 10⁻⁶. 19 cm -3 The intrinsic region is N-type doped with a doping dose of 5 × 10⁻⁶. 16 cm -3 .

[0018] The aforementioned negative capacitance tunneling field-effect transistor has a source region doping dose of 1×10⁻⁶. 20 cm -3 The doping dose of the drain region is 5 × 10⁻⁶. 19 cm -3 The intrinsic region doping dose is 5 × 10⁻⁶. 16 cm -3 .

[0019] In the aforementioned negative capacitance tunneling field-effect transistor, the dielectric constant of the HfO2 ferroelectric layer is 25, and the polarization model parameter is set to α = -1.299 × 10⁻⁶. 11 β = 6.4952 × 10 20 γ = 5 × 10 30 .

[0020] In the aforementioned negative capacitance tunneling field-effect transistor, the length of the metal gate is 15nm–21nm, the length of the gate oxide layer is 30nm–35nm, the length of the source region is 12nm–15nm, the thickness of the HfO2 ferroelectric layer is 4nm–6nm, the length of the intrinsic region is 30nm–35nm, the length of the drain region is 12nm–15nm, the thickness of the source region, intrinsic region, and drain region are all 12nm–15nm, and the work function of the metal gate is 4.515eV.

[0021] A method for fabricating a negative capacitance tunneling field-effect transistor includes the following steps:

[0022] Step S1, Sample pretreatment: Immerse the sample in concentrated sulfuric acid-hydrogen peroxide solution to remove dirt from the sample surface.

[0023] Step S2, Sample photolithography: Photolithography is performed on the pretreated sample. The photolithography process is as follows: coating - pre-baking - exposure - post-baking - development - hardening.

[0024] Step S3, Sample Etching: A plasma etching machine is used to etch the photolithographic sample to form the source region, intrinsic region, and drain region.

[0025] Step S4, Ion implantation and resist removal: Ion implantation is performed on the etched sample to define the doping type and doping dose of the source region, drain region and intrinsic region, and then the resist is removed.

[0026] Step S5, activate implantation doping: Anneal the ion-implanted and de-resisted sample to activate implantation doping.

[0027] Step S6, Gate oxide deposition: A SiO2 thin film is deposited on the sample surface using atomic layer deposition to form a gate oxide layer.

[0028] Step S7, Preparation of HfO2 ferroelectric layer: An HfO2 ferroelectric layer is prepared on the surface of the gate oxide layer using the sol-gel method.

[0029] Step S8, metal gate fabrication: A layer of TiN metal is magnetron sputtered onto the surface of the HfO2 ferroelectric layer using a magnetron sputtering process, and then peeled off to form a metal gate.

[0030] Step S9, Oxide layer removal: During the metal stripping process to form a metal gate, the surface of the metal gate is covered with an oxide film. A wet etching method is used to remove the oxide layer outside the metal gate.

[0031] Step S10, Source and Drain Electrode Deposition: Using a deposition process, a layer of metallic nickel is deposited on the source and drain regions of the sample with the oxide layer removed, and then stripped to form the drain and source electrodes; annealing treatment is performed to form ohmic contacts between the drain electrode and the drain region, and between the source electrode and the source region. A negative capacitance tunneling field-effect transistor is obtained.

[0032] In the above preparation method, step S1, sample pretreatment, uses a concentrated sulfuric acid-hydrogen peroxide solution with a volume ratio of concentrated sulfuric acid to hydrogen peroxide of 1:1; the sample soaking time is 5 minutes.

[0033] In step S4, ion implantation and desizing, the source region is doped with P-type doping at a doping dose of 1×10⁻⁶. 20 cm -3 The drain region is N-type doped with a doping dose of 5 × 10⁻⁶. 18 cm -3 The intrinsic region is N-type doped with a doping dose of 5 × 10⁻⁶. 16 cm -3 .

[0034] In the above preparation method, in step S6 gate oxide layer deposition, the SiO2 thin film is a high-K material with a thickness of 2 nm.

[0035] In step S7, the thickness of the HfO2 ferroelectric layer is 4 nm.

[0036] The beneficial effects of this invention are:

[0037] A negative capacitance tunneling field-effect transistor (FET) improves the subthreshold swing characteristics of the device by adding a HfO2 ferroelectric layer to the gate stack and utilizing the residual polarization of the ferroelectric layer to generate a negative capacitance effect. A short gate design is then used in the gate design. Because the distance between the gate and drain regions is increased, the bipolar current generated from band-to-band tunneling from the intrinsic region to the drain region is suppressed, thus improving the device's operating performance.

[0038] A negative capacitance tunneling field-effect transistor incorporates an HfO2 ferroelectric layer between the metal gate and the gate oxide layer, enabling the transistor to generate a negative capacitance effect within a certain voltage range. This results in a steeper band bend, increasing the tunneling probability and significantly improving the on-state current while reducing the bipolar current generated from the intrinsic region to the drain region due to band-to-band tunneling, thus achieving a smaller subthreshold swing. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the basic structure of a tunneling field-effect transistor (TFET) in the prior art;

[0040] Figure 2 This is a schematic diagram of the basic structure of the existing negative capacitance tunneling field-effect transistor;

[0041] Figure 3 This is a schematic diagram of the negative capacitance tunneling field-effect transistor structure of the present invention;

[0042] Figure 4 This is a comparison diagram of the bipolar current curves of a tunneling field-effect transistor with an existing basic structure and a negative capacitance tunneling field-effect transistor according to the present invention.

[0043] Reference numerals in the figures: 1. Source electrode; 2. Source region; 3. Intrinsic region; 4. Drain region; 5. Gate oxide layer; 6. Metal gate; 7. Drain electrode; 8. Substrate; 9. HfO2 ferroelectric layer. Detailed Implementation

[0044] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0045] Example 1

[0046] A negative capacitance tunneling field-effect transistor and its fabrication method, the design concept is as follows:

[0047] Based on the traditional tunneling transistor (TFET) structure, a ferroelectric negative capacitance effect is introduced by adding a HfO2 ferroelectric layer to the gate and gate oxide layer to improve the on-state current of the device. At the same time, a short gate structure is used to further improve the subthreshold swing of the device.

[0048] The gate region and drain region are partially overlapped. This offset improves the tunneling effect and reduces unwanted electric fields generated at the gate-drain junction. Furthermore, the band barrier at the junction of the channel and drain regions is raised, which leads to a reduction in bipolar current due to the tunneling effect, thus improving device performance.

[0049] The doping concentration of the drain region is further increased to suppress bipolar current. The doping concentration of the source region is 1×10⁻⁶. 20 cm -3 The doping concentration in the drain region is 5 × 10⁻⁶. 19 cm -3 The doping concentration of the intrinsic region is 5 × 10⁻⁶. 16 cm -3 .

[0050] A negative capacitance tunneling field-effect transistor includes a source region 2, an intrinsic region 3, and a drain region 4 arranged from right to left.

[0051] The intrinsic region 3 has a gate oxide layer 5, an HfO2 ferroelectric layer 9 and a metal gate 6 arranged sequentially from the inside to the outside on both the upper and lower sides.

[0052] A drain electrode 7 is provided on the left side of the drain region 4, and a source electrode 1 is provided on the right side of the source region 2;

[0053] The doping types of source region 2 are opposite to those of intrinsic region 3 and drain region 4. Source region 2 is P-type doped, while intrinsic region 3 and drain region 4 are N-type doped.

[0054] The metal gate 6 is made of Metal, and the gate oxide layer 5 is made of SiO2.

[0055] The length of metal gate 6 is 15–21 nm;

[0056] The length of gate oxide layer 5 is 30–35 nm;

[0057] The length of source region 2 is 12–15 nm;

[0058] The thickness of the HfO2 ferroelectric layer 9 is 4–6 nm;

[0059] The length of intrinsic region 3 is 30–35 nm;

[0060] The length of drain region 4 is 12–15 nm;

[0061] The thickness of source region 2, intrinsic region 3, and drain region 4 is 12-15 nm.

[0062] The work function of the metal gate is 4.515 eV.

[0063] Example 2

[0064] The thickness is defined along the x-axis and the length is defined along the y-axis.

[0065] A cross-sectional view of a negative capacitance tunneling field-effect transistor is shown below. Figure 3 As shown, the structure includes a Si substrate 8, a Si source region 2 located on the left side of the substrate 8, a Si intrinsic region 3 located between the intrinsic region 2 and the drain region 4, and three regions: a SiO2 gate oxide layer 5, an HfO2 ferroelectric layer 9, and a Metal gate 6, which are sequentially located on both sides of the intrinsic region 3. A source electrode 1 and a drain electrode 7 are located at the boundary between the source region 2 and the drain region 4.

[0066] Furthermore, the doping type of source region 2 is set to P-type doping, and the doping dose is 1×10⁻⁶. 20 cm -3 The intrinsic region is N-type doped with a doping dose of 5 × 10⁻⁶. 16 cm -3 By making source region 2 heavily doped and intrinsic region 3 lightly doped, the electric field strength at the interface between source region 2 and intrinsic region 3 can be enhanced, thereby increasing the on-state current. Drain region 4 is N-type doped with a doping concentration of 5 × 10⁻⁶. 19 cm -3 Drain region 4 is set to be heavily doped.

[0067] The dielectric constant of HfO2 was further set to 25.

[0068] Furthermore, the capacitance matching of the HfO2 ferroelectric layer was performed using the LK equation, with the polarization model parameter set to α = -1.299 × 10⁻⁶. 11 β = 6.4952 × 10 20 γ = 5 × 10 30 .

[0069] Further adjustments were made to the overlap ratio X between intrinsic region 3 and metal gate 6. Experiments showed that when X = 0.6 (metal gate 6 and intrinsic region 3 are under-stacked by 15 nm), the overlap length determined the tunnel barrier width of the drain region. As the overlap length increased, the bipolar current was effectively controlled. Therefore, by using an appropriate overlap ratio value, not only can bipolar conduction be controlled, but the gate-drain overlap capacitance can also be kept to a minimum.

[0070] To verify the effectiveness of the transistor structure of this invention, the characteristic curves of the short-gate TFET of this invention were compared with those of a conventional dual-gate TFET and a conventional negative capacitance tunneling field-effect transistor with a normal gate stacking length. A schematic diagram of the conventional dual-gate TFET structure is shown below. Figure 1 As shown, a cross-sectional view of a conventional negative capacitor TFET with a normal gate stack length is provided. Figure 2As shown. The dimensions of the source region 2, intrinsic region 3, drain region 4, and gate oxide layer 5 in both devices are consistent with those of the short-gate tunneling field-effect transistor of the present invention. The doping concentrations of the source region 2, intrinsic region 3, and drain region 4 are consistent with those of the short-gate tunneling field-effect transistor. On the gate stack layer, the left side is flush with the interface between the source and intrinsic regions, and the right side is flush with the interface between the intrinsic and drain regions. From Figure 4 As can be seen from the above, the bipolar current of the tunneling field-effect transistor of the present invention is significantly reduced compared with that of the ordinary negative capacitance tunneling field-effect transistor.

[0071] The preparation process consists of the following steps:

[0072] (1) First, place the sample in the prepared concentrated sulfuric acid-hydrogen peroxide solution (volume ratio 1:1). The concentrated sulfuric acid will release a large amount of heat when it comes into contact with the hydrogen peroxide, which can effectively remove the dirt on the surface of the sample. The soaking time for the sample is about 5 minutes.

[0073] (2) After the sample cleaning is completed, the photolithography process begins. The photolithography process includes: coating, pre-baking, exposure, post-baking, development, and hardening.

[0074] (3) After the photolithography is completed, the sample is placed in the plasma etching machine to etch out the source region 2, the intrinsic region 3, and the drain region 4.

[0075] (4) After etching to form the mesa, ion implantation can be completed to define source region 2, drain region 4, and intrinsic region 3. In this experiment, the doping type of source region 2 is P-type, and the doping dose is 1×10⁻⁶. 20 cm -3 Drain region 4 is N-type doped with a doping dose of 5 × 10⁻⁶. 19 cm -3 The intrinsic region 3 is N-type doped with a doping dose of 5 × 10⁻⁶. 16 cm -3 .

[0076] (5) After ion implantation of the source and drain regions is completed and the sample is de-coated, the sample needs to be subjected to RTA rapid thermal annealing to activate the implanted impurities.

[0077] (6) After the RTA annealing process is completed, a SiO2 thin film needs to be deposited on the sample surface as the gate oxide layer 5 using atomic layer deposition (ALD). SiO2 is a high-K material with a thickness of 2nm.

[0078] (7) After the gate dielectric is formed, a 4nm thick HfO2 ferroelectric layer 9 is formed at the gate oxide interface by the sol-gel method.

[0079] (8) After the gate dielectric film is deposited, a TiN metal layer needs to be formed on the sample surface by magnetron sputtering and then peeled off to form a metal gate 6.

[0080] (9) After the metal is stripped to form the gate electrode, the sample surface is covered by an oxide film, and only the film under the gate electrode needs to be retained as the gate dielectric. Therefore, wet etching is required to remove the oxide layer except for the gate dielectric.

[0081] (10) After wet etching of the SiO2 thin film, a layer of metallic nickel needs to be deposited on the sample and stripped to form source electrode 1 and drain electrode 7. Finally, annealing is performed. Annealing can effectively remove tension and initiate a favorable reaction between the metal and the semiconductor to form a good ohmic contact.

Claims

1. A negative capacitance tunneling field-effect transistor, characterized in that, It includes the source region (2), intrinsic region (3), drain region (4), gate oxide layer (5), metal gate (6), drain electrode (7), source electrode (1), and HfO2 ferroelectric layer (9); The drain electrode (7), drain region (4), intrinsic region (3), source region (2), and source electrode (1) are connected sequentially along the length direction, have equal thickness, and are aligned in the thickness direction. The intrinsic region (3), gate oxide layer (5), HfO2 ferroelectric layer (9), and metal gate (6) are connected sequentially from the inside to the outside along the thickness direction; the gate oxide layer (5) and the intrinsic region (3) are of equal length and aligned in the length direction; the HfO2 ferroelectric layer (9) and the metal gate (6) are of equal length and aligned in the length direction, one end of the HfO2 ferroelectric layer (9) is flush with the end of the drain region (4) and the intrinsic region (3), and the length of the HfO2 ferroelectric layer (9) is less than the length of the gate oxide layer (5); The doping types of the source region (2) and the intrinsic region (3) and the drain region (4) are opposite, while the doping types of the intrinsic region (3) and the drain region (4) are the same.

2. The negative capacitance tunneling field-effect transistor according to claim 1, characterized in that, The source region (2), intrinsic region (3), and drain region (4) are Si.

3. The negative capacitance tunneling field-effect transistor according to claim 1, characterized in that, The metal gate (6) is metal, and the gate oxide layer (5) is SiO2.

4. The negative capacitance tunneling field-effect transistor according to claim 1, characterized in that, The source region (2) is P-type doped, the drain region (4) is N-type doped, and the intrinsic region (3) is N-type doped.

5. The negative capacitance tunneling field-effect transistor according to claim 4, characterized in that, The doping dose of the source region (2) is 1×10 20 cm -3 The doping dose of the drain region (4) is 5 × 10⁻⁶. 19 cm -3 The intrinsic region (3) has a doping dose of 5 × 10⁻⁶. 16 cm -3 .

6. The negative capacitance tunneling field-effect transistor according to claim 1, characterized in that, The dielectric constant of the HfO2 ferroelectric layer (9) is 25, and the polarization model parameter is set to α = -1.299 × 10⁻⁶. 11 β = 6.4952 × 10 20 γ = 5 × 10 30 .

7. The negative capacitance tunneling field-effect transistor according to claim 1, characterized in that, The metal gate (6) has a length of 15nm to 21nm, the gate oxide layer (5) has a length of 30nm to 35nm, the source region (2) has a length of 12nm to 15nm, the HfO2 ferroelectric layer (9) has a thickness of 4nm to 6nm, the intrinsic region (3) has a length of 30nm to 35nm, the drain region (4) has a length of 12nm to 15nm, the source region (2), the intrinsic region (3), and the drain region (4) all have a thickness of 12nm to 15nm, and the work function of the metal gate (6) is 4.515eV.

8. A method for fabricating the negative capacitance tunneling field-effect transistors described in claims 1 to 7, characterized in that, Includes the following steps: Step S1, Sample pretreatment: Immerse the sample in concentrated sulfuric acid-hydrogen peroxide solution to remove dirt from the sample surface; Step S2, Sample photolithography: Photolithography is performed on the pretreated sample. The photolithography process is as follows: coating - pre-baking - exposure - post-baking - development - hardening; Step S3, Sample etching: The photolithographic sample is etched using a plasma etching machine to form the source region (2), intrinsic region (3), and drain region (4); Step S4, Ion implantation and resist removal: Ion implantation is performed on the etched sample to define the doping type and doping dose of the source region (2), drain region (4) and intrinsic region (3), and resist removal is performed; Step S5, Activate implantation doping: Anneal the ion-implanted and de-coated sample to activate implantation doping; Step S6, Gate oxide layer (5) deposition: A SiO2 thin film is deposited on the sample surface using atomic layer deposition to form the gate oxide layer (5); Step S7, Preparation of HfO2 ferroelectric layer (9): Using the sol-gel method, an HfO2 ferroelectric layer (9) is prepared on the surface of the gate oxide layer (5); Step S8, metal gate (6) preparation: using magnetron sputtering, a layer of TiN metal is magnetron sputtered on the surface of the HfO2 ferroelectric layer (9), and then peeled off to form the metal gate (6); Step S9, oxide layer removal: During the metal stripping process to form the metal gate (6), the surface of the metal gate (6) is covered with an oxide layer film. The oxide layer outside the metal gate (6) is removed by wet etching. Step S10, source electrode (1) and drain electrode (7) deposition: using a deposition process, a layer of metallic nickel is deposited on the source region (2) end and drain region (4) end of the sample with the oxide layer removed, and the drain electrode (7) and source electrode (1) are formed by peeling. Annealing process is performed to form ohmic contacts between the drain electrode (7) and the drain region (4), and between the source electrode (1) and the source region (2); thus obtaining a negative capacitance tunneling field-effect transistor.

9. The preparation method according to claim 8, characterized in that, In step S1, the sample pretreatment uses a concentrated sulfuric acid-hydrogen peroxide solution with a volume ratio of 1:1; the sample soaking time is 5 minutes. In step S4, ion implantation and desizing, the source region (2) is P-type doped with a doping dose of 1×10⁻⁶. 20 cm -3 ; The drain region (4) is N-type doped with a doping dose of 5 × 10⁻⁶. 19 cm -3 The intrinsic region (3) is N-type doped with a doping dose of 5 × 10⁻⁶. 16 cm -3 .

10. The preparation method according to claim 8, characterized in that, In step S6, the gate oxide layer (5) is deposited, and the SiO2 film is a high-K material with a thickness of 2 nm. In step S7, the thickness of the HfO2 ferroelectric layer (9) is 4 nm.

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