Manufacturing method of semiconductor device
By extending the channel layer in the semiconductor device to suppress the short-channel effect, the limitation of the short-channel effect on FDSOI MOSFET is solved, achieving a larger on-state current and a lower off-state current, thus improving device performance.
Patent Information
- Application Number
- CN202410917976.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-09
- Publication Date
- 2026-01-13
AI Technical Summary
As Moore's Law continues to the 28nm technology node, the impact of short-channel effects on transistor performance has become significant, greatly limiting the miniaturization of FDSOI MOSFETs. Furthermore, traditional methods lead to a decrease in device performance when increasing the doping concentration.
By sequentially stacking a buried oxide layer and a channel layer on a substrate, a gate is formed on the channel layer. The length of the channel layer is made greater than the length of the gate, and the length difference is negatively correlated with the gate length. This extends the channel layer to suppress the short-channel effect while ensuring a larger on-state current.
It effectively suppressed the short-channel effect, increased the on-state current, reduced the off-state current, and improved device performance.
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Figure CN121335129A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor, in particular to a manufacturing method of a semiconductor device. BACKGROUND
[0002] Semiconductor technology has covered application fields such as mobile phones, computers, network communication, automobiles, etc. Among them, network communication, electronic equipment and automobile electronics account for a large part of the semiconductor market. With the development of the times, the fields of 5G technology, artificial intelligence and automobile electronics have put forward higher requirements for semiconductor devices: higher integration, lower power consumption, excellent reliability in harsh environments and lower cost.
[0003] The traditional planar bulk silicon MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure is the most common transistor type in digital circuits and analog circuits, and the working principle of MOSFET is based on the electric field effect to control the conductivity of solid materials. It uses the gate voltage to control the current between the source and the drain. When a certain voltage is applied at the gate, electric charges will be induced on the semiconductor surface under the gate, and these electric charges form a conductive channel, so that the source and the drain can conduct current. However, due to the short channel effect, the control of the gate on the channel current in the MOSFET has been reduced to an unacceptable level, and a process with stronger gate control capability is needed to optimize device performance. Advanced node semiconductor devices with stronger gate control capability mainly include Fin Field Effect Transistor (FinFET) and Fully Depleted Silicon on Insulator (FDSOI).
[0004] Fully Depleted Silicon on Insulator transistor (FDSOI) is a planar process technology, which relies on two main innovations. First, a layer of ultra-thin insulator, called Buried Oxide (BOX), is provided on the top of the substrate, and the transistor channel is realized through a thin layer of silicon on the buried oxide layer, which is called top silicon or SOI layer, realizing the structure of Silicon on Insulator (SOI) of top silicon-buried oxide-substrate. Due to the ultra-thin thickness of the thin layer of silicon, the transistor can be completely depleted without doping the channel. This is due to its electrostatic properties and full dielectric isolation. FDSOI technology is widely used in low-power, radio frequency (RF) and millimeter wave technology fields, and with the help of the ultra-thin silicon film on the buried oxide layer and the unique body bias technology, it meets the requirements of devices in the above fields, and has been applied to multiple technology nodes.
[0005] However, as Moore's Law continued to the 28nm technology node, the impact of short-channel effects on transistor performance became significant, greatly limiting the miniaturization of FDSOI MOSFETs. Summary of the Invention
[0006] In view of this, the purpose of this application is to provide a method for manufacturing a semiconductor device that effectively provides the ability to suppress short-channel effects and ensures a large on-state current.
[0007] This application provides a semiconductor device, including:
[0008] A substrate is provided on which a buried oxide layer and a trench layer are sequentially stacked;
[0009] A gate is formed on the channel layer; a first dimension of the channel layer in a first direction along the surface of the substrate is larger than a second dimension of the gate in the first direction, the difference between the first dimension and the second dimension being determined based on the second dimension and negatively correlated with the second dimension;
[0010] A source electrode is formed that contacts one end of the channel layer, and a drain electrode is formed that contacts the other end of the channel layer, wherein the first direction is the direction of the line connecting the source electrode and the drain electrode.
[0011] Optionally, the difference is linearly related to the second dimension.
[0012] Optionally, the difference is the product of the difference between the preset size and the second size and a preset value, wherein the preset size ranges from 20 to 60 nm and the preset value ranges from 0.1 to 3.
[0013] Optionally, the preset size ranges from 20 to 30 nm, and the preset value ranges from 1 to 3.
[0014] Optionally, the preset size ranges from 40 to 60 nm, and the preset value ranges from 0.1 to 0.8.
[0015] Optionally, the preset size is 50nm, and the preset value is 0.5.
[0016] Optionally, the thickness of the buried oxide layer is 15 nm, and the channel layer material is silicon with a thickness of 5 nm.
[0017] Optionally, the source includes a first substructure flush with the channel layer on one side and a second substructure on the first substructure, and the drain includes a third substructure flush with the channel layer on the other side and a fourth substructure on the third substructure.
[0018] Optionally, the method further comprises:
[0019] forming a gate dielectric layer between the gate and the channel layer.
[0020] Optionally, the method further comprises:
[0021] forming a sidewall of the gate sidewall.
[0022] The application provides a manufacturing method of a semiconductor device, a buried oxygen layer and a channel layer are sequentially stacked on a substrate, a gate is formed on the channel layer, a source is in contact with one end of the channel layer, and a drain is in contact with the other end of the channel layer. The first size of the channel layer in a first direction along the surface of the substrate is greater than the second size of the gate in the first direction, the difference between the first size and the second size is negatively related to the second size, and the first direction is the connection direction of the source and the drain, that is, the length of the channel layer is greater than the length of the gate, and the greater the length of the gate, the smaller the length difference between the two, so that the channel layer and the gate are closer, so that the reduction amplitude of the channel layer is smaller with the reduction of the length of the gate, which is beneficial to inhibiting the short channel effect, and for the case that the length of the gate is large, the length of the channel layer is close to that of the gate, the problem of excessive series resistance caused by the excessive length of the channel layer is avoided, so that the inhibition ability of the short channel effect can be effectively provided, and a large on-state current is ensured. BRIEF DESCRIPTION OF DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0024] Figure 1 A structure schematic diagram of a semiconductor device provided by the embodiment of the application is shown;
[0025] Figure 2 A flowchart of a manufacturing method of a semiconductor device provided by the embodiment of the application is shown;
[0026] Figures 3-6 Structure schematic diagrams of various semiconductor devices provided by the embodiment of the application are shown;
[0027] Figure 7 A schematic diagram of subthreshold swing provided by the embodiment of the application is shown;
[0028] Figure 8 A schematic diagram of drain-induced barrier lowering provided by the embodiment of the application is shown;
[0029] Figure 9A schematic diagram of an on-state current provided for an embodiment of the present application;
[0030] Figure 10 A schematic diagram of another sub-threshold swing provided for an embodiment of the present application;
[0031] Figure 11 A schematic diagram of another drain-induced barrier lowering provided for an embodiment of the present application;
[0032] Figures 12-13 A carrier concentration distribution diagram provided for an embodiment of the present application. DETAILED DESCRIPTION
[0033] In order to make the personnel in the technical field better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person skilled in the art without creative work fall within the scope of protection of the present application.
[0034] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in other ways different from those described herein, and the person skilled in the art can make similar generalizations without departing from the connotation of the present application, so the present application is not limited to the specific embodiments disclosed below.
[0035] The present application is described in detail in conjunction with the schematic diagram, and when the embodiments of the present application are described, the cross-sectional view showing the device structure will be partially enlarged without the general proportion for the convenience of description, and the schematic diagram is only an example, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.
[0036] Reference Figure 1 As shown, a structure schematic diagram of a semiconductor device provided for an embodiment of the present application, the source 130 and the drain 140 at both ends of the transistor are heavily doped, which plays a role of providing carriers when the device is turned on; the channel layer 150 in the middle is lightly doped or not doped, and the PN junction is formed at the junction of the source 130 and the drain 140 at both ends of the channel layer 150. The turning on and turning off of the transistor is realized by adjusting the barrier of the PN junction by applying bias to the gate 170. For the n-type FDSOI MOSFET, that is, the source 130 and the drain 140 are n-type heavily doped, and the positive bias is applied to the gate 170, which will make the channel open, at this time, the positive bias is applied to the drain 140, and the electrons of the source 130 can pass through the channel to enter the drain 140, and the source 130 and the drain 140 can be conductive. When the device is turned off, the channel is not opened, and the drain bias cannot make the carriers pass through the channel.
[0037] PN Junction. A PN junction is a special structure formed by tightly joining a P-type semiconductor with an N-type semiconductor on the same piece of semiconductor. This structure forms a space charge region near their interface, called a PN junction. A PN junction has unidirectional conductivity, that is, it allows current to pass in one direction only, while blocking current in the opposite direction.
[0038] As Moore's Law continues to extend to the 28nm technology node, the influence of short channel effects on transistor performance cannot be ignored, greatly limiting the size of FDSOI MOSFET microshrinkage. Due to the short channel effect, the potential barrier of the PN junction is no longer controlled only by the gate, but is jointly controlled by the drain and the gate, and the gate electrostatic control force is reduced. Specifically, due to the superposition of the lateral electric field of the gate and the drain, current crowding effect occurs at the corner of the channel-gate-drain, and the mobility of the carriers is severely degraded. In addition, the shortening of the channel length also causes part of the carriers to be able to directly tunnel from the source to the drain, increasing the off-state current of the device.
[0039] In order to suppress the short channel effect, it is necessary to increase the channel doping concentration, but continuous increase of the doping concentration will cause the transistor to produce more severe random doping fluctuations, affecting the consistency of the threshold voltage; increase the probability of scattering of the carriers, reduce the on-state current of the device, etc.; high doping concentration increases the PN junction field strength, increases the probability of interband tunneling, and increases the gate-induced leakage current.
[0040] Based on the above technical problems, the embodiments of the present application provide a semiconductor device manufacturing method, a buried oxygen layer and a channel layer are sequentially stacked on a substrate, a gate is formed on the channel layer, and a source is in contact with one end of the channel layer, and a drain is in contact with the other end of the channel layer. The first size of the channel layer in the first direction along the surface of the substrate is greater than the second size of the gate in the first direction, the difference between the first size and the second size is negatively related to the second size, and the first direction is the connection direction of the source and the drain. That is, the length of the channel layer is greater than the length of the gate, and the greater the length of the gate, the smaller the length difference between the two, so that the channel layer and the gate are closer. With the decrease of the length of the gate, the decrease of the channel layer is smaller, which is beneficial to suppress the short channel effect. For the case of a larger gate length, the length of the channel layer and the gate is close, avoiding the problem of excessive series resistance caused by too long channel length. Therefore, the suppression ability of the short channel effect can be effectively provided, and a larger on-state current is ensured.
[0041] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the drawings.
[0042] Reference Figure 2The figure is a flowchart of a semiconductor device manufacturing method provided in an embodiment of this application, which may include:
[0043] S101, a substrate is provided, on which a buried oxide layer and a trench layer are sequentially stacked.
[0044] In this embodiment, the substrate 100 can be a semiconductor substrate to provide support for the film layer thereon. For example, it can be a silicon substrate, germanium substrate, etc. The substrate 100 can be circular during the manufacturing process. For example, it can be a silicon wafer. Multiple chips can be formed on it to form an array, so as to realize the same batch manufacturing of multiple chips and improve manufacturing efficiency.
[0045] A buried oxide layer 110 and a channel layer can be formed on the substrate 100. When the channel layer is made of silicon, the substrate 100, buried oxide layer 110, and channel layer constitute an SOI substrate. The buried oxide layer 110 is an insulating layer used to isolate the channel layer from the substrate 100, preventing carriers in the channel layer from leaking from the substrate 100 during device operation. The buried oxide layer 110 can be, for example, silicon oxide or germanium oxide, and its thickness can be determined according to the node, for example, 15 nm. The channel layer material can be silicon or germanium, and its thickness can be determined according to the node, for example, 5 nm.
[0046] S102, forming a gate on the channel layer; the first dimension of the channel layer in a first direction along the surface of the substrate is greater than the second dimension of the gate in the first direction, the difference between the first dimension and the second dimension being determined based on the second dimension and negatively correlated with the second dimension.
[0047] S103, forming a source electrode that contacts one end of the channel layer and a drain electrode that contacts the other end of the channel layer, wherein the first direction is the direction of the line connecting the source electrode and the drain electrode.
[0048] The source, drain, and gate electrodes can be formed on the substrate, reference. Figures 3-6 The diagram shown is a schematic diagram of the structure of various semiconductor devices provided in the embodiments of this application. The gate 170 is located on the channel layer 150, the source 130 is in contact with one end of the channel layer 150, and the drain 140 is in contact with the other end of the channel layer 150. Taking the line direction connecting the source 130 and the drain 140 as the first direction, the channel layer 150 extends along the first direction. Taking the dimension of the channel layer 150 along the first direction as the first dimension, the first dimension is the first length, and taking the dimension of the gate 170 along the first direction as the second dimension, the second dimension is the second length.
[0049] In addition, a gate dielectric layer 171 can be formed between the gate 170 and the channel layer 150 to isolate the gate 170 and the channel layer 150. The gate dielectric layer 171 can be a high-k dielectric layer, or silicon oxide, etc. The gate 170 can be formed with a sidewall on the sidewall facing the source 130 and the sidewall facing the drain 140, and the sidewall includes a first sidewall 172 and a second sidewall 173 to isolate the gate 170 and the source 130 and the drain 140, respectively. A source contact 131 can be formed on the source 130, and a drain contact 141 can be formed on the drain 140. The source contact 131 and the drain contact 141 can be metal silicide to reduce the contact resistance.
[0050] Generally, the first size and the second size are equal, and the gate electric field generated by the gate 170 acts on the channel layer to control the carrier transmission in the channel layer 150. However, as the size of the transistor is scaled down, the size of the gate 170 is gradually reduced, and at this time, the size of the channel layer 150 is also reduced, and the distance between the source and the drain is reduced, and the channel layer 150 is easily affected by the electric field between the source and the drain, and the control ability of the gate 170 is reduced. In addition, when the channel is short, part of the carriers can directly tunnel from the source to the drain, and the off-state current of the device increases. These adverse effects due to the short channel are called short channel effects.
[0051] In the embodiments of the present application, the first size of the channel layer 150 in the first direction along the surface of the substrate 100 can be greater than the second size of the gate 170 in the first direction, and the difference between the first size and the second size is negatively related to the second size. The first direction is the direction of the connection line of the source 130 and the drain 140, that is, the length of the channel layer 150 is greater than the length of the gate 170, and the greater the length of the gate 170, the smaller the difference between the lengths of the channel layer 150 and the gate 170, so that the lengths of the channel layer 150 and the gate 170 are closer. As the length of the gate 170 decreases, the decrease in the length of the channel layer 150 is smaller, which is beneficial to suppress the short channel effect. For the case where the length of the gate 170 is large, the lengths of the channel layer 150 and the gate 170 are close, which avoids the problem of excessive series resistance caused by the excessive length of the channel layer 150, and thus effectively provides the suppression ability of the short channel effect and ensures a large on-state current. In addition, the channel layer 150 is extended, the channel resistance is increased, and the leakage current between the source and the drain is reduced, thus effectively reducing the off-state current of the device.
[0052] The source electrode 130 includes a first substructure 132 flush with the channel layer 150 on one side (left side in the drawing) and a second substructure 133 on the first substructure 132. The first substructure 132 and the second substructure 133 are distinguished for the purpose of illustrating the device structure, and the boundary between the two is indicated by a dashed line in the drawing. The drain electrode 140 includes a third substructure 142 flush with the channel layer 150 on the other side (right side in the drawing) and a fourth substructure 143 on the third substructure 142. The third substructure 142 and the fourth substructure 143 are distinguished for the purpose of illustrating the device structure, and the boundary between the two is indicated by a dashed line in the drawing. Of course, if the length of the channel layer 150 is determined to be equal to the device length, the sidewall of the channel layer 150 can be flush with the sidewall of the device, and the first substructure 132 and the third substructure 142 do not need to be provided.
[0053] Specifically, the difference between the first size and the second size can be in a linear relationship with the second size, so that the difference varies linearly according to the second size, which is conducive to controlling the gate length. For example, the difference can be the product of the difference between a preset size and the second size and a preset value, the preset size is denoted as c, the preset value is denoted as a, the difference is denoted as Δx, the first size is denoted as x1, and the second size is denoted as x2. Then Δx = a(c-x2) = a*c-a*x2, x1 = x2+Δx = (1-a)*x2+a*c. The preset size is in the range of 20-60 nm, and the preset value is in the range of 0.1-3.
[0054] In this way, the difference between the first size and the second size can be determined when the gate length is less than the preset length, and the difference is a positive value at this time, satisfying the constraint condition that the first size is greater than the second size. When the gate length is greater than the preset length, the calculated difference is a negative value, which does not satisfy the constraint condition that the first size is greater than the second size, and therefore the gate length can be equal to the channel length. The smaller the preset size is set, the larger the preset value can be set, so that the channel length can be effectively increased. For example, when the preset size is in the range of 20-30 nm, the preset value is in the range of 1-3, and when the preset size is in the range of 40-60 nm, the preset value is in the range of 0.1-0.8.
[0055] For example, the preset size can be 50 nm, and the preset value can be 0.5. In this way, when the gate length (second size) is 15 nm, the difference is 17.5, i.e., the channel length (first size) is 32.5 nm, and when the gate length (second size) is 20 nm, the difference is 15, i.e., the channel length (first size) is 35 nm. Simulation shows that the channel sizes corresponding to the two gate sizes can achieve optimal results.
[0056] In addition, if the calculated channel length is less than 20 nm, it can be set to 20 nm.
[0057] In this way, when the difference between the first size and the second size is less than 2 times the side wall, the side wall of the channel can extend below the side wall, as shown in FIG. 2A; when the difference between the first size and the second size is equal to 2 times the side wall, the side wall of the channel layer can be flush with the outer side wall of the side wall, as shown in FIG. 2B; and when the difference between the first size and the second size is greater than 2 times the side wall, the side wall of the channel layer can extend beyond the side wall, as shown in FIG. 2C. When the total size of the device is small, the channel layer can extend to the entire device, as shown in FIG. 2D. Figure 3 Figure 4 Figure 5 Figure 6
[0058] FIG. 3 shows a sub-threshold swing provided by an embodiment of the present application, as shown in FIG. 3A, and a drain-induced barrier lowering provided by an embodiment of the present application, as shown in FIG. 3B. Figure 7 Figure 8 As shown in FIG. 3B, when the gate length is equal to the channel length, the sub-threshold swing and the drain-induced barrier lowering increase significantly when the gate length is reduced to less than 60 nm, and both increase significantly when the gate length is reduced to less than 20 nm, and the ability to resist short channel effects is rapidly degraded, and the performance of the device is severely degraded. Therefore, it is reasonable to set the aforementioned preset size range.
[0059] For example, when the gate length is 15 nm, a plurality of channel sizes can be set, such as 15 nm, 20 nm, 36 nm, 45 nm, and 75 nm, as shown in FIG. 4A, and a schematic diagram of the on-state current provided by an embodiment of the present application is shown in FIG. 4B, and a schematic diagram of the sub-threshold swing provided by an embodiment of the present application is shown in FIG. 4C, and a schematic diagram of the drain-induced barrier lowering provided by an embodiment of the present application is shown in FIG. 4D. Figure 9 Figure 10 Figure 11 As shown in FIG. 4D, when the channel length is greater than 15 nm and less than 60 nm, the on-state current is improved, and the sub-threshold swing and the drain-induced barrier lowering are effectively reduced. When the channel length is 36 nm, the on-state current is the largest. This is because when the channel length is small, the on-state current is small due to the influence of the short channel effect, and when the channel length is large, the influence of the gate electric field on the edge position of the channel layer is reduced, and the series resistance between the source and the drain is large, so the on-state current is small. That is, the channel expansion within the appropriate range effectively enhances the ability of the transistor to suppress the short channel effect.
[0060] FIG. 5 shows a schematic diagram of the on-state current provided by an embodiment of the present application, as shown in FIG. 5A, and a schematic diagram of the sub-threshold swing provided by an embodiment of the present application, as shown in FIG. 5B. Figure 12 Figure 13 As shown, the carrier concentration distribution diagram provided by the embodiment of the application, the different colors in the source, drain and channel are used to indicate the electron density (eDensity), and it can be seen from the diagram that when the channel layer is not extended, the carriers mainly gather in the channel layer and the area close to the sidewall of the source and drain, and after the channel layer is extended, the carriers under the sidewall and the source and drain obtain higher mobility, thereby compensating for the negative influence caused by the increase of the effective channel length. Figure 13 In the embodiment, the electric field from the drain only affects the PN junction between the channel and the drain, and it is difficult to affect the channel part under the gate, so that the channel part under the gate has a uniform electric field distribution, the carrier mobility is improved, and the influence of the increase of the effective channel length on the channel resistance is compensated, and the on-state current of the device is greatly increased.
[0061] The application provides a transistor structure with extended channel, which extends the channel area to the sidewall by controlling the diffusion of source and drain impurities, and does not need to change the size of the transistor, does not additionally increase the manufacturing cost, is easy to implement, can effectively improve the short channel effect suppression capability, greatly improves the on-state current, can meet various application scenarios, has high market demand, and has high economic benefits.
[0062] The application provides a manufacturing method of a semiconductor device, a buried oxygen layer and a channel layer are sequentially stacked on a substrate, a gate is formed on the channel layer, a source is in contact with one end of the channel layer, and a drain is in contact with the other end of the channel layer. The first size of the channel layer in a first direction along the surface of the substrate is greater than the second size of the gate in the first direction, the difference between the first size and the second size is negatively related to the second size, and the first direction is the connection direction of the source and the drain. That is, the length of the channel layer is greater than the length of the gate, and the greater the length of the gate, the smaller the length difference between the two, so that the channel layer and the gate are closer, and the decrease amplitude of the channel layer is smaller with the decrease of the length of the gate, thereby facilitating the suppression of the short channel effect. For the case that the length of the gate is large, the length of the channel layer is close to that of the gate, thereby avoiding the problem of excessive series resistance caused by the excessive length of the channel layer, and therefore the short channel effect suppression capability is effectively provided, and a large on-state current is ensured.
[0063] The above only describes the preferred embodiments of the application, and although the application has been disclosed as above with the preferred embodiments, it is not intended to limit the application. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the application or modify equivalent embodiments without departing from the scope of the technical solutions of the application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application without departing from the content of the technical solutions of the application still belongs to the protection scope of the technical solutions of the application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which a buried oxide layer and a trench layer are sequentially stacked; Form the gate on the channel layer; The first dimension of the channel layer in a first direction along the surface of the substrate is larger than the second dimension of the gate in the first direction. The difference between the first dimension and the second dimension is determined based on the second dimension and is negatively correlated with the second dimension. A source electrode is formed that contacts one end of the channel layer, and a drain electrode is formed that contacts the other end of the channel layer, wherein the first direction is the direction of the line connecting the source electrode and the drain electrode.
2. The method according to claim 1, characterized in that, The difference is linearly related to the second dimension.
3. The method according to claim 2, characterized in that, The difference is the product of the difference between the preset size and the second size and the preset value. The preset size ranges from 20 to 60 nm, and the preset value ranges from 0.1 to 3.
4. The method according to claim 3, characterized in that, The preset size ranges from 20 to 30 nm, and the preset value ranges from 1 to 3.
5. The method according to claim 3, characterized in that, The preset size ranges from 40 to 60 nm, and the preset value ranges from 0.1 to 0.
8.
6. The method according to claim 5, characterized in that, The preset size is 50nm, and the preset value is 0.
5.
7. The method according to any one of claims 1-6, characterized in that, The thickness of the buried oxide layer is 15 nm, and the channel layer material is silicon with a thickness of 5 nm.
8. The method according to any one of claims 1-6, characterized in that, The source electrode includes a first substructure flush with the channel layer on one side and a second substructure on the first substructure, and the drain electrode includes a third substructure flush with the channel layer on the other side and a fourth substructure on the third substructure.
9. The method according to any one of claims 1-6, characterized in that, Also includes: A gate dielectric layer is formed between the gate and the channel layer.
10. The method according to any one of claims 1-6, characterized in that, Also includes: The sidewalls that form the gate sidewalls.