Preparation method of P-GaN gate enhanced GaN HEMT

Abstract

The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a preparation method of a P-GaN gate enhanced GaN HEMT (High Electron Mobility Transistor), which comprises the following steps of: sequentially growing a nucleating layer, a cache layer, a channel layer, a barrier layer and a P-type GaN layer on a substrate; forming active region isolation of the device through photoetching and etching processes; photoetching a source electrode region and a drain electrode region, etching to remove the P-type GaN layer in the regions, and depositing and annealing to form N-type ohmic contact; photoetching a P-type ohmic region, reserving a part of the P-type GaN layer on the drain side, etching to remove the rest part, and depositing and annealing to form P-type ohmic contact; photoetching a gate region, and depositing and annealing to form Schottky gate metal; and performing plasma passivation treatment on the P-type GaN between the gate source and the gate drain by taking the gate metal and the P-type ohmic metal as masks, and annealing in a nitrogen atmosphere to convert the P-type GaN into high-resistance GaN. According to the invention, the phenomenon that the device cannot be positively conducted under low drain electrode voltage can be effectively avoided.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, specifically relating to a method for preparing a P-GaN gate-enhanced GaN HEMT. Background Technology

[0002] With the rapid development of new energy industries such as solar and wind power, power electronic devices play a crucial role in these fields. The power electronic device industry is paying more attention to the environmental performance of its products, and the research and development and production of low-energy-consumption, high-efficiency, and environmentally friendly power electronic devices have become an important development direction for the industry. The working principle of GaN HEMT (Gallium Nitride High Electron Mobility Transistor) is based on the two-dimensional electron gas (2DEG) generated at the heterojunction interface formed by AlGaN and GaN. Unlike traditional silicon-based MOSFETs, GaN HEMTs do not have a PN junction, and therefore lack body diode characteristics, making it impossible to achieve reverse current flow. Although this characteristic is advantageous in some applications, it becomes a limiting factor in circuits that require bidirectional blocking capability (such as T-type inverters, matrix inverters, etc.). Reverse blocking capability is of great significance to power electronic systems: First, it prevents current from flowing in the opposite direction, thus protecting the circuit from damage, especially when the power supply polarity is reversed or abnormal voltage occurs in the circuit; second, reverse blocking capability can reduce energy loss caused by reverse current and improve system efficiency; third, in high-power applications, reverse blocking capability can prevent device damage caused by reverse breakdown and enhance system reliability; finally, devices with reverse blocking capability can reduce the need for external diodes, simplify circuit design, reduce parasitic inductance, and reduce space requirements and costs.

[0003] Problems with existing technology: In existing technologies, to achieve the reverse blocking capability of GaN HEMTs, a p-GaN gate and a hybrid p-GaN ohmic drain structure are typically used. A portion of the p-type GaN layer is retained on the drain side and connected to the drain via an ohmic contact. However, this structure has a serious technical defect: when the device is operating in the forward conduction state (Vds > 0) and the drain voltage is low, the p-type GaN layer retained on the drain side depletes the two-dimensional electron gas below, causing the device to fail to conduct normally. When current needs to flow from the drain to the source, the holes in the drain p-type GaN must be depleted first to restore the two-dimensional electron gas below in order to form a conductive channel. This process causes an additional threshold voltage in the output characteristics of the device, making it unable to conduct normally at low drain voltages (usually below a few volts). This problem seriously affects the logic function of the overall circuit and may lead to abnormal circuit operation, additional power consumption, or even system failure in practical applications. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a P-GaN gate-enhanced GaN HEMT. It proposes a method for fabricating P-GaN with a hybrid ohmic drain and ion passivation of P-GaN except for the area below the gate and drain, which can effectively avoid the phenomenon that the device cannot conduct forward at low drain voltage.

[0005] The specific technical solution adopted by this invention is as follows: A method for fabricating a P-GaN gate-enhanced GaN HEMT includes the following steps: A core layer, a buffer layer, a channel layer, a barrier layer, and a P-type GaN layer are sequentially grown on the substrate. The active region of the device is isolated through photolithography and etching processes; The source and drain regions are lithographically defined, the P-type GaN layer in these regions is etched away, and an N-type ohmic contact is deposited and annealed. The P-type ohmic region is photolithographically etched out, a portion of the P-type GaN layer is retained on the drain side, the remaining portion is etched away, and a P-type ohmic contact is formed by deposition and annealing. The gate region is photolithographically etched, and Schottky gate metal is deposited and annealed to form it. Using gate metal and P-type ohmic metal as masks, the P-type GaN between the gate source and gate drain is subjected to plasma passivation treatment and then annealed in a nitrogen atmosphere to transform it into high-resistivity GaN.

[0006] According to another aspect of the present invention, after obtaining the substrate, it is ultrasonically cleaned with acetone, isoacetone and deionized water respectively, and then placed in MOCVD to sequentially grow a 100nm nucleation layer, a 2μm AlGaN stress control layer, a 300nm high-resistivity GaN layer, a 300nm GaN channel layer, a 20nm AlGaN barrier layer and a 70nm P-type GaN layer.

[0007] According to another aspect of the present invention, forming active region isolation of a device includes the following steps: Spin coating was performed on the wafer using a spin coater at a speed of 4000 rpm for 30 seconds. Perform soft baking, setting the hot plate temperature to 95℃ and the time to 90s; Active area isolation exposure; The exposed sample was placed in the developing solution for development, and then rinsed repeatedly with ultrapure water and dried with nitrogen gas. Mesa etching isolation was performed using an ICP etching device, with an etching depth of 500 nm; Remove the mask by ultrasonic cleaning with acetone solution for 3 minutes, then ultrasonic cleaning with isopropanol solution for 5 minutes, then rinse repeatedly with ultrapure water, and finally dry with nitrogen gas.

[0008] According to another aspect of the present invention, forming an N-type ohmic contact includes the following steps: Spin coating was performed on the wafer using a spin coater at a speed of 4000 rpm for 30 seconds. Perform soft baking, with the hot plate set to 50℃ for 90 seconds; Expose the ohmic region; The exposed sample was placed in the developing solution for development, rinsed repeatedly with ultrapure water and dried with nitrogen gas. The P-type GaN layer in the source and drain regions was etched away using an ICP etching device. Placed in an electron beam evaporation stage, four metal layers of Ti / Al / Ni / Au are sequentially deposited in the source and drain regions not covered by photoresist. After the metal is vapor-deposited, it is stripped off and the stripped sample is placed in a rapid annealing furnace for rapid annealing under nitrogen atmosphere, temperature of 850℃ and time of 30s to form an N-type ohmic contact.

[0009] According to another aspect of the present invention, forming a P-type ohmic contact includes the following steps: Spin coating was performed on the wafer using a spin coater at a speed of 4000 rpm for 30 seconds. Perform soft baking, with the hot plate set to 50℃ for 90 seconds; Perform exposure in the P-type ohmic region; The exposed sample was placed in the developing solution for development, rinsed repeatedly with ultrapure water and dried with nitrogen gas. The drain P-type GaN layer was etched using an ICP etching device, while retaining a 20-30nm thick P-type GaN layer. Place it in an electron beam evaporation stage, and sequentially deposit two metal layers of Ni / Au in the area not covered by photoresist; After the metal is vapor-deposited, it is stripped off and the stripped sample is placed in a rapid annealing furnace for rapid annealing under oxygen atmosphere, temperature of 550℃ and time of 5min to form a P-type ohmic contact.

[0010] According to another aspect of the present invention, forming a Schottky gate metal includes the following steps: Spin coating was performed on the wafer using a spin coater at a speed of 3000 rpm for 30 seconds. Perform soft baking, with the hot plate set to 90℃ for 100 seconds; Expose the gate region; The exposed sample was placed in the developing solution for development, rinsed repeatedly with ultrapure water and dried with nitrogen gas. The photolithographically etched sample is placed in an electron beam evaporation stage, and two metal layers, Ni and Au, are sequentially deposited in the gate region not covered by photoresist. The material is stripped to form the Schottky gate metal.

[0011] According to another aspect of the present invention, the method for converting to high-resistivity GaN includes the following steps: Using gate metal and P-type ohmic metal as a masking film; The sample was placed in an ICP device, and the P-type GaN between the gate source and gate drain was treated with N2 plasma at a power of 100W for 5 minutes. Annealing at 350℃ under a nitrogen atmosphere for 5 minutes transforms the P-type GaN in the treated region into high-resistivity GaN.

[0012] According to another aspect of the present invention, a P-GaN gate enhancement GaN HEMT includes: Substrate; A nucleation layer, a buffer layer, a channel layer, a barrier layer, and a p-type GaN layer are sequentially disposed on the substrate; Schottky gate metal disposed on the P-type GaN layer; Source N-type ohmic contact and drain N-type ohmic contact are disposed on the barrier layer and located on both sides of the Schottky gate metal; A P-type ohmic contact is disposed on the P-type GaN region on the drain N-type ohmic contact side; The P-type GaN region between the gate source and the gate drain is plasma passivated to form a high-resistivity GaN layer.

[0013] According to another aspect of the present invention, a power conversion system includes an input power supply, an output load, and a power switching device, wherein the power switching device is a P-GaN gate enhancement type GaN HEMT as described above.

[0014] According to another aspect of the present invention, a matrix inverter includes a plurality of P-GaN gate enhancement type GaN HEMTs as described above, for implementing bidirectional blocking functionality.

[0015] The technical effects achieved by this invention are as follows: This invention, to prevent the device from failing to conduct under low drain forward voltage, uses plasma to passivate the p-type GaN between the gate and drain. Two-dimensional hole gas is used to connect the p-type GaN below the gate to the p-type GaN at the drain. The gate controls the p-type GaN below the drain; applying a voltage to the gate re-enables the channel below the drain P-GaN. Etching removes a portion of the P-GaN, increasing the gate's control over the P-GaN below the drain. This achieves normal device conduction even under low positive drain voltage.

[0016] This invention retains a portion of P-type GaN at the drain end and connects it to the drain using a P-type ohmic contact. The p-GaN between the gate and source, and between the gate and drain, is passivated using plasma. When the device is in reverse, Vd is less than Vs. Because the P-GaN retained at the drain end depletes the two-dimensional electron gas below, the device cannot conduct normally, thus achieving the reverse blocking function of the device.

[0017] This invention uses plasma to passivate the P-GaN between the gate and source / drain. A two-dimensional electron gas in the high-resistivity GaN connects the P-GaN under the gate with the P-GaN retained under drain ohms, giving the gate some control over the P-GaN below the drain. When the device is under a low positive drain voltage, applying a voltage to the gate restores the two-dimensional electron gas below the drain P-GaN, etching away part of the P-GaN and increasing the gate's control over the P-GaN below the drain. This achieves normal device conduction even under low positive drain voltage conditions. Attached Figure Description

[0018] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is a schematic diagram of the substrate structure in this invention; Figure 3 This is a schematic diagram of the structure after step S1 is completed in this invention; Figure 4 This is a schematic diagram of the structure after steps S2 and S3 are completed in this invention; Figure 5 This is a schematic diagram of the structure after step S4 is completed in this invention; Figure 6 This is a schematic diagram of the structure after step S5 is completed in this invention; Figure 7 This is a schematic diagram of the structure after step S6 is completed in this invention. Detailed Implementation

[0019] To make the objectives and advantages of this invention clearer, the invention will be specifically described below with reference to embodiments. It should be understood that the following text is merely used to describe one or more specific embodiments of the invention and does not strictly limit the scope of protection specifically claimed by the invention.

[0020] It should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] According to an embodiment of the present invention, a method embodiment for fabricating a P-GaN gate-enhanced GaN HEMT is provided. It should be noted that, although the logical order is shown in the flowchart of the accompanying drawings, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0022] like Figure 1 As shown, a method for fabricating a P-GaN gate-enhanced GaN HEMT includes the following steps: S1. A core layer, a buffer layer, a channel layer, a barrier layer, and a P-type GaN layer are sequentially grown on the substrate. S2. The active region of the device is isolated through photolithography and etching processes; S3. Photolithography is used to create the source and drain regions, the P-type GaN layer in these regions is etched away, and N-type ohmic contacts are deposited and annealed. S4. Photolithography is used to create a P-type ohmic region. A portion of the P-type GaN layer is retained on the drain side. The remaining portion is etched away. P-type ohmic contact is deposited and annealed. S5. Photolithography is used to create the gate region, followed by deposition and annealing to form the Schottky gate metal; S6. Using the gate metal and P-type ohmic metal as masks, the P-type GaN between the gate source and gate drain is subjected to plasma passivation treatment and then annealed in a nitrogen atmosphere to transform it into high-resistivity GaN.

[0023] The above steps are based on reference Figure 2-7 The preparation and molding steps; In step S1, refer to Figure 2First, a silicon (Si) substrate is obtained and ultrasonically cleaned with acetone, isopropanol, and deionized water, respectively. Then, it is placed in an MOCVD device to grow a 100nm nucleation layer, a 2μm AlGaN stress control layer, a 300nm high-resistivity GaN layer, a 300nm GaN channel layer, a 20nm AlGaN barrier layer, and a 70nm P-type GaN layer in sequence. The P-type GaN layer is the key layer for gate control, and its thickness and doping concentration directly affect the threshold voltage and conduction characteristics of the device.

[0024] In step S2, refer to Figure 3 Spin-coating was performed on the wafer using a spin coater at 4000 rpm for 30 seconds. This was followed by soft baking at 95°C for 90 seconds. The baked wafer underwent active area isolation exposure. The exposed sample was then developed in a developer solution, repeatedly rinsed with ultrapure water, and dried with nitrogen. After photolithography and development, the wafer underwent mesa etching isolation using an ICP etching system to a depth of 500 nm. Following etching, the mask was removed by ultrasonic cleaning with acetone solution for 3 minutes, followed by ultrasonic cleaning with isopropanol solution for 5 minutes, repeated rinsing with ultrapure water, and finally drying with nitrogen. Active area isolation ensures electrical isolation between devices and prevents leakage current.

[0025] In step S3, refer to Figure 4 Spin-coating was performed on the wafer using a spin coater at 4000 rpm for 30 seconds. Soft baking was then performed at 50°C for 90 seconds. The ohmic regions were then exposed. The exposed sample was developed in a developer solution, repeatedly rinsed with ultrapure water, and dried with nitrogen. The P-type GaN layers in the source and drain regions were etched away using an ICP etching system. The wafer was then placed in an electron beam evaporation stage, where four metal layers (Ti / Al / Ni / Au) were sequentially deposited in the source and drain regions not covered by photoresist. After metal deposition, the wafer was stripped and placed in a rapid annealing furnace at 850°C under a nitrogen atmosphere for 30 seconds to form N-type ohmic contacts. These N-type ohmic contacts provide low-resistance source and drain electrodes, ensuring the device's conductivity.

[0026] In step S4, refer to Figure 5Spin-coating was performed on the wafer using a spin coater at 4000 rpm for 30 seconds. Soft baking was then performed at 50°C for 90 seconds. Exposure of the P-type ohmic region followed. The exposed sample was then developed in a developer solution, repeatedly rinsed with ultrapure water, and dried with nitrogen. The drain P-type GaN layer was etched using an ICP etching system, retaining a 20-30 nm thick layer of P-type GaN. The sample was then placed in an electron beam evaporation stage, where Ni / Au layers were sequentially deposited in the areas not covered by photoresist. After metal deposition, the sample was stripped and placed in a rapid annealing furnace at 550°C in an oxygen atmosphere for 5 minutes to form a P-type ohmic contact. The P-type GaN layer retained on the drain side is crucial for achieving reverse blocking. When Vds is less than 0 volts, the P-type GaN depletes the underlying two-dimensional electron gas, blocking current flow and achieving reverse blocking.

[0027] In step S5, refer to Figure 6 Spin-coating the wafer using a spin coater at 3000 rpm for 30 seconds; soft baking at 90°C for 100 seconds; exposure of the gate region; development of the exposed sample in a developer solution, repeated rinsing with ultrapure water, and drying with nitrogen; placing the photolithographically etched sample in an electron beam evaporation stage, where Ni / Au layers are sequentially deposited on the gate region not covered by photoresist; lift-off to form the Schottky gate metal. The Schottky gate metal forms a Schottky contact with the P-type GaN layer, and the enhancement-mode operation of the device is achieved by controlling the two-dimensional electron gas beneath the P-type GaN layer through the gate voltage.

[0028] In step S6, refer to Figure 7 Using gate metal and P-type ohmic metal as masking films, the sample was placed in an ICP device, and the P-type GaN between the gate source and gate drain was treated with N2 plasma at a power of 100W for 5 minutes. Subsequently, it was annealed at 350℃ in a nitrogen atmosphere for 5 minutes to transform the P-type GaN in the treated area into high-resistivity GaN. This innovative step is key to solving the problem of low drain voltage failure in existing technologies. The high-resistivity GaN layer formed by plasma passivation utilizes the two-dimensional hole gas within it to connect the P-type GaN below the gate to the P-type GaN at the drain, allowing the gate to control the state of the P-type GaN below the drain. When a voltage is applied to the gate, the two-dimensional electron gas below the drain P-GaN can be restored, thereby enabling normal conduction of the device under low forward drain voltage.

[0029] Based on the above steps, by retaining a portion of the P-type GaN layer on the drain side and forming a P-type ohmic contact, when Vds is less than 0 volts, the P-type GaN will deplete the two-dimensional electron gas below, blocking the current flow, thus realizing the reverse blocking function of the device and solving the problem of GaN HEMT lacking reverse blocking capability.

[0030] Furthermore, by using a high-resistivity GaN layer formed through plasma passivation, the state of the P-type GaN below the drain can be controlled by the gate. When a voltage is applied to the gate, the two-dimensional electron gas below the drain P-GaN can be restored, thereby enabling the device to conduct normally under low forward drain voltage, solving the problem of the inability to conduct under low drain voltage in the prior art.

[0031] Furthermore, using plasma passivation technology to replace the traditional dry etching process can avoid physical damage and chemical contamination to the material caused by the etching process, significantly reduce the device interface state density, and improve the device reliability and thermal stability. By precisely controlling the retention thickness of the P-type GaN layer and the passivation process parameters, the threshold voltage and on-resistance of the device can be optimized, thereby improving the overall performance of the device.

[0032] A P-GaN gate-enhanced GaN HEMT includes a substrate, and a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-type GaN layer are sequentially disposed on the substrate. Schottky gate metal disposed on the P-type GaN layer; Source N-type ohmic contact and drain N-type ohmic contact are disposed on the barrier layer and located on both sides of the Schottky gate metal; A P-type ohmic contact is disposed on the P-type GaN region on the drain N-type ohmic contact side; The P-type GaN region between the gate source and the gate drain is plasma passivated to form a high-resistivity GaN layer.

[0033] As in this embodiment and Figure 7 As shown, the P-GaN HEMT device of this embodiment includes, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode S, a drain electrode D, and a p-type GaN on the drain side above the barrier layer. Between the drain-side p-type GaN and the source electrode, there is a high-resistivity GaN and a p-type GaN after plasma passivation. Above the p-type GaN is a gate Schottky metal G, and a certain thickness of drain-side p-type GaN is retained. Above the p-type GaN is a p-type ohmic contact connected to the drain electrode.

[0034] Compared to conventional Schottky P-GaN enhancement-mode HEMT devices: Since HEMTs form conductive channels through the electron gas at the second position of an AlGaN / GaN heterojunction, unlike the PN junctions in traditional bipolar transistors (BJTs) or MOSFETs, HEMTs do not have a PN junction structure and therefore do not possess body diode characteristics, thus lacking reverse recovery charge.

[0035] Unlike common HEMTs, this embodiment retains a portion of P-type GaN at the drain end and connects it to the drain using a P-type ohmic contact. The p-GaN between the gate and source, and between the gate and drain, is passivated using plasma. When the device is in reverse, Vd is less than Vs. Because the P-GaN retained at the drain depletes the two-dimensional electron gas below, the device cannot conduct normally, thus achieving the reverse blocking function of the device.

[0036] Furthermore, compared to conventional hybrid drain enhancement-mode HEMT devices (p-GaN RB-HEMT) with reverse blocking capability: Enhancement-mode HEMT devices with a p-GaN gate and a hybrid p-GaN ohmic drain retain a portion of the p-type GaN at the drain, which is connected to the drain via an ohmic contact. The p-GaN between the gate and source, and between the gate and drain, is removed using dry etching. Because the p-GaN on the drain side depletes the underlying two-dimensional electron gas, the device cannot conduct properly at low positive drain voltages. This can lead to errors in the core logic functions of the device and circuit, and generate additional power losses.

[0037] This embodiment differs from the above in that it uses plasma to passivate the P-GaN between the gate-source and gate-drain. The two-dimensional electron gas in the high-resistivity GaN connects the P-GaN under the gate with the P-GaN retained under the drain ohm, giving the gate some control over the P-GaN below the drain. When the device is under a low positive drain voltage, applying a voltage to the gate restores the two-dimensional electron gas below the drain P-GaN, etching away part of the P-GaN and increasing the gate's control over the P-GaN below the drain. This achieves normal device conduction even under low positive drain voltage conditions.

[0038] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0039] A power conversion system includes an input power supply, an output load, and a power switching device, wherein the power switching device is the aforementioned P-GaN gate enhancement type GaN HEMT.

[0040] A matrix inverter includes multiple P-GaN gate-enhanced GaN HEMTs as described above, for implementing bidirectional blocking functionality.

[0041] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained in this invention are implemented according to conventional methods in the art unless otherwise specified or limited.

Claims

1. A method for fabricating a P-GaN gate enhanced GaN HEMT, characterized in that, The method comprises the following steps: Growth of nucleation layer, buffer layer, channel layer, barrier layer and P-type GaN layer on the substrate in sequence; Formation of active region isolation of the device by photolithography and etching process; Photoetching of source and drain regions, etching of P-type GaN layer in the regions, deposition and annealing to form N-type ohmic contact; Photoetching of P-type ohmic region, retaining part of P-type GaN layer on the drain side, etching of the rest, deposition and annealing to form P-type ohmic contact; Photoetching of gate region, deposition and annealing to form Schottky gate metal; Plasma passivation treatment of P-type GaN between gate-source and gate-drain using gate metal and P-type ohmic metal as mask, and annealing in nitrogen atmosphere to convert it into high-resistance GaN.

2. The method of claim 1, wherein the P-GaN gate enhancement mode GaN HEMT is prepared by the steps of: After the substrate is obtained, it is ultrasonically cleaned with acetone, isopropyl ketone and deionized water, and then is placed in a MOCVD to grow 100 nm nucleation layer, 2 μm AlGaN stress control layer, 300 nm high-resistance GaN layer, 300 nm GaN channel layer, 20 nm AlGaN barrier layer and 70 nm P-type GaN layer in sequence. ​ 3. The method for fabricating a P-GaN gate-enhanced GaN HEMT according to claim 1, characterized in that: The formation of active region isolation of the device comprises the following steps: The wafer is spin-coated with glue by a glue spreader at a speed of 4000 rpm for 30 s; Soft baking is performed at a hot plate temperature of 95℃ for 90 s; Exposure of active region isolation is performed; The exposed sample is developed in a developing solution, repeatedly washed with ultrapure water and dried with nitrogen; ICP etching equipment is used to perform mesa etching isolation, and the etching depth is 500 nm; The mask is removed by ultrasonic cleaning with acetone solution for 3 min, then ultrasonic cleaning with isopropyl alcohol solution for 5 min, repeatedly washing with ultrapure water, and finally drying with nitrogen.

4. The method of claim 1, wherein the P-GaN gate enhancement mode GaN HEMT is prepared by the steps of: The formation of N-type ohmic contact comprises the following steps: The wafer is spin-coated with glue by a glue spreader at a speed of 4000 rpm for 30 s; Soft baking is performed at a hot plate temperature of 50℃ for 90 s; Exposure of ohmic region is performed; The exposed sample is developed in a developing solution, repeatedly washed with ultrapure water and dried with nitrogen; ICP etching equipment is used to etch away the P-type GaN layer in the source and drain regions; The sample is placed in an electron beam evaporation station to evaporate Ti / Al / Ni / Au four-layer metal in the source and drain regions not covered by photoresist in sequence; After the metal is evaporated, stripping is performed, and the stripped sample is placed in a rapid annealing furnace to perform rapid annealing under the conditions of nitrogen atmosphere, temperature 850℃ and time 30 s to form N-type ohmic contact.

5. The method of claim 1, wherein the P-GaN gate enhancement mode GaN HEMT is prepared by the steps of: The formation of P-type ohmic contact comprises the following steps: The wafer is spin-coated with glue by a glue spreader at a speed of 4000 rpm for 30 s; Soft baking is performed at a hot plate temperature of 50℃ for 90 s; Exposure of P-type ohmic region is performed; The exposed sample is developed in a developing solution, repeatedly washed with ultrapure water and dried with nitrogen; ICP etching equipment is used to etch the drain P-type GaN layer and retain a thickness of 20-30 nm of P-type GaN; The sample is placed in an electron beam evaporation station to evaporate Ni / Au two-layer metal in the region not covered by photoresist in sequence; After the metal is evaporated, the sample is peeled off and placed in a rapid annealing furnace for rapid annealing in an oxygen atmosphere at a temperature of 550℃ for 5 minutes to form a P-type ohmic contact.

6. The method of claim 1, wherein the P-GaN gate enhancement mode GaN HEMT is prepared by the steps of: Forming the Schottky gate metal includes the following steps: The wafer is spin-coated with a spin coater at a speed of 3000 rpm for 30 seconds. Soft baking is performed with a hot plate set at a temperature of 90℃ for 100 seconds. Exposure is performed on the gate region. The exposed sample is developed in a developing solution, repeatedly rinsed with ultrapure water and dried with nitrogen. The sample after lithography is placed in an electron beam evaporation station to evaporate Ni / Au two layers of metal on the gate region not covered by photoresist. Peeling is performed to form the Schottky gate metal.

7. The method for fabricating a P-GaN gate-enhanced GaN HEMT according to claim 1, characterized in that, The method for converting high-resistance GaN includes the following steps: The gate metal and P-type ohmic metal are used as a shielding mask; The sample is placed in an ICP device to treat the P-type GaN between the gate source and the gate drain using N2 plasma at a power of 100W for 5 minutes. Annealing is performed at 350℃ in a nitrogen atmosphere for 5 minutes to convert the P-type GaN in the treated area to high-resistance GaN.

8. A P-GaN gate enhanced GaN HEMT using the fabrication method according to any one of claims 1 to 7, characterized in that, It includes: a substrate; a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-type GaN layer arranged in sequence on the substrate; a Schottky gate metal arranged on the P-type GaN layer; a source N-type ohmic contact and a drain N-type ohmic contact arranged on the barrier layer and located on both sides of the Schottky gate metal; a P-type ohmic contact arranged on the P-type GaN region on one side of the drain N-type ohmic contact; a P-type GaN region arranged between the gate source and the gate drain, which is treated by plasma passivation to form a high-resistance GaN layer.

9. A power conversion system comprising an input power source, an output load, and a power switching device, characterized by: The power switch device is the P-GaN gate enhanced GaN HEMT of claim 8.

10. A matrix inverter, characterized by: It includes a plurality of P-GaN gate enhanced GaN HEMTs of claim 8 to realize bidirectional blocking function.

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