Semiconductor device and preparation method
By etching the structure grown in the first epitaxial growth stage in the gate-around process and performing a second epitaxial growth on the etched sidewalls, the problem of void defects in the source and drain epitaxy process is solved, thereby improving the performance of the device.
Patent Information
- Application Number
- CN202410911632.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-08
- Publication Date
- 2026-01-13
AI Technical Summary
In gate-around technology, void defects are easily formed during the epitaxial process of the source and drain, which affects device performance.
By etching the structure grown in the first epitaxial growth and then performing a second epitaxial growth on the etched sidewalls, the source and drain structures are formed, ensuring smooth sidewalls and avoiding segmented growth.
This improves the growth quality of the source and drain electrodes, ensuring the stability and reliability of device performance.
Smart Images
Figure CN121335148A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor processes, and more specifically, to a semiconductor device and a method for fabricating it. Background Technology
[0002] Gate all around (GAA) technology is a next-generation semiconductor device process. Due to its superior gate control capabilities, it can be used to replace fin field-effect transistors (FinFETs) in the sub-3nm range. However, in GAA technology, the source and drain epitaxy are performed on the sidewalls of silicon channels within a stacked layer. Since the upper and lower sidewalls of the silicon channels in the stacked layer are both insulating materials, the different materials of the sidewalls and the segmented epitaxy process make it highly susceptible to void defects during source and drain epitaxy. This affects the stress on the source and drain, leading to reduced device performance. Summary of the Invention
[0003] This application provides a semiconductor device with good source and drain growth quality, which can ensure the performance of the device.
[0004] In a first aspect, a semiconductor device is provided, comprising: a substrate 110, at least one channel layer 121, a gate structure 130, a source structure 150, and a drain structure 160, wherein the at least one channel layer 121 and the gate structure 130 are disposed on the substrate 110, wherein the gate structure 130 surrounds the channel layer 121 and forms an interlayer above and / or below the channel layer 121, and insulating materials are disposed at both ends of the interlayer; the channel layer 121 extends along a first direction parallel to the substrate 110, and the gate structure 130 extends along a second direction and crosses the channel layer 121. The channel layer 121 has a second direction parallel to the substrate 110 and perpendicular to the first direction. The length of the gate structure 130 in the second direction is greater than the width of the channel layer 121 in the second direction, and the width of the gate structure 130 in the first direction is less than the length of the channel layer 121 in the first direction. A first structure 141 and a second structure 142 are provided on both sides of the channel layer 121 in the first direction. The first structure 141 is connected to the channel layer 121, and the second structure 142 is connected to the first structure 141. The interface between the first structure 141 and the second structure 142 has a slope shape.
[0005] In this application, the source structure 150 includes a first structure 141 and a second structure 142 on one side of the channel layer 121 in a first direction, wherein an insulating material is disposed above the source structure; the drain structure 160 includes a first structure 141 and a second structure 142 on the other side of the channel layer 121 in a first direction, wherein an insulating material is disposed above the drain structure.
[0006] The semiconductor device provided in this application grows a second structure epitaxially on the sidewall of the first structure, thereby achieving better growth quality and ensuring device performance.
[0007] In conjunction with the first aspect, in one possible implementation, in the first direction, the size of the upper surface of the first structure 141 is smaller than the size of the lower surface of the first structure 141, or the size of the upper surface of the first structure 141 is 0.
[0008] In conjunction with the first aspect, in one possible implementation, the interface between the first structure 141 and the second structure 142 is a plane, or the interface between the first structure 141 and the second structure 142 is a curved surface.
[0009] In conjunction with the first aspect, in one possible implementation, spacers 231 are provided on both sides of the gate structure 130, wherein the spacers 231 are located above the two ends of the uppermost channel layer 121 in the third direction, and the third direction is perpendicular to the substrate 110.
[0010] In conjunction with the first aspect, in one possible implementation, the first structure 141 is formed by epitaxial growth of a first epitaxial layer 140 on both sides of the etched channel layer 121 in a first direction, and the second structure 142 is formed by epitaxial growth on the side of the first structure 141 in a first direction.
[0011] In conjunction with the first aspect, in one possible implementation, a third structure 143 is disposed below the second structure 142, and the third structure 143 is formed by etching the first epitaxial layer 140.
[0012] In conjunction with the first aspect, in one possible implementation, the first structure 141 and the third structure 143 are an integral structure.
[0013] In conjunction with the first aspect, in one possible implementation, a channel isolation layer 111 is provided on the upper surface of the substrate 110, and the channel isolation layer 111 is located on both sides of the channel layer 121 in the second direction.
[0014] In conjunction with the first aspect, in one possible implementation, a bottom dielectric isolation layer 113 is provided between the substrate 110 and the bottommost channel layer 121 in the third direction, the third direction being perpendicular to the substrate 110.
[0015] In a second aspect, a method for fabricating a semiconductor device is provided, the method comprising: forming a stacked structure 120 and a dummy gate structure 230 on a substrate 110, wherein the stacked structure 120 includes a plurality of sacrificial layers 122 and at least one channel layer 121, the channel layers 121 and the sacrificial layers 122 are stacked alternately, the channel layers 121 and the sacrificial layers 122 are made of different materials, the stacked structure 120 extends along a first direction parallel to the substrate 110, insulating materials are disposed at both ends of the sacrificial layers 122 in the first direction of the stacked structure 120, and the dummy gate structure 230 extends along a second direction and crosses the stacked structure 120, the second direction being parallel to the substrate 110. A dummy gate structure 230, perpendicular to the first direction, has a length in the second direction greater than the width of the stacked structure 120 in the second direction. The width of the dummy gate structure 230 in the first direction is the same as the length of the stacked structure 120 in the first direction. A first epitaxial layer 140 is epitaxially grown on both sides of the stacked structure 120 in the first direction. The first epitaxial layer 140 is etched to form a first structure 141 on both sides of the stacked structure 120. A second structure 142 is epitaxially grown on the first direction of the first structures 141 on both sides of the stacked structure 120, wherein the interface between the first structure 141 and the second structure 142 has a slope shape. The first structure 141 and the second junction 142 on one side of the stacked structure 120 in the first direction form a source structure 150; the first structure 141 and the second structure 142 on the other side of the stacked structure 120 in the first direction form a drain structure 160. The material of the dummy gate structure 230 and the sacrificial layer 122 are replaced to form a gate structure 130.
[0016] In this application, during the growth of the source and drain structures, the structure grown in the first epitaxial growth is etched, and then a second epitaxial growth is performed on the etched sidewalls to finally obtain the source and drain structures. By etching the first epitaxial layer of the first epitaxial growth, smooth sidewalls can be obtained. On the other hand, the second epitaxial growth can be performed on the sidewalls of the entire semiconductor layer (the first epitaxial layer is a semiconductor material, so the first structure formed after etching is also a semiconductor material). This ensures that there are no voids or other defects inside the finally grown source and drain, guaranteeing the growth quality of the source and drain, and thus ensuring the characteristics of the entire device.
[0017] In conjunction with the second aspect, in one possible implementation, etching the first epitaxial layer 140 includes: etching the first epitaxial layer 140 along a third direction and at a certain angle, wherein the third direction is perpendicular to the substrate 110.
[0018] In conjunction with the second aspect, in one possible implementation, the method further includes: forming a pad layer on each side of the dummy gate structure 230 in a first direction, the pad layer serving as a mask layer, the mask layer serving to form the first structure 141 during the etching process.
[0019] In conjunction with the second aspect, in one possible implementation, replacing the materials of the dummy gate structure 230 and the sacrificial layer 122 to form the gate structure 130 includes: replacing the materials of the dummy gate structure 230 and the sacrificial layer 122 according to a high-k metal gate process to form the gate structure 130.
[0020] In conjunction with the second aspect, in one possible implementation, forming a stacked structure 120 and a dummy gate structure 230 on a substrate 110 includes: forming an initial stacked structure 220 on the substrate 110, the initial stacked structure 220 covering the entire upper surface of the substrate 110, the material of the initial stacked structure 220 being the same as the material of the stacked structure 120; etching the initial stacked structure 220 along a third direction to form a fin-shaped stacked structure 320, the fin-shaped stacked structure 320 extending along a first direction, the third direction being perpendicular to the substrate; and forming a dummy gate structure 230 on the fin-shaped stacked structure 320 and the substrate 110, wherein the dummy gate structure 230... The gate structure 230 extends along the second direction and crosses the fin-shaped stacked structure 320. The length of the dummy gate structure 230 in the second direction is greater than the width of the fin-shaped stacked structure 320 in the second direction. The width of the dummy gate structure 230 in the first direction is less than the length of the fin-shaped stacked structure 320 in the first direction. The exposed portion of the fin-shaped stacked structure 320 in the first direction is etched along a third direction to form a stacked structure 120. The width of the stacked structure 120 in the second direction is less than the length of the dummy gate structure 230 in the second direction. The length of the stacked structure 120 in the first direction is the same as the width of the dummy gate structure 230 in the first direction.
[0021] In conjunction with the second aspect, in one possible implementation, in the first direction, the size of the upper surface of the first structure 141 is smaller than the size of the lower surface of the first structure 141, or the size of the upper surface of the first structure 141 is larger than the size of the lower surface of the first structure 141.
[0022] In conjunction with the second aspect, in one possible implementation, the interface between the first structure 141 and the second structure 142 is a plane, or the interface between the first structure 141 and the second structure 142 is a curved surface.
[0023] In conjunction with the second aspect, in one possible implementation, the first structure 141 is formed by epitaxial growth of a first epitaxial layer 140 on both sides of the etched channel layer 121 in a first direction, and the second structure 142 is formed by epitaxial growth on the side of the first structure 141 in a first direction.
[0024] In conjunction with the first aspect, in one possible implementation, a third structure 143 is disposed below the second structure 142, and the third structure 143 is formed by etching the first epitaxial layer 140.
[0025] In conjunction with the first aspect, in one possible implementation, the first structure 141 and the third structure 143 are an integral structure.
[0026] Thirdly, a chip is provided. The chip includes a semiconductor device as described in the first aspect or any possible implementation thereof. Alternatively, the semiconductor device in the chip is fabricated using the method described in the second aspect or any possible implementation thereof.
[0027] Fourthly, an electronic device is provided. This electronic device includes the chip described in the third aspect. Attached Figure Description
[0028] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 100 provided in this application in a first direction.
[0029] Figure 2 This is another schematic diagram of a cross-section of a semiconductor device 100 provided in this application in a first direction.
[0030] Figure 3 This is a schematic flowchart of a semiconductor device fabrication method 300 provided in this application.
[0031] Figure 4 This is a cross-sectional schematic diagram of the structure formed after step 301 in the semiconductor device fabrication method 300 provided in this application in the first direction.
[0032] Figure 5 This is a cross-sectional schematic diagram of the structure formed after step 302 in the semiconductor device fabrication method 300 provided in this application, in the first and second directions.
[0033] Figure 6 This is a cross-sectional schematic diagram of the structure formed after step 303 in the semiconductor device fabrication method 300 provided in this application, in the first and second directions.
[0034] Figure 7 This is a cross-sectional schematic diagram of the structure formed after step 304 in the semiconductor device fabrication method 300 provided in this application, in the first and second directions.
[0035] Figure 8 This is a cross-sectional schematic diagram of the structure formed after step 305 in the semiconductor device fabrication method 300 provided in this application in the first direction.
[0036] Figure 9 This is a cross-sectional schematic diagram of the structure formed after step 306 in a semiconductor device fabrication method 300 provided in this application in the first direction.
[0037] Figure 10 This is a cross-sectional schematic diagram of the structure formed after step 307 in a semiconductor device fabrication method 300 provided in this application in the first direction.
[0038] Figure 11 This is a cross-sectional schematic diagram of the structure formed after step 308 in the semiconductor device fabrication method 300 provided in this application in the first direction.
[0039] Figure 12 This is a cross-sectional schematic diagram of the structure formed after step 309 in the semiconductor device fabrication method 300 provided in this application in the first direction.
[0040] Figure 13 This is a cross-sectional schematic diagram of the structure formed after step 310 in the semiconductor device fabrication method 300 provided in this application in the first direction. Detailed Implementation
[0041] The technical solutions in this application will now be described with reference to the accompanying drawings.
[0042] Gate all around (GAA) technology is a next-generation semiconductor device process. Due to its superior gate control capabilities, it can be used to replace fin field-effect transistors (FinFETs) in the sub-3nm range. However, in GAA technology, the source and drain epitaxy are performed on the sidewalls of silicon channels (i.e., silicon nanolayers) within a stacked layer. Since the sidewalls of the upper and lower layers of the silicon channels are both insulating materials, the different materials of the sidewalls and the segmented epitaxy make it easy for void defects to form during the source and drain epitaxy process. This affects the stress on the source and drain, leading to a decrease in device performance.
[0043] Figure 1 This illustration shows a cross-sectional view of a semiconductor device structure 100 provided in this application in a first direction (which can also be understood as a sectional view cut along the first direction; the remaining cross-sectional views of this application can be understood with reference to the description herein), as shown. Figure 1 As shown, device 100 includes a substrate 110, at least one channel layer 121, a gate structure 130, a source structure 150, and a drain structure 160.
[0044] The substrate 110 in this application may be, for example, a silicon substrate. In this application, a channel isolation layer 111 is provided on the upper surface of the substrate 110. The channel isolation layer 111 is located on both sides of the channel layer 121 in the second direction and is used for channel isolation.
[0045] Optionally, in some embodiments, a bottom dielectric isolation (BDI) layer 113 is disposed between the substrate 110 and the bottommost channel layer 121 in a third direction (the third direction is perpendicular to the substrate). Figure 1 (Not shown in the image), the bottom dielectric isolation layer 113 is used to reduce channel layer current leakage and parasitic capacitance. For example, the material of the bottom dielectric isolation layer 113 can be SiO2, SiCN, SiON, or SiN.
[0046] In this application, the substrate 110 and the channel isolation layer 111 on the substrate 110 are collectively referred to as substrate 110.
[0047] In this application, the gate structure 130 surrounds the channel layer 121 and forms an interlayer above and / or below the channel layer 121, with insulating materials (e.g., SiN, SiCN, low-k dielectric materials, etc.) disposed at both ends of the interlayer. Figure 1 As can be seen, the channel layer 121 surrounds the gate on all four sides. This channel layer 121 extends along a first direction, which is parallel to the substrate 110.
[0048] In this application, the gate structure 130 extends along a second direction and across the channel layer 121, wherein the second direction is parallel to the substrate 110 and perpendicular to the first direction, and the gate structure 130 is perpendicular to the channel layer 121 (e.g., along the second direction and perpendicular to the first direction). In this application, the length of the gate structure 130 in the second direction is greater than the width of the channel layer 121 in the second direction, and the width of the gate structure 130 in the first direction is less than the length of the channel layer 121 in the first direction.
[0049] For example, the material of the gate structure 130 can be a high-k dielectric material. For example, the high-k dielectric material can include, for instance, doped or undoped hafnium oxide (HfO2), hafnium silicate-based materials, or other suitable dielectrics with a k-value greater than 3.9. Specifically, the process of forming the gate structure 130 can refer to existing high-k metal gate (HKMG) processes or alternative gate processes.
[0050] In this application, spacers 231 are disposed on both sides of the gate structure 130, wherein the spacers 231 are located above the two ends of the uppermost channel layer 121 in the third direction. The spacers 231 are used to help determine the final gate length and facilitate gate replacement processing. In some embodiments, the spacers 231 comprise any dielectric material, such as oxides (e.g., silicon dioxide), nitrides (e.g., silicon nitride), high-k dielectrics, low-k dielectrics, etc.
[0051] from Figure 1 As can be seen, all four sides of the channel layer 121 are surrounded by high-k dielectric material, which helps to further reduce leakage current and increase drive current compared with the fin field-effect transistor (Fin FET) structure.
[0052] In this application, a first structure 141 and a second structure 142 are provided on both sides of the channel layer 121 in the first direction. The first structure 141 is connected to the channel layer 121, and the second structure 142 is connected to the first structure 141. The interface between the first structure 141 and the second structure 142 presents a slope shape.
[0053] In one possible implementation, the upper surface of the first structure 141 formed after etching is smaller than the lower surface of the first structure 141. In this case, a trapezoidal shape is formed in the cross-section in the first direction, such as... Figure 1 As shown. For example, the lower surface of the first structure 141 has an angle of approximately 75° to 88° with the inclined plane ("inclined plane" can also be understood as "side plane").
[0054] In another possible implementation, the dimension of the upper surface of the first structure 141 is 0, in which case the cross-section in the first direction forms a triangle, such as... Figure 2 As shown in (a) above. For example, the lower surface of the first structure 141 has an angle of approximately 75° to 88° with the inclined plane.
[0055] In another possible implementation, the inclined surface of the first structure 141 is approximately a straight line; this can also be understood as the side surface of the first structure 141 being planar. Figure 1 and Figure 2 As shown in (a); in another implementation, the inclined surface of the first structure 141 has a certain curvature, which can also be understood as the side of the first structure 141 in the first direction being a curved surface, such as Figure 2 As shown in (b) and (c) in the figure.
[0056] It should be noted that in this application, the side surface (i.e., inclined surface) of the first structure 141 in the first direction has a smooth surface.
[0057] In this application, the gate structure 130 is further provided with spacers 231 on both sides of the first direction. The spacers 231 are used to help determine the final gate length and facilitate gate replacement processing. In some embodiments, the spacers 231 comprise any dielectric material, such as oxides (e.g., silicon dioxide), nitrides (e.g., silicon nitride), high-k dielectrics, low-k dielectrics, etc.
[0058] In this application, the source structure 150 includes a first structure 141 and a second structure 142 on one side of the channel layer 121 in the first direction; the drain structure 160 includes a first structure 141 and a second structure 142 on the other side of the channel layer 121 in the first direction. That is, the source structure 150 and the drain structure 160 are located on both sides of the channel layer 121 in the first direction, and each of the source structure 150 and the drain structure 160 includes a first structure 141 formed after etching and a second structure 142 subsequently grown epitaxially (the second structure 142 can also be understood as a second epitaxial layer 142).
[0059] In some embodiments, a third structure 143 is disposed below the second structure 142. For example, the first structure 141 and the third structure 143 are an integral structure. Figure 2 As shown in (d) in the figure.
[0060] In this application, the first structure 141 and the third structure 143 are made of the same material, both formed by etching the first epitaxial layer 140 grown on both sides of the channel layer 121 in the first direction. For example, etching the first epitaxial layer 140 can form the first structure 141 and the third structure 143.
[0061] In this application, the method for growing the first epitaxial layer 140 can follow existing schemes, and this application does not limit it.
[0062] Optionally, the source structure 150 further includes a third structure 143. Optionally, the drain structure 160 further includes a third structure 143.
[0063] For example, in this application, during the first epitaxial growth, a first epitaxial layer 140 can be grown on both sides of the channel layer 121. After etching, a first structure 141 (optionally, a third structure 143) can be formed on both sides of the channel layer 121. Then, a second epitaxial growth can be performed on the side of the first structure 141 in the first direction, thereby forming a second structure 142 on the first structure 141 on both sides.
[0064] Alternatively, in this application, the first structure 141 is connected to the channel layer 121, and the second structure 142 is connected to the first structure 141, with the interface between the first structure 141 and the second structure 142 exhibiting a sloping shape. In some embodiments, the interface between the first structure 141 and the second structure 142 is planar; in other embodiments, the interface between the first structure 141 and the second structure 142 is curved.
[0065] For example, in this application, the source structure 150 and the drain structure 160 can be epitaxially grown using materials with a concentration gradient. For instance, the first epitaxial layer 140 formed during the first epitaxial growth process can be a low-concentration material (or, as can be understood, the first structure 141 and the third structure 143 formed after etching are both low-concentration materials), such as low-germanium (Ge) silicon-germanium (SiGe); the second epitaxial layer 142 formed during the second epitaxial growth process can be a high-concentration material (or, as can be understood, the second structure 142 is a high-concentration material), such as high-germanium (Ge) silicon-germanium (SiGe).
[0066] For example, in this application, insulating materials are respectively disposed above the source structure 150 and the drain structure 160.
[0067] Figure 3 This is a schematic flowchart of a method 300 for fabricating a semiconductor device as shown in this application. The following is in conjunction with... Figure 3 as well as Figures 4-13 The fabrication process of the semiconductor device structure provided in this application will be described in detail.
[0068] 301, forming an initial stacked structure on the substrate.
[0069] In this application, substrate 110 may be, for example, a silicon substrate.
[0070] In one possible implementation, alternating plurality of sacrificial layers 122 and at least one channel layer 121, the sacrificial layers 122 and the channel layer 121 being made of different materials, can be directly formed on the substrate 110. For example, there can be multiple sets of sacrificial layers 122 and channel layers 121, thereby constituting an initial stacked structure 220. The initial stacked structure 220 covers the entire upper surface of the substrate 110, such as... Figure 4 As shown in (a) in the figure.
[0071] In another possible implementation, a bottom dielectric isolation sacrificial layer 112 can first be grown on the substrate 110, and then an initial stacked structure 220 can be grown on the bottom dielectric isolation sacrificial layer 112, as shown in the figure. Figure 4 As shown in (b) of the diagram.
[0072] For example, the sacrificial layer 122 is silicon-germanium (SiGe), and the channel layer 121 is silicon (Si). Exemplarily, the sacrificial layer 122 and the channel layer 121 can be nanosheet structures or nanowire structures. In some embodiments, when the width of the sacrificial layer 122 and the channel layer 121 along the second direction differs from their height along the third direction (e.g., when the width is greater than or less than their height), it can be understood as a "nanosheet structure." In some embodiments, when the width of the sacrificial layer 122 and the channel layer 121 along the second direction is substantially equal to their height along the third direction, it can be understood as a "nanowire structure." The thickness of the sacrificial layer 122 and the channel layer 121 in the initial stacked structure 220 can be flexibly designed by those skilled in the art and is not limited.
[0073] For example, the initial stacked structure 220 can be grown on the substrate 110 by a chemical vapor deposition (CVD) process.
[0074] 302. Photolithography and etching are performed on the initial stacked structure to form a fin-like stacked structure.
[0075] In this application, for example, a photoresist layer can be spin-coated onto the top layer of the initial stacked structure 220, and then photolithographically etched to form a patterned photoresist structure, and etched to form a vertical fin-like stacked structure 320, the fin-like stacked structure 320 extending along a first direction.
[0076] In this application, the fin-shaped stacked structure 320 can be understood as being formed by etching the initial stacked structure 220. The etching process in step 302 reduces the width of the initial stacked structure 220 in the second direction, thereby forming a fin structure, such as... Figure 5 As shown in (b) of the diagram.
[0077] In some embodiments, during the etching process, etching can also penetrate into the substrate 110. In this case, a trench isolation layer 111 can be regrown, meaning the trench isolation layer 111 is regrown on the upper surface of the etched substrate, making the height of the trench isolation layer 111 the same as the thickness of the unetched substrate. This can also be understood as filling the etched portion of the substrate by growing the trench isolation layer 111, thus flattening the entire substrate. This trench isolation layer 111 can be used for trench isolation, such as... Figure 5 As shown in (a) and (b) in the figure.
[0078] In some embodiments, if a sacrificial layer 112 for bottom dielectric isolation is grown on the surface of the substrate 110, then after step 302, a bottom dielectric isolation layer 113 is also provided between the substrate 110 and the fin stack structure 320, such as... Figure 5 As shown in (c) in the figure.
[0079] 303, forming a pseudo-gate structure.
[0080] For example, polysilicon can be deposited in a blanket manner to cover the sides of the fin stacked structure 320 in the second direction, the upper surface of the fin stacked structure 320, and part of the upper surface of the channel isolation layer 111. Then, insulating material is deposited to form a hard mask 232 for protecting the gate in subsequent processes. Next, photolithography and etching can be performed to form multiple bump structures. Afterward, spacer material can be grown on the two sides of each bump structure in the first direction and photolithography and etching can be used to form spacers 231, which can also be understood as forming multiple dummy gate structures 230, such as... Figure 6 As shown in (a) in the figure.
[0081] The spacer 231 is used to help determine the final gate length and facilitates gate replacement processing. In some embodiments, the spacer 231 comprises any dielectric material, such as oxides (e.g., silicon dioxide), nitrides (e.g., silicon nitride), high-k dielectrics, low-k dielectrics, etc.
[0082] In this application, multiple dummy gate structures 230 can be formed in step 303. In the subsequent process, this application will use one dummy gate structure as an example (for example, the middle dummy gate structure 230). The other dummy gate structures 230 can be understood in the same way.
[0083] In this application, the dummy gate structure 230 is perpendicular to the fin-like stacked structure 320 (e.g., perpendicular to the first direction along the second direction). Typically, the length of the dummy gate structure 230 in the second direction is greater than the width of the fin-like stacked structure 320 in the second direction, and the length of the fin-like stacked structure 320 in the first direction is greater than the width of the dummy gate structure 230 in the first direction, such as... Figure 6 As shown in (b) of the diagram.
[0084] 304 is used to etch the exposed portion of the fin-like stacked structure in the first direction to form the stacked structure.
[0085] As mentioned above Figure 6 As shown, in the first direction, since the width of the dummy gate structure 230 is smaller than the length of the fin-like stacked structure 320, a portion of the fin-like stacked structure (e.g., the first portion and the second portion) is retained on both sides of the dummy gate structure 230 in the first direction. Therefore, the channel layer 121 and the sacrificial layer 122 on both sides of the dummy gate structure 230 can be removed by selective dry etching, wet etching, or a combination thereof, thereby forming the stacked structure 120, as shown. Figure 7 As shown in (a) and (b) in the figure.
[0086] In some embodiments, if a sacrificial layer 112 for bottom dielectric isolation is grown on the substrate 110, then after step 304, a bottom dielectric isolation layer 113 is also provided between the substrate 110 and the stacked structure 120, such as... Figure 7 As shown in (c) in the figure.
[0087] 305, the sacrificial layer in the etched stacked structure.
[0088] For example, in step 304, since the fin-like stacked structures 320 on both sides of the dummy gate structure 230 in the first direction are etched to form the stacked structure 120, the two sides of the dummy gate structure 230 are flat. Next, the exposed edges of the sacrificial layers 122 (e.g., silicon-germanium (SiGe) nanolayers) on both sides of the stacked structure 120 in the first direction can be etched laterally in the first direction, such as... Figure 8 As shown. For example, etching can be performed using a dry etching process and by selecting a material (e.g., a halogenated chemical substance) with high etching selectivity for germanium (Ge) and low etching selectivity for silicon (Si).
[0089] It should be understood that the amount of recessed etching of the sacrificial layer 122 can be flexibly controlled by those skilled in the art and is not limited.
[0090] 306, an insulating layer is formed at both ends of the sacrificial layer in the stacked structure.
[0091] For example, an insulating material can be deposited on both sides of the stacked structure 120 in the first direction using a blanket deposition method. The main purpose of step 306 is to fill the two ends of the etched sacrificial layer 122 in the stacked structure 120, so that both ends of the sacrificial layer 122 are filled with insulating material, such as... Figure 9 As shown. Then, the insulating material other than the insulating layer at both ends of the sacrificial layer 122 in the stacked structure 120 is removed. For example, the insulating layer on the upper surface of the substrate 110, the side of the channel layer 121 in the first direction, the two sides of the dummy gate structure 230 in the first direction, and the upper surface can be removed by dry etching and / or wet etching.
[0092] Alternatively, the stacked structure 120 at this time can be understood as including a sacrificial layer 122 and a channel layer 121, wherein insulating material is provided at both ends of the sacrificial layer 122, and the material of the middle part of the sacrificial layer 122 is still silicon germanium (SiGe).
[0093] 307, the epitaxial layer is grown for the first time on both sides of the first direction of the stacked structure.
[0094] For example, a silicon-germanium (SiGe) epitaxial layer with a germanium concentration gradient can be epitaxially grown on the channel layers 121 on both sides of the first direction of the stacked structure 120 to form a first epitaxial layer 140, such as...Figure 10 As shown. For example, the germanium (Ge) concentration can be gradually increased from 0 (when the germanium concentration is 0, the epitaxial layer can be understood as silicon). Specifically, the thickness of the first epitaxial layer can be flexibly controlled by those skilled in the art.
[0095] 308, etch the epitaxial layer grown for the first time to form the first structure after etching.
[0096] In one possible implementation of this application, the epitaxial layer grown in the first stage can be directly etched along a third direction (the third direction is perpendicular to the substrate). During etching, an etching angle can be formed, thereby forming a first structure 141 with a "slope structure". See [reference needed]. Figure 11 The first structure 141 shown or as Figure 2 The first structure 141 is shown. In another possible implementation, a spacer of a certain thickness can be formed on both sides of the dummy gate structure 230 in the first direction by in-situ growth. During subsequent etching, the spacer acts as a mask, and the first structure 141 with a "slope structure" can also be formed after etching.
[0097] In one possible implementation, the upper surface of the first structure 141 formed after etching is smaller than the lower surface of the first structure 141. In this case, a trapezoidal shape is formed in the cross-section in the first direction, such as... Figure 2 As shown. For example, the lower surface of the first structure 141 has an angle of approximately 75° to 88° with the inclined plane ("inclined plane" can also be understood as "side plane").
[0098] In another possible implementation, the dimension of the upper surface of the first structure 141 is 0, such as... Figure 2 As shown in (a), the cross-section in the first direction forms a triangle. For example, the angle between the lower surface of the first structure 141 and the inclined plane is approximately 75° to 88°.
[0099] In another possible implementation, the inclined surface of the first structure 141 is approximately a straight line; this can also be understood as the side surface of the first structure 141 being planar. Figure 1 and Figure 2 As shown in (a); in another implementation, the inclined surface of the first structure 141 has a certain curvature, which can also be understood as the side of the first structure 141 in the first direction being a curved surface, such as Figure 2 As shown in (b) and (c) in the figure.
[0100] In some embodiments, by controlling the etching depth during etching, a third structure 143 can also be formed, such as... Figure 11 (b) andFigure 2 As shown in (d) in the diagram. For example, in this case, the first structure 141 and the third structure 143 are integrated.
[0101] It should be noted that in this application, the side surface (i.e., inclined surface) of the first structure 141 in the first direction can be a smooth surface.
[0102] 309. An epitaxial layer is grown a second time on the side of the first structure after etching to form the second structure.
[0103] In this application, after etching the first epitaxial layer to form the first structure 141, epitaxial growth continues on the side of the first structure 141 in the first direction to form the second structure 142, as shown below. Figure 12 As shown. For example, compared to the first epitaxial growth, the second epitaxial growth can use silicon germanium (SiGe) with a relatively high germanium (Ge) concentration to form the second structure 142.
[0104] In this application, the interface between the first structure 141 and the second structure 142 is sloping.
[0105] In one possible implementation, the interface between the first structure 141 and the second structure 142 is a plane, or the interface between the first structure 141 and the second structure 142 is a curved surface.
[0106] It should be noted that in this application, the source structure 150 and the drain structure 160 are formed by two epitaxial growth processes. The source structure 150 includes a first structure 141 and a second structure 142, and the drain structure 160 includes a first structure 141 and a second structure 142.
[0107] In some embodiments, the source structure 150 further includes a third structure 143, and the drain structure 160 also includes a third structure 143.
[0108] 310, forming a gate structure.
[0109] In this application, after step 309, the following steps may be included: removing the material between the spacers 231 and the hard mask 232 on both sides of the dummy gate structure 230, removing the material in the middle portion of the sacrificial layer 122 in the stacked structure 120 (note: the insulating material at both ends of the sacrificial layer 122 needs to be retained), depositing high-K dielectric material above and below the channel layer 121 (i.e., replacing the silicon-germanium (SiGe) material in the original sacrificial layer 122 with high-K dielectric material), and depositing high-K dielectric material between the spacers 231 and the hard mask 232 on both sides, thereby forming the gate structure 130 (wherein, the main material of the gate structure 130 includes high-K dielectric material), this process may also be called "HKMG process". At this time, the dummy gate structure 230 is replaced by the gate structure 130. In some embodiments, insulating material may also be deposited above the source structure and the drain structure, such as Figure 13 As shown in the image. Then, the entire top of the device is ground (e.g., by chemical mechanical polishing (CMP)) to remove the hard mask layer, planarize the top of the device, and reduce the device height (i.e., reduce the device size), as shown. Figure 1 As shown.
[0110] As mentioned earlier, in the existing scheme, when forming the source and drain, silicon germanium (SiGe) with a gradually varying germanium concentration is epitaxially grown on the channel layer 121 in the stacked structure 120. Since the two ends of the sacrificial layer 122 are insulating materials and not semiconductor materials, the epitaxial growth is equivalent to segmented epitaxial growth (i.e., epitaxial growth can only be performed on the sidewalls of the channel layer 121). At this time, the growth morphology presents a bulging shape, so the final source and drain growth quality is poor and defects are easy to exist.
[0111] However, in this application, when growing the source structure 150 and drain structure 160, the structure grown in the first epitaxial growth is etched, and then a second epitaxial growth is performed on the etched sidewalls to finally obtain the source structure 150 and drain structure 160. By etching the first epitaxial layer 140 of the first epitaxial growth, smooth sidewalls can be obtained, and the second epitaxial growth can be performed on the sidewalls of the first structure formed after etching, avoiding segmented growth. This ensures that there are no voids or other defects inside the finally grown source and drain, guaranteeing the growth quality of the source and drain, and thus ensuring the characteristics of the entire device.
[0112] This application embodiment may also provide a chip. The chip includes, for example... Figure 1 , Figure 2 , Figures 4 to 13 The semiconductor device shown. Or the semiconductor device in this chip is made of, for example, Figure 3 Prepared using the method described in [the document / reference].
[0113] This application embodiment can also provide an electronic device. This electronic device includes the aforementioned chip.
[0114] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: The structure comprises a substrate (110), at least one channel layer (121), a gate structure (130), a source structure (150), and a drain structure (160), wherein... The at least one channel layer (121) and the gate structure (130) are disposed on the substrate (110), wherein the gate structure (130) surrounds the channel layer (121) and forms an interlayer above and / or below the channel layer (121), the two ends of the interlayer are provided with insulating material, the channel layer (121) extends along a first direction parallel to the substrate (110), the gate structure (130) extends along a second direction and crosses the channel layer (121), the second direction is parallel to the substrate (110) and perpendicular to the first direction, the length of the gate structure (130) in the second direction is greater than the width of the channel layer (121) in the second direction, and the width of the gate structure (130) in the first direction is less than the length of the channel layer (121) in the first direction; The channel layer (121) has a first structure (141) and a second structure (142) on both sides in the first direction. The first structure (141) is connected to the channel layer (121), and the second structure (142) is connected to the first structure (141). The interface between the first structure (141) and the second structure (142) is sloping. The source structure (150) includes a first structure (141) and a second structure (142) on one side of the channel layer (121) in the first direction, wherein an insulating material is disposed above the source structure; The drain structure (160) includes a first structure (141) and a second structure (142) on the other side of the first direction of the channel layer (121), wherein an insulating material is disposed above the drain structure.
2. The device according to claim 1, characterized in that, In the first direction, the size of the upper surface of the first structure (141) is smaller than the size of the lower surface of the first structure (141), or the size of the upper surface of the first structure (141) is 0.
3. The device according to claim 1 or 2, characterized in that, The interface between the first structure (141) and the second structure (142) is a plane, or the interface between the first structure (141) and the second structure (142) is a curved surface.
4. The device according to any one of claims 1 to 3, characterized in that, Spacers (231) are provided on both sides of the gate structure (130), wherein the spacers (231) are above the two ends of the uppermost channel layer (121) in the third direction, and the third direction is perpendicular to the substrate (110).
5. The device according to any one of claims 1 to 4, characterized in that, The first structure (141) is formed by etching the first epitaxial layer (140) on both sides of the first direction of the channel layer (121) and the second structure (142) is formed by epitaxial growth on the side of the first structure (141) in the first direction.
6. The device according to claim 5, characterized in that, A third structure (143) is disposed below the second structure (142), and the third structure (143) is formed by etching the first epitaxial layer (140).
7. The device according to claim 6, characterized in that, The first structure (141) and the third structure (143) are an integral structure.
8. The device according to any one of claims 1 to 7, characterized in that, A channel isolation layer (111) is provided on the upper surface of the substrate (110), and the channel isolation layer (111) is located on both sides of the channel layer (121) in the second direction.
9. The device according to any one of claims 1 to 8, characterized in that, A bottom dielectric isolation layer (113) is provided between the substrate (110) and the channel layer (121) at the bottom in the third direction, the third direction being perpendicular to the substrate (110).
10. A method for fabricating a semiconductor device, characterized in that, include: A stacked structure (120) and a dummy gate structure (230) are formed on a substrate (110). The stacked structure (120) includes a plurality of sacrificial layers (122) and at least one channel layer (121), wherein the channel layer (121) and the sacrificial layer (122) are stacked alternately, and the channel layer (121) and the sacrificial layer (122) are made of different materials. The stacked structure (120) extends along a first direction parallel to the substrate (110). The sacrificial layers of the stacked structure (120) are... Insulating material is provided at both ends of (122) in the first direction. The dummy gate structure (230) extends along the second direction and crosses the stacked structure (120). The substrate (110) is parallel to and perpendicular to the first direction in the second direction. The length of the dummy gate structure (230) in the second direction is greater than the width of the stacked structure (120) in the second direction. The width of the dummy gate structure (230) in the first direction is the same as the length of the stacked structure (120) in the first direction. A first epitaxial layer (140) is epitaxially grown on both sides of the stacked structure (120) in the first direction; The first epitaxial layer (140) is etched so that a first structure (141) is formed on both sides of the stacked structure (120); A second structure (142) is epitaxially grown on the first direction of the first structure (141) on both sides of the stacked structure (120), wherein the interface between the first structure (141) and the second structure (142) presents a slope shape. In this stacked structure (120), the first structure (141) and the second structure (142) on one side of the first direction form a source structure (150). The first structure (141) and the second structure (142) on the other side of the first direction of the stacked structure (120) form a drain structure (160); The materials of the dummy gate structure (230) and the sacrificial layer (122) are replaced to form the gate structure (130).
11. The method according to claim 10, characterized in that, The etching of the first epitaxial layer (140) includes: The first epitaxial layer (140) is etched along a third direction and at a certain angle, wherein the third direction is perpendicular to the substrate (110).
12. The method according to claim 10 or 11, characterized in that, The method further includes: A pad layer is formed on each side of the dummy gate structure (230) in the first direction, the pad layer serving as a mask layer for forming the first structure (141) during the etching process.
13. The method according to claim 12, characterized in that, Replacing the materials of the dummy gate structure (230) and the sacrificial layer (122) to form the gate structure (130) includes: The gate structure (130) is formed by replacing the material of the dummy gate structure (230) and the material of the sacrificial layer (122) according to the high-k metal gate process.
14. The method according to any one of claims 10 to 13, characterized in that, The formation of the stacked structure (120) and the dummy gate structure (230) on the substrate (110) includes: An initial stacked structure (220) is formed on the substrate (110), the initial stacked structure (220) covering the entire upper surface of the substrate (110), and the material of the initial stacked structure (220) is the same as that of the stacked structure (120); The initial stacked structure (220) is etched along a third direction to form a fin-shaped stacked structure (320), which extends along the first direction and the third direction is perpendicular to the substrate (110). The dummy gate structure (230) is formed on the fin stack structure (320) and the substrate (110), wherein the dummy gate structure (230) extends along the second direction and crosses the fin stack structure (320), the length of the dummy gate structure (230) in the second direction is greater than the width of the fin stack structure (320) in the second direction, and the width of the dummy gate structure (230) in the first direction is less than the length of the fin stack structure (320) in the first direction; The exposed portion of the fin-shaped stacked structure (320) in the first direction is etched along the third direction to form the stacked structure (120). The width of the stacked structure (120) in the second direction is less than the length of the dummy gate structure (120) in the second direction. The length of the stacked structure (120) in the first direction is the same as the width of the dummy gate structure (120) in the first direction.
15. The method according to any one of claims 10 to 14, characterized in that, In the first direction, the size of the upper surface of the first structure (141) is smaller than the size of the lower surface of the first structure (141), or the size of the upper surface of the first structure (141) is 0.
16. The method according to any one of claims 10 to 15, characterized in that, The interface between the first structure (141) and the second structure (142) is a plane, or the interface between the first structure (141) and the second structure (142) is a curved surface.
17. The method according to any one of claims 10 to 16, characterized in that, The first structure (141) is formed by etching the first epitaxial layer (140) on both sides of the first direction of the channel layer (121) and the second structure (142) is formed by epitaxial growth on the side of the first structure (141) in the first direction.
18. The method according to any one of claims 10 to 17, characterized in that, A third structure (143) is disposed below the second structure (142), and the third structure (143) is formed by etching the first epitaxial layer (140).
19. The method according to claim 18, characterized in that, The first structure (141) and the third structure (143) are an integral structure.
20. A chip, characterized in that, The semiconductor device includes any one of claims 1 to 9, or the semiconductor device in the chip is prepared by any one of claims 10 to 19.
21. An electronic device, characterized in that, Includes the chip as described in claim 20.