TOPcon battery structure with ultrathin intrinsic amorphous silicon and preparation method

Abstract

The invention discloses a TOPcon battery structure with ultrathin intrinsic amorphous silicon and a preparation method, and relates to the technical field of battery preparation, the battery structure comprises a silicon substrate, the front surface of the silicon substrate is sequentially laminated with an ultrathin intrinsic amorphous silicon layer, an aluminum oxide film layer and a first silicon nitride film layer from inside to outside, a tunneling oxide layer, a doped polycrystalline silicon layer and a second silicon nitride film layer are sequentially stacked on the back face of the silicon substrate from inside to outside, metal grid lines are arranged on the surface of the first silicon nitride film layer and the surface of the second silicon nitride film layer respectively, and the tunneling oxide layer is a silicon dioxide layer. According to the method, the ultrathin intrinsic amorphous silicon layer is introduced, the passivation and contact functions are achieved, the contact resistance can be reduced, the filling factor and efficiency can be improved, compared with the traditional technology, an amorphous silicon deposition procedure is added between RCA cleaning and ALD deposition, implementation is easy on the basis of an existing production line, and good application prospects are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of battery preparation, and in particular to a TOPcon battery structure with ultrathin intrinsic amorphous silicon and a preparation method. BACKGROUND

[0002] At present, the mainstream technical route in the field of battery preparation is to prepare a tunneling silicon oxide and intrinsic amorphous silicon by low-pressure chemical vapor deposition, and then to form a back passivation contact structure through annealing. The existing TOPCon battery is a battery structure obtained by depositing an aluminum oxide film on a P+ emitter by an ALD process to perform surface passivation, and then plating a passivation film or an anti-reflection film on the front and back surfaces, and forming electrodes by screen printing and sintering, wherein the core is a passivation contact structure formed by a tunneling oxide layer and a doped polysilicon layer on the back surface, which effectively reduces the recombination loss of carriers and improves the open-circuit voltage and conversion efficiency of the battery.

[0003] However, in the front surface structure of the battery, the TOPCon battery utilizes aluminum oxide for passivation, and when the front surface is metallized, the paste completely penetrates the aluminum oxide to form an ohmic contact with the silicon substrate. With the increasing requirement for battery efficiency, the sheet resistance of the front emitter is continuously increasing, and the doping concentration is correspondingly decreasing. Although this is beneficial to reducing the recombination rate on the front surface, it also leads to poor surface contact, affecting the fill factor and efficiency. Therefore, a specific paste or an optimized sintering process is usually required, which in turn increases the process complexity and production cost.

[0004] Based on this, the present application provides a TOPcon battery structure with ultrathin intrinsic amorphous silicon and a preparation method, which can eliminate the drawbacks of the prior art. SUMMARY

[0005] The present application aims to provide a TOPcon battery structure with ultrathin intrinsic amorphous silicon and a preparation method to solve the problem of being unable to maintain good passivation effect while achieving low-resistance front surface metal contact in the background art.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical solutions: A TOPcon battery structure with ultrathin intrinsic amorphous silicon, comprising a silicon substrate, wherein the front surface of the silicon substrate is sequentially stacked from inside to outside with an ultrathin intrinsic amorphous silicon layer, an aluminum oxide film layer, and a first silicon nitride film layer, the back surface of the silicon substrate is sequentially stacked from inside to outside with a tunneling oxide layer, a doped polysilicon layer, and a second silicon nitride film layer, the surfaces of the first and second silicon nitride film layers are respectively provided with metal grid lines, the thickness of the ultrathin intrinsic amorphous silicon layer is 3-5 nm, and the tunneling oxide layer is a silicon dioxide layer.

[0007] Preferably, the metal grid lines include front surface grid lines and back surface grid lines, the front surface grid lines are Ag-Al grid lines, and the back surface grid lines are Ag grid lines.

[0008] A method for fabricating a TOPcon solar cell structure with ultrathin intrinsic amorphous silicon specifically includes the following steps: Step S1: Etch the N-type crystalline silicon to form a light-trapping textured surface structure; Step S2: Place the texturized silicon wafer into the diffusion furnace, use boron trichloride as the boron source to perform impurity diffusion, form a P-type emitter on the front side of the silicon wafer, and construct a PN junction cell structure. Step S3: Remove the borosilicate glass layer on the back of the silicon wafer and polish the back side; Step S4: A tunneling oxide layer is formed on the back side of the silicon wafer using a high-temperature oxidation process, and then an intrinsic amorphous silicon layer is deposited on the surface of the tunneling oxide layer. Step S5: Place the silicon wafer processed in step S4 into the annealing furnace and perform high-temperature annealing on the intrinsic amorphous silicon layer to crystallize the intrinsic amorphous silicon layer and form a doped polycrystalline silicon layer. Step S6: Remove the borosilicate glass layer, phosphosilicate glass layer, and residual impurities from the silicon wafer; Step S7: Using PECVD process, deposit an ultrathin intrinsic amorphous silicon layer on the surface of the P-type emitter on the front side of the silicon wafer. Step S8: Using the ALD process, deposit an aluminum oxide film on the surface of the ultrathin intrinsic amorphous silicon layer; Step S9: Using PECVD process, deposit a first silicon nitride film layer on the surface of the alumina film layer and a second silicon nitride film layer on the surface of the doped polycrystalline silicon layer. Step S10: Print metal grid lines on the surfaces of the first silicon nitride film and the second silicon nitride film respectively, and then perform a sintering operation in a high-temperature sintering furnace to make the metal grid lines form an ohmic contact with the film structure. After sintering, the final N-type crystalline silicon solar cell structure is obtained.

[0009] Preferably, step S1 uses a chain cleaning device. Step S1 specifically includes: cleaning the silicon wafer with a mixed solution of HCl and H2O2 at room temperature for 8 minutes, then rinsing it with deionized water, placing the rinsed silicon wafer in a solution containing NaOH, pre-etching it at 75°C for 4 minutes, texturing the silicon wafer in the NaOH solution at 88°C for 15 minutes, after which a 3µm pyramidal textured surface is formed on the silicon wafer, treating the silicon wafer with HF solution at room temperature for 2 minutes to remove the oxide layer, then treating the silicon wafer with HCl solution at room temperature for 5 minutes to remove metal ions, and finally drying the silicon wafer with hot air.

[0010] Preferably, the diffusion furnace in step S2 is a tube-type furnace. Step S2 specifically includes: placing the silicon wafer processed in step S1 into the tube-type furnace, evacuating and heating it to 950°C, introducing a boron source into the tube-type furnace, reacting for 15 minutes to form a high-concentration borosilicate glass layer on the surface of the silicon wafer, stopping the introduction of the boron source, adjusting the internal temperature of the tube-type furnace to 1000°C, maintaining it for 25 minutes of diffusion time to obtain a PN junction, and removing the silicon wafer after the tube-type furnace has cooled down.

[0011] Preferably, step S4 uses a PECVD tubular equipment. Step S4 specifically includes: feeding the alkaline-polished silicon wafer into the PECVD tubular equipment, evacuating and heating it to 420~450℃, then introducing N2O gas into the tubular furnace equipment, ionizing it for 160s to form a tunneling oxide layer on the back of the silicon wafer, keeping the temperature constant, introducing a mixture of SIH4, H2, and PH3 into the PECVD tubular equipment and reacting it for 500s to deposit an intrinsic amorphous silicon layer on the surface of the tunneling oxide layer, introducing N2 gas into the PECVD tubular equipment to restore the pressure inside the equipment to normal, and then removing the silicon wafer.

[0012] Preferably, step S5 uses a tubular annealing furnace. Step S5 specifically includes: placing the silicon wafer processed in step S4 into the tubular annealing furnace, evacuating and heating it to 800°C, then introducing N2 gas into the tubular annealing furnace for annealing treatment at a temperature of 840°C to 880°C for 8000 seconds, then introducing N2 gas into the tubular annealing furnace to restore atmospheric pressure inside the furnace, and finally removing the silicon wafer.

[0013] Preferably, step S7 uses a PECVD tubular equipment. Step S7 specifically includes: placing the silicon wafer processed in step S6 inside the PECVD tubular equipment, adjusting the temperature to 400~500℃, and introducing N2 gas into the PECVD tubular equipment for purging. The purging flow rate of the N2 gas is 10000 sccm, and the purging time is 15s. After purging, introducing SIH4 gas into the PECVD tubular equipment for ionization. The flow rate of the SIH4 gas is 2500~3500 sccm, the ionization time is 10~20s, the process pressure is 2100~3100pa, and the RF power is 10000~15000W. After ionization, an ultrathin intrinsic amorphous silicon layer with a thickness of 3~5nm is deposited on the surface of the silicon wafer. After deposition, N2 gas is introduced again for purging. After breaking the vacuum, the silicon wafer is removed.

[0014] Preferably, step S8 uses an ALD atomic deposition equipment. Step S8 specifically includes: placing the silicon wafer processed in step S7 into the ALD atomic deposition equipment, evacuating and heating it to 220~270°C, pre-watering the surface of the silicon wafer for 10 seconds, and then alternately introducing TMA and H2O for 34 cycles with a cycle interval of 37 seconds, so as to deposit an aluminum oxide film layer on the surface of the ultrathin intrinsic amorphous silicon layer. After the deposition is completed, the vacuum is broken to restore the pressure inside the equipment to normal, and the silicon wafer is taken out.

[0015] Preferably, step S9 uses a plasma PECVD equipment. Step S9 specifically includes: placing the silicon wafer processed in step S8 inside the plasma PECVD equipment, evacuating and heating it to 520~540℃, then introducing a mixed special gas of SIH4, NH3 and N2O3 into the plasma PECVD equipment for a reaction of 30 minutes, and then removing the silicon wafer after breaking the vacuum.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention introduces an ultrathin intrinsic amorphous silicon layer on the front-side P-type emitter of a TOPCon battery, which serves both passivation and contact functions. On one hand, the ultrathin intrinsic amorphous silicon layer provides excellent hydrogen passivation to the silicon surface through its abundant Si-H bonds, effectively reducing the surface recombination rate and increasing the open-circuit voltage. On the other hand, during the subsequent metallization sintering process, the Al element in the slurry can induce the amorphous silicon in the contact area to crystallize into p-type polycrystalline silicon, forming a contact region with a high doping concentration, reducing contact resistance, and improving the fill factor and efficiency. Furthermore, this invention can optimize the PECVD deposition process parameters, ensuring optical transmittance while also improving electrical performance. Compared with the traditional structure that only uses alumina passivation, this invention adds an amorphous silicon deposition process between RCA cleaning and ALD deposition, which is easy to implement on existing production lines and has good application prospects. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the TOPcon battery structure of the present invention.

[0018] Figure 2 This is a schematic diagram of the overall process of the preparation method of the present invention.

[0019] Figure reference numerals: silicon substrate 10, ultrathin intrinsic amorphous silicon layer 20, aluminum oxide film layer 30, first silicon nitride film layer 40, tunneling oxide layer 50, doped polycrystalline silicon layer 60, second silicon nitride film layer 70. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0021] Example 1 In this embodiment, as Figure 1 As shown, a TOPcon cell structure with ultrathin intrinsic amorphous silicon is disclosed. The TOPcon cell is a tunnel oxide passivated contact cell, including a silicon substrate 10. On the front side of the silicon substrate 10, an ultrathin intrinsic amorphous silicon layer 20, an aluminum oxide film layer 30, and a first silicon nitride film layer 40 are stacked sequentially from the inside to the outside. On the back side of the silicon substrate 10, a tunnel oxide layer 50, a doped polycrystalline silicon layer 60, and a second silicon nitride film layer 70 are stacked sequentially from the inside to the outside. Metal grid lines are respectively provided on the surfaces of the first silicon nitride film layer 40 and the second silicon nitride film layer 70. The thickness of the ultrathin intrinsic amorphous silicon layer 20 is 3~5nm, and the tunnel oxide layer 50 is a silicon dioxide layer. Among them, such as Figure 1 As shown, the metal gate line includes a front gate line and a back gate line. The front gate line is an Ag-Al gate line and the back gate line is an Ag gate line. The metal gate line forms a metal silicide in the contact area with the ultrathin intrinsic amorphous silicon layer 20, and the ultrathin intrinsic amorphous silicon layer 20 in the contact area is transformed into a p-poly layer (p-type doped polycrystalline silicon) under the induction of metal Al.

[0022] like Figure 2 As shown, a method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon specifically includes the following steps: Step S1: Etch the N-type crystalline silicon to form a light-trapping textured surface structure; Furthermore, step S1 employs a chain cleaning device, which is existing technology. Its specific structure and principle will not be elaborated further here. Step S1 specifically includes: cleaning the silicon wafer with a mixed solution of HCl and H2O2 at room temperature for 8 minutes, followed by rinsing with deionized water. The rinsed silicon wafer is then placed in a solution containing NaOH and pre-etched at 75°C for 4 minutes. The silicon wafer is then texturized in the NaOH solution at 88°C for 15 minutes, resulting in a 3µm pyramidal textured surface. The silicon wafer is then treated with HF solution at room temperature for 2 minutes to remove the oxide layer, followed by HCl solution at room temperature for 5 minutes to remove metal ions. Finally, the silicon wafer is dried using hot air equipment. The principle of this step is to utilize the different etching rates of the various anisotropic surfaces in the monocrystalline silicon wafer caused by strong alkali to form a pyramidal textured surface. This utilizes the light-trapping effect to increase light absorption and simultaneously increase the surface area of ​​the silicon wafer, facilitating the removal of dirt and damage, thereby reducing composite material buildup and improving efficiency. Step S2: Place the texturized silicon wafer into the diffusion furnace, use boron trichloride as the boron source to perform impurity diffusion, form a P-type emitter on the front side of the silicon wafer, and construct a PN junction cell structure. Furthermore, the diffusion furnace in step S2 is a tube-type furnace, which is existing technology. Step S2 specifically includes: placing the silicon wafer processed in step S1 into the tube-type furnace, evacuating and heating it to 950°C, then introducing a boron source into the tube-type furnace and reacting for 15 minutes to form a high-concentration borosilicate glass layer on the surface of the silicon wafer. The boron source is then stopped, and the internal temperature of the tube-type furnace is adjusted to 1000°C and maintained for 25 minutes to obtain a PN junction. After the tube-type furnace cools down, the silicon wafer is removed. The principle of this step is to utilize the decomposition of boron trichloride (BCl3) at high temperature and its reaction with Si to generate elemental boron (B), which diffuses into the silicon (Si) substrate 10 to form a PN junction. Step S3: Remove the borosilicate glass layer on the back of the silicon wafer and polish the back side; Furthermore, step S3 employs a chain cleaning device. The principle of this step is to anisotropically etch the silicon surface with a strong alkaline solution at a certain temperature, thereby removing the damaged layer, impurities, and micro-roughness on the silicon wafer surface, making the silicon wafer surface smooth and bright. Step S3 specifically includes: placing the diffused silicon wafer into the chain cleaning device, removing the borosilicate glass (BSG) on the back and edges of the silicon wafer with an HF acid bath at room temperature, placing the silicon wafer with back acid washing into a tank device, polishing the back surface of the silicon wafer with a solution prepared by mixing tetramethylammonium hydroxide (TMAH), polishing fluid, and water, and removing the PN junction on the back and edges through etching and polishing. Since there is phosphosilicate glass (PSG) on the front of the silicon wafer, it can protect the PN junction on the front of the silicon wafer from being corroded and polished by inorganic alkali. After alkaline polishing, the phosphosilicate glass (PSG) on the front is removed with an HF solution, completing the entire etching process. Step S4: Using a high-temperature oxidation process, a tunneling oxide layer 50 is formed on the back side of the silicon wafer, and then an intrinsic amorphous silicon layer is deposited on the surface of the tunneling oxide layer 50. Furthermore, step S4 employs a PECVD tubular equipment, which is existing technology. PECVD is plasma-enhanced chemical vapor deposition. Step S4 specifically includes: feeding the alkaline-polished silicon wafer into the PECVD tubular equipment, evacuating and heating to 420~450℃, then introducing N2O gas into the tubular furnace, ionizing it for 160s to form a tunneling oxide layer 50 on the back of the silicon wafer, maintaining a constant temperature, and then introducing SIH4 and H2 into the tubular furnace. The mixture of PH3 and special gas reacts for 500 seconds, depositing an intrinsic amorphous silicon layer on the surface of the tunneling oxide layer 50. N2 gas is then introduced into the tube furnace to restore the pressure inside the equipment to normal. The silicon wafer is then removed. The principle of this step is as follows: depositing an ultrathin oxide layer on the back of the silicon wafer provides good interface passivation and provides tunneling barriers for different charge carriers. Depositing an amorphous silicon layer on the tunneling oxide layer 50 increases the electron migration rate while inhibiting the hole migration rate. In addition, the amorphous silicon contacts the metal and acts as an electron transport bridge. Step S5: Place the silicon wafer processed in step S4 into the annealing furnace and perform high-temperature annealing on the intrinsic amorphous silicon layer to crystallize the intrinsic amorphous silicon layer and form a doped polycrystalline silicon layer 60. Furthermore, step S5 employs a tubular annealing furnace, which is existing technology. Step S5 specifically includes: placing the silicon wafer processed in step S4 into the tubular annealing furnace, evacuating and heating it to 800°C, then introducing N2 gas into the PECVD tubular equipment for annealing at a temperature of 840°C to 880°C for 8000 seconds, then introducing N2 gas into the PECVD tubular equipment to restore atmospheric pressure inside the furnace, and finally removing the silicon wafer. The principle of this step is: annealing activates the doped atoms in the deposited film layer to provide charge carriers, reduces interface traps, increases charge carrier lifetime, and thus promotes crystallization. Dangling bonds at defects are replaced by saturated or recombined doped atoms, which then enter the crystal lattice to form effective donor or acceptor atoms. Step S6: Remove the borosilicate glass layer, phosphosilicate glass layer, and residual impurities from the silicon wafer; Furthermore, the RCA cleaning method is adopted. This method is an existing technology, and its specific operation and principle will not be elaborated here. Step S7: Using PECVD process, deposit an ultrathin intrinsic amorphous silicon layer 20 on the surface of the P-type emitter on the front side of the silicon wafer. Further, step S7 uses a PECVD tubular equipment, which is existing technology. Step S7 specifically includes: placing the silicon wafer processed in step S6 inside the PECVD tubular equipment, adjusting the temperature to 400~500℃, and introducing N2 gas into the PECVD tubular equipment for purging. The N2 gas purging flow rate is 10000 sccm, and the purging time is 15s. After purging, introducing SIH4 gas into the PECVD tubular equipment for ionization. The SIH4 gas flow rate is 2500~3500 sccm, the ionization time is 10~20s, the process pressure is 2100~3100pa, and the RF power is 10000~15000W. After ionization, an ultrathin intrinsic amorphous silicon layer 20 with a thickness of 3~5nm is deposited on the surface of the silicon wafer. After deposition, N2 gas is introduced again for purging. After breaking the vacuum, the silicon wafer is removed. Specifically, the difference between this embodiment and the prior art is that an additional step is added between step S6 and step S8 to deposit an ultrathin intrinsic amorphous silicon layer 20. Based on the deposition, four sets of comparative verifications are designed, namely SY1, SY2, SY3, and SY4. Among them, SY2 is the optimal efficiency group variation in SY1, SY3 is the optimal variation in SY2, and so on. Then, the optimal parameter range is obtained through multiple sets of comparative experiments and applied to the preparation method. The specific details are shown in the table below. Class is the number of silicon wafers, Eta is the conversion efficiency, Isc is the short-circuit current, Uoc is the open-circuit voltage, FF is the fill factor, Rser is the series resistance, Rshunt is the parallel resistance, and Irev3 is the leakage current under reverse bias. These are all common indicators when testing battery performance. Table 1 - Comparison of Battery Performance for SY1 Group

[0023] Specifically, with other process parameters remaining unchanged, changing the flow rate of SIH4 gas, according to Table 1 above, shows that the optimal flow rate of SIH4 gas is between 2500 and 3500 sccm. Table 2 - Comparison of Battery Performance for SY2 Group

[0024] Specifically, when the flow rate of SIH4 gas is between 2500 and 3500 sccm, 2500 sccm is preferred. The flow rate of SIH4 gas in group SY2 remains the same. With other process parameters unchanged, the process pressure is changed. According to Table 2 above, the optimal process pressure is between 2100 and 3100 Pa. Table 3 - Comparison of Battery Performance for SY3 Group

[0025] Specifically, when the flow rate of SIH4 gas is between 2500 and 3500 sccm, 2500 sccm is preferred. The flow rate of SIH4 gas in group SY3 is kept constant. When the process pressure is between 2100 and 3100 Pa, 3100 Pa is preferred. The process pressure in group SY3 is kept constant. With other process parameters unchanged, the RF power is changed. According to Table 3 above, the RF power is optimal when it is between 10000 and 15000 W. Table 4 - Comparison of Battery Performance for SY4 Group

[0026] Specifically, when the flow rate of SIH4 gas is between 2500 and 3500 sccm, preferably 2500 sccm, the flow rate of SIH4 gas in the SY4 group remains the same. When the process pressure is between 2100 and 3100 Pa, preferably 3100 Pa, the process pressure in the SY4 group remains the same. When the RF power is between 10000 and 15000 W, preferably 15000 W, the RF power in the SY4 group remains the same. With other process parameters unchanged, the ionization time is changed. According to Table 4 above, the ionization time of 10 to 20 s is optimal. Step S8: Using the ALD process, deposit an aluminum oxide film 30 on the surface of the ultrathin intrinsic amorphous silicon layer 20; Further, step S8 employs an ALD atomic deposition equipment. Step S8 specifically includes: placing the silicon wafer processed in step S7 into the ALD atomic deposition equipment, evacuating and heating it to 220~270℃, pre-watering the surface of the silicon wafer for 10s, and then alternately introducing TMA and H2O for 34 cycles with a cycle interval of 37s, so that an aluminum oxide film layer 30 is deposited on the surface of the ultrathin intrinsic amorphous silicon layer 20. After deposition, the vacuum is broken to restore the pressure inside the equipment to normal, and the silicon wafer is removed. The principle of this step is: on the back of the silicon wafer, surface passivation technology is used to passivate the back of the battery to reduce the back surface recombination rate. Aluminum oxide carries a fixed negative charge, and the negative charge is exactly at the junction of the interface between aluminum oxide and silicon oxide generated on the surface of the silicon wafer. The high density of negative charge can ensure the generation of a highly efficient field passivation effect. Step S9: Using PECVD process, a first silicon nitride film layer 40 is deposited on the surface of the alumina film layer 30, and a second silicon nitride film layer 70 is deposited on the surface of the doped polycrystalline silicon layer 60. Furthermore, step S9 employs a plasma PECVD equipment. Step S9 specifically includes: placing the silicon wafer processed in step S8 inside the plasma PECVD equipment, evacuating and heating it to 520~540℃, then introducing a mixture of special gases of SIH4, NH3, and N2O3 into the plasma PECVD equipment for a reaction of 30 minutes, and removing the silicon wafer after breaking the vacuum. The principle of this step is: using pulsed radio frequency to excite the heated rarefied gas to perform glow discharge to form plasma, and applying opposite alternating voltages to adjacent graphite sheets to accelerate the plasma between the plates and collide with the gas, moving to the surface of the silicon wafer to complete the coating process. Step S10: Metal grid lines are printed on the surfaces of the first silicon nitride film layer 40 and the second silicon nitride film layer 70, respectively. The fine grid is used to collect current, and the main grid is used to concentrate current and provide sufficient tension. Subsequently, a sintering operation is performed in a high-temperature sintering furnace. After sintering, H ions are activated to form good passivation in the non-contact area. At the same time, due to the inductive effect of Al, the amorphous silicon in the grid line contact area is transformed into p-poly (p-type doped polycrystalline silicon), forming metal silicide in the front contact area to achieve good ohmic contact, thus obtaining the final N-type crystalline silicon solar cell structure, as shown in Figure 10. Figure 1 As shown; Specifically, the existing TOPcon battery process involves cleaning the front side in step S6, followed immediately by depositing an aluminum oxide passivation film on the front side using the ALD process. This invention, however, deposits an ultrathin intrinsic amorphous silicon layer 20 before the ALD process. The principle is as follows: an ultrathin intrinsic amorphous silicon layer 20 is deposited on the front side of the TOPcon battery, and then the intrinsic amorphous silicon is used to passivate the P-type emitter of the battery, improving the passivation effect. Secondly, during the high-temperature metallization sintering process, the TOPcon front-side slurry contacts the amorphous silicon, where Al induces the amorphous silicon in the contact area to crystallize and transform into p-poly. The effective impurity concentration in p-poly is higher than that in a normal PN junction. The deposited amorphous silicon layer serves as a buffer layer for the contact between the gate line and the silicon substrate, and metal silicides are formed in the contact area to achieve better impedance matching. The ultra-thin intrinsic amorphous silicon layer 20 is a wide-bandgap amorphous silicon, which is optically transparent and does not sacrifice the incident light on the front side. The thin film contains a large number of Si-H bonds, which can provide a large amount of H passivation to the battery surface and improve the passivation effect of the battery. During the high-temperature sintering of the ultra-thin intrinsic amorphous silicon layer 20, Al in the slurry induces the amorphous silicon to undergo a crystallization transformation. Al acts as a dopant source, which transforms the amorphous silicon into p-type poly and forms metal silicides in the contact area, thereby reducing the contact resistance. This process is achieved during sintering. The amorphous silicon acts as a transition between the metal and crystalline silicon, realizing a low contact gate contact area between the metal and the junction region, which significantly reduces the contact loss on the front side. Comparative Example 1 Among them, such asFigure 1 As shown, this comparative example is the prior art. The battery structure includes a silicon substrate 10. On the front side of the silicon substrate 10, an aluminum oxide film layer 30 and a first silicon nitride film layer 40 are stacked sequentially from the inside to the outside. On the back side of the silicon substrate 10, a tunneling oxide layer 50, a doped polycrystalline silicon layer 60, and a second silicon nitride film layer 70 are stacked sequentially from the inside to the outside. Metal grid lines are respectively provided on the surfaces of the first silicon nitride film layer 40 and the second silicon nitride film layer 70. The tunneling oxide layer 50 is a silicon dioxide layer. The difference from Example 1 is that this battery structure does not have an ultrathin intrinsic amorphous silicon layer 20. The preparation method of this battery structure lacks step S7. Other steps, parameters, and equipment are consistent with Example 1. Specifically, the ultrathin intrinsic amorphous silicon layer 20 can passivate the front surface of the solar cell and provide good contact for metallization. The specific performance is shown in Table 5 below. According to the comparison of the battery structure performance, it can be seen that the preparation method in this invention can improve the conversion efficiency, fill factor, open circuit voltage and other performance of TOPcon battery. The increase in Uoc (open circuit voltage) indicates that Example 1 has a good passivation effect. The decrease in Rser (series resistance) and the increase in FF (fill factor) indicate that the metal contact in Example 1 is optimized and the loss is reduced. This verifies the effectiveness of the preparation method in this invention and shows obvious improvement.

[0027] In summary, this invention introduces an ultra-thin intrinsic amorphous silicon layer on the front P-type emitter of a TOPCon battery, which has both passivation and contact functions, reducing contact resistance and improving fill factor and efficiency, and has good application prospects.

[0028] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A TOPcon battery structure with ultrathin intrinsic amorphous silicon, characterized in that, The device includes a silicon substrate (10). On the front side of the silicon substrate (10), an ultrathin intrinsic amorphous silicon layer (20), an aluminum oxide film layer (30), and a first silicon nitride film layer (40) are stacked sequentially from the inside to the outside. On the back side of the silicon substrate (10), a tunneling oxide layer (50), a doped polycrystalline silicon layer (60), and a second silicon nitride film layer (70) are stacked sequentially from the inside to the outside. Metal gate lines are respectively provided on the surfaces of the first silicon nitride film layer (40) and the second silicon nitride film layer (70). The thickness of the ultrathin intrinsic amorphous silicon layer (20) is 3~5nm, and the tunneling oxide layer (50) is a silicon dioxide layer.

2. The TOPcon battery structure with ultra-thin intrinsic amorphous silicon according to claim 1, characterized in that, The metal gate line includes a front gate line and a back gate line, wherein the front gate line is an Ag-Al gate line and the back gate line is an Ag gate line.

3. The method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon according to any one of claims 1-2, characterized in that, Specifically, the following steps are included: Step S1: Etch the N-type crystalline silicon to form a light-trapping textured surface structure; Step S2: Place the texturized silicon wafer into the diffusion furnace, use boron trichloride as the boron source to perform impurity diffusion, form a P-type emitter on the front side of the silicon wafer, and construct a PN junction cell structure. Step S3: Remove the borosilicate glass layer on the back of the silicon wafer and polish the back side; Step S4: A tunneling oxide layer (50) is formed on the back side of the silicon wafer using a high-temperature oxidation process, and then an intrinsic amorphous silicon layer is deposited on the surface of the tunneling oxide layer (50). Step S5: Place the silicon wafer processed in step S4 into the annealing furnace and perform high-temperature annealing on the intrinsic amorphous silicon layer to crystallize the intrinsic amorphous silicon layer and form a doped polycrystalline silicon layer (60). Step S6: Remove the borosilicate glass layer, phosphosilicate glass layer, and residual impurities from the silicon wafer; Step S7: Using PECVD process, deposit an ultrathin intrinsic amorphous silicon layer (20) on the surface of the P-type emitter on the front side of the silicon wafer. Step S8: Using the ALD process, deposit an aluminum oxide film (30) on the surface of the ultrathin intrinsic amorphous silicon layer (20). Step S9: Using PECVD process, a first silicon nitride film layer (40) is deposited on the surface of the alumina film layer (30), and a second silicon nitride film layer (70) is deposited on the surface of the doped polycrystalline silicon layer (60). Step S10: Print metal grid lines on the surfaces of the first silicon nitride film layer (40) and the second silicon nitride film layer (70), and then perform a sintering operation in a high-temperature sintering furnace to make the metal grid lines form an ohmic contact with the film layer structure. After sintering, the final N-type crystalline silicon solar cell structure is obtained.

4. The method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon according to claim 3, characterized in that, Step S1 employs a chain cleaning device and specifically includes: cleaning the silicon wafer with a mixed solution of HCl and H2O2 at room temperature for 8 minutes, followed by rinsing with deionized water, immersing the rinsed silicon wafer in a solution containing NaOH, pre-etching it at 75°C for 4 minutes, texturing the silicon wafer in the NaOH solution at 88°C for 15 minutes, resulting in a 3µm pyramidal textured surface on the silicon wafer, treating the silicon wafer with HF solution at room temperature for 2 minutes to remove the oxide layer, then treating the silicon wafer with HCl solution at room temperature for 5 minutes to remove metal ions, and finally drying the silicon wafer with hot air.

5. The method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon according to claim 3, characterized in that, The diffusion furnace in step S2 is a tube-type furnace. Step S2 specifically includes: placing the silicon wafer processed in step S1 into the tube-type furnace, evacuating and heating it to 950°C, then introducing a boron source into the tube-type furnace and reacting for 15 minutes to form a high-concentration borosilicate glass layer on the surface of the silicon wafer. The boron source is then stopped, and the internal temperature of the tube-type furnace is adjusted to 1000°C and maintained for 25 minutes to obtain a PN junction. After the tube-type furnace cools down, the silicon wafer is removed.

6. The method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon according to claim 3, characterized in that, Step S4 uses a PECVD tubular equipment. Step S4 specifically includes: sending the alkaline-polished silicon wafer into the PECVD tubular equipment, evacuating and heating it to 420~450℃, then introducing N2O gas into the tubular furnace equipment, ionizing it for 160s to form a tunneling oxide layer (50) on the back of the silicon wafer, keeping the temperature constant, introducing a mixture of SIH4, H2, and PH3 into the PECVD tubular equipment and reacting it for 500s to deposit an intrinsic amorphous silicon layer on the surface of the tunneling oxide layer (50), introducing N2 gas into the PECVD tubular equipment to restore the pressure inside the equipment to normal, and then taking out the silicon wafer.

7. The method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon according to claim 3, characterized in that, Step S5 uses a tubular annealing furnace. Step S5 specifically includes: placing the silicon wafer processed in step S4 into the tubular annealing furnace, evacuating and heating it to 800°C, then introducing N2 gas into the tubular annealing furnace for annealing treatment at a temperature of 840°C to 880°C for 8000 seconds, then introducing N2 gas into the tubular annealing furnace to restore the furnace to normal pressure, and finally removing the silicon wafer.

8. The method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon according to claim 3, characterized in that, Step S7 uses a PECVD tubular equipment. Step S7 specifically includes: placing the silicon wafer processed in step S6 inside the PECVD tubular equipment, adjusting the temperature to 400~500℃, and introducing N2 gas into the PECVD tubular equipment for purging. The purging flow rate of the N2 gas is 10000 sccm, and the purging time is 15s. After purging, introducing SIH4 gas into the PECVD tubular equipment for ionization. The flow rate of the SIH4 gas is 2500~3500 sccm, the ionization time is 10~20s, the process pressure is 2100~3100pa, and the RF power is 10000~15000W. After ionization, depositing an ultrathin intrinsic amorphous silicon layer (20) with a thickness of 3~5nm on the surface of the silicon wafer. After deposition, introducing N2 gas again for purging, and removing the silicon wafer after breaking the vacuum.

9. The method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon according to claim 3, characterized in that, Step S8 uses an ALD atomic deposition equipment. Step S8 specifically includes: placing the silicon wafer processed in step S7 into the ALD atomic deposition equipment, evacuating and heating it to 220~270℃, pre-watering the surface of the silicon wafer for 10s, and then alternately introducing TMA and H2O for 34 cycles with a cycle interval of 37s, so that an aluminum oxide film layer (30) is deposited on the surface of the ultrathin intrinsic amorphous silicon layer (20). After the deposition is completed, the vacuum is broken to restore the pressure inside the equipment to normal, and the silicon wafer is taken out.

10. The method for fabricating a TOPcon battery structure with ultrathin intrinsic amorphous silicon according to claim 3, characterized in that, Step S9 uses a plasma PECVD equipment. Step S9 specifically includes: placing the silicon wafer processed in step S8 inside the plasma PECVD equipment, evacuating and heating it to 520~540℃, then introducing a mixed special gas of SIH4, NH3 and N2O3 into the plasma PECVD equipment for a reaction of 30 minutes, and then removing the silicon wafer after breaking the vacuum.

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