A method for manufacturing a semiconductor structure

Abstract

The application provides a preparation method of a semiconductor structure, and belongs to the field of semiconductors. The method comprises the following steps: sequentially forming a doped layer, a pad oxide layer and a pad nitride layer on a substrate; etching the pad nitride layer, the pad oxide layer, the doped layer and part of the substrate to form a shallow trench, then depositing an insulating material in the shallow trench until the insulating material in the shallow trench protrudes from the pad nitride layer; first planarizing the insulating material until the pad nitride layer is exposed; sequentially etching and removing the pad nitride layer and the pad oxide layer until the doped layer is exposed; depositing a compensating insulating material on the doped layer and the insulating material in the shallow trench; second planarizing the compensating insulating material and the insulating material until the doped layer is exposed to form a shallow trench isolation structure; and removing the doped layer. The preparation method of the semiconductor structure can improve the corner recess phenomenon of the shallow trench isolation structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for preparing a semiconductor structure. Background Technology

[0002] During the fabrication of shallow trench isolation structures, the significant differences in physical properties between the insulating material filling the trench and the pad oxide layer on the substrate surface directly lead to differences in the etching rates of the insulating material and the pad oxide layer. Therefore, when etching away the pad oxide layer, this difference in etching rate causes over-etching at the edges of the shallow trench isolation structure, resulting in corner depressions. Consequently, in subsequent processes, polysilicon fills these corner depressions, creating parasitic regions, leading to a decrease in turn-on voltage, additional leakage current, and ultimately affecting the quality of the semiconductor structure. Summary of the Invention

[0003] This invention proposes a method for fabricating a semiconductor structure. The method provided by this invention can improve the corner depression phenomenon of shallow trench isolation structures and improve the quality of semiconductor structures.

[0004] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor structure, comprising at least the following steps:

[0005] Provide a substrate;

[0006] A doped layer, a pad oxide layer, and a pad nitride layer are sequentially formed on the substrate;

[0007] After etching the pad nitride layer, the pad oxide layer, the doped layer and part of the substrate to form a shallow trench, an insulating material is deposited in the shallow trench until the insulating material in the shallow trench protrudes from the pad nitride layer;

[0008] The insulating material is first planarized until the pad nitride layer is exposed;

[0009] The pad nitride layer and the pad oxide layer are etched and removed sequentially until the doped layer is exposed;

[0010] A compensating insulating material is deposited on the insulating material within the doped layer and the shallow trench;

[0011] A second planarization is performed on the compensating insulating material and the insulating material until the doped layer is exposed, forming a shallow trench isolation structure; and

[0012] The doped layer is removed by etching.

[0013] In one embodiment of the present invention, the material of the doped layer includes silicon germanide.

[0014] In one embodiment of the present invention, the etching selectivity ratio of the doped layer and the insulating material is greater than 100:1.

[0015] In one embodiment of the present invention, the doped layer is removed by dry etching.

[0016] In one embodiment of the present invention, the etching gas in the dry etching process includes at least one of chlorine trifluoride and hydrogen chloride.

[0017] In one embodiment of the present invention, before etching away the pad oxide layer, the pad oxide layer and the doped layer are used as ion implantation buffer layers to implant ions into the substrate under the shallow trench to form a deep well region.

[0018] In one embodiment of the present invention, after the insulating material is planarized for the second time, ions are implanted into the substrate using the doped layer as an ion implantation buffer layer to form a trap region.

[0019] In one embodiment of the present invention, the thickness of the doped layer and the step height between the shallow trench isolation structure and the substrate are equal.

[0020] In one embodiment of the present invention, the etching selectivity ratio of the pad nitride layer and the insulating material is greater than 100:1.

[0021] In one embodiment of the present invention, the compensating insulating material and the insulating material are the same in terms of material and deposition method.

[0022] In summary, this invention proposes a method for fabricating a semiconductor structure. By improving this method, the unexpected technical effect is the ability to mitigate the corner concavity phenomenon in shallow trench isolation structures, thereby reducing leakage current and performance instability, and improving the overall quality of the semiconductor structure. Furthermore, the semiconductor structure fabrication method proposed in this invention can precisely control the step height of the shallow trench isolation structure, effectively reducing edge electric field coupling between adjacent structures, decreasing parasitic capacitance, and ultimately improving the speed and reducing power consumption of the semiconductor structure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram showing the sequential formation of a doped layer, a pad oxide layer, a pad nitride layer, a hard mask layer, a silicon oxynitride layer, an anti-reflection layer, and a photoresist layer on a substrate.

[0025] Figure 2 A schematic diagram to illustrate the formation of the first opening.

[0026] Figure 3 This is a schematic diagram illustrating the formation of the second opening.

[0027] Figure 4 A schematic diagram illustrating the formation of shallow trenches.

[0028] Figure 5 This is a schematic diagram of depositing insulating material in a shallow trench.

[0029] Figure 6 This is a schematic diagram of the first planarization of the insulating material.

[0030] Figure 7 This is a schematic diagram of the nitrided layer on the etching pad.

[0031] Figure 8 This is a schematic diagram of the formation of a deep trap region.

[0032] Figure 9 This is a schematic diagram of the oxide layer on the etching pad.

[0033] Figure 10 This is a schematic diagram of depositing compensating insulating material on a doped layer and an insulating material.

[0034] Figure 11 This is a schematic diagram of the insulation material and the insulation material used for the second flattening compensation.

[0035] Figure 12 This is a schematic diagram of the formation of the trap region.

[0036] Figure 13 This is a schematic diagram of the etched doped layer.

[0037] Label Explanation:

[0038] 10. Substrate; 11. Doped layer; 12. Pad oxide layer; 13. Pad nitride layer; 14. Hard mask layer; 15. Silicon oxynitride layer; 16. Anti-reflective layer; 17. Photoresist layer; 171. First opening; 172. Second opening; 18. Shallow trench; 19. Insulating material; 191. Corner recess; 20. Deep well region; 21. Shallow trench isolation structure; 22. First well region; 23. Second well region; 24. Compensating insulating material. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0041] The technical solution of the present invention will be further described in detail below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] During the fabrication of shallow trench isolation structures, the difference in etching rate between the insulating material filling the trench and the pad oxide layer on the substrate surface leads to over-etching at the edges of the shallow trench isolation structure during the etching process to remove the pad oxide layer. This results in corner depressions, which are subsequently filled by polysilicon in later processes, creating parasitic regions. This leads to a decrease in turn-on voltage, generating additional leakage current and affecting the performance of the semiconductor structure. Furthermore, after etching away the pad oxide layer, a sacrificial oxide layer is typically grown on the substrate as an ion implantation buffer layer using in-situ water vapor generation before ion implantation to form the trap region. However, subsequent etching to remove the sacrificial oxide layer exacerbates the corner depressions of the shallow trench isolation structure, further degrading its performance. Additionally, the presence of corner depressions makes it impossible to precisely control the step height of the shallow trench isolation structure, thus affecting both the performance and yield of the semiconductor structure. Therefore, the present invention provides a method for fabricating a semiconductor structure that can improve the corner concavity phenomenon of shallow trench isolation structures, thereby improving the leakage current and performance instability of semiconductor structures, improving the quality of semiconductor structures, and can also precisely control the step height of shallow trench isolation structures, thereby effectively reducing the edge electric field coupling of adjacent structures, reducing parasitic capacitance, and thus improving the speed of semiconductor structures and reducing power consumption.

[0043] Please see Figure 1As shown, in one embodiment of the present invention, a substrate 10 is first provided. The substrate 10 can be any material suitable for forming a semiconductor structure, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other semiconductor materials formed from III / V compounds. It also includes stacked structures composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, and germanium-on-insulator. The substrate 10 can be an intrinsic semiconductor, or ions can be implanted into the substrate 10 to form an N-type semiconductor or a P-type semiconductor. Furthermore, the present invention does not limit the thickness of the substrate 10. In this embodiment, for example, a silicon wafer substrate 10 is used as an example to describe the method for fabricating the semiconductor structure.

[0044] Please see Figure 1 As shown, in one embodiment of the present invention, a doped layer 11 is formed on the surface of the substrate 10. The doped layer 11 is formed, for example, by chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or evaporation growth. The material of the doped layer 11 includes, for example, silicon germanide, with the chemical formula Si. 1-x Ge x x is, for example, 0.3-0.7. The present invention does not limit the thickness of the doped layer 11. The thickness of the doped layer 11 is equal to the preset step height of the subsequent shallow trench isolation structure 21, which is the height by which the surface of the shallow trench isolation structure 21 protrudes above the surface of the substrate 10. In this embodiment, the thickness of the doped layer 11 is, for example, 200Å-500Å, specifically, for example, 350Å, 300Å, or 250Å. By limiting the height of the doped layer 11, the step height of the shallow trench isolation structure 21 can be precisely controlled, thereby effectively reducing the edge electric field coupling of adjacent structures, reducing parasitic capacitance, and thus improving structure speed and reducing power consumption.

[0045] Please see Figure 1 As shown, in one embodiment of the present invention, after forming a doped layer 11, a pad oxide layer 12 is formed on the doped layer 11. The pad oxide layer 12 is formed, for example, by liquid phase epitaxy, molecular beam epitaxy, chemical vapor deposition, or sputtering. The material of the pad oxide layer 12 includes, for example, silicon oxide. The present invention does not limit the thickness of the pad oxide layer 12, which can be 80 Å to 120 Å, specifically, for example, 100 Å, 110 Å, or 120 Å. In this embodiment, the pad oxide layer 12 is formed, for example, by sputtering. Specifically, silicon dioxide is used as the target material, and the pad oxide layer 12 is prepared by radio frequency reactive magnetron sputtering. The pad oxide layer 12 can absorb some stress, reducing stress transmission to the substrate 10, thereby reducing the risk of substrate 10 cracking.

[0046] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the pad oxide layer 12, a pad nitride layer 13 is formed on the pad oxide layer 12. The material of the pad nitride layer 13 includes, for example, silicon nitride. The pad nitride layer 13 is formed by methods such as liquid phase epitaxy, molecular beam epitaxy, chemical vapor deposition, or evaporation growth. The present invention does not limit the thickness of the pad nitride layer 13 and can be selected according to actual needs. In this embodiment, the pad nitride layer 13 is formed, for example, by chemical vapor deposition. Specifically, a substrate 10 with the pad oxide layer 12 and the doped layer 11 is placed in a chamber containing a nitrogen source and a silicon source, and the pad nitride layer 13 is deposited on the pad oxide layer 12 under conditions such as a pressure of, for example, 2 Torr-10 Torr and a temperature of, for example, 600°C-800°C. The nitrogen source includes at least one of ammonia, nitrogen, dimethylamine, and trimethylamine, and the silicon source includes at least one of silane, chlorosilane, dichlorosilane, and disilane. The thickness of the pad nitride layer 13 is, for example, 50 Å to 1500 Å, specifically 900 Å, 1000 Å, or 1200 Å. By providing the pad nitride layer 13, the substrate 10 can be protected from etching, polishing, and other processes during the subsequent formation of the shallow trench isolation structure 21, avoiding unnecessary damage to the substrate 10.

[0047] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the pad nitride layer 13, a hard mask layer 14 is formed on the pad nitride layer 13. The material of the hard mask layer 14 includes, for example, amorphous carbon. The present invention does not limit the thickness and formation method of the hard mask layer 14, and can select it according to actual needs. In this embodiment, the thickness of the hard mask layer 14 is, for example, 1800 Å-2200 Å, specifically, 1900 Å, 2000 Å, or 2100 Å, etc. The hard mask layer 14 is prepared, for example, by vacuum evaporation, sputtering, or chemical vapor deposition. By setting the hard mask layer 14 as a mask layer, a clear "boundary constraint" can be provided for etching during the subsequent formation of the shallow trench 18, reducing lateral erosion during the etching process.

[0048] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the hard mask layer 14, a silicon oxynitride layer 15 is formed on the hard mask layer 14. The material of the silicon oxynitride layer 15 includes, for example, SiON. The present invention does not limit the thickness and formation method of the silicon oxynitride layer 15, and can be selected according to actual needs. In this embodiment, the thickness of the silicon oxynitride layer 15 is, for example, 300 Å-500 Å, specifically, for example, 350 Å, 370 Å, or 400 Å. The silicon oxynitride layer 15 is prepared, for example, by chemical vapor deposition or thermal oxidation.

[0049] Please see Figure 1As shown, in one embodiment of the present invention, after forming a silicon oxynitride layer 15, an antireflective layer 16 is formed on the silicon oxynitride layer 15. The material of the antireflective layer 16 is, for example, an organic material such as a phenolic resin derivative or an acrylate polymer. The present invention does not limit the thickness and formation method of the antireflective layer 16, and can be selected according to actual needs. In this embodiment, the thickness of the antireflective layer 16 is, for example, 200 Å-400 Å, specifically, 200 Å, 220 Å, or 250 Å, and the antireflective layer 16 is prepared, for example, by chemical vapor deposition or physical vapor deposition. By setting the silicon oxynitride layer 15 and the antireflective layer 16, the standing wave response can be improved, and the etching uniformity can be enhanced.

[0050] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, after forming the antireflective layer 16, a photoresist layer 17 is formed on the antireflective layer 16, for example, by spin coating. The thickness of the photoresist layer 17 is, for example, 900 Å-2000 Å, specifically, 1000 Å, 1200 Å, or 1500 Å. Then, after exposure and development processes, the photoresist layer 17 is patterned, forming at least one first opening 171 in the photoresist layer 17. The first opening 171 exposes a portion of the antireflective layer 16. Then, using the patterned photoresist layer 17 as a mask, the exposed antireflective layer 16, the silicon oxynitride layer 15, and the hard mask layer 14 are etched sequentially. At least one second opening 172 is formed in the hard mask layer 14, and during the etching process, the photoresist layer 17, the antireflective layer 16, and the silicon oxynitride layer 15 are substantially completely etched. The number of first openings 171 and second openings 172 are equal. In this embodiment, the preparation method is described using two first openings 171 as an example. Specifically, the two first openings 171 are spaced apart within the photoresist layer 17, and the two second openings 172 are spaced apart within the hard mask layer 14.

[0051] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after the second opening 172 is formed, the pad nitride layer 13, pad oxide layer 12, doped layer 11, and substrate 10 exposed by the second opening 172 are etched using a hard mask layer 14 as a mask, forming two shallow trenches 18 at intervals. During the etching process, the hard mask layer 14 is essentially completely etched, and the shallow trenches 18 are recessed from the surface of the pad nitride layer 13 into the substrate 10. The present invention does not limit the recess depth of the shallow trenches 18 into the substrate 10, and can be selected according to actual needs.

[0052] Please see Figures 4 to 5As shown, in one embodiment of the present invention, after forming the shallow trench 18, an insulating material 19 is formed on the pad nitride layer 13 and within the shallow trench 18 until the insulating material 19 within the shallow trench 18 protrudes from the pad nitride layer 13. The insulating material 19 may be made of materials such as silicon oxide. The present invention does not limit the method of forming the insulating material 19; for example, it may be formed by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD).

[0053] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, after the insulating material 19 is formed, the insulating material 19 is planarized for the first time, for example by chemical mechanical polishing (CMP), until polishing stops at the pad nitride layer 13.

[0054] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after the first planarization of the insulating material 19, the pad nitride layer 13 is selectively etched away. The etching method may be, for example, dry etching or wet etching. In this embodiment, the pad nitride layer 13 is removed by wet etching, specifically, by using hot phosphoric acid as the etching solution to chemically react with the pad nitride layer 13, generating soluble silica and ammonia gas, thereby achieving the purpose of removing the pad nitride layer 13. The temperature of the hot phosphoric acid is, for example, 150°C-180°C, and the etching selectivity ratio of the wet etching for the pad nitride layer 13 and the insulating material 19 is, for example, greater than 100:1, thereby protecting the insulating material 19 within the shallow trench 18 from damage during the etching process of removing the pad nitride layer 13.

[0055] Please see Figures 7 to 8 As shown, in one embodiment of the present invention, after removing the pad nitride layer 13, the pad oxide layer 12 and the doped layer 11 are used as ion implantation buffer layers to implant first ions into the substrate 10 under the shallow trench 18, forming a deep well region 20. The first ion is, for example, an N-type ion such as phosphorus (P) or arsenic (As). A predetermined distance is maintained between the deep well region 20 and the bottom of the shallow trench 18, for example, 300 nm to 100 nm. Specifically, the first ion is implanted using the pad oxide layer 12 and the doped layer 11 as ion implantation buffer layers. The silicon germanium in the doped layer 11 acts as a pre-amorphization layer, which can prevent the channeling effect of ions and improve the quality of the semiconductor structure.

[0056] Please see Figure 4 , Figures 8 to 9As shown, in one embodiment of the present invention, after forming the deep well region 20, the pad oxide layer 12 is selectively etched away. The etching method may be, for example, dry etching or wet etching. In this embodiment, the pad oxide layer 12 is removed by wet etching, specifically, by using hydrofluoric acid or buffered oxide etch (BOE) as the etching solution to react with the pad oxide layer 12 and grow soluble fluorosilicic acid, thereby achieving the purpose of removing the pad oxide layer 12. The materials of the pad oxide layer 12 and the insulating material 19 are chemically similar, both being silicon oxides. However, due to the different growth processes of the pad oxide layer 12 and the insulating material 19, as well as their different hardness and density, the pad oxide layer 12 has a looser structure and lower density than the insulating material 19, making it more susceptible to etching. Therefore, the wet etching rates for the pad oxide layer 12 and the insulating material 19 are different. The etching selectivity ratio between the pad oxide layer 12 and the insulating material 19 located on the surface of the shallow trench 18 is, for example, (1.05-1.2):1. Consequently, the thickness of the insulating material 19 will be reduced during the etching process of removing the pad oxide layer 12. Furthermore, due to the small radius of curvature of the insulating material 19 at the corners, the diffusion rate of the etching solution at the corners is high, resulting in a larger contact area between the etching solution and the insulating material 19 at the corners. This increases the etching rate of the etching solution on the insulating material 19 at the corners. Consequently, during the etching process of removing the pad oxide layer 12, the etching solution may over-etch the insulating material 19 at the corners, forming corner depressions 191. The etching selectivity ratio of the etching solution for the pad oxide layer 12 and the insulating material 19 located at the corners of the shallow trench 18 is, for example, (0.7-0.9):1.

[0057] Please see Figures 9 to 10 As shown, in one embodiment of the present invention, after removing the pad oxide layer 12, a compensating insulating material 24 is deposited on the doped layer 11 and the insulating material 19 to fill the corner depression 191. The compensating insulating material 24 and the insulating material 19 are made of the same material and are deposited using the same method, which will not be elaborated upon here.

[0058] Please see Figures 10 to 11 As shown, in one embodiment of the present invention, after depositing the compensation insulating material 24, the compensation insulating material 24 and the insulating material 19 are planarized a second time by CMP, for example, until the doped layer 11 is exposed, and the remaining insulating material 19 is defined as a shallow trench isolation structure 21. The preset step height of the shallow trench isolation structure 21 is equal to the thickness of the doped layer 11, and there are, for example, two shallow trench isolation structures 21, spaced apart.

[0059] Please see Figures 11 to 12As shown, in one embodiment of the present invention, after the second planarization compensation of insulating material 24 and insulating material 19, the formed shallow trench isolation structure 21 divides the substrate 10 into multiple active regions. Using the doped layer 11 as an ion implantation buffer layer, ions are implanted into the active regions between two adjacent shallow trench isolation structures 21 to form well regions. Specifically, in this embodiment, a second ion can be implanted into a portion of the active region to form a first well region 22, and a third ion can be implanted into a portion of the active region to form a second well region 23. The second ion is, for example, an N-type ion such as P or As, and the third ion is, for example, a P-type ion such as boron (B) or gallium (Ga) to form different types of semiconductor devices. The first well region 22 and the second well region 23 are each free from the surface of the substrate 10 and extend into the substrate 10. The distance between the first well region 22 and the deep well region 20 is, for example, greater than the distance between the shallow trench isolation structure 21 and the deep well region 20, and the distance between the second well region 23 and the deep well region 20 is, for example, greater than the distance between the shallow trench isolation structure 21 and the deep well region 20. By implanting ions using doped layer 11 as an ion implantation buffer layer, the germanium doped in doped layer 11 has a pre-amorphization effect, which can prevent ion channeling effect and improve the quality of semiconductor structure.

[0060] Please see Figures 12 to 13 As shown, in one embodiment of the present invention, after the well region is formed, the doped layer 11 is selectively etched away. The etching method may be, for example, dry etching or wet etching. In this embodiment, the doped layer 11 is removed by dry etching, and the etching gas used in the dry etching process includes at least one of chlorine trifluoride and hydrogen chloride. The etching selectivity ratio of the dry etching for the doped layer 11 and the insulating material 19 in the shallow trench isolation structure 21 is, for example, greater than 100:1, so that when the doped layer 11 is etched away, the insulating material 19 in the shallow trench isolation structure 21 is hardly etched, and the shallow trench isolation structure 21 does not develop corner depressions 191. Therefore, by setting a doped layer 11 instead of a sacrificial oxide layer as an ion implantation buffer layer, on the one hand, the formation process of the sacrificial oxide layer can be omitted, simplifying the preparation process; on the other hand, the corner depressions 191 of the shallow trench isolation structure 21 can be avoided, the channel stress distribution will not be changed, the carrier mobility will not be affected, and the threshold voltage will remain stable; moreover, the isolation integrity will be maintained, the leakage phenomenon of the semiconductor structure will be improved, and no additional capacitor will be introduced, thereby improving the circuit speed.

[0061] In summary, this invention proposes a method for fabricating a semiconductor structure. By setting a doped layer between the substrate and the pad oxide layer, the unexpected technical effect of this application is that it can improve the corner concavity phenomenon of shallow trench isolation structures, thereby improving leakage current and performance instability of the semiconductor structure and enhancing its quality. Furthermore, the semiconductor structure fabrication method proposed in this invention, by controlling the thickness of the doped layer, can precisely control the step height of the shallow trench isolation structure, thereby effectively reducing edge electric field coupling between adjacent structures, reducing parasitic capacitance, and ultimately improving the speed of the semiconductor structure while reducing power consumption.

[0062] The above description is merely a preferred embodiment of this application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the inventive concept. For example, technical solutions formed by replacing the above-mentioned features with technical features with similar functions disclosed in this application (but not limited to) each other.

[0063] Apart from the technical features described in the specification, the other technical features are known to those skilled in the art. To highlight the innovative features of this invention, the other technical features will not be described in detail here.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, At least the following steps are included: Provide a substrate; A doped layer, a pad oxide layer, and a pad nitride layer are sequentially formed on the substrate; After etching the pad nitride layer, the pad oxide layer, the doped layer and the substrate to form a shallow trench, an insulating material is deposited in the shallow trench until the insulating material in the shallow trench protrudes from the pad nitride layer; The insulating material is first planarized until the pad nitride layer is exposed; The pad nitride layer and the pad oxide layer are etched and removed sequentially until the doped layer is exposed; A compensating insulating material is deposited on the doped layer and the insulating material, wherein the compensating insulating material and the insulating material are made of the same material and are deposited using the same method. The compensation insulating material and the insulating material are planarized a second time until the doped layer is exposed, forming a shallow trench isolation structure; as well as The doped layer is removed by dry etching, wherein the etching selectivity ratio of the doped layer to the insulating material is greater than 100:1, and the thickness of the doped layer is equal to the step height between the shallow trench isolation structure and the substrate.

2. The preparation method according to claim 1, characterized in that, The material of the doped layer includes silicon germanide.

3. The preparation method according to claim 1, characterized in that, The etching gas used in the dry etching process includes at least one of chlorine trifluoride and hydrogen chloride.

4. The preparation method according to claim 1, characterized in that, Before etching away the pad oxide layer, ions are implanted into the substrate under the shallow trench using the pad oxide layer and the doped layer as ion implantation buffer layers to form a deep well region.

5. The preparation method according to claim 1, characterized in that, After the insulating material is planarized for the second time, ions are implanted into the substrate using the doped layer as an ion implantation buffer layer to form a trap region.

6. The preparation method according to claim 1, characterized in that, The etching selectivity ratio of the nitrided pad layer to the insulating material is greater than 100:1.

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