Semiconductor device and forming method

Abstract

The invention relates to a semiconductor device and a forming method. Before a conductive structure of the semiconductor device is formed on a contact structure of the semiconductor device, a pre-cleaning operation using a metal precursor is performed to remove a metal oxide layer from a top surface of the contact structure. The use of a metal precursor as a pre-cleaning agent for a pre-cleaning operation enables complete removal of native oxides (not only components such as oxygen) without causing formation of pores in the top surface of the contact structure, enabling low contact resistance between the contact structure and the conductive structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and forming methods. BACKGROUND

[0002] An interconnect layer (sometimes referred to as a back end region or back end of line (BEOL) region) is a region of a semiconductor device that includes a multilayer conductive structure arranged to carry signals and / or provide power distribution throughout the semiconductor device. The multilayer conductive structure can include various vertically-arranged interconnect structure layers (e.g., vias) and metallization structure layers (e.g., trenches, conductive lines, traces). SUMMARY

[0003] According to one embodiment of the present disclosure, a method of forming a semiconductor device is provided, comprising: forming a recess in a dielectric layer in an interconnect layer of the semiconductor device, wherein a top surface of a contact structure of the semiconductor device is exposed through the recess; performing a pre-clean operation on the top surface of the contact structure using a metal precursor pre-cleaner; and forming a conductive structure of the interconnect layer on the top surface of the contact structure in the recess.

[0004] According to one embodiment of the present disclosure, a method of forming a semiconductor device is provided, comprising: forming a recess in a dielectric layer in an interconnect layer of the semiconductor device, wherein the interconnect layer is located above a device layer of the semiconductor device, and wherein a top surface of a contact structure of the semiconductor device is exposed through the recess; performing a pre-clean operation on the top surface of the contact structure using a metal precursor pre-cleaner to remove metal and oxygen from the top surface of the contact structure; and forming a conductive structure of the interconnect layer on the top surface of the contact structure in the recess, wherein the pre-clean operation and forming the conductive structure are performed in a same processing chamber while maintaining a vacuum in the same processing chamber between the pre-clean operation and forming the conductive structure.

[0005] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate layer; an integrated circuit device, the integrated circuit device satisfying at least one of: being located within the substrate layer or being located on the substrate layer; a contact structure, the contact structure being located in a first dielectric layer above the substrate layer and electrically coupled to the integrated circuit device, wherein the contact structure comprises a first metal material; and a conductive structure, the conductive structure being located in a second dielectric layer above the first dielectric layer and in contact with the contact structure, wherein a bottom surface of the conductive structure is recessed from a top surface of the contact structure. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can best be understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions can be intentionally increased or reduced for the sake of discussion. It should be understood that many of the details provided can be implemented in any number of manners that would be appreciated by those skilled in the art. For example, the various features can be combined in a single embodiment, or implemented in a plurality of separate embodiments, and in any suitable sub-combination.

[0007] FIG. 1A and FIG. 1B is an illustration of a portion of an example semiconductor device described herein.

[0008] FIG. 2A-FIG. 2E is an illustration of an example implementation of a semiconductor device described herein.

[0009] FIG. 3A-FIG. 3H is an illustration of an example implementation of a source / drain interconnect structure described herein.

[0010] FIG. 4A-FIG. 4D is an illustration of an example implementation of a source / drain contact structure and a source / drain interconnect structure of a semiconductor device described herein.

[0011] FIG. 5A-FIG. 5E is an illustration of an example implementation of a source / drain contact structure and a source / drain interconnect structure of a semiconductor device described herein.

[0012] FIG. 6 is a flowchart of an example process associated with forming a semiconductor device described herein.

[0013] FIG. 7 is a flowchart of an example process associated with forming a semiconductor device described herein. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments where the first feature is formed in direct contact with the second feature, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature can not be in direct contact with the second feature. Furthermore, the present disclosure can refer to a number of reference numerals in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, spatially relative terms (for example, "beneath", "below", "lower", "above", "upper", and the like) can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] Interconnect layers of a semiconductor device can be formed above device layers of the semiconductor device. The device layers can include substrate layers of the semiconductor device and integrated circuit devices (e.g., transistors, capacitors, diodes, memory cells) located in and / or on the semiconductor substrate. A layer of contact structures (referred to as source / drain contacts) can be included between the integrated circuit devices and the interconnect layers and can electrically connect the integrated circuit devices to the bottommost conductive structures (referred to as source / drain interconnects and gate interconnects) in the interconnect layers.

[0017] To form the conductive structures of the interconnect layers on the contact structures, a recess can be formed through the dielectric layer to expose a top surface of the contact structures. Then, a material of the conductive structures can be deposited on the top surface of the contact structures such that the conductive structures and the contact structures are electrically coupled.

[0018] In some cases, a pre-clean operation can be performed on the top surface of the contact structures after the recess is formed and before the material of the contact structures is deposited. After the recess is formed, a thin layer of metal oxide material (referred to as "native oxide") can be formed on the top surface of the contact structures due to exposure of the top surface of the contact structures to atmospheric oxygen and / or oxygen used in semiconductor processes performed for the semiconductor device. This layer of metal oxide, if not removed, can increase the contact resistance between the contact structures and the conductive structures. However, the pre-clean operation can only remove the oxygen in the layer of metal oxide, resulting in the formation of pores or other types of voids in the surface of the top surface of the contact structures. This porosity can increase the contact resistance between the contact structures and the conductive structures.

[0019] In some implementations described herein, a pre-clean operation using a metal precursor is performed to remove a metal oxide layer from a top surface of a contact structure of a semiconductor device prior to forming a conductive structure of the semiconductor device on the contact structure. The metal precursor can include a metal precursor of a metal material of the contact structure, a metal precursor of a metal material of the conductive structure, and / or other metal precursors. The metal precursor can be a halogen-based metal precursor that etches and removes both the oxygen and metal components of the metal oxide layer on the top surface of the contact structure, rather than just the oxygen component of the metal oxide (which can otherwise result in the formation of pores in the top surface of the contact structure that increase the contact resistance between the contact structure and the conductive structure). The resulting top surface of the contact structure after the pre-clean operation is smooth and substantially free of pores and other voids.

[0020] In this way, the use of a metal precursor as a pre-clean agent for the pre-clean operation enables the complete removal of native oxides (rather than just constituent components such as oxygen) without causing the formation of pores in the top surface of the contact structure, enabling low contact resistance to be achieved between the contact structure and the conductive structure. Furthermore, the metal precursor can also etch some of the metal material of the top surface of the contact structure, causing the top surface to become slightly recessed, providing a greater surface area for the conductive structure to contact the contact structure. The increased surface area can further reduce the contact resistance between the conductive structure and the contact structure.

[0021] FIG. 1A and FIG. 1B is an illustration of a portion of an example semiconductor device 100 described herein. The semiconductor device 100 can include a system-on-a-chip (SoC) device, a logic device such as a central processing unit (CPU) or a graphics processing unit (GPU), a memory device (e.g., a high-bandwidth memory (HBM) device), a panel driver device, an integrated circuit (IC) driver, a radio frequency (RF) power amplifier, a display driver IC (DDIC), and / or other types of semiconductor devices.

[0022] As shown in FIG. 1A The semiconductor device 100 can include a device layer 102 and an interconnect layer 104 located above the device layer 102 in a z-direction of the semiconductor device 100. The device layer 102 includes a substrate layer 106. The substrate layer 106 can correspond to a portion of a semiconductor wafer on which the semiconductor device 100 is formed. The substrate layer 106 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (e.g., gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates. The substrate layer 106 can extend in an x-direction and / or a y-direction of the semiconductor device 100.

[0023] A dielectric layer 108 is included over the substrate layer 106. The dielectric layer 108 includes an interlayer dielectric (ILD) layer (e.g., an ILD0 layer), an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 108 includes dielectric material(s) that enable selective etching or immunity to etching of various portions of the substrate layer 106, and / or electrically isolates the integrated circuit devices 110 in the device layer 102. The dielectric layer 108 includes silicon nitride (Si x N y ), oxide (e.g., silicon oxide (SiO x ), and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 108 can extend along the x-direction and / or the y-direction of the semiconductor device 100.

[0024] The integrated circuit devices 110 can be included in and / or on the substrate layer 106 of the semiconductor device 100, and / or in the dielectric layer 108 in the device layer 102. The integrated circuit devices 110 include transistors (e.g., planar transistors, fin field effect transistors (finFETs), gate all around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, emitters, receivers, optical circuits, and / or other types of semiconductor devices.

[0025] The integrated circuit devices 110 can include a plurality of source / drain regions 112 that are grown and / or otherwise formed on and / or around portions of the substrate layer 106. The “source / drain region(s)” can refer to a source or a drain, individually or collectively, depending on the context. The source / drain regions 112 can be formed by epitaxial growth of doped semiconductor regions and / or other semiconductor processes. In some embodiments, the source / drain regions 112 are formed in recessed portions in the substrate layer 106. The recessed portions can be formed by a strain source / drain (SSD) etch and / or other types of etching operations on the substrate layer 106. In some embodiments, the source / drain regions 112 are formed in recesses formed in an alternating stack of channel layers and sacrificial layers (e.g., silicon germanium (SiGe)) layers.

[0026] The integrated circuit device 110 can further include a gate dielectric layer 114 located between the gate structure 116 and the channel layer 118 of the integrated circuit device 110. The channel layer 118 can extend between the source / drain regions 112 of the integrated circuit device 110, and the gate dielectric layer 114 and the gate structure 116 can surround two or more sides of the channel layer 118. In some embodiments, the gate dielectric layer 114 and the gate structure 116 surround all four sides of the channel layer 118. In these embodiments, the integrated circuit device 110 can be referred to as a nanostructure transistor, e.g., a GAA transistor.

[0027] The channel layer 118 can include a nanoscale layer of semiconductor material, e.g., silicon (Si), silicon germanium (SiGe), and / or doped silicon, etc. The channel layer 118 can be formed from silicon nanosheets that are formed as part of a nanosheet stack over the substrate layer 106.

[0028] In some embodiments, the gate dielectric layer 114 includes a low dielectric constant (low-k) dielectric material, e.g., silicon oxide (SiO x ) In some embodiments, the gate dielectric layer 114 includes a high dielectric constant (high-k) dielectric material, e.g., hafnium oxide (HfO x ).

[0029] The gate structure 116 can be located laterally between the source / drain regions 112. In some embodiments, the gate structure 116 is formed from a polysilicon material. In these embodiments, the polysilicon material can be doped with one or more types of dopants (e.g., p-type dopants, n-type dopants) to adjust the work function of the gate structure 116.

[0030] In some embodiments, the gate structure 116 is formed from one or more metallic materials (e.g., tungsten (W), titanium (Ti), cobalt (Co), and / or other metals). In these embodiments, the gate structure 116 can include one or more work function metal layers (e.g., p-type metal layers, n-type metal layers) for adjusting the work function of the gate structure 116. The work function metal layer(s) can be included between the gate dielectric layer 114 and the gate structure 116.

[0031] A p-type work function metal layer can include one or more p-type metals, e.g., tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals having a work function greater than about 4.7 electron volts (eV), etc. The p-type work function metal layer can be included to adjust the work function of the gate structure 116 such that the work function is adjusted to be close to the valence band of the material of the channel layer 118.

[0032] The n-type work function metal layer can include one or more metal materials that adjust or tune the work function of the gate structure 116 to be close to the conduction band of the material of the channel layer 118 of the semiconductor device 100. In some embodiments, the n-type work function metal layer can include titanium aluminum (TiAl). In some embodiments, the n-type work function metal layer includes titanium aluminum carbon (TiAlC). In some embodiments, the n-type work function metal layer includes other aluminum-containing metals. In some embodiments, other n-type metal materials are included in the n-type work function metal layer.

[0033] Various spacers can be included in the integrated circuit device 110. For example, sidewall spacers 120a can be included on the sidewalls of the gate structure 116 to provide electrical isolation for the gate structure 116, among other things. In some embodiments, the sidewall spacers 120a are in contact with the gate dielectric layer 114. In some embodiments, the sidewall spacers 120a are in contact with the work function metal layer. The sidewall spacers 120a can include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and / or other suitable materials.

[0034] As another example, an internal spacer 120b can be included laterally between the gate structure 116 and the source / drain regions 112 of the integrated circuit device 110. The internal spacer 120b can be included to reduce parasitic capacitance in the integrated circuit device 110 and to protect the source / drain regions 112 from being etched during a nanosheet release operation that removes a sacrificial layer between the channel layer 118. The internal spacer 120b can include silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or other dielectric materials.

[0035] The source / drain region 112 is electrically coupled and / or physically coupled to the source / drain contact structure 122. The source / drain contact structure 122 may include contact vias, contact plugs, and / or other types of contact structures that electrically connect the source / drain region 112 of the integrated circuit device 110 to the interconnect layer 104 of the semiconductor device 100. The source / drain contact structure 122 includes cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), copper (Cu), and / or other conductive or metallic materials. One or more pad layers 124 may be included on the sidewalls of the source / drain contact structure 122. The pad layers 124 may include a barrier layer (included to prevent or minimize material diffusion from the source / drain contact structure 122 to the surrounding dielectric layer), an adhesive layer or glue layer (included to promote adhesion between the source / drain contact structure 122 and the surrounding dielectric layer), and / or other types of pads. Examples of materials for one or more of the padding layers 124 include titanium nitride (TiN), tantalum nitride (TaN), and / or other suitable padding materials.

[0036] Interconnect layer 104 of semiconductor device 100 is included above device layer 102 and integrated circuit device 110 along the z-direction of semiconductor device 100. Interconnect layer 104 includes a plurality of dielectric layers arranged in a direction approximately perpendicular to substrate layer 106 (e.g., the z-direction). The dielectric layers may include ILD layers 126 and ESL layers 128 arranged alternately along the z-direction. ILD layers 126 and ESL layers 128 may extend along the x-direction and / or y-direction of semiconductor device 100.

[0037] Each of the ILD layers 126 may comprise an oxide (e.g., silicon oxide (SiO2)). x The dielectric material can be an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorinated silicate glass (FSG), a tetraethyl orthosilicate (TEOS), a hydrogen silsesquioxane (HSQ), or other suitable dielectric materials. In some embodiments, the ILD layer 126 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x amorphous fluorinated carbon (aC) x F y), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbonate (SiOC) polymers, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE), and / or porous silica (SiO2) x )wait.

[0038] Each of the ESL 128 may include silicon nitride (Si) x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, ILD layers 126 and ESL 128 comprise different dielectric materials to provide etch selectivity, enabling the formation of various structures in interconnect layer 104.

[0039] The metallization structure 130 and the interconnect structure 132 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials. In some embodiments, one or more padding layers are included between the metallization structure 130 and / or the interconnect structure 132 and the surrounding dielectric layer in the interconnect layer 104. The one or more padding layers may include barrier pads, adhesive pads, and / or other types of pads. Examples of materials for the one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN), etc.

[0040] In some embodiments, the metallization structure 130 and the interconnect structure 132 of the interconnect layer 104 may be arranged vertically (e.g., along the z-direction). In other words, multiple stacked metallization structures 130 and interconnect structures 132 may extend between the top of the device layer 102 and the interconnect layer 104 to facilitate the transmission of electrical signals and / or power between the device layer 102 and the connection structure (not shown) of the semiconductor device 100. Multiple stacked metallization structures 130 may be arranged in a layer that may be referred to as the M layer, and multiple stacked interconnect structures 132 may be arranged in a layer that may be referred to as the V layer.

[0041] The bottommost interconnect structure in interconnect layer 104 includes multiple conductive structures. These conductive structures are electrically and / or physically coupled to one or more integrated circuit devices 110 in device layer 102 and / or interconnect layer 104. The conductive structures enable the supply of signals and / or power to and / or from integrated circuit devices 110.

[0042] The conductive structure includes a combination of metallization structure 130 and interconnect structure 132. Metallization structure 130 may include trenches, conductive traces, and / or other types of conductive structures extending primarily along the x-direction and / or y-direction of interconnect layer 104. Interconnect structure 132 may include vias, plugs, conductive pillars, and / or other types of conductive structures extending primarily along the z-direction of the semiconductor device. In some embodiments, the conductive structure in interconnect layer 104 includes a dual damascene structure, which comprises a combination of metallization structure 130 and interconnect structure 132.

[0043] Interconnect structures 132 in interconnect layer 104 are electrically connected to the gate structure 116 and source / drain contact structure 122 of integrated circuit device 110. The bottommost interconnect structure 132 includes a source / drain interconnect structure 134 electrically coupled and / or physically coupled to the source / drain contact structure 122, and a gate interconnect structure 136 electrically coupled and / or physically coupled to the gate structure 116. In some embodiments, a gate contact (not shown) is included between the gate structure 116 and the gate interconnect structure 136. In some embodiments, the bottommost interconnect structure 132 is referred to as a via-0 (V0) layer, the source / drain interconnect structure 134 is referred to as a source / drain via (VD), and the gate interconnect structure 136 is referred to as a gate via (VG).

[0044] A metal-0 (M0) layer may be located above the source / drain interconnect structure 134 and the gate interconnect structure 136. A metallization structure 130 in the M0 layer may be coupled to the source / drain interconnect structure 134 and the gate interconnect structure 136. A via-1 (V1) layer, including one or more interconnect structures 132, may be included above the M0 layer. A metal-1 (M1) layer may be located above the V1 layer in interconnect layer 104, a via-2 (V2) layer may be included above the M1 layer, a metal-2 (M2) layer may be located above the V2 layer, and so on.

[0045] FIG. 1B A detailed diagram shows the connection between the source / drain contact structure 122 and the source / drain interconnect structure 134 of the semiconductor device 100. (See diagram for reference.) FIG. 1B As shown, the source / drain contact structure 122 may be included in the dielectric layer 108. The ESL 128 of the interconnect layer 104 may be included on the source / drain contact structure 122. The ILD layer 126 (e.g., ILD1 layer) of the interconnect layer 104 may be included on the ESL 128.

[0046] like FIG. 1BAs further shown, the source / drain interconnect structure 134 is located above and / or on the source / drain contact structure 122, such that the source / drain contact structure 122 and the source / drain interconnect structure 134 are vertically aligned (e.g., along the z-direction) in the semiconductor device 100. The top surface of the source / drain contact structure 122 is located below the ESL 128 and includes a recess 138 filled by the bottom of the source / drain interconnect structure 134. Therefore, the top surface of the source / drain contact structure 122 is recessed below the ESL 128, and the bottom of the source / drain interconnect structure 134 is recessed in the top surface of the source / drain contact structure 122.

[0047] The recess 138 in the top surface of the source / drain contact structure 122 is due to a pre-cleaning process performed on the top surface of the source / drain contact structure 122 before forming the source / drain interconnect structure 134, to remove the metal oxide layer (e.g., native oxide) from the top surface of the source / drain contact structure 122. FIG. 3A-FIG. 3H An example pre-cleaning process is described.

[0048] The recess 138 provides an increased surface area contact between the top surface of the source / drain contact structure 122 and the bottom of the source / drain interconnect structure 134. The source / drain contact structure 122 and the source / drain interconnect structure 134 may comprise different types of metals (e.g., the source / drain contact structure 122 may comprise tungsten (W), and the source / drain interconnect structure 134 may comprise copper (Cu)), and the different metal interfaces between the source / drain contact structure 122 and the source / drain interconnect structure 134 can generate increased contact resistance between them. Therefore, the recess 138 can offset some of the increased contact resistance and / or achieve a lower overall contact resistance.

[0049] like FIG. 1B As further shown, due to the recess 138, the bottom of the source / drain interconnect structure 134 is located below the bottom of the ESL 128. The bottom surface of the source / drain interconnect structure 134 may have a circular cross-sectional profile that matches the cross-sectional profile of the top surface of the source / drain contact structure 122.

[0050] like FIG. 1BAs further shown, the source / drain contact structure 122 and / or the source / drain interconnect structure 134 may have one or more example dimensions. Example dimension D1 corresponds to the top lateral width (e.g., top width) of the source / drain interconnect structure 134, and another example dimension D2 corresponds to the bottom lateral width (e.g., bottom width) of the source / drain interconnect structure 134. Dimensions D1 and D2 may each include a range from about 3 nanometers to about 50 nanometers. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, dimension D1 is larger than dimension D2, such that the sidewalls of the source / drain interconnect structure 134 are angled outward from the center of the source / drain interconnect structure 134, and such that the lateral width of the source / drain interconnect structure 134 decreases from dimension D1 to dimension D2.

[0051] In some embodiments, dimension D2 also corresponds to the top lateral width of the top surface of the source / drain contact structure 122. In some embodiments, the top lateral width of the top surface of the source / drain contact structure 122 is greater than dimension D2, such that the top surface of the source / drain contact structure 122 extends laterally outward from the bottom of the source / drain interconnect structure 134, such as... FIG. 5A-FIG. 5E The examples are shown in the document.

[0052] Another example dimension D3 corresponds to the z-direction height (or vertical thickness) of the source / drain interconnect structure 134. In some embodiments, dimension D3 includes a range of about 15 nanometers to about 45 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0053] Another example dimension D4 corresponds to the z-direction height (or vertical thickness) of the source / drain contact structure 122. In some embodiments, dimension D3 includes a range of about 15 nanometers to about 45 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0054] In some embodiments, the ratio of dimension D3 to dimension D4 is included in the range of about 1:4 to about 45:1. However, other values ​​and ranges are within the scope of this disclosure.

[0055] Another example dimension D5 includes the z-direction depth of the recess 138. The z-direction depth of the recess 138 corresponds to the vertical (e.g., z-direction) distance between the lowest portion of the recess 138 and the bottom of the ESL 128. In some embodiments, dimension D5 includes a range of about 0.5 nanometers to about 5 nanometers. If dimension D5 is outside this range, the metal oxide layer formed on the top surface of the source / drain contact structure 122 may not be completely removed, resulting in increased contact resistance between the source / drain contact structure 122 and the source / drain interconnect structure 134. However, other values ​​and ranges are within the scope of this disclosure.

[0056] Another example dimension D6 includes the vertical (e.g., z-direction) distance between the lowest portion of the recess 138 and the top of the ESL 128. In some embodiments, dimension D6 includes a range of about 3 nanometers to about 12 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0057] As mentioned above, FIG. 1A and FIG. 1B Provided as an example. Other examples may be related to... FIG. 1A and FIG. 1B The differences are as described.

[0058] FIG. 2A-FIG. 2E This is an illustration of an exemplary embodiment 200 that forms the semiconductor device 100 described herein. In some embodiments, combined with FIG. 2A-FIG. 2E The one or more semiconductor processing operations described can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor processing tools.

[0059] Go to FIG. 2A A substrate 106 is provided. The substrate 106 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, a silicon-on-insulator (SOI) wafer, and / or other types of semiconductor workpieces. The semiconductor device 100 may be formed on the semiconductor wafer together with other semiconductor devices.

[0060] A layer stack can be formed on the substrate 106. The layer stack may be referred to as a superlattice. The layer stack may include multiple alternating layers arranged in a direction approximately perpendicular to the substrate 106 (e.g., the z-direction). For example, the layer stack may include vertically alternating sacrificial layers 202 and nanostructured channel layers 204 on the substrate 106. FIG. 2A The number of sacrificial layers 202 and nanostructured channel layers 204 shown are examples, and other numbers of sacrificial layers 202 and nanostructured channel layers 204 are within the scope of this disclosure.

[0061] The sacrificial layer 202 enables the definition of a vertical distance between adjacent nanostructure channels formed by the nanostructure channel layer 204 and serves as a placeholder layer for the subsequently formed gate structures of the integrated circuit device 110 of the semiconductor device 100, which are formed around the nanostructure channels.

[0062] The sacrificial layer 202 comprises a first material component, and the nanostructured channel layer 204 comprises a second material component. In some embodiments, the first and second material components are the same material component. In some embodiments, the first and second material components are different material components. For example, the sacrificial layer 202 may comprise silicon germanium (SiGe), and the nanostructured channel layer 204 may comprise silicon (Si). This allows the sacrificial layer 202 and / or the nanostructured channel layer 204 to be selectively etched depending on the type of etchant used (e.g., etching the sacrificial layer 202 without etching the nanostructured channel layer 204, or etching the nanostructured channel layer 204 without etching the sacrificial layer 202).

[0063] One or more types of deposition tools can be used to deposit and / or grow alternating layers of stacked layers to include nanostructures (e.g., nanosheets) on substrate layer 106. For example, the sacrificial layer 202 and / or the nanostructured channel layer 204 can be grown via epitaxial growth using deposition tools, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or other suitable epitaxial techniques. Additionally and / or alternatively, the sacrificial layer 202 and / or the nanostructured channel layer 204 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition techniques.

[0064] Along the y direction (in FIG. 2A (Not visible in the diagram), the layer stack and substrate 106 can be etched to form a fin structure extending along the x-direction. The fin structure may include a portion of the layer stack and a portion of the substrate 106 beneath the layer stack. The fin structure can be formed by patterning one or more masking layers and etching based on the pattern formed in the one or more masking layers. One or more masking layers can be patterned using photolithography techniques, including dual-patterning or multi-patterning techniques. The layer stack and substrate 106 can be etched based on the pattern using etching tools employing dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof. In some embodiments, shallow trench isolation (STI) regions (not shown) may be formed between adjacent fin structures along the y-direction.

[0065] like FIG. 2BAs shown, a dummy gate structure 206 (also called a dummy gate stack or temporary gate structure) can be formed on some portions of the stack of sacrificial layer 202 and nanostructured channel layer 204. The dummy gate structure 206 can extend along the y-direction and can be aligned along the x-direction such that the dummy gate structure 206 is substantially perpendicular to the fin structure. The dummy gate structure 206 is a sacrificial structure that will be replaced by a replacement gate structure or replacement gate stack in subsequent processing stages of the integrated circuit device 110 of the semiconductor device 100. The dummy gate structure 206 can also be used to define a source / drain (S / D) recess in which the source / drain regions of the nanostructured transistor are formed in the stack of sacrificial layer 202 and nanostructured channel layer 204.

[0066] The dummy gate structure 206 may include polysilicon (polysilicon or PO) or other materials. The layers of the dummy gate structure 206 may be formed using various semiconductor processing techniques, such as depositing the layers of the dummy gate structure 206, patterning the layers of the dummy gate structure 206 to define the dummy gate structure 206, and / or other semiconductor processing techniques. Sidewall spacers 120a may be formed on the sidewalls of the dummy gate structure 206.

[0067] like FIG. 2C As shown, the source / drain region 112 of the integrated circuit device 110 is formed in a layer stack of sacrificial layer 202 and nanostructured channel layer 204. To form the source / drain region 112, source / drain recesses can be formed in an etching operation through the layer stack of sacrificial layer 202 and nanostructured channel layer 204. The source / drain recesses can be formed on opposite sides of the dummy gate structure 206 along the x-direction. The etching operation can be performed using an etching tool and may be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes using plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques.

[0068] The formation of source / drain recesses may define a channel layer 118. The channel layer 118 may include silicon-based nanostructures (e.g., nanosheets or nanowires) that serve as semiconductor channels for the integrated circuit device 110 of the semiconductor device 100. The channel layer 118 is aligned in a direction approximately perpendicular to the substrate layer 106 (e.g., the z-direction). In other words, the channel layer 118 is vertically aligned or stacked on the substrate layer 106.

[0069] Before forming the source / drain region 112 in the source / drain recess, the ends of the sacrificial layer 202 exposed in the source / drain recess can be laterally etched during an etching operation, thereby forming a cavity in the ends of the sacrificial layer 202. An internal spacer 120b can be formed in the cavity. To form the internal spacer 120b, a dielectric material layer can be deposited in the cavity and along the sidewalls and bottom surface of the source / drain recess using a deposition tool. CVD, PVD, ALD, and / or other deposition techniques can be used to deposit the dielectric material layer. An etching tool is then used to remove excess material from the source / drain recess, such that the remaining portion corresponds to the internal spacer 120b in the cavity.

[0070] After forming the internal spacer 120b, the source / drain recess can be filled with one or more layers of epitaxial material to form the source / drain region 112 within the source / drain recess. For example, a buffer region can be deposited at the bottom of the source / drain recess using a deposition tool, and the deposition tool can deposit the source / drain region 112 on the buffer region within the source / drain recess. In some embodiments, a capping layer is deposited on the source / drain region 112 within the source / drain recess using a deposition tool. As another example, the deposition tool can epitaxially grow a first layer (referred to as L1) of the source / drain region 112 over a relevant buffer region (which may be referred to as L0), and can epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 112 over the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or other dopants) and may be included as a shielding layer to reduce short-channel effects in the semiconductor device 100 and reduce dopants squeezed out or migrated into the channel layer 118. The second layer may include highly doped silicon or highly doped silicon-germanium. The second layer may be included to provide compressive stress in the source / drain regions 112 to reduce boron losses.

[0071] like FIG. 2C As further shown, a dielectric layer 108 may be formed over the source / drain regions 112 and around the dummy gate structure 206. The dielectric layer 108 may fill the regions between the dummy gate structures 206. In some embodiments, a contact etch stop layer (CESL) is conformally deposited over the source / drain regions 112 (e.g., by a deposition tool) before forming the dielectric layer 206. The dielectric layer 108 is then formed on the CESL. The CESL may provide a mechanism to stop the etch process when forming the source / drain contacts 122 for the source / drain regions 112. The CESL may be formed of a dielectric material having a different etch selectivity than adjacent layers or elements. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may include or may be silicon nitride (Si).x N y Silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon carbon oxide (SiCO), or combinations thereof. CESL can be deposited using deposition processes, such as ALD, CVD, or other deposition techniques.

[0072] like FIG. 2D As shown, a gate replacement process can be performed to replace the dummy gate structure 206 with the gate structure 116 of the integrated circuit device 110. A dummy gate removal operation can be performed to remove the dummy gate structure 206 from the semiconductor device 100. Removing the dummy gate structure 206 leaves an opening (or recess) in the dielectric layer 108 and provides access to the underlying sacrificial layer 202. The dummy gate structure 206 can be removed in one or more etching operations. Such etching operations may include plasma etching, wet chemical etching, and / or other types of etching techniques.

[0073] The gate replacement process may include a nanostructure release operation (e.g., a SiGe release operation). The nanostructure release operation is performed to remove the sacrificial layer 202 (e.g., a silicon-germanium layer). This creates openings between the channel layers 118 (e.g., in the region surrounding the channel layers 118). The sacrificial layer 202 can be removed through the space previously occupied by the dummy gate structure 206. The nanostructure release operation may include performing an etching operation using an etching tool to remove the sacrificial layer 202 based on the etch selectivity differences between the materials of the sacrificial layer 202 and the channel layers 118, and between the materials of the sacrificial layer 202 and the internal spacer 120b. The internal spacer 120b may be used as an etch stop layer in the etching operation to protect the source / drain regions 112 from etching.

[0074] The gate replacement operation involves forming a gate dielectric layer 114 and a gate structure (e.g., a replacement gate structure) 116 of the integrated circuit device 110 in openings between the source / drain regions 112 and between the internal spacers 120b. Specifically, the gate dielectric layer 114 and the gate structure 116 fill the regions between and around the channel layers 118 previously occupied by the sacrificial layer 202, such that the gate structure 116 completely surrounds and encloses the channel layers 118. This improves control over the channel layers 118, increases the drive current of the integrated circuit device 110, and / or reduces the short-channel effect (SCE) of the integrated circuit device 110, etc. The gate structure 116 may also fill the space previously occupied by the dummy gate structure 206. Some portions of the gate structure 116 are formed in an alternating vertical arrangement between pairs of channel layers 118. In other words, the semiconductor device 100 includes one or more vertically stacked portions of alternating channel layers 118 and gate structures 116.

[0075] likeFIG. 2D As further shown, the source / drain contact structure 122 of the integrated circuit device 110 can be formed through the dielectric layer 108. The source / drain contact structure 122 can be formed in a recess in the dielectric layer 108. In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 108 to form the recess. In these embodiments, the photoresist layer can be formed on the dielectric layer 108 using a deposition tool. The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer based on the pattern to form the recess. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portions of the photoresist layer can be removed using a photoresist removal tool (e.g., using chemical stripping, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique for pattern-based etching of the dielectric layer 108 to form recesses.

[0076] Source / drain contact structure 122 may be formed in a recess such that the source / drain contact structure 122 rests on the source / drain region 112. Material for the source / drain contact structure 122 may be deposited in the recess using deposition tools employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The material for the source / drain contact structure 122 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the material for the source / drain contact structure 122 is deposited on the seed layer. In some embodiments, one or more pad layers 124 are deposited in the recess, and the source / drain contact structure 122 is deposited on (one or more) pad layers 124. In some embodiments, after depositing the source / drain contact structure 122, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the source / drain contact structure 122 such that the top of the source / drain contact structure 122 is approximately coplanar with the top of the dielectric layer 108.

[0077] like FIG. 2EAs shown, an interconnect layer 104 of the semiconductor device 100 is formed on top of a dielectric layer 108. Alternating layers of ILD layers 126 and ESL layers 128 are deposited in the interconnect layer 104 of the semiconductor device 100 using one or more deposition tools. In this way, the ILD layers 126 and ESL layers 128 can be aligned along the z-direction of the semiconductor device 100. Each ILD layer 126 and each ESL layer 128 can be deposited using one or more deposition tools employing PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, after depositing the ILD layers 126 and / or ESL layers 128, a planarization tool can be used to planarize the ILD layers 126 and / or ESL layers 128.

[0078] like FIG. 2E As further shown, various operations can be performed using deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form source / drain interconnect structures 134 and / or gate interconnect structures 136 on the bottom of interconnect layer 104. One or more source / drain interconnect structures 134 may be formed on one or more source / drain contact structures 122 of one or more integrated circuit devices 110. One or more gate interconnect structures 136 may be formed on one or more gate structures 116 of one or more integrated circuit devices 110.

[0079] Various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form metallization structures 130 and interconnect structures 132 in the interconnect layer 104 of the semiconductor device 100. In some embodiments, the interconnect layer 104 may be formed as a multilayer. For example, ILD layers 126 and ESL 128 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), recesses may be formed in and / or through ILD layers 126 and ESL 128 (e.g., using exposure tools, developing tools, and / or etching tools), and a metallization structure 130 (e.g., an MO layer) may be formed in ILD layers 126 and ESL 128 (e.g., using one or more deposition tools and / or one or more planarization tools). Another ILD layer 126 and another ESL 128 may be formed, and an interconnect structure 132 (e.g., V1 layer) may be formed in the ILD layer 126 and ESL 128. The metallization structure 130 of the additional layer and the interconnect structure 132 of the additional layer may be formed in a similar manner.

[0080] The source / drain interconnect structure 134, gate interconnect structure 136, metallization structure 130, and / or interconnect structure 132 can be deposited using one or more deposition tools employing PVD, ALD, CVD, electroplating (e.g., electrochemical plating) and / or other suitable deposition techniques. In some embodiments, after depositing the source / drain interconnect structure 134, gate interconnect structure 136, metallization structure 130, and / or interconnect structure 132, a planarization tool can be used to planarize the source / drain interconnect structure 134, gate interconnect structure 136, metallization structure 130, and / or interconnect structure 132.

[0081] As mentioned above, FIG. 2A-FIG. 2E Provided as an example. Other examples may be related to... FIG. 2A-FIG. 2E The differences are as described.

[0082] FIG. 3A-FIG. 3H This is an illustration of an example embodiment 300 forming the source / drain interconnect structure 134 described herein. In some embodiments, combined with FIG. 3A-FIG. 3H The described one or more semiconductor processing operations can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor processing tools. In some embodiments, combined with FIG. 3A-FIG. 3H One or more semiconductor processing operations described can be used as a means to form a bond. FIG. 2A-FIG. 2E The process of the semiconductor device 100 shown and described is performed as part of the process.

[0083] like FIG. 3A As shown, the source / drain contact structure 122 of the semiconductor device 100 may be formed in the dielectric layer 108. An ESL 128 may be formed on and / or on the dielectric layer 108, and on and / or on the source / drain contact structure 122, such that the ESL 128 covers the top surface of the source / drain contact structure 122.

[0084] like FIG. 3B As shown, a recess 302 is formed through the ILD layer 126 and the ESL 128. The recess 302 is formed to the source / drain contact structure 122 such that the top surface of the source / drain contact structure 122 is exposed in the recess 302.

[0085] In some embodiments, the ILD layer 126 and / or ESL 128 are etched using a pattern in the photoresist layer to form the recess 302. In these embodiments, the photoresist layer can be formed on the ILD layer 126 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The ILD layer 126 and / or ESL 128 can be etched using an etchant 304 based on the pattern using an etching tool to form the recess 302. In some embodiments, the etching operation includes dry etching operations (e.g., etching operations using plasma-based etchant 304, etching operations using gas-based etchant 304), wet chemical etching operations (e.g., etching operations using wet chemical etchant 304), and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using chemical stripping, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based recess 302.

[0086] like FIG. 3C As shown, a metal oxide layer 306 can be formed in the recess 302 on the top surface of the source / drain contact structure 122. The metal oxide layer 306 may be referred to as "native oxide" because it is formed naturally due to oxidation of the top surface of the source / drain contact structure 122. The top surface of the source / drain contact structure 122 may be oxidized due to exposure to various oxygen sources, such as oxygen in the atmosphere of the etching tool's processing chamber, oxygen in the atmosphere of the semiconductor manufacturing equipment that manufactures the semiconductor device 100, and / or oxygen from other oxygen sources. In some embodiments, the top surface of the source / drain contact structure 122 may be oxidized due to exposure to oxygen while queuing for the next processing step of the semiconductor device 100.

[0087] The metal oxide layer 306 may correspond to the portion of the top surface of the source / drain contact structure 122 to which atmospheric oxygen has bonded. Therefore, the metal oxide layer 306 comprises the metal of the source / drain contact structure 122 and extends below the ESL 128. For example, if the source / drain contact structure 122 comprises tungsten (W), then the metal oxide layer 306 may comprise oxidized tungsten (or tungsten oxide (WO)). x (e.g., WO3). As another example, if the source / drain contact structure 122 includes molybdenum (Mo), then the metal oxide layer 306 may include oxidized molybdenum (or molybdenum oxide (MoO)). x (e.g., MoO3).

[0088] likeFIG. 3D and FIG. 3E As shown, a pre-cleaning operation can be performed to remove the metal oxide layer 306 from the top surface of the source / drain contact structure 122. The metal oxide layer 306 can be removed from the top surface of the source / drain contact structure 122 to provide a bare metal substrate on which the source / drain interconnect structure 134 will be formed in the recess 302 on the source / drain contact structure 122.

[0089] In some embodiments, the pre-cleaning operation is performed in the processing chamber of a deposition tool, such as a CVD or PVD tool. This allows the pre-cleaning operation to be performed in the same processing chamber used for depositing the source / drain interconnect structure 134. In other words, the pre-cleaning operation and the deposition of the material for the source / drain interconnect structure 134 can be performed in the same processing chamber of the deposition tool. This allows the pre-cleaning operation and the deposition of the material for the source / drain interconnect structure 134 to be performed under the same vacuum (e.g., while maintaining a vacuum in the processing chamber), reducing the likelihood that the metal oxide layer 306 will regrow on the top surface of the source / drain contact structure 122 in the recess 302 before the source / drain interconnect structure 134 is formed.

[0090] like FIG. 3D As shown, the pre-cleaning operation includes the use of pre-cleaning agent 308. Pre-cleaning agent 308 may include wet chemical pre-cleaning agents, dry gas pre-cleaning agents, and / or other types of pre-cleaning agents. Pre-cleaning agent 308 is provided into recess 302 (e.g., using a deposition tool or a dedicated pre-cleaning tool) such that the metal oxide layer 306 is immersed in pre-cleaning agent 308 for a period of time.

[0091] Pre-cleaning agent 308 includes a metal precursor for etching or removing material from metal oxide layer 306. For example, pre-cleaning agent 308 may include a halogen-based metal precursor, such as a transition metal halide. Examples of transition metal halides used for pre-cleaning agent 308 may include tungsten fluoride (e.g., WF6), tungsten chloride (e.g., WCl6, WCl5), molybdenum chloride (e.g., MoCl6, MoCl5), tantalum chloride (e.g., TaCl5), and / or titanium chloride (e.g., TiCl4), etc. In some embodiments, pre-cleaning agent 308 includes a metal precursor of the material for source / drain contact structure 122. In some embodiments, pre-cleaning agent 308 includes a metal precursor of the material for source / drain interconnect structure 134. In these embodiments, the pre-cleaning operation can be performed as part of depositing source / drain interconnect structure 134, reducing the process complexity of fabricating semiconductor device 100.

[0092] The metal precursor of the pre-cleaner 308 selectively etches the metal oxide layer 306, with minimal etching to the point of not etching the ILD layer 126 and / or ESL 128. In this way, the pre-cleaner 308 removes the metal oxide layer 306, with minimal widening to the point of not widening the recess 302. Therefore, using a metal precursor for the pre-cleaner 308 makes it possible to maintain the aspect ratio (e.g., the height-to-width ratio) of the recess 302.

[0093] In some embodiments, the metal precursor of the pre-cleaning agent 308 is a tungsten precursor. For example, the tungsten precursor may be tungsten fluoride (WF). x (e.g., tungsten fluoride gas), for example, tungsten hexafluoride (WF6). In these embodiments, the pre-cleaning operation can be performed in a treatment chamber at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius to promote the reaction between the tungsten fluoride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are within the scope of this disclosure. Additionally and / or alternatively, the pre-cleaning operation can be performed in a treatment chamber at a pressure ranging from about 0.1 Torr to about 50 Torr to promote the reaction between the tungsten fluoride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are within the scope of this disclosure.

[0094] As another example, the tungsten precursor can be tungsten chloride (WCl). x (e.g., tungsten chloride gas, tungsten chloride liquid), for example, tungsten hexachloride (WCl6). In these embodiments, the pre-cleaning operation can be performed in a treatment chamber at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius to promote the reaction between the tungsten chloride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are within the scope of this disclosure. Additionally and / or alternatively, the pre-cleaning operation can be performed in a treatment chamber at a pressure ranging from about 0.1 Torr to about 50 Torr to promote the reaction between the tungsten chloride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are within the scope of this disclosure.

[0095] In some embodiments, the metal precursor of the pre-cleaning agent 308 is a molybdenum precursor. For example, the molybdenum precursor may be molybdenum fluoride (MoF2). x(e.g., molybdenum fluoride gas), for example, molybdenum hexafluoride (MoF6). In these embodiments, the pre-cleaning operation can be performed in a treatment chamber at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius to promote the reaction between the molybdenum fluoride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are within the scope of this disclosure. Additionally and / or alternatively, the pre-cleaning operation can be performed in a treatment chamber at a pressure ranging from about 0.1 Torr to about 260 Torr to promote the reaction between the molybdenum fluoride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are within the scope of this disclosure.

[0096] As another example, the molybdenum precursor can be molybdenum chloride (MoCl₂). x (e.g., molybdenum chloride gas, molybdenum chloride liquid), for example, molybdenum pentachloride (MoCl5). In these embodiments, the pre-cleaning operation can be performed in a treatment chamber at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius to promote the reaction between the molybdenum chloride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are within the scope of this disclosure. Additionally and / or alternatively, the pre-cleaning operation can be performed in a treatment chamber at a pressure ranging from about 0.1 Torr to about 260 Torr to promote the reaction between the molybdenum chloride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are within the scope of this disclosure.

[0097] like FIG. 3E As shown, the pre-cleaning operation causes the top surface of the source / drain contact structure 122 to become recessed. The pre-cleaning agent 308 removes metal and oxygen components from the metal oxide layer 306, which corresponds to the metal in the source / drain contact structure 122. Therefore, removing the metal oxide layer 306 using the pre-cleaning agent 308 removes metal from the top surface of the source / drain contact structure 122.

[0098] FIG. 3F An alternative embodiment is shown in which a residual layer 310 remains on the top surface of the source / drain contact structure 122 after the pre-cleaning operation. The residual layer 310 may be a metallic element from the pre-cleaning agent 308. For example, if molybdenum chloride (MoCl₂) is used... x As a pre-cleaning agent, the residual layer 310 may include a layer of molybdenum on the surface of the source / drain contact structure 122. Therefore, if the source / drain contact structure 122 is formed of tungsten (W), the top surface of the source / drain contact structure 122 may have a thin layer of molybdenum.

[0099] like FIG. 3GAs shown, material for the source / drain interconnect structure 134 is formed on the top surface of the source / drain contact structure 122 in the recess 302. The material for the source / drain interconnect structure 134 fills the recess 302. The material for the source / drain interconnect structure 134 can be deposited using a deposition tool (e.g., the same deposition tool using the same processing chamber for performing pre-cleaning operations) employing CVD, ALD, PVD, electroplating, and / or other suitable deposition techniques.

[0100] A metal precursor can be used to deposit the material of the source / drain interconnect structure 134. The metal precursor can be the same as the metal precursor used in the pre-cleaning agent 308 for the pre-cleaning operation, or it can be a different metal precursor. The metal precursor used to deposit the material of the source / drain interconnect structure 134 can be selectively deposited on a metal, such as the top surface of the source / drain contact structure 122. This allows the material of the source / drain interconnect structure 134 to be deposited in a "bottom-up" material growth manner, wherein the material of the source / drain interconnect structure 134 accumulates on the top surface of the source / drain contact structure 122, and not on the sidewalls of the recesses 302 corresponding to the ILD layers 126 and ESL 128. The bottom-up material growth manner of the source / drain interconnect structure 134 reduces the likelihood of voids forming in the source / drain interconnect structure 134.

[0101] In some embodiments, the source / drain interconnect structure 134 is formed of tungsten (W) and a tungsten precursor for depositing the source / drain interconnect structure 134. For example, the tungsten precursor may be tungsten fluoride (WF). x (For example, tungsten fluoride gas), such as tungsten hexafluoride (WF6). As another example, the tungsten precursor can be tungsten chloride (WCl). x (e.g., tungsten chloride gas, tungsten chloride liquid), for example, tungsten hexachloride (WCl6). The material using the tungsten precursor to deposit the source / drain interconnect structure 134 can be deposited in the processing chamber of a deposition tool at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius. However, other values ​​and ranges are within the scope of this disclosure. Additionally and / or alternatively, the material using the tungsten precursor to deposit the source / drain interconnect structure 134 can be deposited in the processing chamber at a pressure ranging from about 0.1 Torr to about 50 Torr. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, the tungsten precursor may or may not be used with a processing gas (e.g., hydrogen (H2) gas and / or ammonia (NH3) gas, etc.).

[0102] In some embodiments, the source / drain interconnect structure 134 is formed from molybdenum (Mo) and a molybdenum precursor for depositing the source / drain interconnect structure 134. For example, the molybdenum precursor may be molybdenum fluoride (MoF). x(e.g., molybdenum fluoride gas), for example, molybdenum hexafluoride (MoF6). The deposition of the source / drain interconnect structure 134 using molybdenum fluoride as a precursor can be performed in the processing chamber of a deposition tool at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, the deposition of the source / drain interconnect structure 134 using molybdenum fluoride as a precursor can be performed in a processing chamber at a pressure ranging from about 0.1 Torr to about 260 Torr. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, molybdenum fluoride may or may not be used with a process gas (e.g., hydrogen (H2) gas, etc.).

[0103] As another example, the molybdenum precursor can be molybdenum chloride (MoCl₂). x (e.g., molybdenum chloride gas, molybdenum chloride liquid), for example, molybdenum pentachloride (MoCl5). The deposition of the source / drain interconnect structure 134 using molybdenum chloride as a precursor can be performed in the processing chamber of a deposition tool at a temperature ranging from about 300 degrees Celsius to about 450 degrees Celsius. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, the deposition of the source / drain interconnect structure 134 using molybdenum chloride as a precursor can be performed in a processing chamber at a pressure ranging from about 0.1 Torr to about 300 Torr. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, molybdenum chloride may or may not be used with a process gas (e.g., hydrogen (H2) gas, etc.).

[0104] In some embodiments, the source / drain interconnect structure 134 is formed of ruthenium (Ru) and a ruthenium precursor for depositing the source / drain interconnect structure 134. For example, the ruthenium precursor may be ruthenium oxide (RuO). x (e.g., RuO2). The deposition of the source / drain interconnect structure 134 using ruthenium oxide as a precursor can be performed in the processing chamber of a deposition tool at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, the deposition of the source / drain interconnect structure 134 using ruthenium oxide as a precursor can be performed in a processing chamber at a pressure ranging from about 0.1 Torr to about 260 Torr. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, the ruthenium precursor may or may not be used with a process gas (e.g., hydrogen (H2) gas, etc.).

[0105] In some embodiments, the source / drain interconnect structure 134 is formed from cobalt (Co) and a cobalt precursor for depositing the source / drain interconnect structure 134. For example, the cobalt precursor may be cobalt chloride (CoCl). xFor example, CoCl2); cobalt sulfate (CoS) x ) and cobalt oxide (CoO) y A combination of [various agents]; and / or other cobalt precursors. In some embodiments, the cobalt precursor may or may not be with a treatment agent (e.g., dimethylamine borane (DMAB), ammonium chloride (NH4Cl) and / or boron hydroxide (BO). x H y (etc.) are used together. In some embodiments, the pH value of the chemical being treated may include a range of about 6 to about 9. However, other values ​​and ranges are within the scope of this disclosure.

[0106] In some embodiments, the source / drain interconnect structure 134 is formed of copper (Cu) and a copper precursor for depositing the source / drain interconnect structure 134. For example, the copper precursor may be copper chloride (CuCl). x For example, CuCl2; copper sulfate (CoS) x ) and copper oxide (CoO) y A combination of [various copper precursors]; and / or other copper precursors. In some embodiments, the copper precursor may or may not be with a treatment agent (e.g., a cobalt / carbon / hydrogen / nitrogen compound (CoC)). x H y N z ) and / or carbon hydroxide (CH) x O y (e.g., etc.) are used together. In some embodiments, the pH value of the chemical being treated may include a range of about 7 to about 10. However, other values ​​and ranges are within the scope of this disclosure.

[0107] like FIG. 3H As shown, a planarization operation (e.g., CMP operation) can be performed using a planarization tool to planarize the source / drain interconnect structure 134. In this way, the top surface of the source / drain interconnect structure 134 can be substantially coplanar with the top surface of the ILD layer 126.

[0108] As mentioned above, FIG. 3A-FIG. 3H Provided as an example. Other examples may be related to... FIG. 3A-FIG. 3H The differences are as described.

[0109] FIG. 4A-FIG. 4D This is an illustration of an example embodiment of the source / drain contact structure 122 and the source / drain interconnect structure 134 of the semiconductor device 100 described herein. FIG. 4A An example embodiment 400 of the source / drain contact structure 122 and the source / drain interconnect structure 134 is shown. FIG. 4A As shown, the source / drain contact structure 122 and source / drain interconnect structure 134 in the example embodiment 400 are similar to FIG. 1BThe source / drain interconnect structure 134 in the example implementation shown.

[0110] However, in example embodiment 400, the bottom portion of the source / drain interconnect structure 134 located in the recess 138 of the source / drain contact structure 122 includes an extension region 402 that extends laterally outward through the sidewall of the source / drain interconnect structure 134. This may be due to the bonding... FIG. 3D and FIG. 3E This is caused by lateral etching of the top surface of the source / drain contact structure 122 during the described pre-cleaning operation. In some embodiments, the lateral width (dimension D7) of the extended region 402 can be greater than 0 nanometers, with a maximum of about 5 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0111] like FIG. 4A As shown in the close-up diagram, the bottom portion of the source / drain interconnect structure 134 may have rounded corners. The angle (dimension D8) of the rounded corners may range from about 10 degrees to about 80 degrees. However, other values ​​and ranges are within the scope of this disclosure.

[0112] like FIG. 4A As further shown in the close-up illustration, the highest portion of the top surface of the source / drain contact structure 122 (e.g., the outer boundary of the source / drain contact structure 122) can be spaced apart from the bottom of the ESL 128 along the z-direction by a distance corresponding to dimension D9. In some embodiments, dimension D9 includes a range of about 0 nanometers to about 7 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0113] FIG. 4B An example embodiment 404 of the source / drain contact structure 122 and the source / drain interconnect structure 134 is shown. FIG. 4B As shown, the source / drain contact structure 122 and source / drain interconnect structure 134 in example embodiment 404 are similar to FIG. 1B The source / drain interconnect structure 134 in the example implementation shown.

[0114] However, in example embodiment 404, the source / drain interconnect structure 134 and the source / drain contact structure 122 may be partially offset from each other along the x-direction and / or y-direction of the semiconductor device 100. This partial offset may occur due to overlay misalignment during the formation of the recess 302. Therefore, the bottom surface of the source / drain interconnect structure 134 formed in the recess 302 may be laterally displaced relative to the top surface of the source / drain contact structure 122.

[0115] This may cause a portion 406 of the bottom surface of the source / drain interconnect structure 134 to contact the dielectric layer 108, and / or may cause a portion 408 of the top surface of the source / drain contact structure 122 to contact the ESL 128. In some embodiments, the lateral dimension (dimension D10) of portion 408 may include a range from about 0 nanometers to about 3 nanometers. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, the lateral dimension (dimension D11) of portion 406 may include a range from about 0 nanometers to about 3 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0116] FIG. 4C An example embodiment 410 is shown, comprising the source / drain contact structure 122 and the source / drain interconnect structure 134. (See example 410 410 410 5 ... FIG. 4B As shown, the source / drain contact structure 122 and source / drain interconnect structure 134 in Example Implementation 410 are similar to FIG. 1B The source / drain interconnect structure 134 in the example implementation shown.

[0117] However, in example implementation 410, the interface between the bottom surface of the source / drain interconnect structure 134 and the top surface of the source / drain contact structure 122 may be non-uniform and / or inconsistent, and may have inconsistent depths. This may result in various high and low points in the interface between the bottom surface of the source / drain interconnect structure 134 and the top surface of the source / drain contact structure 122. The maximum low point 412 may be the lowest point of the interface between the bottom surface of the source / drain interconnect structure 134 and the top surface of the source / drain contact structure 122, and the maximum high point 414 may be the highest point of the interface between the bottom surface of the source / drain interconnect structure 134 and the top surface of the source / drain contact structure 122. The interface between the bottom surface of the source / drain interconnect structure 134 and the top surface of the source / drain contact structure 122 may have various intermediate points 416, which may correspond to local high points and / or local low points.

[0118] In some embodiments, the z-direction distance (dimension D12) between the maximum low point 412 and the bottom of ESL 128 may range from about 0 nanometers to about 5 nanometers. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, the z-direction distance (dimension D13) between the maximum high point 414 and the bottom of ESL 128 may range from about 0 nanometers to about 3 nanometers. However, other values ​​and ranges are within the scope of this disclosure. In some embodiments, the z-direction difference (dimension D14) between dimensions D12 and D13 may range from about 0 nanometers to about 2 nanometers.

[0119] In some embodiments, the z-direction distance (dimension D15) between the midpoint 416 and the bottom of ESL 128 can be less than dimension D12 and greater than dimension D13. In some embodiments, there is a z-direction difference (dimension D16) between dimensions D13 and D14.

[0120] FIG. 4D An example embodiment 418 of the source / drain contact structure 122 and the source / drain interconnect structure 134 is shown. FIG. 4D As shown, the source / drain contact structure 122 and source / drain interconnect structure 134 in Example Implementation 418 are similar to FIG. 4C The example embodiment 410 shows a source / drain interconnect structure 134. However, in example embodiment 418, the lowest point 412 and the highest point 414 at the interface between the bottom surface of the source / drain interconnect structure 134 and the top surface of the source / drain contact structure 122 are located on opposite sides of the source / drain contact structure 122 and the source / drain interconnect structure 134. This interface can transition between the lowest point 412 located on the first side of the source / drain contact structure 122 and the first side of the source / drain interconnect structure 134, and the highest point 414 located on the second (opposite) side of the source / drain contact structure 122 and the second (opposite) side of the source / drain interconnect structure 134.

[0121] As mentioned above, FIG. 4A-FIG. 4D Provided as an example. Other examples may be related to... FIG. 4A-FIG. 4D The differences are as described.

[0122] FIG. 5A-FIG. 5E This is an illustration of an example embodiment of the source / drain contact structure 122 and the source / drain interconnect structure 134 of the semiconductor device 100 described herein. FIG. 5A An example embodiment 500 is shown, comprising a source / drain contact structure 122 and a source / drain interconnect structure 134. FIG. 5B An example embodiment 502 of the source / drain contact structure 122 and the source / drain interconnect structure 134 is shown. FIG. 5C An example embodiment 504 of the source / drain contact structure 122 and the source / drain interconnect structure 134 is shown. FIG. 5D An example embodiment 506 is shown, comprising the source / drain contact structure 122 and the source / drain interconnect structure 134. FIG. 5E An example embodiment 508 of the source / drain contact structure 122 and the source / drain interconnect structure 134 is shown.

[0123] FIG. 5A-FIG. 5E The example implementations 500-508 are respectively similar to FIG. 1B , FIG. 4A ,FIG. 4B , FIG. 4C and FIG. 4D Example embodiments 100, 400, 404, 410, and 418 of the source / drain contact structure 122 and the source / drain interconnect structure 134. However, in FIG. 5A-FIG. 5E In example embodiments 500-508, the top surface of the source / drain contact structure 122 is wider than the bottom surface of the source / drain interconnect structure 134. Therefore, in FIG. 5A-FIG. 5E In example embodiments 500-508, the top surface of the source / drain contact structure 122 extends laterally outward beyond one or more sides of the bottom surface of the source / drain interconnect structure 134. This can reduce the likelihood and / or amount of lateral misalignment between the source / drain contact structure 122 and the source / drain interconnect structure 134.

[0124] As mentioned above, FIG. 5A-FIG. 5E Provided as an example. Other examples may be related to... FIG. 5A-FIG. 5E The differences are as described.

[0125] FIG. 6 This is a flowchart of an example process 600 associated with forming the semiconductor device described herein. In some embodiments, FIG. 6 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools.

[0126] like FIG. 6 As shown, process 600 may include forming a recess in a dielectric layer within an interconnect layer of a semiconductor device (box 610). For example, a recess (e.g., recess 302) may be formed in a dielectric layer (e.g., ILD layer 126, ESL 128) within an interconnect layer (e.g., interconnect layer 104) of a semiconductor device (e.g., semiconductor device 100), as described herein, using one or more semiconductor processing tools. In some embodiments, the top surface of a contact structure of the semiconductor device (e.g., source / drain contact structure 122) is exposed via the recess.

[0127] like FIG. 6 As further shown, process 600 may include performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaner (block 620). For example, one or more semiconductor processing tools may be used to perform the pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaner (e.g., pre-cleaner 308), as described herein.

[0128] like FIG. 6As further shown, process 600 may include a conductive structure (box 630) in which an interconnect layer is formed on the top surface of the contact structure within the recess. For example, a conductive structure (e.g., source / drain interconnect structure 134) in which an interconnect layer is formed on the top surface of the contact structure within the recess may be formed using one or more semiconductor processing tools, as described herein.

[0129] Process 600 may include other implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other process descriptions described elsewhere herein.

[0130] In a first embodiment, performing the pre-cleaning operation includes performing a chemical immersion, wherein a metal precursor pre-cleaning agent is held on the top surface of the contact structure for a period of time.

[0131] In the second embodiment, either alone or in combination with the first embodiment, the metal precursor pre-cleaning agent includes a halogen-containing metal precursor.

[0132] In the third embodiment, the metal precursor pre-cleaner includes a fluorinated metal precursor, either alone or in combination with one or more of the first and second embodiments.

[0133] In the fourth embodiment, the metal precursor pre-cleaner includes a chlorinated metal precursor, either alone or in combination with one or more of the first to third embodiments.

[0134] In the fifth embodiment, the metal precursor pre-cleaner, alone or in combination with one or more of the first to fourth embodiments, comprises a metal precursor of the material in contact with the structure.

[0135] In the sixth embodiment, the metal precursor pre-cleaner, alone or in combination with one or more of the first to fifth embodiments, comprises a metal precursor of a material with a conductive structure.

[0136] Although FIG. 6 An example block diagram of process 600 is shown, but in some embodiments, process 600 includes more than FIG. 6 The boxes depicted may include more boxes, fewer boxes, different boxes, or boxes arranged differently. Alternatively or additionally, two or more boxes in process 600 may be executed in parallel.

[0137] FIG. 7 This is a flowchart of an example process 700 associated with the formation of the semiconductor device described herein. In some embodiments, FIG. 7One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools.

[0138] like FIG. 7 As shown, process 700 may include forming a recess in a dielectric layer within an interconnect layer of a semiconductor device (box 710). For example, a recess (e.g., recess 302) may be formed in a dielectric layer (e.g., ILD layer 126, ESL 128) within an interconnect layer (e.g., interconnect layer 104) of a semiconductor device (e.g., semiconductor device 100), as described herein, using one or more semiconductor processing tools. In some embodiments, the interconnect layer is located above a device layer (e.g., device layer 102) of the semiconductor device. In some embodiments, the top surface of a contact structure of the semiconductor device (e.g., source / drain contact structure 122) is exposed through the recess.

[0139] like FIG. 7 As further shown, process 700 may include performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaner to remove metal and oxygen from the top surface of the contact structure (box 720). For example, one or more semiconductor processing tools may be used to perform a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaner to remove metal and oxygen from the top surface of the contact structure, as described herein.

[0140] like FIG. 7 As further shown, process 700 may include a conductive structure (box 730) in which an interconnect layer is formed on the top surface of the contact structure within the recess. For example, one or more semiconductor processing tools may be used to form the conductive structure (e.g., source / drain interconnect structure 134) in the recess on the top surface of the contact structure, as described herein. In some embodiments, the pre-cleaning operation and the formation of the conductive structure are performed in the same processing chamber, while a vacuum is maintained in that same processing chamber between the pre-cleaning operation and the formation of the conductive structure.

[0141] Process 700 may include other implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other process descriptions described elsewhere herein.

[0142] In a first embodiment, the metal precursor pre-cleaning agent includes a first metal precursor, and forming a conductive structure includes forming a conductive structure using a second metal precursor, wherein the first metal precursor and the second metal precursor include the same metal precursor.

[0143] In the second embodiment, either alone or in combination with the first embodiment, the metal precursor pre-cleaning agent includes a first metal precursor, and forming a conductive structure includes forming a conductive structure using a second metal precursor, wherein the first metal precursor and the second metal precursor include different metal precursors.

[0144] In the third embodiment, alone or in combination with one or more of the first and second embodiments, the contact structure comprises tungsten (W), and the metal precursor pre-cleaning agent comprises tungsten fluoride (WF). x ) or tungsten chloride (WCl) x At least one of them.

[0145] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the contact structure comprises molybdenum (Mo), wherein the metal precursor pre-cleaner comprises molybdenum fluoride (MoF). x ) or molybdenum chloride (MoCl) x At least one of them.

[0146] In the fifth embodiment, performing a pre-cleaning operation, either alone or in combination with one or more of the first to fourth embodiments, includes performing the pre-cleaning operation at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius.

[0147] Although FIG. 7 An example block diagram of process 700 is shown, but in some embodiments, process 700 includes more than FIG. 7 The boxes depicted may include more boxes, fewer boxes, different boxes, or boxes arranged differently. Additionally or alternatively, two or more boxes in process 700 may be executed in parallel.

[0148] In this way, before forming the conductive structure of the semiconductor device on the contact structure, a pre-cleaning operation using a metal precursor is performed to remove the metal oxide layer from the top surface of the contact structure. Using a metal precursor as a pre-cleaning agent for the pre-cleaning operation allows for the complete removal of native oxides (not just components such as oxygen) without causing the formation of pores in the top surface of the contact structure, thus enabling low contact resistance between the contact structure and the conductive structure.

[0149] As described in more detail above, some embodiments described herein provide a method. The method includes forming a recess in a dielectric layer of an interconnect layer of a semiconductor device, wherein a top surface of a contact structure of the semiconductor device is exposed through the recess. The method includes performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent. The method includes forming a conductive structure of the interconnect layer in the recess on the top surface of the contact structure.

[0150] As described in more detail above, some embodiments described herein provide a method. The method includes forming a recess in a dielectric layer of an interconnect layer of a semiconductor device, wherein the interconnect layer is located above a device layer of the semiconductor device, and a top surface of a contact structure of the semiconductor device is exposed through the recess. The method includes performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent. The method includes forming a conductive structure of the interconnect layer in the recess on the top surface of the contact structure, wherein the pre-cleaning operation and the formation of the conductive structure are performed in the same processing chamber, while maintaining a vacuum in the same processing chamber between the pre-cleaning operation and the formation of the conductive structure.

[0151] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a substrate layer. The semiconductor device includes an integrated circuit device that satisfies at least one of the following: located within or on the substrate layer. The semiconductor device includes a contact structure located in a first dielectric layer above the substrate layer and electrically coupled to the integrated circuit device, wherein the contact structure includes a first metallic material. The semiconductor device includes a conductive structure located in a second dielectric layer above the first dielectric layer and in contact with the contact structure, wherein the bottom surface of the conductive structure is recessed into the top surface of the contact structure.

[0152] The terms “about” and “substantially” can mean that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are merely examples and are not intended to be limiting. It should be understood that the terms “about” and “substantially” can refer to a percentage of the value of a given quantity according to this disclosure.

[0153] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0154] Example 1 is a method of forming a semiconductor device, comprising: forming a recess in a dielectric layer of an interconnect layer of the semiconductor device, wherein a top surface of a contact structure of the semiconductor device is exposed through the recess; performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent; and forming a conductive structure of the interconnect layer in the recess on the top surface of the contact structure.

[0155] Example 2 is the method of Example 1, wherein performing the pre-cleaning operation includes performing a chemical soak, wherein the metal precursor pre-cleaning agent is held on the top surface of the contact structure for a period of time.

[0156] Example 3 is the method described in Example 1, wherein the metal precursor pre-cleaning agent comprises a halogen-containing metal precursor.

[0157] Example 4 is the method described in Example 1, wherein the metal precursor pre-cleaning agent comprises a fluorinated metal precursor.

[0158] Example 5 is the method described in Example 1, wherein the metal precursor pre-cleaning agent comprises a chlorinated metal precursor.

[0159] Example 6 is the method of Example 1, wherein the metal precursor pre-cleaning agent comprises a metal precursor of the material of the contact structure.

[0160] Example 7 is the method described in Example 1, wherein the metal precursor pre-cleaning agent comprises a metal precursor of the material of the conductive structure.

[0161] Example 8 is a method of forming a semiconductor device, comprising: forming a recess in a dielectric layer of an interconnect layer of the semiconductor device, wherein the interconnect layer is located above a device layer of the semiconductor device, and wherein a top surface of a contact structure of the semiconductor device is exposed through the recess; performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent to remove metal and oxygen from the top surface of the contact structure; and forming a conductive structure of the interconnect layer in the recess on the top surface of the contact structure, wherein the pre-cleaning operation and the formation of the conductive structure are performed in the same processing chamber while maintaining a vacuum in the same processing chamber between the pre-cleaning operation and the formation of the conductive structure.

[0162] Example 9 is the method of Example 8, wherein the metal precursor pre-cleaning agent includes a first metal precursor; wherein forming the conductive structure includes forming the conductive structure using a second metal precursor; and wherein the first metal precursor and the second metal precursor include the same metal precursor.

[0163] Example 10 is the method of Example 8, wherein the metal precursor pre-cleaning agent includes a first metal precursor; wherein forming the conductive structure includes forming the conductive structure using a second metal precursor; and wherein the first metal precursor and the second metal precursor include different metal precursors.

[0164] Example 11 is the method of Example 8, wherein the contact structure comprises tungsten (W), and wherein the metal precursor pre-cleaning agent comprises at least one of the following: tungsten fluoride (WF)x ) or tungsten chloride (WCl) x ).

[0165] Example 12 is the method of Example 8, wherein the contact structure comprises molybdenum (Mo), and wherein the metal precursor pre-cleaner comprises at least one of the following: molybdenum fluoride (MoF). x ) or molybdenum chloride (MoCl) x ).

[0166] Example 13 is the method of Example 8, wherein performing the pre-cleaning operation includes performing the pre-cleaning operation at a temperature ranging from about 200 degrees Celsius to about 450 degrees Celsius.

[0167] Example 14 is a semiconductor device comprising: a substrate layer; an integrated circuit device satisfying at least one of the following: located within or on the substrate layer; a contact structure located in a first dielectric layer above the substrate layer and electrically coupled to the integrated circuit device, wherein the contact structure comprises a first metallic material; and a conductive structure located in a second dielectric layer above the first dielectric layer and in contact with the contact structure, wherein a bottom surface of the conductive structure is recessed into a top surface of the contact structure.

[0168] Example 15 is the semiconductor device described in Example 14, wherein the depth of the recess in the top surface of the contact structure of the conductive structure is in the range of about 0.5 nanometers to about 5 nanometers.

[0169] Example 16 is the semiconductor device described in Example 14, wherein the conductive structure is laterally offset relative to the contact structure such that a portion of the bottom surface of the conductive structure contacts the first dielectric layer.

[0170] Example 17 is the semiconductor device described in Example 16, wherein a portion of the top surface of the contact structure is in contact with a third dielectric layer located vertically between the first dielectric layer and the second dielectric layer.

[0171] Example 18 is the semiconductor device described in Example 14, wherein the lateral width of the top surface of the contact structure is greater than the lateral width of the bottom surface of the conductive structure; and wherein the recess of the conductive structure into the top surface of the contact structure comprises only a portion of the top surface of the contact structure.

[0172] Example 19 is the semiconductor device described in Example 14, wherein the lateral width of a first portion of the conductive structure recessed into the top surface of the contact structure is greater than the lateral width of a second portion of the conductive structure located above the top surface of the contact structure.

[0173] Example 20 is the semiconductor device described in Example 14, wherein the bottom surface of the conductive structure is recessed to a non-uniform depth across the entire top surface of the contact structure.

Claims

1. A method for forming a semiconductor device, comprising: A recess is formed in the dielectric layer of the interconnect layer in a semiconductor device. The top surface of the contact structure of the semiconductor device is exposed through the recess; The top surface of the contact structure was pre-cleaned using a metal precursor pre-cleaning agent; and A conductive structure of the interconnect layer is formed in the recess on the top surface of the contact structure.

2. The method according to claim 1, wherein, Performing the pre-cleaning operation includes: A chemical immersion is performed, wherein the metal precursor pre-cleaning agent is held on the top surface of the contact structure for a period of time.

3. The method according to claim 1, wherein, The metal precursor pre-cleaning agent includes halogen-containing metal precursors.

4. The method according to claim 1, wherein, The metal precursor pre-cleaning agent includes fluorinated metal precursors.

5. The method according to claim 1, wherein, The metal precursor pre-cleaning agent includes chlorine-containing metal precursors.

6. The method according to claim 1, wherein, The metal precursor pre-cleaning agent comprises a metal precursor of the material of the contact structure.

7. The method according to claim 1, wherein, The metal precursor pre-cleaning agent comprises a metal precursor of the material of the conductive structure.

8. A method of forming a semiconductor device, comprising: A recess is formed in the dielectric layer of the interconnect layer in a semiconductor device. The interconnect layer is located above the device layer of the semiconductor device, and The top surface of the contact structure of the semiconductor device is exposed through the recess; A pre-cleaning operation is performed on the top surface of the contact structure using a metal precursor pre-cleaning agent to remove metal and oxygen from the top surface of the contact structure; and A conductive structure of the interconnect layer is formed in the recess on the top surface of the contact structure. The pre-cleaning operation and the formation of the conductive structure are performed in the same processing chamber, while a vacuum is maintained in the same processing chamber between the pre-cleaning operation and the formation of the conductive structure.

9. The method according to claim 8, wherein, The metal precursor pre-cleaning agent includes a first metal precursor; The formation of the conductive structure includes forming the conductive structure using a second metal precursor; and The first metal precursor and the second metal precursor both include the same metal precursor.

10. A semiconductor device, comprising: Substrate layer; An integrated circuit device, wherein the integrated circuit device satisfies at least one of the following: is located within the substrate layer or is located on the substrate layer; A contact structure is located in a first dielectric layer above the substrate and electrically coupled to the integrated circuit device. The contact structure includes a first metallic material; and A conductive structure is located in a second dielectric layer above the first dielectric layer and is in contact with the contact structure. The bottom surface of the conductive structure is recessed into the top surface of the contact structure.

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