Multi-chip high-density three-dimensional interconnected board-level packaging structure and packaging method
By combining copper bumps and copper pillars, the challenge of high aspect ratio interconnect microvias in multi-chip 3D stacked packaging is solved, achieving high-density, low-cost chip interconnection and adapting to packaging requirements of different sizes and specifications.
Patent Information
- Application Number
- CN202511473873.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-15
- Publication Date
- 2026-01-13
AI Technical Summary
In existing multi-chip 3D stacked packaging technologies, the fabrication and metallization processes of high aspect ratio interconnect microvias are difficult, have low yields, high costs, and poor reliability, and are difficult to adapt to chip packaging of different sizes.
Copper bumps are used to align the chip height, and copper pillars and distributed circuit layers are used to interconnect the chips, avoiding the fabrication and metallization of high aspect ratio interconnect microvias, and adapting to multi-chip packages of different sizes and specifications.
It achieves multi-chip three-dimensional interconnection with simple process, high interconnect density and low cost, and adapts to chip packaging of different sizes and specifications.
Smart Images
Figure CN121335531A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor packaging, in particular to a multi-chip high-density three-dimensional interconnection board-level packaging structure, and also provides a packaging method of the packaging structure. BACKGROUND
[0002] With the continuous development of integrated plating technology, the requirements for product computing power performance, volume, power consumption, cost and the like are higher and higher, and Moore's law is approaching the limit, so it is increasingly difficult to improve chip performance from the perspective of chip process, and integrated circuit practitioners are increasingly focusing on advanced packaging. Through three-dimensional stacking and interconnection packaging of different functional chips, the product volume can be effectively reduced, and the length of the connection line between the chips can be shortened, so as to achieve the purpose of shortening the delay of the integrated circuit product and modularizing the function.
[0003] However, the prior art still has many problems in the field of multi-chip three-dimensional stacked advanced packaging. First, the interconnection channels between the layers often rely on TSV, TMV, TGV and other high aspect ratio interconnection micro-holes, and the manufacturing and metallization of these interconnection micro-holes are difficult processes for three-dimensional stacked packaging technology. Process difficulty, low yield, high cost and poor reliability limit the further application of three-dimensional stacking technology, in addition, different size specifications of chips are also a technical problem in the field of multi-chip three-dimensional stacked packaging. Therefore, the existing three-dimensional stacking technology has defects and needs to be improved. SUMMARY
[0004] In view of the above problems, the present application provides a multi-chip high-density three-dimensional interconnection board-level packaging structure, which can avoid the difficult process of manufacturing and metallizing high aspect ratio interconnection micro-holes, and is suitable for multi-chip packaging of different size specifications, and has the core advantages of simple process, high interconnection density and low cost.
[0005] A multi-chip high-density three-dimensional interconnection board-level packaging structure, characterized in that it comprises: an upper chip group comprising an upper distribution line layer, an upper plastic encapsulation layer, an upper copper column and a plurality of upper chips arranged and disposed; a lower chip group comprising a lower distribution line layer, a lower plastic encapsulation layer, a lower copper column and a plurality of lower chips arranged and disposed; and a tin ball; The upper chip group is stacked above the lower chip group, the bottom of the upper copper column is connected to the top of the lower copper column, the lower copper column and the plurality of lower chips are electrically connected to the corresponding positions of the lower distribution line layer, the lower side of the lower distribution line layer is exposed to a pad, and the upper copper column and the plurality of upper chips are electrically connected to the corresponding positions of the upper distribution line layer.
[0006] It is further characterized in that: According to the requirement, tin ball is welded to the exposed pad of the upper distribution circuit layer, and the exposed pad of the lower distribution circuit layer does not need to be welded with tin ball any more; A passivation layer is arranged between the bottom of the upper chip and the top of the lower chip; The upper chip in the upper chip group is pre-processed to be the same height by adding copper bump at the pad position, and the lower chip in the lower chip group is pre-processed to be the same height by adding copper bump at the pad position; When the lower chip is a double-sided interconnection product, the upper chip group is no longer arranged, and an interconnection circuit layer is arranged on the front surface of the lower copper column and the front surface of the plurality of lower chips to complete the interconnection connection of the front surface of the lower chip group.
[0007] A multi-chip high-density three-dimensional interconnection board-level packaging method, characterized in that it comprises the following steps: S1, when different size chips are packaged together, copper Bump is made on the wafer surface, the chip size is pulled to the same height through the height of the copper Bump, and then the chip is cut to obtain the chip; S2, a temporary bonding film is attached to the carrier board, and then the chip and the copper column are attached, and the height of each chip and copper column is consistent; S3, the chip and the copper column are wrapped with plastic; S4, the copper Bump and the copper column of the chip are exposed by grinding; S5, a distribution circuit layer is made on the surface of the exposed copper column and copper Bump to interconnect the copper column and copper Bump; S6, for a double-sided interconnection product, the bonding carrier board is removed, the entire structure is turned over, and an interconnection circuit layer is made on the corresponding surface of the exposed copper column and chip; For a three-dimensional stacked product, the product obtained in step S5 is turned over to form a lower chip group, then the bonding carrier board is removed, a passivation layer is made in the area where the chip is to be placed, then the upper chip and the upper copper column are attached, the bottom of the upper copper column is connected to the top of the lower copper column, then the upper chip and the upper copper column are plastic-wrapped to form an upper plastic-wrapped layer, then the copper Bump of the upper chip and the upper copper column are exposed by grinding, and an upper distribution circuit layer is made; S7, tin ball is welded.
[0008] It is further characterized in that: Or S6 is replaced by, for a double-sided interconnection product, removing the bonding carrier board, turning over the entire structure, and making an interconnection circuit layer on the corresponding surface of the exposed copper column and chip; The chips in steps S2 and S6 are completed by step S1 to align the height; The height of the copper Bump in step S1 ranges from 5 to 200 μm, and making the copper Bump on the wafer surface is beneficial to improve the interconnection density.
[0009] By adopting the technical scheme, the height of each chip group of the three-dimensional stacked product is configured to be equal by setting copper Bump, and then the same-layer chip interconnection or chip interconnection at different height positions is completed through copper pillars and distribution line layers, which can avoid the difficulties in manufacturing and metallization of high aspect ratio interconnection micro-holes, and is suitable for multi-chip packaging of different size specifications, and has the core advantages of simple process, high interconnection density and low cost. BRIEF DESCRIPTION OF DRAWINGS
[0010] Figure 1 is a front view of a specific embodiment one of the present application; Figure 2 is a front view of a specific embodiment two of the present application; Figure 3 is a flow chart of packaging method steps S1-S5 of the specific embodiment one and two of the present application; Figure 4 is a flow chart of packaging method step S6 of the specific embodiment one of the present application Figure 5 is a flow chart of packaging method step S6 of the specific embodiment two of the present application; The names corresponding to the serial numbers in the drawings are as follows: The upper chip group 10, the upper distribution line layer 11, the upper molding layer 12, the upper copper pillar 13, a plurality of upper chips 14 arranged and disposed, the lower chip group 20, the lower distribution line layer 21, the lower molding layer 22, the lower copper pillar 23, a plurality of lower chips 24 arranged and disposed, the solder ball 30, the passivation layer 40, and the interconnection line layer 50. The copper bump 1, the carrier board 2, the temporary bonding film 3, and the wafer 100. DETAILED DESCRIPTION
[0011] A multi-chip high-density three-dimensional interconnection board-level packaging structure, see Figure 1 and Figure 2 which comprises an upper chip group 10, a lower chip group 20, and a solder ball 30. The upper chip group 10 comprises an upper distribution line layer 11, an upper molding layer 12, an upper copper pillar 13, and a plurality of upper chips 14 arranged and disposed. The lower chip group 20 comprises a lower distribution line layer 21, a lower molding layer 22, a lower copper pillar 23, and a plurality of lower chips 24 arranged and disposed.
[0012] Specific embodiment one, see Figure 1The upper chip group 20 is stacked above the lower chip group 10, the bottom of the upper copper column 13 is connected to the top of the lower copper column 23, the lower copper column 23 and the plurality of lower chips 24 are electrically connected to the corresponding positions of the lower distribution circuit layer 21, the lower side exposed pads of the lower distribution circuit layer 21 are correspondingly provided with lower convex tin balls 30, and the upper copper column 13 and the plurality of upper chips 14 are electrically connected to the corresponding positions of the upper distribution circuit layer 11.
[0013] A passivation layer 40 is arranged between the bottom of the upper chip 14 and the top position of the lower chip 24.
[0014] The upper chip 14 of the upper chip group 10 is previously processed to be the same height by additionally arranging a copper bump 1 at the pad position, and the lower chip 24 of the lower chip group 20 is previously processed to be the same height by additionally arranging a copper bump 1 at the pad position.
[0015] Specific embodiment two, see Figure 2 When the lower chip 24 is a double-sided interconnection product, the upper chip group 20 is no longer arranged, and at this time, the interconnection circuit layer 50 is arranged on the front side of the lower copper column 23 and the plurality of lower chips 24, and the front side interconnection connection of the lower chip group 20 is completed.
[0016] A board-level packaging method for multi-chip high-density three-dimensional interconnection, when the packaging structure corresponding to the specific embodiment one is manufactured, the method comprises the following steps, see Figure 3 and Figure 4 : S1, when different size chips are packaged together, copper Bump 1 is made on the surface of wafer 100, the height of the chip size is pulled to the same height through the height of copper Bump 1, and then the upper chip 14 and the lower chip 24 are obtained by cutting; S2, the temporary bonding film 3 is attached to the carrier board 2, and then the lower chip 24 and the lower copper column 23 are attached, and the height of each lower chip 24 and the lower copper column 23 is consistent; S3, the lower chip 24 and the lower copper column 23 are wrapped by plastic packaging to obtain the lower plastic packaging layer 22; S4, the copper Bump 1 of the chip and the lower copper column 23 are exposed by grinding; S5, the lower distribution circuit layer 21 is made on the surface of the exposed lower copper column 23 and copper Bump 1, and the lower copper column 23 and copper Bump 1 are interconnected; S6, making a three-dimensional stacked product, turning over the product obtained in step S5 to form the lower chip group 20, then removing the bonding carrier plate 2, making a passivation layer 40 in the area where the chip is needed to be placed, then attaching the upper chip 14 and the upper copper pillar 13, the bottom of the upper copper pillar 13 being connected to the top of the lower copper pillar 23, then performing plastic packaging on the upper chip 14 and the upper copper pillar 13 to form the upper plastic packaging layer 12, then exposing the copper bump 1 of the upper chip and the upper copper pillar 13 by grinding, and making the upper distribution circuit layer 11; S7, welding the tin ball 30, the lower side exposed pad of the lower distribution circuit layer 21 being provided with a lower convex tin ball 30.
[0017] The making method of the second embodiment is the same as steps S1-S5 of the first embodiment, and for the double-sided interconnection product, step S6 (see Figure 5 ) is replaced by the following operation: removing the bonding carrier plate 2, turning over the whole structure, and making an interconnection circuit layer 50 on the exposed lower copper pillar 23 and the lower chip 24. The chips in steps S2 and S6 of the first and second embodiments are completed by step S1 for height alignment. The height of the copper bump 1 in step S1 is 5-200 μm, and making the copper bump on the wafer 100 surface is beneficial to improve the interconnection density.
[0018] The height of each chip group of the three-dimensional stacked product is configured by setting the copper bump, and then the same-layer chip interconnection or chip interconnection at different height positions is completed by the copper pillar and the distribution circuit layer, which can avoid the difficult process of high aspect ratio interconnection micro-hole and its metallization, and is suitable for multi-chip packaging of different size specifications, and has the core advantages of simple process, high interconnection density and low cost.
[0019] It is apparent for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, but can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all aspects as illustrative and not restrictive, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended to encompass all changes falling within the meaning and range of equivalents of the elements of the claims. Any reference signs in the claims should not be considered as limiting the claims involved.
[0020] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A board-level packaging structure for high-density three-dimensional interconnection of multiple chips, characterized in that, It includes: The upper-layer chipset includes an upper-layer distribution circuit layer, an upper-layer molding layer, upper-layer copper pillars, and several upper-layer chips arranged in a specific configuration. The lower-level chipset includes a lower-level distribution circuit layer, a lower-level molding layer, lower-level copper pillars, and several lower-level chips arranged in a specific configuration. And tin balls; The upper-layer chipset is stacked on top of the lower-layer chipset. The bottom of the upper-layer copper pillar is connected to the top of the lower-layer copper pillar. The lower-layer copper pillar and several lower-layer chips are electrically connected to the corresponding positions of the lower-layer distributed circuit layer. The exposed pads on the lower side of the lower-layer distributed circuit layer are provided with protruding solder balls. The upper-layer copper pillar and several upper-layer chips are electrically connected to the corresponding positions of the upper-layer distributed circuit layer.
2. The board-level packaging structure for multi-chip high-density three-dimensional interconnection according to claim 1, characterized in that: Depending on the requirements, solder balls are soldered to the exposed pads of the upper distribution circuit layer. At this time, the exposed pads of the lower distribution circuit layer do not need to be soldered with solder balls.
3. The board-level packaging structure for multi-chip high-density three-dimensional interconnection according to claim 1, characterized in that: A passivation layer is provided between the bottom of the upper chip and the top of the lower chip.
4. The board-level packaging structure for multi-chip high-density three-dimensional interconnection according to claim 1, characterized in that: The upper-layer chips in the upper chipset are pre-heightened by adding copper bumps at the pad positions, and the lower-layer chips in the lower chipset are pre-heightened by adding copper bumps at the pad positions.
5. The board-level packaging structure for multi-chip high-density three-dimensional interconnection according to claim 1, characterized in that: When the lower-layer chip is a double-sided interconnect product, the upper-layer chipset is no longer set. Instead, an interconnection layer is set on the front of the lower-layer copper pillar and the front of several lower-layer chips to complete the interconnection and interoperability of the front of the lower-layer chipset.
6. A board-level packaging method for multi-chip high-density three-dimensional interconnection, applicable to the board-level packaging structure for multi-chip high-density three-dimensional interconnection as described in any one of claims 1-5, characterized in that, It includes the following steps: S1. When packaging chips of different sizes together, a copper bump is made on the surface of the wafer. The height of the copper bump is used to align the chip size with the height of the chip, and then the chip is cut to obtain the chip. S2. Apply a temporary bonding film to the carrier board, then mount the chips and copper pillars, ensuring that all chips and copper pillars are at the same height. S3, plastic-encapsulated chips and copper pillars; S4. Expose the copper bump and copper pillars of the chip by grinding; S5. Fabricate a distribution layer on the exposed copper pillars and copper bumps to interconnect the copper pillars and copper bumps. S6. For double-sided interconnect products, disassemble the bonding substrate, flip the entire structure, and fabricate the interconnect circuit layer on the exposed copper pillars and the corresponding chip surfaces. For 3D stacked products, the product obtained in step S5 is flipped to form a lower chipset. Then the bonding substrate is disassembled, a passivation layer is made in the area where the chip needs to be placed, and then the upper chip and upper copper pillar are mounted. The bottom of the upper copper pillar is connected to the top of the lower copper pillar. Then, the upper chip and upper copper pillar are encapsulated to form an upper encapsulation layer. Then, the copper bump of the upper chip and the upper copper pillar are exposed by grinding, and the upper distribution circuit layer is made. S7, Solder ball.
7. The board-level packaging method for multi-chip high-density three-dimensional interconnection according to claim 6, characterized in that: Alternatively, for double-sided interconnect products, the S6 can be replaced by disassembling the bonding substrate, flipping the entire structure, and creating interconnect layers on the exposed copper pillars and corresponding chip surfaces.
8. A board-level packaging method for multi-chip high-density three-dimensional interconnection according to claim 6, characterized in that: The chips in steps S2 and S6 are both aligned at a high level through step S1.
9. A board-level packaging method for high-density three-dimensional interconnection of multiple chips according to claim 6, characterized in that: In step S1, the height of the copper bump ranges from 5 to 200 μm. Fabricating copper bumps on the wafer surface is beneficial for increasing interconnect density.