Semiconductor device and method of forming heat sink with surface plasma treatment for fcbga-h package

Abstract

Semiconductor devices and methods of forming heat spreaders with surface plasma treatment for FCBGA-H packages. A semiconductor device has a substrate and an electrical component disposed over the substrate. A heat sink having a plasma enhanced surface is disposed over the electrical component. The TIM is disposed between the electrical component and the plasma enhanced surface of the heat sink. The TIM may be deposited on an electrical component or a plasma enhanced surface. The plasma enhanced surface comprises argon ions and oxygen ions. A heat sink is disposed in the reaction chamber. Reactant gases, such as argon and oxygen, are introduced into the reaction chamber. An electric field is formed within the reaction chamber to ionize argon and oxygen and form a plasma enhanced surface. The plasma enhanced surface has characteristics of roughness and tackiness or adhesion as the properties of the surface exhibit chemically bonded groups. An underfill material is deposited between the electrical component and the substrate. The electrical component may be a flip-chip type semiconductor die.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and a method of forming a heat sink with a surface plasmon treatment for fcBGA-H packaging. BACKGROUND

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, light-emitting and light-detecting devices, and producing visual images for television displays. Semiconductor devices are found in communication, power conversion, network, computer, entertainment, and consumer products.

[0003] Semiconductor devices are susceptible to heat from the operation of the semiconductor die. Some semiconductor dies, such as microprocessors, operate at high clock frequencies and generate heat from fast transistor switching. Other semiconductor devices, such as power MOSFETs, generate heat by conducting large currents. High output power and associated heat can be attributed to multi-function and high performance operation.

[0004] Semiconductor dies are typically mounted to a substrate, and a heat sink or heat spreader is mounted to the semiconductor die and to the area of the substrate surrounding the semiconductor die. In one example, a flip chip ball grid array (fcBGA) package typically uses a heat sink (fcBGA-H) to manage heat for stable and long term use of the device. The heat sink can be made of nickel-plated copper. The surface of the nickel-plated copper is smooth. A portion of the heat sink thermally contacts a thermal interface material (TIM) deposited on the top surface of the semiconductor die, and another portion of the heat spreader mechanically and thermally contacts the substrate. The TIM can be made of a silicon-based epoxy with thermally conductive fillers. The TIM dissipates heat by effectively increasing the contact area between the semiconductor die and the heat sink.

[0005] The semiconductor die and the TIM are homogenous because both contain silicon. However, the heat sink and the TIM are heterogeneous because each contains a different material. The adhesion properties of the heterogeneous interface are not as effective as the adhesion of the homogenous interface. Better adhesion and bonding capabilities are needed between the heat sink and the TIM. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures la-lc illustrates a semiconductor wafer with multiple semiconductor dies separated by a saw street;

[0007] Figures 2a-2v illustrates a process of forming a fcBGA-H package with a plasma enhanced surface on a header extender to interface with a TIM;

[0008] Figures 3a-3b forming a plasma enhanced surface on a heat sink; and

[0009] Figure 4 illustrating a printed circuit board (PCB) with different types of packages arranged on a surface of the PCB. DETAILED DESCRIPTION

[0010] The application is described in one or more embodiments in the following description with reference to the figures, in which like reference characters designate identical or similar elements. While the application is described in terms of the best mode for achieving the objects of the application, it will be appreciated by those skilled in the art that the application is intended to cover any alternatives, modifications, and equivalents as can be included within the spirit and scope of the application as defined by the appended claims and as supported by the following disclosure and drawings. The term "semiconductor die" as used herein refers to both the singular and the plural of the word and can thus refer to both a single semiconductor device and multiple semiconductor devices.

[0011] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming a plurality of dies on a surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. The active electrical components, such as transistors and diodes, have a

[0012] Back-end manufacturing refers to the process of cutting or singulating the completed wafers into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scribed and broken along non-functional areas of the wafer, known as saw streets or scribe lines. A laser cutting tool or saw blade is used to singulate the wafer. After singulation, the individual semiconductor dies are disposed on a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed over the semiconductor dies are then connected to the contact pads within the package. The electrical connections can be made with conductive layers, bumps, pillars, conductive paste, or wire bonds. An encapsulant or other molding material is deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, and the functionality of the semiconductor device is made available to other system components.

[0013] Figure laA semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by non-active die-to-die wafer area or streets 106. The streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 is circular with a diameter of 100-450 millimeters (mm). The semiconductor wafer 100 can be rectangular or any other geometric shape.

[0014] Figure lb A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or non-active surface 108 and an active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry can include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog circuitry or digital circuitry such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a memory, or other signal processing circuitry. The semiconductor die 104 can also contain IPD for RF signal processing such as inductors, capacitors, and resistors.

[0015] A conductive layer 112 is formed on the active surface 110 using a PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. The conductive layer 112 serves as a contact pad electrically connected to the circuitry on the active surface 110.

[0016] A conductive bump material is deposited on the conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and optionally a flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 114. In one embodiment, the bumps 114 are formed over under bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesion layer. The bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed over the conductive layer 112. Interconnect structures can also use bond wires, conductive paste, columnar bumps, micro bumps, or other electrical interconnects.

[0017] In Figure lc semiconductor wafer 100 into individual semiconductor dies 104 through the streets 106 using a saw blade or laser cutting tool 118. In one embodiment, the semiconductor dies 104 are flip chip type semiconductor dies. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies or units (KGD / KGU) after singulation.

[0018] Figures 2a-2v A process of forming an fcBGA-H package with a plasma enhanced surface on the header extender to interface with a TIM is illustrated. Figure 2aA cross-sectional view of an interconnect substrate or interposer 120 is shown that includes one or more conductive layers 122 and one or more insulating layers 124. The conductive layers 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The conductive layers 122 can be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive layers 122 provide horizontal electrical interconnects across the substrate 120 as well as vertical electrical interconnects between the top surface 126 and the bottom surface 128 of the substrate 120. Depending on the design and functionality of the semiconductor die 104 and other electrical components, portions of the conductive layers 122 can be electrically common or electrically isolated. The insulating layers 124 include one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layers 124 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layers 124 provide isolation between the conductive layers 122. There can be multiple conductive layers separated by insulating layers 124, such as 122.

[0019] In Figure 2b , one or more electrical components 130 are disposed on the surface 126 of the interposer 130 and electrically and mechanically connected to the conductive layers 122. The electrical component(s) 130 are each positioned over the interposer 120 using a pick and place operation. The electrical components 130 can be fabricated similar to the semiconductor die 104 from Figure lc , with the bumps 114 oriented toward the surface 126 of the interposer 120. Alternatively, the electrical components 130 can include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, interconnect structures, or IPDs.

[0020] The electrical components 130 are brought into contact with the surface 126 of the interposer 120 and bonded to the conductive layers 122 by reflowing the bumps 114. Figure 2c The electrical components 130 are shown electrically and mechanically connected to the conductive layers 122 of the interposer 120.

[0021] In Figure 2d , an underfill material 136, such as epoxy, is deposited between the interposer 120 and the electrical components 130 around the bumps 114. In Figure 2e , a TIM layer 138 can be deposited on the back surface 108 in a variety of patterns and shapes. For example, the TIM layer 138 can be a serpentine pattern, as shown in the top view of Figure 2f . The TIM layer 138 can be a concentric circle pattern, as shown in the top view ofFigure 2g in a top view. The TIM layer 138 can be a rectangle with a center point, as shown in a top view. Figure 2h in a top view. The TIM layer 138 can be a grid of points, as shown in a top view. Figure 2i in a top view. The TIM layer 138 can be a plurality of parallel segments, as shown in a top view. Figure 2j in a top view. The TIM layer can be a star pattern extending outwardly from the side surface of the electrical component 130, as shown in a top view. Figure 2k in a top view. The TIM layer 138 is deposited as a soft, compliant material and solidified into a hard material with high adhesion properties. In one embodiment, the TIM layer 138 is a silicon-based adhesive with fillers containing aluminum oxide (AI2O3), Al, Ag, or aluminum zinc oxide and a thermal conductivity of 1.9-11 W / m.K.

[0022] Figure 21 A heat sink or fin 140 is shown, which includes a horizontal member 142, a downwardly sloped leg 144, and a horizontal member 146. The horizontal member 142 has a surface 148. The heat sink 140 can be made of one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable thermally conductive material. In one embodiment, the heat sink 140 is Ni-plated Cu. Figure 2m is a perspective view of the heat sink 140 with the horizontal member 142, the downwardly sloped leg 144, and the horizontal member 146.

[0023] Turning to Figure 3a , the heat sink 140 is arranged in a reaction chamber 150 on a pedestal 152. In one embodiment, the reaction chamber 150 is a reactive ion etching (RIE) mode direct plasma chamber. The pedestal 152 extends from the reaction chamber 150 to support the heat sink 140 by contacting the horizontal member 146. A ground electrode 154 is arranged on the surface 148 of the heat sink 140. A power electrode 156 is arranged opposite the ground electrode 154. A reaction gas 155, such as argon (Ar) and oxygen (O2), is introduced into the reaction chamber 150 through a conduit 157. As an example, the reaction gas 155 can have a flow rate of 10.0 standard cubic centimeters per minute (seem) into the reaction chamber 150 at a chamber pressure of 200.0 mTorr for 30-60 seconds. The power electrode 156 is a radio frequency (RF) signal that is energized to create an electric field 158 within the reaction chamber 150. In one embodiment, the power electrode 156 is RF powered at 13.56 MHz to 350.0 kilowatts (kW) to create the electric field 158. The reaction gas 155 within the electric field 158 ionizes gas molecules and creates plasma ions. For example, the electric field can form Ar + ions 160 and O2 +Ions 162. RF power provides high density energy to Ar and O2 to discharge the gas and form plasma ions. The plasma ions deposit on the surface 148 of the heat spreader 150 and form a plasma enhanced surface 164. In particular, Ar + Ions 160 roughen the surface 148, while O2 + Ions 162 activate the surface 148 with chemical bonding groups, leaving the plasma enhanced surface 164 with the characteristics of roughness and activation. The plasma enhanced surface 164 exhibits improved adhesion and coverage characteristics.

[0024] Figure 3b Further details are shown from block 166 of Figure 3a , where a portion of the plasma enhanced surface 164 is formed on the horizontal member 142 of the heat spreader 140. The plasma enhanced surface 164 has carbon (C) - oxygen (O) bonds 168 and O-C bonds 170 to obtain adhesion characteristics.

[0025] Figure 2n The heat spreader 140 with the plasma enhanced surface 164 is shown outside the reaction chamber 150 after plasma processing. Figure 20 A perspective view of the heat spreader 140 with the plasma enhanced surface 164 after plasma processing is shown.

[0026] In Figure 2p , the heat spreader 140 with the plasma enhanced surface 164 is disposed over the TIM 138 and the interposer 120. In one embodiment, the surface 164 is a plasma enhanced Ni plated Cu. Figure 2q Further details are shown from block 180 with the plasma enhanced surface 164 exhibiting bonding groups 184 and the TIM 138 exhibiting bonding groups 186 to obtain improved adhesion or bonding characteristics.

[0027] In another embodiment, the TIM 138 is deposited on the plasma enhanced surface 164 prior to mounting the heat spreader 140 to the electrical component 130, as shown in Figure 2r .

[0028] In Figure 2s , the plasma enhanced surface 164 of the heat spreader 140 is brought into contact with the TIM 138 under heat and pressure 190. The thermal paste 192 makes the connection between the horizontal member 146 and the surface 126 of the interposer 120. Figure 2tFurther details are shown of the plasma enhanced surface 164 with contact TIM 138 and bonding group 184 and the bond enhanced bonding group 186 of the block 194. The TIM 138 is cured at 120-150 °C for 30-120 minutes to form a solid bond between the heat spreader 140 and the electrical component 130 with superior TIM coverage on the surface 108. Figure 2u A uniform and continuous TIM 138 coverage is shown on the surface 108 of the electrical component 130.

[0029] In Figure 2v In the block 128, a conductive bump material is deposited on the conductive layer 112 on the surface 128 using an evaporation, electrochemical plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and optionally a flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the bump material above its melting point to form balls or bumps 198. In one embodiment, the bumps 198 are formed over the UBM with a wetting layer, barrier layer, and adhesion layer. The bumps 198 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bumps 198 represent one type of interconnect structure that can be formed over the conductive layer 112. Interconnect structures can also use bond wires, conductive paste, columnar bumps, micro bumps, or other electrical interconnects.

[0030] The electrical component 130 with the interposer 120 and the heat spreader 140 is shown as the fcBGA-H package 200. The heat spreader 140 with the plasma enhanced surface 164 provides uniform and continuous TIM coverage between the electrical component 130 and the horizontal member 142. The physical treatment of the Ar + The physical treatment of the ions 160 cleans the surface 148 of the heat spreader 140. The O2 + The ions 162 provide more adhesion, bonding capability, or adhesive properties to the TIM 138. The surface activation by the O2 + The surface activation of the ions 162 provides more and stronger chemical bonding between the TIM 138 and the heat spreader 140. The TIM 138 can withstand more heat or physical stress through the chemical treatment of the O2 + The chemical treatment of the ions provides more heat or physical stress. The plasma enhanced surface 164 with the TIM 138 reduces the risk of delamination.

[0031] Figure 4An electrical device 400 is illustrated having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages, including fcBGA-H package 200, disposed on a surface of the PCB 402. Depending on the application, electrical device 400 can have one type of semiconductor package or multiple types of semiconductor packages.

[0032] Electrical device 400 can be a stand-alone system that uses semiconductor packages to perform one or more electrical functions. Alternatively, electrical device 400 can be a subcomponent of a larger system. For example, electrical device 400 can be part of a tablet computer, cell phone, digital camera, communication system, or other electrical device. Alternatively, electrical device 400 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for products to be market accepted. The distance between semiconductor devices can be reduced to achieve higher density.

[0033] In Figure 4 , PCB 402 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on the surface or within layers of PCB 402 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 404 also provide power and ground connections to each of the semiconductor packages.

[0034] In some embodiments, the semiconductor device has two levels of packaging. The first level of packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device can have a first level of packaging where the die is mechanically and electrically disposed directly on the PCB. For illustrative purposes, several types of first level packaging are shown on the PCB 402, including wire bond packaging 406 and flip chip 408. Additionally, several types of second level packaging are shown disposed on the PCB 402, including ball grid array (BGA) 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat no-lead package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424, and wafer level chip scale package (WLCSP) 426. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Any combination of semiconductor packages configured with any combination of first level packaging styles and second level packaging styles, as well as other electrical components, can be connected to the PCB 402 depending on the system requirements. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electrical devices and systems. Because the semiconductor packages include complex functionality, less expensive components and simplified manufacturing processes can be used to manufacture the electrical devices. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs to the consumer.

[0035] While one or more embodiments of the application have been illustrated and described, it will be understood by those skilled in the art that various changes and modifications can be made to the embodiments without departing from the scope of the application as set forth in the following claims.

Claims

1. A semiconductor device, comprising: Substrate; Electrical components are arranged above the substrate; A heat sink, comprising a plasma-enhanced surface disposed above an electrical component; as well as Thermal interface material (TIM) is arranged between the plasma-enhanced surfaces of the electrical components and the heat sink.

2. The semiconductor device according to claim 1, wherein, Plasma-enhanced surfaces include argon ions and oxygen ions.

3. The semiconductor device according to claim 1, wherein, Plasma-enhanced surfaces include properties of roughness and viscosity.

4. The semiconductor device according to claim 1, wherein, Plasma-enhanced surfaces include chemically bonded groups.

5. The semiconductor device of claim 1, further comprising an underfill material deposited between the electrical component and the substrate.

6. A semiconductor device, comprising: Electrical components; A heat sink, comprising a plasma-enhanced surface disposed above an electrical component; as well as Thermal interface material (TIM) is arranged between the electrical component and the plasma-enhanced surface.

7. The semiconductor device of claim 6, further comprising a substrate, wherein, The electrical components are arranged above the substrate.

8. The semiconductor device according to claim 6, wherein, Plasma-enhanced surfaces include argon ions and oxygen ions.

9. The semiconductor device of claim 6, wherein the plasma-enhanced surface comprises chemically bonded groups.

10. The semiconductor device of claim 6, further comprising an underfill material deposited between the electrical component and the substrate.

11. A method for manufacturing a semiconductor device, comprising: Provide substrate; Electrical components are arranged above the substrate; A heat sink including a plasma-enhanced surface is arranged above the electrical components; as well as Thermal interface material (TIM) is arranged between the plasma-enhanced surfaces of the electrical components and the heat sink.

12. The method of claim 11, further comprising: Install heat sinks in the reaction chamber; Argon and oxygen are introduced into the reaction chamber; as well as An electric field is created in the reaction chamber to ionize argon and oxygen and form a plasma-enhanced surface.

13. The method according to claim 11, wherein, Plasma-enhanced surfaces include properties of roughness and viscosity.

14. The method according to claim 11, wherein, Plasma-enhanced surfaces include chemically bonded groups.

15. The method of claim 11, further comprising depositing an underfill material between the electrical component and the substrate.

Images