High-integration multipath semiconductor device array module structure and integration method thereof
By using a multi-layer stacked semiconductor device array module structure, the problems of low packaging integration and poor heat dissipation are solved, achieving high integration, low cost and high reliability semiconductor device packaging.
Patent Information
- Application Number
- CN202511581881.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-01-13
AI Technical Summary
Existing discrete semiconductor devices have low integration levels in their packaging. High-integration packaging processes are complex, have low yield rates, high costs, and poor heat dissipation capabilities.
It adopts a multi-layer stacked structure of horizontal and vertical array module units, uses Kovar alloy or copper metal lead electrodes, connects chips and electrodes through solder material layers, and adopts integrated or separate combination packaging, combined with injection molding or potting encapsulation, eliminating the wire bonding process, and realizing multi-chip stacking and multi-form array arrangement.
It improves integration, reduces production costs, saves installation space, enhances heat dissipation and mechanical strength, and improves product performance and reliability. It is suitable for packaging highly integrated, high-power diode chips.
Smart Images
Figure CN121335562A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic components technology, and more specifically to the field of semiconductor device assembly technology. In particular, it relates to a highly integrated multi-channel semiconductor device array module structure and its integration method. Background Technology
[0002] Traditional semiconductor devices, including integrated circuits and discrete devices, primarily utilize planar single-layer packaging processes. For example, ceramic-encapsulated integrated semiconductor modules employ a soldering and wire bonding process, which is complex, results in low yield, and high cost. The chip pads of these semiconductor devices are thin (typically with lead thickness of 0.2-0.3mm), leading to small heat dissipation volume, limited heat dissipation area, and poor heat dissipation capabilities. Discrete devices, on the other hand, use single-layer stacking soldering or wire bonding processes, which are also costly, complex, and result in unstable product performance. Discrete semiconductor devices also suffer from thin chip pads (typically with a thickness of 0.2-0.3mm), small heat dissipation volume, limited heat dissipation area, and poor heat dissipation capabilities.
[0003] In view of this, the present invention is hereby proposed. Summary of the Invention
[0004] The technical problem to be solved by this invention is to address the issues of low integration density, complex high-integration packaging processes, low yield, high cost, and poor heat dissipation in existing semiconductor discrete devices.
[0005] Technical terms: Leaded: This refers to a package with leads extending from the housing, used to bring out the positive and negative electrodes of the diode chip. It is a leaded package type.
[0006] Leadless: This refers to a package without protruding leads. Instead, a metal disc is formed at the bottom of the package where the leads would normally be, used to bring out the positive and negative electrodes of the diode chip. This is also known as a leadless package.
[0007] Therefore, the present invention provides a highly integrated multi-channel semiconductor device array module structure, such as... Figure 1-4 As shown. Includes: In the diagram: Pin electrode 1, Pin electrode 2, Diode chip (referred to as chip), Soldering material layer.
[0008] The lead electrodes 1 and 2 are made of Kovar alloy or copper, with one end serving as the chip mounting area and the other end as the electrode lead-out terminal. The surface of the chip mounting area is plated with gold or nickel. The electrode lead-out terminal is plated with tin or gold.
[0009] The chip is assembled in the chip mounting area of pin electrode 1 and pin electrode 2, and a soldering material layer is placed between the chip and the chip mounting area to form a horizontally arranged array module unit.
[0010] The horizontally arranged array module units are stacked horizontally in multiple layers with positive and negative polarities on the same side or symmetrically to form a horizontally arranged highly integrated semiconductor device product array module.
[0011] An insulating connecting piece is welded to the back of the pin electrode 1 of the horizontally laid-out array module unit through a welding material layer to form a vertically laid-out array module unit.
[0012] The vertically arranged array module units are vertically stacked in multiple layers with electrodes distributed on the same side or on both sides of the electrodes to form a vertically arranged highly integrated semiconductor device product array module.
[0013] When the horizontal or vertical array module units are integrated, they are either integrated into a single package or separated into separate packages.
[0014] The integration method of the highly integrated multi-channel semiconductor device array module structure includes the following integration method: (1) Unit combination method: Multiple single-row unit arrays or multiple symmetrical unit arrays are welded into the module product according to the set circuit to form a multi-unit semiconductor device integration.
[0015] (2) Product packaging process: injection molding or high-strength engineering plastic shell with potting compound for potting and curing.
[0016] (3) Connection between chip electrode and electrode pad (i.e. chip mounting area) and exposed soldering pin (with or without pin): The chip and electrode pad are soldered using a hot melt soldering process with soldering material. The electrode pad and exposed soldering pin adopt an integrated structure and are integrally stamped with copper material with a thickness greater than 0.3mm. The integrated frame does not require wire bonding process connection when it is subsequently soldered and connected to the chip.
[0017] (4) Array module unit: The chip, positive electrode and negative electrode together form an array module unit. The connection between two symmetrical array module units is connected by an insulating connecting piece.
[0018] (5) Connecting pieces are added between the array module units, and then all components are welded into a multi-unit array module using hot melt welding process with welding material.
[0019] (6) According to the actual needs, the size and shape are combined into corresponding integrated module products (in the multi-unit array module), and then packaged and shaped.
[0020] The main advantages of this invention are as follows: (1) The internal structure of a semiconductor device integrated module product can be composed of multiple stacked chips and then arranged in a unidirectional multi-form or multi-directional multi-form array. An integrated module structure product can effectively replace the original multiple discrete devices or other integrated packaged modules in the circuit. Under the same quantity usage, it saves 20%-70% of the space on the PCB board and reduces the procurement and installation costs.
[0021] (2) The product packaging shape can be adjusted to any spacing size, shape and packaging form as needed, which is convenient to install and the overall structure is solid and reliable. The packaging shell can be potted by injection molding of engineering plastic shell or injection molded. The process selection is flexible and not limited when making the packaging. At the same time, it can meet the production needs of various production scales, reduce the production cost threshold, and improve the overall performance of the product.
[0022] (3) The chip connection electrode pads and exposed solder pins are integrally stamped. This ensures sufficient mechanical structural strength while providing better current carrying capacity and heat dissipation. The integrated frame eliminates the need for wire bonding when connecting and combining with the chip, greatly optimizing the production process, saving production costs, and significantly improving the overall performance of the product.
[0023] (4) One unit, two units, or multiple units are combined to form a product array module. The product module can be encapsulated in the corresponding packaging shape according to actual needs, using a molded shell or injection molding to encapsulate the required integrated module product. The number of packaging modules is flexible and can meet different product needs.
[0024] (5) When the integrated module product is packaged using the potting process, the production cost and manufacturing threshold can be greatly reduced, making it very suitable for small-scale production and use.
[0025] (6) When the integrated module product is packaged using injection molding, the production capacity can be greatly improved, which can meet the needs of large-scale production.
[0026] The integrated modules produced by the method of this invention have the characteristics of diverse combinations, flexible packaging process, high product integration, stable performance, and convenient installation. They achieve high integration, high power, fast heat dissipation, small size, high structural reliability, and convenient installation, thereby solving many drawbacks and defects of the original products.
[0027] The pin spacing can be adjusted as needed, as long as the spacing meets the insulation distance requirements. Each die group inside this module is an independent working unit, saving installation space in circuit design while providing greater flexibility in combination, achieving high product integration, improving product reliability, and solving the problems of large circuit board area, messy circuits, uneven heat dissipation, poor heat dissipation capacity, and reduced response speed caused by single-chip products in multi-channel integrated circuits. It significantly reduces the space required for mounting boards and optimizes circuit layout. It is widely used in the field of high-integration, high-power, and high-reliability diode chip packaging technology. It has strong promotional value and high economic and social benefits. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of the unit diode chip array module structure. Figure 1 middle: 1-1 is a schematic diagram of a vertically integrated unit structure with the positive and negative terminals of the diode on the same side and no leads.
[0029] Figure 1-2 is a schematic diagram of a unit integrated structure with vertically arranged pins on the same side of the diode's positive and negative terminals.
[0030] Figure 1-3 is a schematic diagram of a unit integrated structure with pins on the same side of the diode's positive and negative terminals arranged horizontally.
[0031] Figure 1-4 shows a schematic diagram of a symmetrical, pinless unit integrated structure with no leads on both sides of the positive and negative terminals of a diode.
[0032] Figure 2 This is a schematic diagram of the arrangement structure of two-unit integrated combination and non-integrated combination. Figure 2 middle: 2-1a is a schematic diagram of a dual-unit integrated structure with a vertical layout and no pins on the same side for positive and negative poles.
[0033] Figure 2-1b is a schematic diagram of a dual-unit vertical layout dual-unit discrete integrated structure with positive and negative terminals on the same side and no pins.
[0034] 2-2a is a schematic diagram of a dual-unit integrated structure with pins vertically arranged on the same side of the positive and negative poles.
[0035] Figure 2-2b is a schematic diagram of a dual-unit discrete integrated structure with pins vertically arranged on the same side of the positive and negative terminals.
[0036] Figure 2-3a is a schematic diagram of a dual-unit integrated structure with a symmetrical layout without pins on both the positive and negative sides.
[0037] Figure 2-3b is a schematic diagram of a dual-unit discrete integrated structure with a symmetrical layout without pins on both the positive and negative sides.
[0038] Figure 2-4 shows a schematic diagram of a horizontally stacked integrated structure with pins distributed on both sides of the chip.
[0039] Figure 3 This is a schematic diagram of a multi-unit integrated array combination arrangement module structure. Figure 3 middle: 3-1 is a schematic diagram of a multi-unit discrete integrated structure with pinless vertical layout distributed on both sides.
[0040] 3-2 is a schematic diagram of a multi-unit discrete integrated structure with pins vertically arranged on both sides.
[0041] 3-3 is a schematic diagram of a multi-unit integrated structure with pins vertically arranged on both sides.
[0042] Figure 3-4 shows a schematic diagram of a multi-unit discrete integrated structure with pins horizontally arranged on both sides.
[0043] Figure 4 A schematic diagram of the external structure of the integrated module package. Figure 4 middle: 4-1 is a schematic diagram of the package structure of a pinned integrated module.
[0044] 4-2 is a schematic diagram of the external structure of a leadless integrated module package.
[0045] In the diagram: 1 is pin electrode 1, 2 is pin electrode 2, 3 is the chip, 4 is the soldering material layer, and 5 is the insulating connector. Detailed Implementation
[0046] like Figure 1-4 As shown, the specific implementation of the highly integrated multi-channel semiconductor device array module structure and its integration method is as follows: The chip mounting area has a gold or silver plating layer on its surface, and the electrode leads have a tin or gold plating layer.
[0047] The unit structure can be combined in various ways, and the positive and negative pins of the array module product can be arranged horizontally, such as... Figure 1-4 As shown. It can also be arranged vertically, such as... Figure 1-1 , Figure 1-2 , Figure 1-3 As shown.
[0048] like Figure 2 , Figure 3 As shown, non-integrated modules (i.e., separate modular modules) can be single-row integrated or double-row integrated. Multi-unit integrated modules can be designed and adjusted as needed, and can be integrated or independent. The arrangement direction can be horizontal single row, horizontal double row, or vertical single row or vertical double row.
[0049] like Figure 4 As shown, the integrated module product is packaged in the form of a leaded surface-mount package, a leadless surface-mount package, or other types of packages. The package shell of the integrated module product is square or other shapes.
[0050] The specific implementation process of the integration method is as follows: (1) Assembly: Assemble the chip and electrode according to the assembly requirements.
[0051] (2) Welding: Place the packaged product into a vacuum reflow oven or other welding equipment (such as chain furnace, laser welding equipment, wave soldering equipment) and weld it according to the corresponding welding process route or procedure.
[0052] (3) Encapsulation: When using potting process, potting glue is used to encapsulate product modules according to product requirements. The glue is injected into the product using a dispensing machine, and then cured according to the curing temperature and time requirements corresponding to the potting glue used. When using injection molding process, the welded unit assembly is loaded into the injection mold, and injection molding is performed after preheating.
[0053] (4) Use a cutting die to cut the ribs and remove excess lead edge material.
[0054] (5) After deburring the product, perform electrical characteristic testing, and after the test, metallize the pins.
[0055] (6) Conduct electrical characteristic tests on the metallized products.
[0056] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This invention includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all possible implementations. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this invention are within the protection scope of this invention.
Claims
1. A highly integrated multi-channel semiconductor device array module structure, characterized in that: Includes lead electrode 1, lead electrode 2, diode chip, and soldering material layer; One end of the pin electrode 1 and the pin electrode 2 is the chip mounting area, and the other end is the electrode lead-out end; The chip is assembled in the chip mounting area of pin electrode 1 and pin electrode 2, and a soldering material layer is between the chip and the chip mounting area to form a horizontally laid-out array module unit. The horizontally arranged array module units are stacked horizontally in multiple layers with positive and negative polarities on the same side or symmetrically arranged to form a horizontally arranged highly integrated semiconductor device product array module. An insulating connecting piece is welded to the back of the pin electrode 1 of the horizontally laid-out array module unit through a welding material layer to form a vertically laid-out array module unit; The vertically arranged array module units are vertically stacked in multiple layers with electrodes distributed on the same side or on both sides of the electrodes to form a vertically arranged highly integrated semiconductor device product array module. When the horizontal or vertical array module units are integrated, they are either integrated into a single package or separated into separate packages.
2. The highly integrated multi-channel semiconductor device array module structure as described in claim 1, characterized in that: The pin electrode 1 and pin electrode 2 are made of Kovar alloy or metallic copper.
3. The highly integrated multi-channel semiconductor device array module structure as described in claim 1, characterized in that: The chip mounting area has a gold or nickel plating layer on its surface, and the electrode leads have a tin or gold plating layer.
4. The highly integrated multi-channel semiconductor device array module structure as described in claim 1, characterized in that: The array module structure is packaged in either a leaded surface-mount package or a leadless surface-mount package.
5. The highly integrated multi-channel semiconductor device array module structure as described in claim 1, characterized in that: The array module structure has a square-shaped encapsulation shell.
6. The integration method of a highly integrated multi-channel semiconductor device array module structure as described in claim 1, characterized in that... This includes the following integration methods: (1) Unit combination method: Multiple single-row unit arrays or multiple symmetrical unit arrays are welded into the module product according to the set circuit to form a multi-unit semiconductor device integration; (2) Product packaging and molding process: injection molding or high-strength engineering plastic shell with potting compound and curing process; (3) Connection between chip electrode and electrode pad and exposed welding pin: The chip and electrode pad are welded by hot melt welding process using welding material. The electrode pad and exposed welding pin adopt an integrated structure and are integrally stamped with copper material with a thickness greater than 0.3mm. (4) Array module unit: The chip, positive electrode and negative electrode together form an array module unit. The connection between two symmetrical array module units is connected by an insulating connecting piece. (5) Connecting pieces are added between the array module units, and then all components are welded into a multi-unit array module using hot melt welding process with welding material; (6) According to the actual needs, the size and shape are combined into corresponding integrated module products, and then packaged and shaped.
7. The integration method of a highly integrated multi-channel semiconductor device array module structure as described in claim 6, characterized in that: The welding equipment includes vacuum reflow ovens, chain furnaces, laser welding equipment, or wave soldering equipment.
8. The integration method of a highly integrated multi-channel semiconductor device array module structure as described in claim 6, characterized in that: When using the potting process, the product modules are potted and encapsulated with potting compound according to product requirements. The dispensing machine is used to inject the compound into the product, and then the product is cured according to the curing temperature and time requirements corresponding to the potting compound used. When using the injection molding process, the welded units are assembled and filled with material using an injection mold. After preheating, the product is injection molded and encapsulated.
9. The integration method of a highly integrated multi-channel semiconductor device array module structure as described in claim 6, characterized in that: Use a cutting die to cut the ribs and remove excess lead edge material.
10. The integration method of a highly integrated multi-channel semiconductor device array module structure as described in claim 6, characterized in that: After deburring the product, electrical characteristic tests are performed, and the pins are then metallized.