Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same. A semiconductor device may include a substrate dielectric structure and a substrate conductive structure, the substrate conductive structure traversing the substrate dielectric structure and including a first substrate terminal and a second substrate terminal; an electronic component having a component terminal coupled to the first substrate terminal; and a first antenna assembly having a first assembly terminal coupled to the second substrate terminal, a first assembly head side adjacent to the first antenna pattern, a first assembly base side opposite to the first assembly side, and a first assembly sidewall. The first component terminal may be exposed from the first component dielectric structure at the first component base side or at the first component sidewall. The first antenna pattern may be coupled to the substrate via the first component terminal. The substrate conductive structure may couple the first antenna assembly to the electronic component.

Description

[0001] This application is a divisional application of the invention patent application filed on October 9, 2020, with a priority date of October 2, 2019, application number 202011070747.6, and entitled "Semiconductor Device and Method of Manufacturing Semiconductor Device". Technical Field

[0002] This disclosure relates generally to electronic components, and more specifically to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0003] Existing semiconductor packages and methods for forming semiconductor packages are inadequate, resulting in excessive costs, reduced reliability, relatively low performance, or excessively large package sizes. Further limitations and drawbacks of the conventional and prior art will become apparent to those skilled in the art through a comparison of the present disclosure and figures with those of conventional and prior art. Summary of the Invention

[0004] One embodiment of the present invention is a semiconductor device, the semiconductor device comprising: a substrate, including: a top side of the substrate; a bottom side of the substrate; a substrate dielectric structure between the top side of the substrate and the bottom side of the substrate; and a substrate conductive structure passing through the substrate dielectric structure and including: a first substrate terminal; and a second substrate terminal located at the top side of the substrate; an electronic component coupled to the substrate and including: a component terminal coupled to the first substrate terminal; and a first antenna assembly coupled to the substrate and including: a first assembly dielectric structure; a first antenna pattern coupled to the first assembly dielectric structure; and a first group of The components include: a first component terminal coupled to a second substrate terminal; a first component head side adjacent to the first antenna pattern; a first component base side relative to the first component side; and a first component sidewall between the first component head side and the first component base side; wherein: at least one of the first component terminals on the first component base side or the first component sidewall is exposed from the first component dielectric structure; the first antenna pattern is coupled to the substrate via the first component terminal; the first antenna assembly is coupled to the substrate outside the coverage area of ​​the electronic component; and the substrate conductive structure couples the first antenna assembly to the electronic component.

[0005] As described in one aspect of the semiconductor device of the present invention, the first antenna assembly includes: a first antenna path that traverses the dielectric structure of the first assembly and is coupled to the first antenna pattern and the first assembly terminal.

[0006] As described in one aspect of the semiconductor device of the present invention, the first antenna pattern is oriented to communicate along a direction substantially orthogonal to the first antenna head side.

[0007] The semiconductor device as described in one aspect of the present invention includes: a first component head side facing a vertical direction, and a first antenna pattern oriented to communicate along the vertical direction; and a first component base side coupled to the substrate.

[0008] The semiconductor device as described in one aspect of the present invention includes: a first component head side facing a first horizontal direction, and a first antenna pattern oriented to communicate along the first horizontal direction; and a first component sidewall coupled to the substrate.

[0009] The semiconductor device according to one embodiment of the present invention includes: a second antenna assembly coupled to the substrate; wherein: the substrate surrounding the coverage area of ​​the electronic component includes: a left-facing portion of the substrate, a right-facing portion of the substrate, an upward-facing portion of the substrate, and a downward-facing portion of the substrate; the first antenna assembly is coupled to the top side of the substrate at the left-facing portion of the substrate; and the second antenna assembly is coupled to the top side of the substrate at the right-facing portion of the substrate.

[0010] The semiconductor device according to one embodiment of the present invention includes: an encapsulation on the top side of the substrate; wherein: the second antenna assembly includes a second antenna pattern adjacent to the head side of the second assembly; the second antenna assembly includes a second assembly sidewall; the encapsulation covers the first assembly sidewall and the second assembly sidewall; and the encapsulation exposes the head side of the first assembly and the head side of the second assembly.

[0011] The semiconductor device according to one aspect of the present invention includes: a first component side coupled to a top side of a substrate; a second component side opposite to the first component side; a component sidewall between the first component side and the second component side; and a shielding structure covering the second component side and the component sidewall; and an encapsulant covering the shielding structure adjacent to the component sidewall.

[0012] As described in one aspect of the present invention, the semiconductor device includes: a first component head side facing a vertical direction, and a first antenna pattern oriented to communicate along the vertical direction; and a first component base side coupled to the substrate; and the second antenna assembly includes: a second component head side facing the vertical direction, and a second antenna pattern oriented to communicate along the vertical direction; and a second component base side coupled to the substrate.

[0013] As described in one aspect of the semiconductor device of the present invention, the first antenna pattern is oriented to communicate upwards along the vertical direction; the second antenna pattern is oriented to communicate downwards along the vertical direction.

[0014] As described in one aspect of the present invention, the semiconductor device includes: a first component head side facing a right direction, and a first antenna pattern oriented to communicate along the right direction; and a first component sidewall coupled to the substrate; and the second antenna assembly includes: a second component head side facing a left direction opposite to the right direction, and a second antenna pattern oriented to communicate along the left direction; and a second component sidewall coupled to the substrate.

[0015] As described in one aspect of the present invention, the semiconductor device includes: a first component head side facing a vertical direction, and a first antenna pattern oriented to communicate along the vertical direction; and a first component base side coupled to the substrate; and the second antenna assembly includes: a second component head side facing a right direction, and a second antenna pattern oriented to communicate along the right direction; and a second component sidewall coupled to the substrate.

[0016] The semiconductor device according to one embodiment of the present invention includes: a third antenna assembly coupled to the substrate at an upward portion of the substrate and including: a third assembly head side facing upward direction, and a third antenna pattern oriented to communicate along the upward direction; and a third assembly sidewall coupled to the substrate.

[0017] The semiconductor device according to one embodiment of the present invention includes: a fourth antenna assembly coupled to the substrate at a downward portion of the substrate and including: a fourth assembly head side facing downward direction, and a fourth antenna pattern oriented to communicate along the downward direction; and a fourth assembly sidewall coupled to the substrate.

[0018] The semiconductor device according to one embodiment of the present invention includes: a fifth antenna assembly coupled to the substrate at a leftward portion and including: a fifth assembly head side facing a leftward direction, and a fifth antenna pattern oriented to communicate along the leftward direction; and a fifth assembly sidewall coupled to the substrate.

[0019] The semiconductor device according to one embodiment of the present invention includes: a sixth antenna assembly coupled to the substrate at a right-hand portion and including: a sixth assembly head side and a sixth antenna pattern oriented for communication along the vertical direction; and a sixth assembly sidewall coupled to the substrate.

[0020] In one embodiment of the semiconductor device of the present invention, the electronic components are coupled to the bottom side of the substrate.

[0021] The semiconductor device as described in one aspect of the present invention includes a passive component coupled to the substrate and above the electronic component.

[0022] The semiconductor device as described in one aspect of the present invention includes a passive member coupled to the top side of the substrate between the first antenna assembly and the second antenna assembly.

[0023] Another aspect of the present invention is a method comprising: providing a substrate, the substrate including: a top side of the substrate; a bottom side of the substrate; a substrate dielectric structure between the top side of the substrate and the bottom side of the substrate; and a substrate conductive structure passing through the substrate dielectric structure and including: a first substrate terminal; and a second substrate terminal at the top side of the substrate; coupling an electronic component to the substrate, the electronic component including: a component terminal coupled to the first substrate terminal; and coupling a first antenna assembly to the substrate, the first antenna assembly including: a first assembly dielectric structure; a first antenna pattern coupled to the first assembly dielectric structure; and a first assembly terminal. The first component terminal is coupled to the second substrate terminal; a first component head side is adjacent to the first antenna pattern; a first component base side is opposite to the first component side; and a first component sidewall is located between the first component head side and the first component base side; wherein: at least one of the first component terminals is exposed from the first component dielectric structure on the first component base side or the first component sidewall; the first antenna pattern is coupled to the substrate via the first component terminal; the first antenna assembly is coupled to the substrate outside the coverage area of ​​the electronic component; and the substrate conductive structure couples the first antenna assembly to the electronic component. Attached Figure Description

[0024] Figure 1 A cross-sectional view of an exemplary semiconductor device is shown.

[0025] Figures 2A to 2I A cross-sectional view is shown of an exemplary method for manufacturing an exemplary semiconductor device.

[0026] Figure 3 As shown Figure 2C The diagram shows an exemplary method for manufacturing an exemplary semiconductor device.

[0027] Figure 4A and Figure 4B Plan and cross-sectional views of an exemplary antenna assembly and an exemplary layout of the antenna assembly are shown, which can be applied to exemplary methods for manufacturing exemplary semiconductor devices.

[0028] Figures 5A to 5C Plan and cross-sectional views of an exemplary antenna assembly and an exemplary layout of the antenna assembly are shown, which can be applied to exemplary methods for manufacturing exemplary semiconductor devices.

[0029] Figures 6A to 6FPlan and cross-sectional views of an exemplary antenna assembly and an exemplary layout of the antenna assembly are shown, which can be applied to exemplary methods for manufacturing exemplary semiconductor devices.

[0030] Figures 7A to 7D Plan view and cross-sectional view of an exemplary semiconductor device are shown.

[0031] Figures 8A to 8F A cross-sectional view is shown of an exemplary method for manufacturing an exemplary semiconductor device.

[0032] Figures 9A to 9F As shown Figures 8A to 8F The diagram shows a cross-sectional view of an exemplary method for manufacturing an exemplary semiconductor device.

[0033] Figure 10A and Figure 10B As shown Figure 8A and Figure 8B The diagram shows an exemplary method for manufacturing an exemplary semiconductor device.

[0034] Figure 11 A cross-sectional view of an exemplary semiconductor device is shown.

[0035] Figures 12A to 12F A cross-sectional view is shown of an exemplary method for manufacturing an exemplary semiconductor device.

[0036] Figure 13 As shown Figure 12A The diagram shows an exemplary method for manufacturing an exemplary semiconductor device.

[0037] Figure 14 A cross-sectional view of an exemplary semiconductor device is shown.

[0038] Figures 15A to 15G A cross-sectional view is shown of an exemplary method for manufacturing an exemplary semiconductor device.

[0039] Figure 16A and Figure 16B As shown Figure 15A and Figure 15B The diagram shows an exemplary method for manufacturing an exemplary semiconductor device. Detailed Implementation

[0040] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed herein. In the following discussion, the terms "example" and "for example" are non-limiting.

[0041] These figures illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the content of this disclosure. Furthermore, components in the figures are not necessarily drawn to scale. For example, the dimensions of some components may be enlarged relative to others to aid in understanding the paradigms discussed in this disclosure. The same reference numerals denote the same components in different figures.

[0042] The term "or" refers to any one or more items in a list linked by "or". For example, "x or y" represents any one of the three components in the set {(x), (y), (x,y)}. As another example, "x, y or z" represents any one of the seven components in the set {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}.

[0043] The terms “include” or “contain” are “open-ended” terms and specify the presence of the stated feature, but do not exclude the presence or addition of one or more other features.

[0044] The terms “first,” “second,” etc., may be used here to describe various components, and these components should not be limited by these terms. These terms are used only to distinguish one component from another. Thus, for example, without departing from the teachings of this disclosure, the first component discussed herein may be referred to as the second component.

[0045] Unless otherwise specified, the term "coupled" can be used to describe two components that are in direct contact with each other or to describe two components that are indirectly connected by one or more other components. For example, if component A is coupled to component B, then component A may be in direct contact with component B or indirectly connected to component B through an intermediate component C. Similarly, the terms "above" or "over" can be used to describe two components that are in direct contact with each other or to describe two components that are indirectly connected by one or more other components.

[0046] In one example, a semiconductor device may include: (a) a substrate, including: a top side of the substrate; a bottom side of the substrate; a substrate dielectric structure between the top side and the bottom side of the substrate; and a substrate conductive structure, the substrate conductive structure passing through the substrate dielectric structure and including: a first substrate terminal; and a second substrate terminal at the top side of the substrate; (b) an electronic component coupled to the substrate and including a component terminal coupled to the first substrate terminal; and (c) a first antenna assembly coupled to the substrate and including: a first component dielectric structure; a first antenna pattern coupled to the first component dielectric structure; a first component terminal coupled to the second substrate terminal; a first component head side adjacent to the first antenna pattern; a first component base side relative to the first component side; and a first component sidewall between the first component head side and the first component base side. The first component terminal may be exposed from the first component dielectric structure at at least one of the first component base side or the first component sidewall. The first antenna pattern may be coupled to the substrate via the first component terminal. The first antenna assembly may be coupled to the substrate outside the coverage area of ​​the electronic component. The substrate conductive structure may couple the first antenna assembly to the electronic component.

[0047] Other examples are included in this disclosure. These examples may be found in the drawings, in the claims, or in the detailed description of this disclosure.

[0048] Figure 1 A cross-sectional view of an exemplary semiconductor device 100 is shown. Figure 1 In the example shown, the semiconductor device 100 may include electronic components 110, antenna assembly 130, encapsulation 140, substrate 150, and external interconnects 160.

[0049] Electronic component 110 includes internal interconnects 111 and electromagnetic interference (EMI) shielding 112. Antenna assembly 130 may include dielectric structures 131, conductive structures 132 and 133, and antenna pattern 134. Substrate 150 may include dielectric structures 151 and 153 and conductive structure 152.

[0050] Antenna assembly 130, encapsulation 140, substrate 150, and external interconnect 160 may include, or be referred to as, semiconductor package 101 or package 101, and may protect electronic components 110 from exposure to external components or the environment. Semiconductor package 101 provides electrical coupling between external components and electronic components 110.

[0051] Figures 2A to 2I A cross-sectional view is shown of an exemplary method for manufacturing an exemplary semiconductor device 100. Figure 3 A plan view of an exemplary method for manufacturing an exemplary semiconductor device 100 is shown.

[0052] Figure 2A A cross-sectional view of the semiconductor device 100 at the front end of its manufacturing process is shown. Figure 2A In the example shown, the bottom surface 110b of the electronic component 110 may be attached to a temporary bonding layer 11 formed on the carrier 10. In some examples, multiple electronic components 110 may be arranged in a matrix configuration with rows or columns and spaced apart from each other, and may be attached to the carrier 10.

[0053] In some examples, the pick-and-place device can pick up and place the electronic component 110 onto the temporary bonding layer 11 of the carrier 10, and can also adhere to the temporary bonding layer 11. The electronic component 110 may have a substantially flat top surface (or non-active region), a substantially flat bottom surface (or active region) opposite the top surface, and side surfaces connecting the top and bottom surfaces to each other. The bottom surface of the electronic component 110 can be adhered to the temporary bonding layer 11 of the carrier 10. The electronic component 110 may include at least one internal interconnect 111 on its bottom surface. The internal interconnect 111 can be adhered to the temporary bonding layer 11 of the carrier 10. The internal interconnect 111 may be an external input / output terminal of the electronic component 110 and may include, or be referred to as, a die pad or bonding pad. The internal interconnect 111 may have a width ranging from about 2 μm to about 500 μm. The internal interconnect 111 may have a thickness ranging from about 3 μm to about 50 μm. The internal interconnect 111 may include a conductive material, such as a metal, aluminum, copper, aluminum alloy, or copper alloy.

[0054] Electronic component 110 may include, or be referred to as, a semiconductor die, a semiconductor chip, or a semiconductor package or subpackage. In some examples, electronic component 110 may include at least one of an application-specific integrated circuit, a logic die, a microcontroller unit, memory, a digital signal processor, a network processor, a power management unit, an audio processor, a radio frequency circuit, and a wireless baseband system-on-a-chip processor. Electronic component 110 may have a thickness ranging from about 0.01 mm to about 1 mm.

[0055] The carrier 10 may be a substantially flat plate. For example, the carrier 10 may include or be referred to as a plate, wafer, panel, semiconductor, or strip. In some examples, the carrier 10 may include, for example, steel, stainless steel, aluminum, copper, ceramic, glass, or a wafer. The carrier 10 may have a thickness ranging from about 0.5 mm to about 1.5 mm and a width ranging from about 200 mm to about 320 mm.

[0056] The carrier 10 can serve to integrate multiple components, such as attaching electronic components 110 and antenna assembly 130, forming EMI shielding 112, and forming encapsulation 140. The carrier 10 can be frequently used in some examples of the present disclosure.

[0057] A temporary bonding layer 11 may be disposed on the surface of the carrier 10. The temporary bonding layer 11 may be disposed on the surface of the carrier 10 in the following ways: coating processes, such as spin coating, doctor blade coating, casting, spraying, slot die coating, curtain coating, slide coating, or knife over edge coating; printing processes, such as screen printing, pad printing, gravure printing, flexographic coating, or offset printing; inkjet printing processes, which have intermediate characteristics of coating and printing; or direct attachment of an adhesive film or adhesive tape. The temporary bonding layer 11 may include or be referred to as a temporary adhesive film or temporary adhesive tape. The temporary bonding layer 11 may be, for example, a thermally peelable tape (film) or a UV-peelable tape (film), and its bonding strength may be weakened or removed by heating or UV irradiation. In some examples, the temporary bonding layer 11 may have weakened bonding strength or may be removable by physical or chemical external forces. The temporary bonding layer 11 may have a thickness ranging from about 20 μm to about 500 μm. The temporary bonding layer 11 may allow the carrier 10 to separate after the encapsulation 140, described later, is formed. The temporary bonding layer 11 may be frequently used in some examples of this disclosure.

[0058] Figure 2B A semiconductor device 100 is shown in the later stages of manufacturing. (As shown in...) Figure 2B In the example shown, EMI shielding 112 may cover electronic component 110. EMI shielding 112 may contact the top and side surfaces of electronic component 110. EMI shielding 112 may completely cover the top and side surfaces of electronic component 110 to achieve a uniform thickness.

[0059] The EMI shield 112 may be made of a conductive material to perform the function of shielding EMI induced from the antenna assembly 130 or shielding externally induced EMI to the electronic components 110. In some examples, the EMI shield 112 may include silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), palladium (Pd), or chromium (Cr). In some examples, the EMI shield 112 may be formed by sputtering, spraying, coating, or plating. In some examples, a cap-shaped metal cover may be used as the EMI shield 112. The EMI shield 112 may have a thickness ranging from about 0.1 μm to about 10 μm.

[0060] Figure 2C and Figure 3 A semiconductor device 100 is shown in the later stages of manufacturing. (As shown in...) Figure 2C In the example shown, the bottom surface 130b of the antenna assembly 130 can be bonded to a temporary bonding layer 11 disposed on the carrier 10.

[0061] In some examples, the pick-and-place device can pick up the antenna assembly 130 and place it on the surface of the temporary bonding layer 11 of the carrier 10, and it can be bonded. In some examples, the antenna assembly 130 can be configured such that two antennas are bonded to the carrier 10 to be positioned on opposite sides of the electronic component 110. The inner surface 130c of the antenna assembly 130 can be spaced apart from the side surface 110c of the electronic component 110 having the EMI shield 112. Here, the inner surface 130c of the antenna assembly 130 can face the side surface 110c of the electronic component 110, and the outer surface 130d of the antenna assembly 130 can face outwards to face the inner surface 130c of the antenna assembly 130. The antenna assembly 130 can extend parallel to the side surface 110c of the electronic component 110. The antenna assembly 130 can include a length ranging from about 0.01 mm to about 20 mm. The antenna assembly 130 can include a width ranging from about 0.01 mm to about 20 mm. Each of the antenna assemblies 130 may have a thickness or height ranging from about 0.01 mm to about 1 mm. In some examples, the antenna assembly 130 may include or be referred to as an antenna substrate, an antenna module, or an antenna block.

[0062] Antenna assembly 130 may include: a dielectric structure 131 having a substantially flat top surface and a bottom surface; conductive structures 132 and 133 exposed to the interior and bottom surface of dielectric structure 131; and an antenna pattern 134 exposed to the top surface of dielectric structure 131. Conductive structures 132 and 133 may include: a conductive pattern or terminal 132 exposed to the bottom surface of dielectric structure 131; and a conductive path 133 formed within dielectric structure 131. In some examples, antenna assembly 130 may be configured such that one or more of dielectric structures 131 and conductive paths 133 are stacked vertically in sequence.

[0063] In some examples, dielectric structure 131 may have substantially flat top and bottom surfaces. In some examples, dielectric structure 131 may include, or be referred to as, one or more dielectric layers, dielectrics, dielectric materials, insulating layers, or insulating materials. In some examples, dielectric structure 131 may include epoxy resin, phenolic resin, glass epoxy resin, polyimide, polyester fiber, epoxy molding compound, glass, or ceramic. Dielectric structure 131 may be configured such that one or more dielectric layers are stacked upwards. Dielectric structure 131 may keep antenna assembly 130 in a substantially flat state.

[0064] Conductive terminals 132 may be exposed through the bottom surface of dielectric structure 131. Conductive terminals 132 may have one or more patterns. Conductive terminals 132 may be electrically connected to at least one conductive path 133. Each of the conductive terminals 132 may include or be referred to as a conductor, conductive material, antenna land, conductive pad, antenna pad, wiring pad, connection pad, micropad, trace, or under-bump metal (UBM). In some examples, conductive terminals 132 may include copper, iron, nickel, gold, silver, palladium, or tin.

[0065] Conductive path 133 may pass through dielectric structure 131 to electrically connect conductive terminal 132 to antenna pattern 134. In some examples, conductive path 133 may include or be referred to as a conductor, conductive material, conductive via, conductive path, conductive trace, conductive pattern, conductive layer, redistribution layer, or circuit pattern. Conductive path 133 may be configured such that one or more conductive layers are stacked upwards using various patterns. In some examples, conductive path 133 may include copper, iron, nickel, gold, silver, palladium, or tin.

[0066] Antenna pattern 134 may be exposed through the top surface 130a of dielectric structure 131 to enable communication. Antenna pattern 134 may have one or more patterns. Antenna pattern 134 may be electrically connected to at least one conductive path 132. In some examples, each of antenna patterns 134 may include or be referred to as a dipole antenna, monopole antenna, patch antenna, loop antenna, beam antenna, dipole antenna, folded antenna, rhomboid antenna, or half-wave antenna. In some examples, antenna pattern 134 may include copper, gold, or silver.

[0067] Antenna assembly 130 can vertically transmit / receive signals using antenna pattern 134 positioned on the upper portion of antenna assembly 130. This antenna assembly 130 can be a vertical antenna. Antenna assembly 130 can vary in various ways considering structure and layout. In the following discussion, exemplary antenna assemblies and exemplary layouts of antenna assemblies that can be varied in various ways will be described.

[0068] Figure 4A and Figure 4B A view showing the layout of an exemplary antenna assembly is presented, which has along... Figure 4A The cross-sectional view taken by line 4B-4B can be applied to exemplary methods for manufacturing exemplary semiconductor devices, such as semiconductor device 100 or semiconductor device 1004. In some examples, antenna assembly 230 may be similar to antenna assembly 130, but may be oriented in a different manner. Figure 4A and Figure 4B In the example shown, the two antenna assemblies 230 can be coupled to the carrier 10 or the substrate 150 so that they can be positioned on opposite sides of the electronic component 110, as... Figure 2C and Figure 3 The antenna assembly 130 is shown. In some examples, the antenna assembly 230 may be similar to... Figure 2C The antenna assembly 130 shown is configured. In some examples, the antenna assembly 230 may be configured such that one or more of each of the dielectric structure 231 and the conductive structure 232 are stacked sequentially, whether inward, outward, or upward.

[0069] Each of the antenna assemblies 230 may include: a dielectric structure 231 having a substantially flat top surface and a bottom surface; a conductive structure 232 formed inside the dielectric structure 231 and exposed on a portion of the bottom surface 230b of the dielectric structure 231; and an antenna pattern 234 exposed on the outer surface 230d of the dielectric structure 231.

[0070] In some examples, the dielectric structure 231 can be similar to that in Figure 2 and Figure 3 The dielectric structure 131 is shown. The dielectric structure 231 can be configured such that one or more dielectric layers are stacked along the y-axis.

[0071] Conductive structure 232 may be formed within dielectric structure 131 and may be exposed to the bottom surface 230b of dielectric structure 231. Conductive structure 232 may be electrically connected to antenna pattern 134 and may be exposed to the bottom surface 230b of dielectric structure 231. In some examples, conductive structure 232 may include or be referred to as a conductor, conductive material, conductive via, conductive path, conductive trace, conductive pattern, conductive layer, redistribution layer (RDL), or circuit pattern. Conductive structure 232 may be configured such that one or more conductive layers are stacked from inner surface 230c to outer surface 230d using various patterns. In some examples, conductive path 232 may include copper, iron, nickel, gold, silver, palladium, or tin.

[0072] Antenna pattern 234 may be exposed through the outer surface 230a of dielectric structure 231 to enable communication. Antenna pattern 234 may be formed on the outer surface 230a of dielectric structure 231 to have one or more patterns. Antenna pattern 234 may be electrically connected to at least one conductive structure 232. In some examples, each of antenna patterns 134 may include or be referred to as a dipole antenna, monopole antenna, patch antenna, loop antenna, beam antenna, dipole antenna, folded antenna, rhomboid antenna, or half-wave antenna. In some examples, antenna pattern 234 may include copper, gold, or silver.

[0073] Antenna assembly 230 can transmit / receive signals using an antenna pattern 234 positioned on its outer surface 230d. This antenna assembly 230 can be a horizontal antenna.

[0074] Figure 5A , Figure 5B and Figure 5C A view showing the layout of an exemplary antenna assembly is presented, which has along... Figure 5A The cross-sectional views taken along lines 5B-5B and 5C-5C can be applied to exemplary methods for manufacturing exemplary semiconductor devices, such as semiconductor device 100 or semiconductor device 1005. Figures 5A to 5C In the example shown, four antenna assemblies 330 can be coupled to the carrier 10 or the substrate 150 such that two antennas are positioned on opposite sides of the electronic component 110. The antenna assemblies 330 may include, for example, similar to... Figure 2C and Figure 3 The antenna assembly 130 shown has two vertical antennas 330x with antenna pattern 334x, and similar to Figure 4A and Figure 4B The antenna assembly 230 shown has two horizontal antennas 330y with antenna pattern 334y. The vertical antenna 330x can be similar to... Figure 2C and Figure 3 The antenna assembly 130 shown, and the horizontal antenna 330y can be similar to Figure 4A and Figure 4B Antenna assembly 230 shown.

[0075] The antenna assembly 330 can use a vertical antenna 330X having an antenna pattern 334x located on the upper portion of the antenna assembly 330 to transmit / receive signals vertically, and can use a horizontal antenna 330y having an antenna pattern 334y located on the outer surface of a horizontal antenna 330y to transmit / receive signals laterally.

[0076] The antenna assembly 330 can be configured such that two antennas 330x and 330y with different orientations are longitudinally arranged on one side of the electronic component 110, and two antennas 330x and 330y with different orientations are longitudinally arranged on the other side of the electronic component 110.

[0077] Each of antennas 330x and 330y may extend in length ranging from about 0.01 mm to about 20 mm. Each of antennas 330x and 330y may extend in width ranging from about 0.01 mm to about 20 mm. Each of antenna assemblies 330x and 330y may have a thickness or height ranging from about 0.01 mm to about 1 mm. In some examples, each of antenna assemblies 330 may include or be referred to as an antenna substrate, antenna module, or antenna block.

[0078] Figure 6A , Figure 6B , Figure 6C and Figure 6D A view showing the layout of an exemplary antenna assembly is presented, which has along... Figure 6A The cross-sectional views taken by lines 6B-6B, 6C-6C, and 6D-6D can be applied to exemplary methods for manufacturing exemplary semiconductor devices, such as semiconductor device 100 or semiconductor device 1006. Figures 6A to 6D In the example shown, six antenna assemblies can be coupled to the carrier 10 or the substrate 150 such that antennas 330x and 330y are longitudinally positioned on the first opposite sides of the electronic component 110, as shown in the example. Figure 5A , Figure 5B and Figure 5C The antenna assembly 330 is shown in the layout, and the antenna 430z is longitudinally arranged on the second opposite side of the electronic component 110.

[0079] Antenna assembly 330 may include: a vertical antenna assembly 330x having an antenna pattern 334 facing one or more vertical directions at the assembly head side 135; and two horizontal antennas 330y having similar patterns at the assembly head side 135. Figures 5A to 5C The antenna assembly 330 shown has antenna patterns 334 facing the right and left horizontal directions, respectively. The antenna assembly 430 may include a horizontal antenna assembly 430z, which has antenna patterns 134 facing the upward and downward horizontal directions at the assembly head side 135, respectively.

[0080] Vertical antenna 330x can be used with Figure 2C and Figure 3 The antenna assembly 130 shown is configured in a similar manner, and the horizontal antennas 330y and 430z can be connected with... Figure 4A and Figure 4BThe antenna assembly 230 shown is configured in a similar manner.

[0081] The antenna assembly of semiconductor device 1006 can transmit / receive signals vertically using vertical antenna assembly 330x, and can transmit / receive signals horizontally using horizontal antenna assemblies 330y and 430z. In some examples, the individual antenna assemblies 330x, 330y, and 430z can all be similar to antenna assembly 130 or similar to each other. In some examples, the main difference between antenna assemblies 330x, 330y, and 430z may be their different orientations when coupled to carrier 10 or substrate 150.

[0082] Apart from Figure 2C , Figure 3 , Figure 4A , Figure 4B , Figures 5A to 5C and Figures 6A to 6D In addition to the configuration and layout of the antenna assemblies 130, 230, 330 and 430 shown, the construction and layout of the antenna assemblies can be changed by setting up the vertical or horizontal antennas in a manner similar to the vertical or horizontal antennas described in various ways.

[0083] Figure 2D A semiconductor device 100 is shown in the later stages of manufacturing. Figure 2D In the illustrated example, the encapsulation 140 may cover the carrier 10, the electronic component 110, and the antenna assembly 130. In some examples, the encapsulation 140 may be in contact with the top surface of the temporary bonding layer 11 of the carrier 10, the outer surface of the EMI shield 112 of the electronic component 110, and the side surface of the antenna assembly 130. Here, the antenna pattern 134 of the antenna assembly 130 may be exposed.

[0084] In some examples, encapsulation 140 may include, or be referred to as, an epoxy molding compound, epoxy molding resin, or sealant. In some examples, encapsulation 140 may include, or be referred to as, a molding portion, a sealing portion, an encapsulation portion, a protective portion, an encapsulation, or a body. In some examples, encapsulation 140 may include organic resins, inorganic fillers, curing agents, catalysts, coupling agents, colorants, and flame retardants. Encapsulation 140 can be formed by any of a variety of processes. In some examples, compression molding, transfer molding, liquid phase encapsulation molding, vacuum lamination, paste printing, or film-assisted molding can be used to form encapsulation 140. Encapsulation 140 may have a thickness ranging from about 0.1 mm to about 2 mm. Encapsulation 140 may cover electronic components 110 and antenna assembly 130 to protect them from exposure to external components or the environment.

[0085] Figure 2EA semiconductor device 100 is shown in the later stages of manufacturing. Figure 2E In the example shown, the semiconductor device 100 can be flipped to remove the carrier 110 while the carrier 10 is positioned on the electronic component 110, the antenna assembly 130, and the encapsulation 140. If the semiconductor device 100 is flipped in this manner, the antenna pattern 134 of the antenna assembly 130 can be positioned on the bottom surface of the semiconductor device 100.

[0086] The carrier 10 can be removed from the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulation 140. The temporary bonding layer 11 can be removed from the electronic component 110, the antenna assembly 130, and the encapsulation 140 while the temporary bonding layer 11 is bonded to the carrier 10. In some examples, heat, light, chemical solutions, or physical forces can be applied to the temporary bonding layer 11, thereby removing or reducing the bonding strength of the temporary bonding layer 11. Therefore, the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulation 110 can be exposed. The internal interconnects 111 of the electronic component 110 and the conductive terminals 130 of the antenna assembly 130 can also be exposed.

[0087] Figure 2F A semiconductor device 100 is shown in the later stages of manufacturing. Figure 2F In the example shown, dielectric structure 151 may be formed on the top surface 110b of electronic component 110, top surface 130b of antenna assembly 130 and top surface 140b of encapsulation 140, and may be patterned to expose internal interconnects 111 and conductive terminals 132.

[0088] The dielectric structure 151 may have a uniform thickness to cover the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulation 140. Holes 151x and 151y may be formed in the dielectric structure 151 to expose the internal interconnects 111 of the electronic component 110 and the conductive terminals 132 of the antenna assembly 130.

[0089] The dielectric structure 151 may include, or be referred to as, a dielectric, dielectric material, dielectric layer, passivation layer, insulating layer, or protective layer. In some examples, the dielectric structure 151 may include an electrically insulating material, such as a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding material, phenolic resin, epoxy resin, silicone resin, or acrylate polymer. In some examples, the dielectric structure 151 may be formed by any of a variety of processes. The dielectric structure 151 may be formed by, for example, spin coating, spraying, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The dielectric structure 151 may have a thickness ranging from about 5 μm to about 50 μm.

[0090] For example, a shielding pattern can be formed on the top surface of the dielectric structure 151, and the exposed dielectric structure 151 can be removed by etching to form holes 151x and 151y. Holes 151x and 151y may include, or be referred to as, openings or holes. The dielectric structure 151 can expose the top surface of the internal interconnects 111 of the electronic component 110 through hole 151x, and the top surface of the conductive terminals 132 of the antenna assembly 130 through hole 151y. For example, photoresist can be used as a shielding pattern.

[0091] Figure 2G A semiconductor device 100 is shown in the later stages of manufacturing. Figure 2G In the example shown, the conductive structure 152 may cover the top surface of the dielectric structure 151 exposed via holes 151x and 151y, the internal interconnects 111 of the electronic component 110, and the conductive terminals 132 of the antenna assembly 130.

[0092] The conductive structure 152 may have various patterns and may contact and be electrically connected to the internal interconnects 111 of the electronic component 110 and the conductive terminals 132 of the antenna assembly 130, which are exposed through holes 151x and 151y, respectively. The conductive structure 152 may include a conductor 152x that electrically connects the internal interconnects 111 of the electronic component 110 and the conductive terminals 132 of the antenna assembly 130 to each other. The conductor 152x may extend from a point above the electronic component 110 to a point above each antenna assembly in the antenna assembly 130 to electrically connect the electronic component 110 to the antenna assembly 130.

[0093] In some examples, the conductive structure 152 may include or be referred to as a conductor, conductive material, conductive layer, redistribution layer (RDL), wiring pattern, trace pattern, or circuit pattern. In some examples, the conductive terminal 132 may include copper, iron, nickel, gold, silver, palladium, or tin. In some examples, one or more conductors 152x may include or be referred to as traces, terminals, pads, vias, conductive patterns, conductive layers, or conductive paths, and may extend within and outside the coverage area of ​​the electronic component 110. In some examples, the conductive structure 152 may be formed using any of a variety of conductive materials, such as copper, gold, silver, or equivalents. The conductive structure 152 may be formed by any of a variety of processes, such as sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalent methods. The conductive structure 152 can be formed to have a uniform thickness to cover the top surface of the dielectric structure 151 exposed through the holes 151x and 151y, the internal interconnects 111 of the electronic component 110, and the conductive terminals 132 of the antenna assembly 130, and can be patterned using a shielding pattern to have multiple patterns. The conductive structure 152 can have a thickness ranging from about 3 μm to about 50 μm.

[0094] Figure 2H A semiconductor device 100 is shown in the later stages of manufacturing. Figure 2H In the example shown, dielectric structure 153 can cover dielectric structure 151 and conductive structure 152 to achieve a uniform thickness. Apertures 153x exposing the top surface 152b of conductive structure 152 can be formed in dielectric structure 153. Dielectric structure 153 can also expose the top surface of conductor 152x through apertures 153x. Dielectric structure 153 can be similar to dielectric structure 151 and can be formed in a similar manner to dielectric structure 151.

[0095] Although only two dielectric structures 151 and 153 and one conductive structure 152 in substrate 150 are shown, this is not a limitation of the present disclosure. In some examples, the number of structures constituting substrate 150 may be less or greater than the number of structures shown in the present disclosure.

[0096] In this example, substrate 150 is presented as a redistribution layer (RDL) substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, which (a) may be formed layer-by-layer over an electronic component electrically coupled to the RDL substrate, or (b) may be formed layer-by-layer over a carrier that can be completely or at least partially removed after the electronic component and the RDL substrate are coupled together. The RDL substrate may be fabricated layer-by-layer as a wafer-level substrate on a circular wafer in a wafer-level process, or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed in an additive manufacturing process and may include one or more dielectric layers stacked alternately with one or more conductive layers defining individual conductive redistribution patterns or traces, the conductive redistribution patterns or traces being configured to collectively (a) fan out of the coverage area of ​​the electronic component, or (b) fan in into the coverage area of ​​the electronic component. Conductive patterns can be formed using plating processes, such as electroplating or electroless plating. The conductive patterns can include conductive materials, such as copper or other platingable metals. The locations of the conductive patterns can be formed using photolithography processes, such as photolithography and photoresist processes that form photolithography shields. The dielectric layer of the RDL substrate can be patterned using a photolithography process that may include a photolithography shield through which light is exposed to have desired optical pattern features (e.g., vias in the dielectric layer). The dielectric layer can be made of a light-definable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). This dielectric material can be spin-coated or otherwise coated in liquid form, rather than being attached as a pre-formed film. To allow for the proper formation of the desired optically definable features, this light-definable dielectric material may omit structural reinforcing agents or may be filler-free, without strands, weaves, or other particles that could interfere with the photolithography process. In some examples, the filler-free nature of the dielectric material can reduce the thickness of the resulting dielectric layer. While the aforementioned light-defined dielectric material can be organic, in some examples, the dielectric material of the RDL substrate can comprise one or more inorganic dielectric layers. Some examples of inorganic dielectric layers can include silicon nitride (Si3N4), silicon oxide (SiO2), or SiON. Inorganic dielectric layers can be formed by growing them using oxidation or nitriding processes instead of light-defined organic dielectric materials. This inorganic dielectric layer can be filler-free, without strands, braids, or other distinct inorganic particles. In some examples, the RDL substrate can omit a permanent core structure or carrier, such as dielectric materials comprising bismaleimide triazine (BT) or FR4, and these types of RDL substrates can include, or are referred to as, coreless substrates. Other substrates described in this disclosure may also include RDL substrates.

[0097] In some examples, substrate 150 may be a pre-formed substrate. The pre-formed substrate can be manufactured before attachment to electronic components and may include a dielectric layer between individual conductive layers. The conductive layers may include copper and can be formed using an electroplating process. The dielectric layer may be a relatively thick, light-indistinguishable layer that can be attached as a pre-formed film rather than a liquid and may include a resin with fillers, such as strands, braids, or other inorganic particles, to improve rigidity or structural support. Because the dielectric layer is light-indistinguishable, features such as through-holes or openings can be formed using drilling or lasers. In some examples, the dielectric layer may include a prepreg material or an ajinomoto-based composite film (ABF). The pre-formed substrate may include a permanent core structure or carrier, such as a dielectric material comprising bismaleimide triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In some examples, the pre-formed substrate may be a coreless substrate omitting the permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier, which is removed after the dielectric and conductive layers are formed and before attachment to electronic components. The pre-formed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. This pre-formed substrate can be formed by a semi-additive or modified semi-additive process. Other substrates described in this disclosure may also include pre-formed substrates.

[0098] Figure 2I A semiconductor device 100 is shown in the later stages of manufacturing. Figure 2I In the example shown, external interconnect 160 may be formed on the top surface 152b of conductive structure 152.

[0099] External interconnect 160 can be electrically connected to the top surface 152b of conductive structure 152. External interconnect 160 can be electrically connected to electronic component 110 or to antenna assembly 130 via substrate 150. External interconnect 160 can be electrically connected to electronic component 110 and antenna assembly 130 via conductor 152x of substrate 150.

[0100] In some examples, external interconnect 160 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. External interconnect 160 may be formed using, for example, a ball-drop process, a screen printing process, or an electroplating process. For example, external interconnect 160 may be formed by pre-preparing a solder-containing conductive material on the top surface 152b of the conductive structure 152 of the substrate 150 using a ball-drop process followed by a reflow process. External interconnect 160 may include, or be referred to as, conductive balls (e.g., solder balls), conductive pillars (e.g., copper pillars), or conductive rods having solder caps on copper pillars. External interconnect 160 may have dimensions ranging from about 0.01 mm to about 1 mm. The completed semiconductor device 100 can be flipped so that the external interconnect 160 is positioned on the bottom surface 100y of the semiconductor device 100.

[0101] entire Figures 2A to 2I The proposed method can be used to complete different semiconductor devices, such as those with... Figures 4A to 6F The configuration corresponds to the semiconductor device. For example, Figure 6A A top view of semiconductor assembly 1006 is shown. Figures 6B to 6F A cross-sectional view of a semiconductor device 1006 along different antenna components 330x, 330y, and 430z is shown.

[0102] Figure 6A Several antenna assemblies are shown, which are coupled to substrate 150 at a substrate portion defined around the coverage area 119 of electronic component 110 or around the center of the arrangement of the antenna assemblies, this substrate portion being divided by dashed lines. Antenna assembly 330x1 is shown coupled to the left portion 156 of the substrate, antenna assembly 330x2 is shown coupled to the right portion 157 of the substrate, antenna assembly 330y1 is shown coupled to the right portion 157 of the substrate, antenna assembly 330y2 is shown coupled to the left portion 156 of the substrate, antenna assembly 430z1 is shown coupled to the upward portion 158 of the substrate, and antenna assembly 430z2 is shown coupled to the downward portion 159 of the substrate.

[0103] Substrate 150 includes a substrate dielectric structure having one or more dielectric layers, such as dielectric layers 151 and 153, between a top side 154 and a bottom side 155 of the substrate. Substrate 150 also includes a substrate conductive structure 152, which includes one or more conductors, conductive layers, pads, vias, or traces that traverse the substrate dielectric structure horizontally or vertically. The substrate conductive structure 152 may include substrate terminals 1521, and may include substrate terminals 1522 exposed at the top side 154 of the substrate. In some examples, substrate terminals 1521 and 1522 may include, or be referred to as, pads, vias, or traces.

[0104] Electronic component 110 may be coupled to substrate 150 and may include component terminals 115 coupled to substrate terminals 1521. In some examples, component terminals 115 may include, or be referred to as, pads, bumps, or pillars. In some examples, component side 117 of electronic component 110 may directly contact the top side 154 of substrate. In some examples, for instance, when component terminals 115 include bumps or pillars, component side 117 of electronic component 110 may be separated from the top side of substrate by a gap distance defined by the height of component terminals 115.

[0105] In some examples, Figure 6A The coverage area 119 shown may represent a region of the substrate 150 covered by the electronic component 110, wherein the electronic component 110 may be, for example, related to Figures 1 to 2I The electronic component 110 may be coupled to the top side 154 of the substrate in the manner shown and described, or the electronic component 110 may be, for example, related to the following Figures 11 to 16B The corresponding component is coupled to the bottom side 155 of the substrate in the manner shown and described.

[0106] Semiconductor device 1006 may include one or more passive components coupled to substrate 150. In some examples, the passive components may be similar in characteristics or location to the following relative to... Figures 7A to 10B or Figures 14 to 16BThe passive components 520 or 720 are further described. In some examples, one or more of the passive components may be at least partially coupled to the substrate 150 within the coverage area 119 of the electronic component 110, whether the passive component is on the bottom side 155 of the substrate and the electronic component 110 is on the top side 154 of the substrate, or whether the passive component is on the top side 154 of the substrate and the electronic component 110 is on the bottom side 155 of the substrate. In some examples, one or more of the passive components may be coupled to the upward portion 158 of the substrate, whether at the top side 154 of the substrate or the bottom side 155 of the substrate, between antenna assembly 330x1 and antenna assembly 330y1, adjacent to antenna assembly 430z1, or adjacent to electronic component 110. In some examples, one or more passive components may be coupled to the lower portion 159 of the substrate, whether at the top side 154 or the bottom side 155 of the substrate, between antenna assembly 330y2 and antenna assembly 330x2, adjacent to antenna assembly 430z2, or adjacent to electronic component 110. In some examples, one or more passive components may be coupled to the left portion 156 of the substrate, whether at the top side 154 or the bottom side 155 of the substrate, between antenna assembly 430z1 and antenna assembly 430z2, adjacent to antenna assembly 330x1 or antenna assembly 330y2, or adjacent to electronic component 110. In some examples, one or more passive components may be coupled to the right portion 157 of the substrate, whether at the top side 154 or the bottom side 155 of the substrate, between antenna assembly 430z1 and antenna assembly 430z2, adjacent to antenna assembly 330y1 or antenna assembly 330x2, or adjacent to electronic component 110.

[0107] Antenna assemblies 330x, 330y, and 430z may include an outwardly facing vertical surface horizontally outward of the semiconductor device 1006, and an inwardly facing vertical surface opposite to the outwardly facing vertical surface. Depending on the antenna assembly, the outwardly facing vertical surface may correspond to the assembly head side 135 or the assembly sidewall 136, and the inwardly facing vertical surface may correspond to the assembly base side 137 or the assembly sidewall 136. The semiconductor device 1006 may include an encapsulation 140 on the top side 154 of the substrate. In some examples, the encapsulation 140 may cover the inwardly facing vertical surface of the antenna assemblies 330x, 330y, or 430z. In some examples, the encapsulation 140 may cover the outwardly facing vertical surface of the antenna assemblies 330x, 330y, or 430z. In some examples, the encapsulation 140 exposes the outwardly facing vertical surface of the antenna assemblies 330x, 330y, or 430z. Encapsulation 140 may also cover the component sidewall 116 or component sidewall 115 of electronic component 110. In some examples, shielding structure 112 may cover both component sidewall 116 and component sidewall 115, and encapsulation 140 may subsequently cover shielding structure 112 adjacent to component sidewall 116 or adjacent component sidewall 115. In some examples, encapsulation 140 may expose shielding structure 112 adjacent to component sidewall 115.

[0108] Figure 6B The cross-sectional view shown corresponds to Figure 6A Lines 6B-6B are shown, and antenna assemblies 330x1 and 330x2 are coupled to the substrate 150 outside the coverage area 119 of the electronic component 110. Antenna assembly 330x1 or antenna assembly 330x2 may be similar to the previously described antenna assembly 130. Antenna assembly 330x1 may be similar to antenna assembly 330x2, but may be coupled relative to each other. The configuration, orientation, or characteristics of antenna assemblies 330y1 and 330y2 may be similar to those described above. Figures 1 to 3 The configuration, orientation, or characteristics described in the antenna assembly 130.

[0109] As an example, antenna assembly 330x2 includes: an assembly dielectric structure 131 including one or more dielectric layers; an antenna pattern 134 coupled to the assembly dielectric structure 131; and an assembly terminal 132 coupled to a substrate terminal 1522. The assembly terminal 132 may be part of a conductive structure 133 providing a conductive path or antenna path including one or more traces or vias passing through the assembly dielectric structure 131 to couple the antenna pattern 134 to the assembly terminal 132. Antenna assembly 330x1 also includes: an assembly head side 135 adjacent to the antenna pattern 134; an assembly base side 137 opposite to the assembly head side 135; and an assembly sidewall 136 between the assembly head side 135 and the assembly base side 137. In some examples, the antenna pattern 134 may be exposed at or through the assembly head side 134 for outbound or inbound wireless communication. In this example, component terminal 132 is exposed at component substrate side 137, and antenna pattern 134 is coupled to substrate 150 via component terminal 132 and substrate terminal 1522. Substrate conductive structure 152 couples antenna assembly 330x2 to electronic component 110, thereby providing a conductive path between component terminal 132 and component terminal 115.

[0110] Antenna pattern 134 can be configured or oriented to transmit or receive wireless communications along a direction substantially orthogonal to antenna head side 135 or antenna pattern 134. For antenna assembly 330x2, assembly head side 135 faces a top-vertical direction, antenna pattern 134 is oriented along this vertical direction for communication, and assembly base side 137 is coupled to substrate 150. Similarly, in this example, antenna assembly 330x1 includes assembly head side 135 facing a top-vertical direction, antenna pattern 134 is oriented along this vertical direction for communication, and assembly base side 137 is coupled to substrate 150. In some examples, encapsulation 140 may cover assembly head side 135 or antenna pattern 134. In some examples, encapsulation 140 may be applied, or antenna assembly 330x1 or antenna assembly 330x2 may be positioned such that assembly head side 135 or antenna pattern 134 remains exposed from encapsulation 140.

[0111] However, several examples are possible in which one or both of antenna assembly 330x1 or antenna assembly 330x2 can be oriented such that the antenna head side 135 faces a horizontal direction for communication along this horizontal direction. In these examples, the assembly sidewall 136 can be coupled to the substrate 150, or the assembly terminal 132 can be exposed at the assembly sidewall 137 and coupled to the substrate terminal 1522. Several examples are possible in which one of antenna assembly 330x1 or antenna assembly 330x2 can be oriented as described above for top-facing vertical communication, and the other of antenna assembly 330x1 or antenna assembly 330x2 can be oriented such that the antenna head side 135 faces a bottom-facing vertical direction for communication along this vertical direction.

[0112] Figure 6C The cross-sectional view shown corresponds to Figure 6A Lines 6C-6C show antenna assemblies 330y1 and 330y2 coupled to a substrate 150 outside the component coverage area 119 of the electronic component 110. Antenna assembly 330y1 or antenna assembly 330y2 may be similar to the previously described antenna assembly 130. Antenna assembly 330y1 may be similar to antenna assembly 330y2, but may be coupled opposite to each other. The configuration, orientation, or characteristics of antenna assemblies 330y1 and 330y2 may be similar to those described above regarding... Figures 4A to 4B Antenna assembly 230 in the middle.

[0113] exist Figure 6C In the antenna assembly 330y1, there is a component head side 135 facing a right-hand horizontal direction, an antenna pattern 134 oriented for communication along the right-hand horizontal direction, and a component sidewall 136 coupled to the substrate 150. Antenna assembly 330y2 includes a component head side 135 facing a left-hand horizontal direction, an antenna pattern 134 facing a left-hand horizontal direction, and a component sidewall 136 coupled to the substrate 150. In some examples, an encapsulation 140 may cover the component head side 135 or the antenna pattern 134. In some examples, the encapsulation 140 may be applied or the antenna assembly 330y1 or antenna assembly 330y2 may be positioned such that the component head side 135 or the antenna pattern 134 remains exposed from the encapsulation 140.

[0114] Figure 6D The cross-sectional view shown corresponds to Figure 6A Lines 6D-6D show antenna assemblies 330x1 and 330y1 coupled to a substrate 150 outside the component coverage area 119 of the electronic component 110. Antenna assembly 330x1 or antenna assembly 330y1 may be similar to the previously described antenna assembly 130. Antenna assembly 330x1 may be similar to antenna assembly 330y1, but may be coupled opposite to each other or coupled in different orientations.

[0115] exist Figure 6D In this embodiment, antenna assembly 330x1 includes a component head side 135 facing a vertically upward direction, an antenna pattern 134 oriented for communication along the vertically upward direction, and a component base side 137 coupled to substrate 150. Antenna assembly 330y1 has a component head side 135 facing a right-hand horizontal direction, an antenna pattern 134 oriented for communication along the right-hand horizontal direction, and a component sidewall 136 coupled to substrate 150. In some examples, encapsulation 140 may cover the component head side 135 or the antenna pattern 134. In some examples, encapsulation 140 may be applied or antenna assembly 330x1 or antenna assembly 330y1 may be positioned such that the component head side 135 or the antenna pattern 134 remains exposed from encapsulation 140.

[0116] Figure 6E The cross-sectional view shown corresponds to Figure 6A Lines 6E-6E show antenna assemblies 330y2 and 330x2 coupled to a substrate 150 outside the component coverage area 119 of the electronic component 110. Antenna assembly 330y2 or antenna assembly 330x2 may be similar to the previously described antenna assembly 130. Antenna assembly 330x2 may be similar to antenna assembly 330y2, but may be coupled opposite to each other or coupled in different orientations.

[0117] exist Figure 6E In the antenna assembly 330y2, there is a component head side 135 facing a left-hand horizontal direction, an antenna pattern 134 facing the left-hand horizontal direction, and a component sidewall 136 coupled to the substrate 150. Antenna assembly 330x2 includes a component head side 135 facing a top-vertical direction, an antenna pattern 134 oriented to communicate along the top-vertical direction, and a component base side 137 coupled to the substrate 150. In some examples, an encapsulation 140 may cover the component head side 135 or the antenna pattern 134. In some examples, the encapsulation 140 may be applied or the antenna assembly 330y2 or antenna assembly 330x2 may be positioned such that the component head side 135 or the antenna pattern 134 remains exposed from the encapsulation 140.

[0118] Figure 6F The cross-sectional view shown corresponds to Figure 6A Lines 6F-6F show antenna assemblies 430z1 and 430z2 coupled to a substrate 150 outside the component coverage area 119 of the electronic component 110. Antenna assembly 430z1 or antenna assembly 430z2 may be similar to the previously described antenna assembly 130. Antenna assembly 430z1 may be similar to antenna assembly 430z2, but may be coupled opposite to each other or coupled in different orientations.

[0119] exist Figure 6F In the antenna assembly 430z1, there is an upwardly facing head side 135, an antenna pattern 134 oriented to communicate along the upwardly facing vertical direction, and a sidewall 136 coupled to the substrate 150. Antenna assembly 430z2 includes a downwardly facing head side 135, an antenna pattern 134 communicating along the downwardly facing vertical direction, and a base side 137 coupled to the substrate 150. In some examples, an encapsulation 140 may cover the head side 135 or the antenna pattern 134. In some examples, the encapsulation 140 may be applied or the antenna assembly 430z1 or antenna assembly 430z2 may be positioned such that the head side 135 or the antenna pattern 134 remains exposed from the encapsulation 140.

[0120] Figures 7A to 7D Showing a perspective plan view of an exemplary semiconductor device, along... Figure 7A The cross-sectional view along line 7B-7B, along Figure 7A The cross-sectional view along line 7C-7C and along Figure 7A The cross-sectional view of line 7D-7D.

[0121] In such Figures 7A to 7D In the example shown, the semiconductor device 500 may include electronic components 110, passive components 520, antenna assembly 130, encapsulation 540, substrate 550, and external interconnects 160.

[0122] Electronic component 110, antenna assembly 130, and external interconnect 160 may be similar to, for example Figure 1 The components of the semiconductor device 100 shown are shown. Passive component 520 may include terminal 521. Substrate 550 may include dielectric structures 551 and 553 and conductive structure 552.

[0123] Antenna assembly 130, encapsulation 540, substrate 550, and external interconnect 160 may include, or be referred to as, a semiconductor package 501 or package 501, and may protect electronic components 110 and passive components 520 from exposure to external components or the environment. Semiconductor package 501 provides electrical coupling between external components and electronic components, and between said external components and passive components 520.

[0124] Figures 8A to 8F A cross-sectional view showing an exemplary method for manufacturing an exemplary semiconductor device 500. Figures 9A to 9F Display used for manufacturing Figures 8A to 8F The diagram shows a cross-sectional view of an exemplary method for manufacturing the exemplary semiconductor device 500. In particular, the cross-sectional view shows the exemplary method for manufacturing the exemplary semiconductor device 500. Figures 8A to 8F Show along Figure 7AThe cross-sectional view of line 7C-7C in the middle, and Figures 9A to 9F Show along Figure 7A A cross-sectional view along line 7D-7D. Specifically, along... Figure 7A The cross-sectional view of line 7B-7B in the middle can be similar to Figures 2C to 2I The cross-sectional view shown.

[0125] Figure 8A , Figure 9A and Figure 10A Semiconductor device 500 is shown in the front-end manufacturing stage.

[0126] As in Figure 8A , Figure 9A and Figure 10A In the example shown, a semiconductor device 500 can be fabricated. For example... Figure 8A , Figure 9A and Figure 10A The semiconductor device 500 shown may be similar to, for example Figures 2A to 2C and Figure 3 The semiconductor device 100 is manufactured by the exemplary method of manufacturing the semiconductor device 100 shown.

[0127] Figure 8B , 9B And 10B shows the semiconductor device 500 in the later stages of manufacturing. In Figure 8B , Figure 9B and Figure 10B In the example shown, the bottom surface 520b of the passive member 520 can be bonded to the surface of the temporary bonding layer 11 of the carrier 10. The passive member 520 can be bonded to the carrier 10 so as to be positioned on the opposite side of the electronic member 110 along the first direction x. The passive member 520 can be arranged on and bonded to the temporary bonding layer 11 of the carrier 10 in a matrix configuration having rows or columns, so that the passive member 520 can be positioned in the second direction y between the antenna assemblies 130 that are spaced apart from each other. The terminals 521 of the passive member 520 can be bonded to the temporary bonding layer 11.

[0128] In some examples, the pick-and-place device can pick up and place the passive member 520 onto and adhere it to the temporary bonding layer 11 of the carrier 10. The bottom surface of the passive member 520 can be adhered to the temporary bonding layer 11. The passive member 520 may include terminals 521 exposed on its bottom surface. The terminals 521 can be adhered to the temporary bonding layer 11 of the carrier 10. The terminals 521 may be input / output terminals of the passive member 520.

[0129] In some examples, the passive component 520 may include at least one of a resistor, capacitor, inductor, connector, and equivalent. The passive component 520 may have an overall thickness ranging from about 0.01 mm to about 2 mm.

[0130] Antenna assembly 130 can be used by Figure 2C , Figure 3 , Figure 4A , Figure 4B , Figures 5A to 5C as well as Figures 6A to 6D The layout of the antenna assemblies 130, 230, 330, and 430 shown can be varied. Alternatively, antenna assembly 130 can be varied by arbitrarily configuring a vertical or horizontal antenna in various ways. Here, the passive member 520 can be varied according to the layout, thus being configured in various ways within the surface of the temporary bonding layer 11 of the carrier 10 according to the layout of the antenna assemblies 130, 230, 330, and 430.

[0131] Figure 8C and Figure 9C Semiconductor device 500 is displayed during the later stages of manufacturing. (In such...) Figure 8C and Figure 9C In the illustrated example, encapsulation 540 may cover carrier 10, electronic components 110, passive components 520, and antenna assembly 130. In some examples, encapsulation 540 may contact the top surface of the temporary bonding layer 11 of carrier 10, the outer surface of EMI shield 112, the top and side surfaces of passive components 520, and the side surface of antenna assembly 130. Here, the antenna pattern 134 of antenna assembly 130 may be exposed. Encapsulation 540 may be similar to and formed similarly to encapsulation 140.

[0132] Figure 8D and Figure 9D Semiconductor device 500 is displayed during the later stages of manufacturing. (In such...) Figure 8D and Figure 9D In the example shown, the semiconductor device 500 can be flipped to remove the carrier 10 when it is positioned on the electronic component 110, the passive component 520, the antenna assembly 130, and the encapsulation 540.

[0133] The carrier 10 can be removed from the top surface 110b of the electronic component 110, the top surface 520b of the passive component 520, the top surface of the antenna assembly 130, and the top surface 540b of the encapsulation 540. Therefore, the top surface 110b of the electronic component 110, the top surface 520b of the passive component 520, the top surface of the antenna assembly 130, and the top surface 540b of the encapsulation 540 can be exposed. The internal interconnects 111 of the electronic component 110, the terminals 521 of the passive component 520, and the conductive terminals 132 of the antenna assembly 130 can also be exposed. The removal of the carrier 10 can be similar to... Figure 2E The removal of carrier 10 shown.

[0134] Figure 8E and Figure 9E Semiconductor device 500 is displayed during the later stages of manufacturing. (In such...) Figure 8E and Figure 9E In the illustrated example, substrate 550 may be formed on the top surface 110b of electronic component 110, the top surface 520b of passive component 520, the top surface of antenna assembly 130, and the top surface 540b of encapsulation 540. In some examples, substrate 550 may be similar to substrate 150 or may include or be referred to as substrate. Substrate 550 may include dielectric structure 551, conductive structure 552, and dielectric structure 553 and are formed sequentially.

[0135] The dielectric structure 551 may be first formed on the substrate 550 to cover the top surface 110b of the electronic component 110, the top surface 520b of the passive component 520, the top surface of the antenna assembly 130, and the top surface 540b of the encapsulation 540 to a uniform thickness. Holes 551x, 551y, and 551z, respectively exposing the internal interconnects 111 of the electronic component 110, the conductive terminals 132 of the antenna assembly 130, and the terminals 521 of the passive component 520, may be formed in the dielectric structure 551. The dielectric structure 551 may expose the top surface of the internal interconnects 111 of the electronic component 110 through hole 551x, the top surface of the conductive terminals 132 of the antenna assembly 130 through hole 551y, and the top surface of the terminals 521 of the passive component 520 through hole 551z. The dielectric structure 551 may be similar to and formed in a manner similar to dielectric structure 151.

[0136] The conductive structure 552 may cover the internal interconnects 111 of the electronic component 110, the conductive terminals 132 of the antenna assembly 130, and the terminals 521 of the passive component 520, and is exposed through the top surface of the dielectric structure 551 and the holes 551x, 551y, and 551z.

[0137] The conductive structure 552 may be formed with multiple patterns and connected to the interconnects 111 of the electronic component 110, the conductive terminals 132 of the antenna assembly 130, and the terminals 521 of the passive component 520. It may be exposed through apertures 551x, 551y, and 551z, respectively, and may be electrically connected. The conductive structure 552 may include traces 552x that electrically connect the internal interconnects 111 of the electronic component 110 and the terminals 521 of the passive component 520 to each other. The traces 552x may extend from a point on the electronic component 110 to a point on the passive component 520 to electrically connect the internal interconnects 111 of the electronic component 110 and the conductive terminals 132 of the antenna assembly 130 to each other, just as with the passive component 520. The traces 552x may also electrically connect the internal interconnects 111 of the electronic component 110 and the conductive terminals 132 of the antenna assembly 130, just as with the passive component 520. Figure 2G The conductive structure 552 is the same as the conductive structure 152 shown. The conductive structure 552 may be similar to and may be formed in a similar manner to the conductive structure 152.

[0138] The dielectric structure 553 can cover the dielectric structure 551 and the conductive structure 552 to form a uniform thickness. A hole 553x exposing the top surface 552b of the conductive structure 552 can be formed in the dielectric structure 553. The dielectric structure 553 can also expose the top surface of the trace 552y through the hole 553x. The dielectric structure 553 can be similar to and formed in a manner analogous to the dielectric structure 151.

[0139] Although only two dielectric structures 551 and 553 and one conductive structure 552 are shown in the substrate 550, this is not a limitation of the invention. In some embodiments, the number of structures forming the substrate 550 may be less or greater than the number shown in the embodiments of the invention.

[0140] Figure 8F and Figure 9F Semiconductor device 500 is displayed during the later stages of manufacturing. Figure 8F and Figure 9F In the example shown, external interconnect 160 may be formed on the top surface 552b of the conductive structure 552.

[0141] External interconnect 160 may be electrically connected to the top surface 552b of conductive structure 552. External interconnect 160 may be electrically connected to electronic component 110, passive component 520, or antenna assembly 130 via substrate 150. External interconnect 160 may be electrically connected to electronic component 110 and antenna assembly 130 via conductor 152x, or external interconnect 160 may be electrically connected to both electronic component 110 and passive component 520 simultaneously. External interconnect 160 may be similar to and formed similarly to the external interconnect 160 of semiconductor device 100.

[0142] Figure 11 This shows a cross-sectional view of an exemplary semiconductor device 600. (Example:) Figure 11 As shown in the example, semiconductor device 600 may include electronic components 610, antenna assembly 630, encapsulation 640, substrate 650, and external interconnects 660.

[0143] Electronic component 610 may include internal interconnects 611. Antenna assembly 630 may include dielectric structure 631, conductive structures 632 and 633, and antenna pattern 634. Substrate 650 may include dielectric structures 651 and 653 and conductive structure 652.

[0144] Antenna assembly 630, encapsulation 640, substrate 650 and external interconnect 660 may include or be referred to as semiconductor package 601 or package 601 and may protect electronic components 610 from exposure to external components or the environment.

[0145] Figures 12A to 12F A cross-sectional view showing an exemplary method for manufacturing an exemplary semiconductor device 600. Figure 13 Display used for manufacturing such as Figure 12A A cross-sectional view of an exemplary method of the exemplary semiconductor device 600 shown.

[0146] Figure 12A and Figure 13 Semiconductor device 600 is shown in the front-end manufacturing stage. In such... Figure 12A and Figure 13 In the example shown, the bottom surface 630b of the antenna assembly 630 can be bonded to a temporary bonding layer 11 provided on the carrier 10.

[0147] In some examples, the pick-and-place device can pick up and place the antenna assembly 630 onto the surface of the temporary bonding layer 11 of the carrier 10 and can be bonded to the temporary bonding layer 11. In some examples, two antenna assemblies 630 can be bonded to the carrier 10 so as to be positioned on opposite sides along the second direction y. The two antenna assemblies 630 can be arranged such that the inner surfaces 630c of the two antenna assemblies 630 face each other and are spaced apart from each other. Each of the antenna assemblies 630 can extend longitudinally along the first direction x. The antenna assembly 630 can be similar to and can be formed similarly to the antenna assembly 130. The antenna assembly 630 can be formed by means of... Figure 3 , Figure 4A , Figure 4B , Figures 5A to 5C as well as Figures 6A to 6D The layout used by antenna assemblies 230, 330, and 430 shown can be changed. Alternatively, antenna assembly 630 can be changed by arbitrarily configuring vertical or horizontal antennas in various ways.

[0148] Figure 12B Semiconductor device 600 is shown during the later stages of manufacturing. Figure 12B In the illustrated example, encapsulation 640 may cover carrier 10 and antenna assembly 630. In some examples, encapsulation 640 may contact the top surface of temporary bonding layer 11 of carrier 10 and the side surface of antenna assembly 630. Here, antenna pattern 634 of antenna assembly 630 may be exposed. Encapsulation 640 may be similar to and formed similarly to encapsulation 140.

[0149] Figure 12C Semiconductor device 600 is shown during the later stages of manufacturing. Figure 12C In the example shown, the semiconductor device 600 can be flipped to remove the carrier 10 when it is positioned on the antenna assembly 630 and the encapsulation 640.

[0150] The carrier 10 can be removed from the top surface 630b of the antenna assembly 630 and the top surface 640b of the encapsulation 640. Therefore, the top surface 630b of the antenna assembly 630 and the top surface 640b of the encapsulation 640 can be exposed. The conductive pattern 632 of the antenna assembly 630 can also be exposed. The removal of the carrier 10 is similar to... Figure 2E The removal of carrier 10 shown.

[0151] Figure 12D Semiconductor device 600 is shown during the later stages of manufacturing. Figure 12DIn the illustrated example, substrate 650 may be formed on the top surface 630b of antenna assembly 630 and the top surface 640b of encapsulation 640. In some examples, substrate 650 may be similar to substrate 150, or may include or be referred to as substrate. Substrate 650 may include dielectric structure 651, conductive structure 652, and dielectric structure 653 and are formed sequentially.

[0152] The dielectric structure 651 can cover the top surface 630b of the antenna assembly 630 and the top surface 640b of the encapsulant 640 with a uniform thickness. Apertures 651x exposing the conductive pattern 632 of the antenna assembly 630 can be formed in the dielectric structure 651. The dielectric structure 651 can expose the top surface of the conductive pattern 632 of the antenna assembly 630 through the apertures 651x. The dielectric structure 651 can be similar to and formed similarly to dielectric structure 151.

[0153] Conductive structure 652 may cover the top surface of dielectric structure 651 and the conductive pattern 632 of antenna assembly 630 exposed via aperture 651x. Conductive structure 652 may have multiple patterns that respectively contact and are electrically connected to the conductive pattern 632 of antenna assembly 630 exposed via aperture 651x. Conductive structure 652 may be electrically connected to the conductive pattern 632 of antenna assembly 630 and may include traces 652x extending along the top surface 640b of encapsulation 640. Conductive structure 652 may be similar to and may be formed in a manner similar to conductive structure 152.

[0154] The dielectric structure 653 can cover the dielectric structure 651 and the conductive structure 652 to form a uniform thickness. A hole 653x exposing the top surface 652b of the conductive structure 652 can be formed in the dielectric structure 653. The dielectric structure 653 can also expose the top surface of the trace 652x through the hole 653x. The dielectric structure 653 can be similar to and formed in a manner analogous to the dielectric structure 651.

[0155] Although only two dielectric structures 651 and 653 and one conductive structure 652 are shown in the substrate 650, this is not a limitation of the invention. In some embodiments, the number of structures forming the substrate 650 may be less or greater than the number shown in the embodiments of the invention.

[0156] Figure 12E Semiconductor device 600 is shown during the later stages of manufacturing. Figure 12E In the example shown, the internal interconnect 611 of the electronic component 610 is electrically connected to the top surface 652b of the conductive structure 652. The electronic component 610 can be positioned at the center of the substrate 650.

[0157] In some examples, the pick-and-place device can pick up and place electronic component 610 onto trace 652x of conductive structure 652 of substrate 650. Subsequently, electronic component 610 can be electrically connected to conductive structure 652 of substrate 650 using a mass reflow process, thermoforming process, or film-assisted bonding process. Electronic component 610 can be electrically connected to antenna assembly 630 via conductive structure 652 of substrate 650.

[0158] In some examples, electronic component 610 may include active and inactive regions. In some examples, the active region may be formed facing the substrate 650. In some examples, the active region may include internal interconnects 611. In some examples, the internal interconnects 611 may include or be referred to as die pads, bonding pads, aluminum pads, conductive pillars, or conductive rods.

[0159] Internal interconnects 611 can be connected to the conductive structure 652 of the substrate 650 using a low-melting-point material 612. In some examples, the low-melting-point material 612 may comprise one selected from the group consisting of: Sn, Ag, Pb, Cu, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, Sn-Ag-Cu, and equivalents. The internal interconnects 611 of the electronic component 610 and the conductive structure 652 of the substrate 650 can be electrically connected to each other by means of the low-melting-point material 612. The electronic component 610 may have an overall thickness in the range of approximately 0.1 mm to approximately 1 mm.

[0160] Figure 12F Semiconductor device 600 is shown during the later stages of manufacturing. Figure 12F In the example shown, an external interconnect 660 is formed on the top surface 652b of the conductive structure 652. The external interconnect 660 can be electrically connected to the top surface 652b of the conductive structure 652.

[0161] External interconnects 660 may be disposed on the outside of electronic component 610 and spaced apart from each other in a matrix configuration having rows or columns. External interconnects 660 may be electrically connected to electronic component 610 or antenna assembly 630 via substrate 650. External interconnects 660 may be electrically connected to electronic component 610 and antenna assembly 630 via traces 652x. External interconnects 660 may be similar to and formed similarly to external interconnect 160.

[0162] Figure 14 This shows a cross-sectional view of an exemplary semiconductor device 700. Figure 14In the example shown, the semiconductor device 700 may include electronic components 710, passive components 720, antenna assembly 630, encapsulation 740, substrate 750, and external interconnects 760.

[0163] Electronic component 710 may include internal interconnects 711. Passive component 720 may include terminals 721. Antenna assembly 630 may include dielectric structures 631, conductive structures 632 and 633, and antenna pattern 634. Substrate 750 may include dielectric structures 751 and 653 and conductive structure 752.

[0164] Antenna assembly 630, encapsulation 740, substrate 750, and external interconnect 760 may include, or be referred to as, a semiconductor package 701 or package 701, and may protect electronic component 710 from exposure to external components or the environment. Semiconductor package 701 provides electrical coupling between external components and electronic component 710.

[0165] Figures 15A to 15G A cross-sectional view showing an exemplary method for manufacturing an exemplary semiconductor device 700. Figures 16A to 16B Display used for manufacturing Figures 15A to 15B A plan view of an exemplary method of the exemplary semiconductor device 700 shown.

[0166] Figure 15A and Figure 16A Semiconductor device 700 is shown in the front-end manufacturing stage. Figure 15A and Figure 16A In the example shown, a semiconductor device 700 can be fabricated. For example... Figure 15A and Figure 16A The semiconductor device 700 shown may be similar to, for example Figure 12A and Figure 13 The semiconductor device 600 shown is manufactured by an exemplary method.

[0167] Figure 15B Semiconductor device 700 is shown during the later stages of manufacturing. (As in...) Figure 15B In the example shown, the bottom surface 720b of the passive member 720 can be bonded to the surface of the temporary bonding layer 11 of the carrier 10. The passive member 720 can be positioned between the inner surfaces 630c of two separated antenna assemblies 630. The passive members 720 can be disposed on the temporary bonding layer 11 of the carrier 10 and separated from each other in a matrix configuration having rows or columns, so as to be positioned between two antenna assemblies 630 separated from each other in the second direction y and bonded to the temporary bonding layer 11 of the carrier 10. The terminals 721 of the passive member 720 can also be bonded to the temporary bonding layer 11. The passive member 720 can be similar to and can be formed similarly to the passive member 520.

[0168] Figure 15C Semiconductor device 700 is displayed during the later stages of manufacturing. For example... Figure 15C In the illustrated example, encapsulation 740 may cover carrier 10, passive member 720, and antenna assembly 630. In some examples, encapsulation 740 may contact the top surface of temporary bonding layer 11 of carrier 10, the side surface of passive member 720, and the side surface of antenna assembly 630. Here, antenna pattern 634 of antenna assembly 630 may be exposed. Encapsulation 740 may be similar to and formed similarly to encapsulation 140.

[0169] Figure 15D Semiconductor device 700 is displayed during the later stages of manufacturing. For example... Figure 15D In the example shown, the semiconductor device 700 can be flipped, and the carrier 10 can be removed while the carrier 10 is in the state of being on the antenna assembly 630 and the encapsulation 740.

[0170] The carrier 10 can be removed from the top surface 630b of the antenna assembly 630, the top surface 720b of the passive member 720, and the top surface 740b of the encapsulation 740. Therefore, the top surface 630b of the antenna assembly 630, the top surface 720b of the passive member 720, and the top surface 740b of the encapsulation 740 can also be exposed. The terminals 721 of the passive member 720 and the conductive pattern 632 of the antenna assembly 630 can also be exposed. The removal of the carrier 10 can be similar to... Figure 2E The removal of carrier 10 shown.

[0171] Figure 15E Semiconductor device 700 is displayed during the later stages of manufacturing. For example... Figure 15E In the illustrated example, substrate 750 may be formed on the top surface 630b of antenna assembly 630 and the top surface 740b of encapsulation 740. In some examples, substrate 650 may be similar to substrate 150, or may include or be referred to as substrate. Substrate 750 may include dielectric structure 751, conductive structure 752, and dielectric structure 753 and formed sequentially.

[0172] The dielectric structure 751 can cover the top surface 630b of the antenna assembly 630, the top surface 720b of the passive member 720, and the top surface 740b of the encapsulant 740 with a uniform thickness. Holes 751x and 751y exposing the conductive pattern 632 of the antenna assembly 630 and the terminals 721 of the passive member 720 can be formed in the dielectric structure 751. The dielectric structure 751 can also expose the conductive pattern 632 of the antenna assembly 630 and the terminals 721 of the passive member 720 via the holes 751x and 751y. The dielectric structure 751 can be similar to and formed in a manner similar to dielectric structure 151.

[0173] The conductive structure 752 may cover the top surface of the dielectric structure 751 exposed through apertures 751x and 751y, the conductive pattern 632 of the antenna assembly 630, and the terminals 721 of the passive member 720. The conductive structure 752 may have multiple patterns, and these multiple patterns respectively contact and are electrically connected to the conductive pattern 632 of the antenna assembly 630 and the terminals 721 of the passive member 720 exposed through apertures 751x and 751y. The conductive structure 752 may be electrically connected to the terminals 721 of the passive member 720 and may include a trace 752y extending along the top surface 740b of the encapsulation 740. The trace 752y may be electrically connected to the conductive pattern 632 of the antenna assembly 630 (such as...). Figure 12D The conductive structure 652 shown may extend along the top surface 740b of the encapsulation 740. The conductive structure 752 may be similar to and formed similarly to the conductive structure 152.

[0174] The dielectric structure 753 may cover both the dielectric structure 751 and the conductive structure 752 to achieve a uniform thickness. A hole 753x exposing the top surface 752b of the conductive structure 752 may be formed in the dielectric structure 753. The dielectric structure 753 may also expose the top surface of the trace 752y through the hole 753x. The dielectric structure 753 may be similar to and formed in a manner analogous to the dielectric structure 751.

[0175] Although only two dielectric structures 751 and 753 and one conductive structure 752 are shown in the substrate 750, this is not a limitation of the invention. In some embodiments, the number of structures forming the substrate 750 may be less or greater than the number shown in the embodiments of the invention.

[0176] Figure 15F Semiconductor device 700 is displayed during the later stages of manufacturing. For example... Figure 15F In the illustrated example, the internal interconnect 711 of the electronic component 710 can be electrically connected to the top surface 752b of the conductive structure 752. The electronic component 710 can be positioned at the center of the substrate 750. The electronic component 710 can be positioned on the trace 752y for electrical connection to the conductive structure 752. The electronic component 710 can be electrically connected to the passive component 720 or the antenna assembly 730 via the substrate 750. The electronic component 710 can be similar to and can be formed similarly to the electronic component 610.

[0177] Figure 15G Semiconductor device 700 is displayed during the later stages of manufacturing. For example... Figure 15GIn the example shown, an external interconnect 760 may be formed on the top surface 752b of the conductive structure 752. The external interconnect 760 may be electrically connected to the top surface 752b of the conductive structure 752.

[0178] External interconnects 760 may be formed on the outside of electronic components 710 and spaced apart from each other in a matrix configuration with rows or columns. External interconnects 760 may be electrically connected to electronic components 710, passive components 720, or antenna assembly 730 via substrate 750. External interconnects 760 may be electrically connected to both electronic components 710 and passive components 720 simultaneously via trace 752y, or electrically connected to both electronic components 710 and antenna assembly 730. External interconnects 760 may be similar to and formed similarly to external interconnects 160.

[0179] This disclosure contains references to certain examples. However, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the disclosed examples, but rather to include all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes: Top side of the substrate; Bottom side of the substrate; A substrate dielectric structure, the substrate dielectric structure being located between the top side and the bottom side of the substrate; and A substrate conductive structure, the substrate conductive structure passing through the substrate dielectric structure and comprising: First substrate terminal; and The second substrate terminal is located on the top side of the substrate. Electronic components, coupled to the substrate and comprising: Component terminals, wherein the component terminals are coupled to the first substrate terminals; as well as A first antenna assembly, coupled to the substrate and comprising: First component head side; First component dielectric structure; A first component conductive structure, the first component conductive structure including a first component terminal and in contact with the first component dielectric structure; and A first antenna pattern is located at the head side of the first component and is grouped with the first component terminals and the first component conductive structure; in: The first antenna assembly is coupled to the substrate outside the coverage area of ​​the electronic component; and The first component terminal is coupled to the second substrate terminal.

2. The semiconductor device as claimed in claim 1, characterized in that: The head side of the first component is oriented to face a first direction substantially parallel to the top side of the substrate, a second direction substantially opposite to the first direction, or a third direction substantially orthogonal to the first direction.

3. The semiconductor device as claimed in claim 1, characterized in that: The head side of the first component is oriented to face a first direction substantially orthogonal to the top side of the substrate, or to face a second direction substantially opposite to the first direction, or to face a third direction substantially orthogonal to the first direction.

4. The semiconductor device as claimed in claim 1, characterized in that, The head side of the first component is oriented at the 12 o'clock position in a top view facing the substrate.

5. The semiconductor device as claimed in claim 1, characterized in that, The head side of the first component is oriented at the 3 o'clock position in a top view facing the substrate.

6. The semiconductor device as claimed in claim 1, characterized in that, The head side of the first component is oriented at the 6 o'clock position in a top view facing the substrate.

7. The semiconductor device as claimed in claim 1, characterized in that, The head side of the first component is oriented at the 9 o'clock position in a top view facing the substrate.

8. The semiconductor device as claimed in claim 1, characterized in that: The substrate conductive structure includes a third substrate terminal located on the top side of the substrate; and The semiconductor device includes: A second antenna assembly, coupled to the substrate and comprising: Second component head side; The dielectric structure of the second component; A second component conductive structure, the second component conductive structure including a second component terminal and in contact with the second component dielectric structure; and The second antenna pattern is located at the head side of the second component and is grouped with the second component terminals and the second component conductive structure; in: The second antenna assembly is coupled to the substrate outside the coverage area of ​​the electronic component; and The second component terminal is coupled to the third substrate terminal.

9. The semiconductor device as claimed in claim 8, characterized in that, The first component head side is oriented to face a first direction substantially parallel to the top side of the substrate, and the second component head side is oriented to face a second direction substantially opposite to the first direction.

10. The semiconductor device as claimed in claim 8, characterized in that, The first component head side is oriented to face a first direction substantially parallel to the top side of the substrate, and the second component head side is oriented to face a second direction substantially orthogonal to the first direction and substantially parallel to the top side of the substrate.

11. The semiconductor device as claimed in claim 8, characterized in that, The first component head side is oriented to face a first direction substantially parallel to the top side of the substrate, and the second component head side is oriented to face a second direction substantially orthogonal to the first direction and substantially orthogonal to the top side of the substrate.

12. The semiconductor device as claimed in claim 1, characterized in that, The electronic component is coupled to the bottom side of the substrate, and also includes a passive component of the substrate coupled to the top of the electronic component.

13. The semiconductor device as claimed in claim 8, characterized in that, include: A passive component, the passive component being coupled to the top side of the substrate located between the first antenna assembly and the second antenna assembly.

14. The semiconductor device as claimed in claim 1, characterized in that, include: Encapsulation material, the encapsulation material being located on the top side of the substrate and in contact with the side of the electronic component; The first antenna pattern does not extend beyond the top side of the envelope.

15. The semiconductor device as claimed in claim 1, characterized in that, include: Encapsulation material, the encapsulation material being located on the top side of the substrate and in contact with the side of the electronic component; The first antenna pattern extends below the top side of the envelope.

16. The semiconductor device as claimed in claim 1, characterized in that, The first component's conductive structure includes a vertical through-hole and a horizontal trace.

17. The semiconductor device as claimed in claim 1, characterized in that, The bottom side of the conductive structure of the first component is substantially flush with the bottom side of the dielectric structure of the first component.

18. The semiconductor device as claimed in claim 1, characterized in that, The first component conductive structure contacts the top side of the substrate.

19. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising: Top side of the substrate; Bottom side of the substrate; A substrate dielectric structure, the substrate dielectric structure being located between the top side and the bottom side of the substrate; and A substrate conductive structure, the substrate conductive structure passing through the substrate dielectric structure and comprising: First substrate terminal; and The second substrate terminal is located on the top side of the substrate. An electronic component is coupled to the substrate, the electronic component comprising: Component terminals coupled to the first substrate terminals; and A first antenna assembly is coupled to the substrate, the first antenna assembly comprising: First component head side; First component dielectric structure; A first component conductive structure, the first component conductive structure including a first component terminal and in contact with the first component dielectric structure; and A first antenna pattern is located at the head side of the first component and is grouped with the first component terminals and the first component conductive structure; in: The first antenna assembly is coupled to the substrate outside the coverage area of ​​the electronic component; and The first component terminal is coupled to the second substrate terminal.

20. The method as described in claim 19, characterized in that, In a top view of the substrate, the head side of the first component is oriented to face the 12 o'clock, 3 o'clock, 6 o'clock, or 9 o'clock direction.

21. A semiconductor device, characterized in that, include: A substrate, the substrate comprising a top side and a bottom side, a substrate dielectric structure and a substrate conductive structure; An electronic component, the electronic component being located above the top side of the substrate and coupled to the conductive structure of the substrate; A first antenna conductive structure is located below the bottom side of the substrate and coupled to the substrate conductive structure; as well as A first antenna pattern is located below the bottom side of the substrate and coupled to the first antenna conductive structure.

22. The semiconductor device according to claim 21, characterized in that, include: An interconnect structure located on the top side of the substrate and coupled to the conductive structure of the substrate.

23. The semiconductor device according to claim 21, characterized in that, include: A shielding component covering the electronic components.

24. The semiconductor device according to claim 21, characterized in that: The first antenna pattern is configured to radiate along a direction parallel to the bottom side of the substrate.

25. The semiconductor device according to claim 21, characterized in that: The first antenna pattern is configured to radiate in a direction perpendicular to the bottom side of the substrate.

26. The semiconductor device according to claim 21, characterized in that, include: An insulator surrounding the first antenna conductive structure.

27. The semiconductor device according to claim 21, characterized in that, include: A second antenna conductive structure located below the bottom side of the substrate and coupled to the conductive structure of the substrate; as well as The second antenna pattern is located below the bottom side of the substrate and is coupled to the second antenna pattern.

28. The semiconductor device according to claim 21, characterized in that: The first antenna conductive structure includes a horizontal conductive structure and a vertical conductive structure.

29. A method for manufacturing a semiconductor device, characterized in that, include: A substrate including a top side and a bottom side, a substrate dielectric structure, and a substrate conductive structure is provided; An electronic component is disposed above the top side of the substrate and coupled to the conductive structure of the substrate; A first antenna conductive structure is disposed below the bottom side of the substrate and coupled to the substrate conductive structure; as well as A first antenna pattern is provided below the bottom side of the substrate and coupled to the first antenna conductive structure.

30. The method according to claim 29, characterized in that, include: An interconnect structure is provided on the top side of the substrate and coupled to the conductive structure of the substrate.

31. The method according to claim 29, characterized in that, include: A shielding device is provided to cover the electronic components.

32. The method according to claim 29, characterized in that: The first antenna pattern is configured to radiate along a direction parallel to the bottom side of the substrate.

33. The method according to claim 29, characterized in that: The first antenna pattern is configured to radiate along a direction perpendicular to the bottom side of the substrate.

34. The method according to claim 29, characterized in that, include: An insulator is provided around the conductive structure of the first antenna.

35. The method according to claim 29, characterized in that, include: A second antenna conductive structure is disposed below the bottom side of the substrate and coupled to the substrate conductive structure; as well as A second antenna pattern is provided below the bottom side of the substrate and coupled to the second antenna pattern.

36. The method according to claim 29, characterized in that: The first antenna conductive structure includes a horizontal conductive structure and a vertical conductive structure.

37. A semiconductor device, characterized in that, include: A first substrate, the first substrate including a first side and a second side, a first substrate dielectric structure and a first substrate conductive structure; An electronic component, the electronic component being located on the first side of the first substrate and coupled to the conductive structure of the first substrate; A first interconnect structure is located on the first side of the first substrate and coupled to the conductive structure of the first substrate. A first antenna conductive structure, wherein the first antenna conductive structure is coupled to the first substrate conductive structure; A first antenna pattern, coupled to a first antenna conductive structure, wherein the first antenna pattern is configured to radiate along a first direction perpendicular to the first substrate; A second antenna conductive structure, wherein the second antenna conductive structure is coupled to the first substrate conductive structure; and A second antenna pattern is coupled to a second antenna conductive structure, wherein the second antenna pattern is configured to radiate along a second direction parallel to the first substrate.

38. The semiconductor device according to claim 37, characterized in that, include: A shielding component covering the electronic components.

39. The semiconductor device according to claim 37, characterized in that, include: An insulator surrounding the first antenna conductive structure.

40. The semiconductor device according to claim 37, characterized in that, include: A second interconnect structure extending from the first substrate and coupled to the conductive structure of the first substrate.

41. A semiconductor device, characterized in that, include: The substrate includes a top side and a bottom side of the substrate; An electronic component, the electronic component being coupled to the substrate; A first antenna assembly is coupled to the top side of the substrate; A second antenna assembly is coupled to the top side of the substrate; A passive component, the passive component being coupled to the top side of the substrate between the first antenna assembly and the second antenna assembly.

42. The semiconductor device according to claim 41, characterized in that, The electronic component is coupled to the top side of the substrate; the electronic component is located on the opposite side of the passive component along a first direction; and in a second direction, the electronic component is located between the first antenna assembly and the second antenna assembly; and the first direction and the second direction are perpendicular.

43. The semiconductor device according to claim 41, characterized in that, The passive components are arranged in a matrix of rows or columns on the top side of the substrate.

44. The semiconductor device according to claim 41, characterized in that, The electronic component is coupled to the bottom side of the substrate and to the top of the passive component.

45. The semiconductor device according to any one of claims 42 to 44, characterized in that, The substrate includes: A substrate dielectric structure, the substrate dielectric structure being located between the top side and the bottom side of the substrate; and A substrate conductive structure, the substrate conductive structure passing through the substrate dielectric structure and comprising: First substrate terminal; A second substrate terminal, a third substrate terminal, and a fourth substrate terminal; wherein the second substrate terminal, the third substrate terminal, and the fourth substrate terminal are located on the top side of the substrate; The electronic component includes component terminals, which are coupled to the first substrate terminals; The first antenna assembly includes a first component terminal, and the first component terminal is coupled to the second substrate terminal; The second antenna assembly includes a second component terminal, and the second component terminal is coupled to the third substrate terminal; The passive component includes a terminal, which is coupled to the fourth substrate terminal.

46. ​​The semiconductor device according to claim 45, characterized in that, The first antenna assembly includes: First component head side; First component dielectric structure; A first component conductive structure, the first component conductive structure including a first component terminal and in contact with a first component dielectric structure; and A first antenna pattern is located at the head side of the first component and is grouped with the first component terminals and the first component conductive structure; Wherein: the first antenna assembly is coupled to the substrate outside the coverage area of ​​the electronic component; The second antenna assembly includes: Second component head side; The dielectric structure of the second component; A second component conductive structure, the second component conductive structure including a second component terminal and in contact with a second component dielectric structure; and The second antenna pattern is located at the head side of the second component and is grouped with the second component terminals and the second component conductive structure; Wherein: the second antenna assembly is coupled to the substrate outside the coverage area of ​​the electronic component.

47. The semiconductor device according to any one of claims 42 to 44, characterized in that, The semiconductor device further includes an encapsulation located on the top side of the substrate and in contact with the top and side surfaces of the passive component, the side surfaces of the first antenna assembly, and the second antenna assembly.

48. A method for manufacturing a semiconductor device, characterized in that, include: The first antenna assembly and the second antenna assembly are attached to the carrier; The passive component is bonded to the carrier and is located between the first antenna assembly and the second antenna assembly; The encapsulation material covers the carrier, the passive component, the first antenna assembly, and the second antenna assembly; Remove the carrier to expose the first antenna assembly, the second antenna assembly, the passive component, and the encapsulation. A substrate including a top side and a bottom side is formed, and the first antenna assembly, the second antenna assembly, and the passive component are coupled to the top side of the substrate; The electronic component is coupled to the bottom side of the substrate and is located above the passive component.

49. The method according to claim 48, characterized in that, The first antenna assembly and the second antenna assembly include conductive patterns, and the passive component includes terminals; The formed substrate includes a first dielectric structure, a conductive structure, and a second dielectric structure; wherein, The first dielectric structure covers the top surfaces of the first antenna assembly and the second antenna assembly, the top surface of the passive component, and the top surface of the encapsulation, and exposes the conductive pattern and the terminals via holes; The conductive structure covers the top surface of the first dielectric structure exposed through the aperture, the conductive pattern, and the terminal; The second dielectric structure covers the first dielectric structure and the conductive structure, and exposes the top surface of the conductive structure via a hole.

50. The method according to claim 49, characterized in that, The electronic component is coupled to the substrate through the top surface of the conductive structure.

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