Semiconductor chip and installation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and discloses a semiconductor chip and a mounting method thereof.The semiconductor chip comprises a substrate, a chip function layer, an insulating layer and a plurality of first mounting sites, one face of the substrate serves as an arrangement face, and the first mounting sites are arranged on the chip function layer extending to the face away from the arrangement face; the first mounting site is electrically connected with the chip function layer. The semiconductor chip is connected with the outside by adopting the design of the first mounting site, a traditional pin structure is canceled, the problem of cracks of an insulating layer caused by stress generated by thickness tolerance of the substrate and the pins during plastic packaging is fundamentally avoided, and the product reliability is remarkably improved; besides, pin purchasing and rib cutting forming equipment using are not needed in manufacturing, material and equipment cost is greatly reduced, the risk of chip functional layer electrostatic breakdown caused by mistakenly touching the pins in transportation and production is also reduced due to the pin-free design, and safety is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a semiconductor chip and a mounting method thereof. BACKGROUND

[0002] In the field of semiconductor chip manufacturing, there are many technical problems in the production process of semi-encapsulated products. In order to ensure that the exposed back surface of the substrate can be closely attached to the inner surface of the mold cavity, the industry generally uses the method of using a pin to press against the front surface of the substrate in the plastic packaging link to promote the attachment of the back surface of the substrate to the mold cavity, thereby preventing the occurrence of glue overflow phenomenon. However, due to the thickness tolerance of the circuit metal substrate needs to meet the industry standard of ±10% (i.e. the deviation of the actual thickness of the substrate from the designed thickness is controlled within ±10%), the pressure applied by the pin will be uneven due to the difference in the thickness of the substrate. This uneven stress will cause stress between the substrate and the pin, and then cause cracks in the insulating layer, which seriously affects the reliability of the product. There are also deficiencies in the installation process of traditional semiconductor chips with pins on the electric control board. The existing scheme uses the wave soldering welding method for installation, which has low efficiency, and is prone to problems such as virtual welding and missed welding during the welding process, affecting the stability of the connection between the semiconductor chip and the electric control board. At the same time, the semiconductor chip with pins needs to specially purchase pins and use special cutting and forming equipment to process the pins, which undoubtedly increases the material cost and equipment investment cost of production. In addition, the pins of the semiconductor chip with pins are easy to be touched by mistake during transportation and production, which causes the problem of electrostatic breakdown of the chips inside the semiconductor chip, seriously affecting the quality and safety of the semiconductor chip. SUMMARY

[0003] The present application aims to improve at least one technical problem in the background art.

[0004] The first aspect of the present application provides a semiconductor chip, comprising: a substrate, one side of the substrate serving as a layout surface, and two sides of the substrate each forming an extension extending outwardly; a chip functional layer, the chip functional layer being disposed on the layout surface, and the chip functional layer extending along the extension to a side away from the layout surface to form a chip functional layer extension end; an insulating layer, the insulating layer being disposed between the chip functional layer and the substrate; a plurality of first mounting sites, the first mounting sites being disposed on the chip functional layer extension end, and the first mounting sites being electrically connected to the chip functional layer.

[0005] The beneficial effects of a semiconductor chip according to the first aspect of the present invention are as follows: The semiconductor chip of the present invention uses a first mounting point design to connect to the outside, eliminating the traditional pin structure, fundamentally avoiding the problem of insulation layer cracking caused by stress due to thickness tolerance between the substrate and the pin during molding, and significantly improving product reliability; in addition, there is no need to purchase pins and use lead cutting and forming equipment in the manufacturing process, which greatly reduces material and equipment costs. The pinless design also reduces the risk of electrostatic breakdown of the chip functional layer caused by accidental contact with pins during transportation and production, thus improving safety.

[0006] Furthermore, a gap is formed between the extended end of the chip functional layer and the side surface of the substrate.

[0007] Furthermore, several of the first mounting sites are spaced apart.

[0008] Furthermore, the substrate is a metal substrate, and a heat dissipation structure is formed on the side away from the arrangement surface, and the heat dissipation structure is fixedly connected to the substrate.

[0009] Furthermore, the heat dissipation structure is an array of heat dissipation fins, which are fixedly connected to the substrate.

[0010] Furthermore, the chip functional layer includes a circuit wiring layer and a circuit component assembly. The circuit wiring layer is disposed on the arrangement surface and extends along the extension portion to a side away from the arrangement surface, forming a circuit wiring layer extension end. The insulating layer is disposed between the circuit wiring layer and the substrate. The first mounting point is disposed on the circuit wiring layer extension end and is electrically connected to the circuit wiring layer. The circuit component assembly is disposed on the circuit wiring layer located on the arrangement surface and is electrically connected to the circuit wiring layer.

[0011] Furthermore, a green solder mask layer is provided on the circuit wiring layer, which is used to protect the circuit wiring layer.

[0012] Furthermore, the circuit component assembly is connected to the circuit wiring layer via wires.

[0013] Furthermore, the semiconductor chip also includes a molding compound that covers the functional layer of the chip, and the first mounting point extends outward from the molding compound.

[0014] A second aspect of the present invention provides a method for mounting the semiconductor chip described above, wherein the electronic control board has semiconductor chip mounting holes and a plurality of second mounting points corresponding to the first mounting points, the second mounting points being located on both sides of the semiconductor chip mounting holes, and the mounting method includes the following steps: Apply solder paste to the first mounting point; Align the semiconductor chip with the semiconductor chip mounting hole, and align the first mounting point with the second mounting point; The semiconductor chip is mounted on the electronic control board; The semiconductor chip is installed on the electronic control board by reflow soldering.

[0015] The beneficial effects of the semiconductor chip mounting method of the second aspect of the present invention are as follows: the mounting method has simple steps and does not require the complex positioning and processing procedures for pins as in traditional semiconductor chips; at the same time, the mounting method is perfectly adapted to the mass production characteristics of SMT (Surface Mount Technology), and through the automated production line of SMT, the entire process of continuous operation of semiconductor chips and other surface mount components on the control board from solder paste application, component mounting to reflow soldering can be realized, reducing manual intervention and lowering the operational difficulty and error rate in the production process. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of a semiconductor chip that is not encapsulated, according to one embodiment. Figure 2 This is a schematic diagram of the heat dissipation structure of a semiconductor chip according to one embodiment; Figure 3 This is a schematic diagram of the structure of a plastic-encapsulated semiconductor chip according to one embodiment; Figure 4 This is a schematic diagram of the structure of an electronic control board in one embodiment; Figure 5 This is a schematic diagram of a semiconductor chip mounted on an electronic control board, as shown in one embodiment.

[0017] In the attached figures: 100-substrate; 101-extension; 102-gap; 103-heat sink fins; 200-insulating layer; 300-circuit wiring layer; 400-first mounting point; 501-component; 502-high-power component; 503-surface resistor; 504-surface capacitor; 505-heat sink; 600-wire; 700-molding package; 800-semiconductor chip; 900-control board; 901-semiconductor chip mounting hole; 902-second mounting point. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0020] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0021] The following is combined Figures 1 to 5 Embodiments of the present invention will be described.

[0022] This invention provides a semiconductor chip, comprising: The substrate 100 has one side as an arrangement surface and extension portions 101 extending outward are formed on both sides of the substrate 100. A chip functional layer is disposed on the arrangement surface, and the chip functional layer extends along the extension 101 to a side away from the arrangement surface to form a chip functional layer extension end; An insulating layer 200 is disposed between the chip functional layer and the substrate 100; A plurality of first mounting points 400 are disposed on the extended end of the chip functional layer and are electrically connected to the chip functional layer.

[0023] The semiconductor chip in this embodiment does not have a traditional pin structure. Instead, it achieves electrical connection with the outside by providing extensions 101 on both sides of the substrate 100, and extending the chip functional layer along the extensions 101 to the side of the substrate 100 away from the placement surface. A first mounting point 400 is then provided on the chip functional layer extending to this side (the extended end of the chip functional layer) to achieve electrical connection. This structural design fundamentally avoids the problem of stress caused by thickness tolerances between the substrate 100 and the pins during molding of traditional pin-based semiconductor chips, which can lead to cracks in the insulating layer 200, thus improving the reliability of the semiconductor chip. Secondly, since no pins are required, there is no need to specially purchase pins or use lead-cutting equipment to process them, reducing material procurement costs and equipment investment costs in semiconductor chip manufacturing. Furthermore, due to the absence of a pin structure, the semiconductor chip will not experience electrostatic discharge (ESD) damage to the chip functional layer caused by accidental contact with pins during transportation and production, reducing the risk of ESD damage and improving the safety of the semiconductor chip during its transfer process. Furthermore, a gap 102 is formed between the extended end of the chip functional layer and the side surface of the substrate 100.

[0024] In this embodiment, the presence of the gap 102 effectively prevents direct contact between the chip functional layer and the side of the substrate 100, physically cutting off unnecessary conductive paths between them, thereby avoiding short-circuit risks and ensuring the electrical safety and stability of the circuit. Simultaneously, this gap 102 provides a more reliable environment for stable circuit operation. Even if the substrate 100 or the chip functional layer experiences slight positional shifts during production or use, the gap 102 can act as a buffer, reducing the possibility of accidental contact and short circuits due to shifts, further improving the electrical reliability of the product.

[0025] Furthermore, several of the first mounting points are spaced 400 apart.

[0026] In this embodiment, the spaced first mounting points 400 can, on the one hand, avoid signal interference or short circuits when connected to external circuits, ensuring the stability and accuracy of electrical connections and improving the working performance of semiconductor chips; on the other hand, the spaced first mounting points 400 facilitate the subsequent installation of semiconductor chips on the control board 900. The spaced mounting points are easier for automated equipment to identify and locate, reducing installation errors and improving installation efficiency and quality. At the same time, when it is necessary to repair or replace individual first mounting points 400, the spaced layout also facilitates operation, reduces the impact on other first mounting points 400, and enhances the maintainability of semiconductor chips.

[0027] Furthermore, the substrate 100 is a metal substrate, and a heat dissipation structure is formed on the side away from the arrangement surface, and the heat dissipation structure is fixedly connected to the substrate 100.

[0028] As the integration requirements of semiconductor chips continue to increase, they generate a large amount of heat during operation. If this heat cannot be dissipated in time, the temperature of the semiconductor chip will rise, affecting its performance and even shortening its lifespan. In this embodiment, a heat dissipation structure is formed on the side of the semiconductor chip away from the mounting surface on the substrate 100 (a metal substrate, such as an aluminum substrate, copper substrate, alloy material substrate, etc.). This accelerates heat conduction and dissipation, effectively solving the high heat dissipation problem caused by high integration and ensuring the stability and reliability of the semiconductor chip during long-term operation. Furthermore, the heat dissipation structure of the semiconductor chip in this embodiment is directly formed on the substrate 100, eliminating the need for an additional heat sink on the semiconductor chip surface, simplifying the manufacturing process, improving manufacturing efficiency, and reducing overall manufacturing costs. In addition, this heat dissipation structure can also be used to position the semiconductor chip when it is mounted on the control board 900, eliminating the need for positioning via pins or external brackets as in traditional solutions. This further reduces the use of related components, lowers production costs, and improves the convenience and accuracy of positioning.

[0029] Furthermore, the heat dissipation structure is an array of heat dissipation fins 103, which are fixedly connected to the substrate 100.

[0030] In this embodiment, the heat dissipation structure is an array of heat dissipation fins 103. This structure maximizes the heat dissipation area and, compared to other forms of heat dissipation structures, can more efficiently transfer the heat generated by the circuit operation to the surrounding environment, significantly improving heat dissipation efficiency. Furthermore, from a manufacturing perspective, the array of heat dissipation fins 103 facilitates mass production using standardized processing techniques, offering greater controllability in the manufacturing process. This helps ensure the consistency and stability of the heat dissipation structure and reduces the defect rate during manufacturing.

[0031] Further, the chip functional layer includes a circuit wiring layer 300 and a circuit component assembly. The circuit wiring layer 300 is disposed on the arrangement surface and extends along the extension portion 101 to a side away from the arrangement surface, forming a circuit wiring layer extension end. The insulating layer 200 is disposed between the circuit wiring layer 300 and the substrate 100. The first mounting point 400 is disposed on the circuit wiring layer extension end and is electrically connected to the circuit wiring layer 300. The circuit component assembly is disposed on the circuit wiring layer 300 located on the arrangement surface and is electrically connected to the circuit wiring layer 300.

[0032] In this embodiment, the clear separation between the circuit wiring layer 300 and the circuit component assembly makes the circuit function implementation more targeted and reliable. The circuit wiring layer 300 is specifically responsible for constructing electrical connection paths. Its design, which extends along the extension portion 101 to the side away from the placement surface and sets the first mounting point 400, ensures a more stable connection path and better conductivity with external circuits. Meanwhile, the circuit component assembly is concentrated on the circuit wiring layer 300 on one side of the placement surface, which can directly form an efficient electrical connection with the wiring layer. This reduces the signal loss or poor contact problems that may occur in the indirect connection between components and pins in traditional structures, and improves the overall working performance of the circuit.

[0033] Furthermore, a green solder mask layer is provided on the circuit wiring layer 300, which is used to protect the circuit wiring layer 300.

[0034] In this embodiment, the circuit wiring layer 300 serves as the core conductive path of the semiconductor chip, and its integrity directly affects the electrical performance and lifespan of the circuit. The application of a solder mask layer on the circuit wiring layer is based on the specific protection requirements of the circuit wiring layer 300: the solder mask layer is an insulating material that can tightly cover the surface of the wiring layer, forming a physical barrier. During the manufacturing process, the solder mask layer can prevent foreign objects from scratching or contaminating the circuit wiring layer 300 during welding, assembly, and other processes; during use, it can effectively isolate the circuit wiring layer 300 from moisture in humid environments, corrosive gases in the air, and external mechanical wear, reducing the risks of oxidation and breakage of the circuit wiring layer 300.

[0035] Furthermore, the circuit component assembly is connected to the circuit wiring layer 300 via a wire 600.

[0036] In this embodiment, the circuit component assembly and the circuit wiring layer 300 are connected by a wire 600. This connection is designed to adapt to the installation positions and connection requirements of different component assemblies, improving the flexibility and reliability of the connection. The wire 600 has a certain length and flexibility, allowing the connection path to be flexibly adjusted according to the installation position of the component assembly on the layout surface. It is particularly suitable for connecting components of different specifications and installation heights within the circuit component assembly to the circuit wiring layer 300. In this embodiment, the wire 600 is a copper wire; in other embodiments, gold wire, aluminum wire, etc., can also be used.

[0037] Furthermore, the circuit component assembly includes a surface mount resistor 503, a surface mount capacitor 504, a component 501, and a high-power component 502.

[0038] Among them, component 501 and high-power component 502 are composed of chips required for various internal functional circuits of semiconductor chip; surface mount resistor 503 is connected at the gate of IGBT chip in semiconductor chip, and achieves the function of limiting switching speed by limiting current; surface mount capacitor 504 plays the role of filtering, coupling and bootstrapping in semiconductor chip.

[0039] Furthermore, a heat sink 505 is provided between the high-power component 502 and the circuit wiring layer 300.

[0040] In this embodiment, the heat sink 505 is a copper heat sink with silver plating. Copper has excellent thermal conductivity and can quickly absorb the heat generated by the high-power component 502 and transfer it to the substrate 100 (and its heat dissipation structure). The silver plating not only enhances the conductivity of the heat sink 505 (facilitating good electrical contact with components and wiring layers), but also improves its corrosion resistance and oxidation resistance, extending the service life of the heat sink 505.

[0041] Furthermore, the semiconductor chip also includes a molding compound 700, which covers the functional layer of the chip, and the first mounting point 400 extends outward from the molding compound 700.

[0042] In this embodiment, the molding compound 700 is composed of epoxy resin, phenolic resin, silica powder, and additives. Epoxy resin serves as the base resin, providing the basic structure and mechanical strength of the molding compound 700. Phenolic resin acts as a curing agent, reacting chemically with the epoxy resin to form a cross-linked structure, thereby curing and molding. Silica powder acts as a filler, increasing the volume stability of the molding compound 700 and improving its thermal conductivity and electrical insulation properties. In this embodiment, the first mounting point 400 extends outward from the molding compound 700; that is, the first mounting point 400 is not filled by the molding compound 700 during molding. This ensures that the molding compound 700 protects the chip's functional layer without affecting the connection between the chip's functional layer and the outside world via the first mounting point 400.

[0043] The semiconductor chip manufacturing method of this embodiment includes the following steps: A heat dissipation structure is formed on the side of the substrate 100 away from the arrangement surface; The insulating layer 200 is pressed with the copper foil layer to obtain a pressed semi-finished product. Then the pressed semi-finished product is pressed with the substrate 100, wherein one side of the insulating layer 200 in the pressed semi-finished product faces the arrangement surface of the substrate 100. The copper foil layer is etched to obtain the circuit wiring layer 300; A green solder mask is formed on the surface of the circuit wiring layer 300, and the green solder mask avoids the preset positions of the circuit components. The substrate 100 is placed on a carrier (in this embodiment, the carrier is a ceramic material that can withstand temperatures above 200°C; in other embodiments, the carrier may also be made of aluminum, polyphenylene sulfide, synthetic stone, or other materials). Solder paste is applied to the preset positions of the circuit component assembly, and the circuit component assembly is then mounted to its preset positions using an automatic die bonding device (wherein the components are first mounted to the silver-plated copper heat sink 505 using a soft solder die bonder). The carrier carries the substrate 100 into the reflow oven to solder all the circuit components to the corresponding preset positions, solder the first pin to the pad, and inspect the soldering quality of the circuit components using visual inspection equipment (AOI optical inspection instrument). The flux and aluminum shavings remaining on the substrate 100 are removed by spraying and ultrasonic cleaning methods. Electrical connections are formed between the circuit component assembly and the circuit wiring layer 300 via wires 600; Perform molding to form a molding body 700 (during molding, the first mounting point 400 is not filled by the molding body 700). After completing the electrical parameter tests, a semiconductor chip is obtained.

[0044] This embodiment also provides the above-described semiconductor chip mounting method. The control board 900 has semiconductor chip mounting holes 901 and a plurality of second mounting points 902 corresponding to the first mounting points 400. The second mounting points 902 are located on both sides of the semiconductor chip mounting holes 901. The mounting method includes the following steps: Apply solder paste to the first mounting point 400; Align the semiconductor chip 800 with the semiconductor chip mounting hole 901, and align the first mounting point 400 with the second mounting point 902; The semiconductor chip 800 is mounted on the electronic control board 900; The semiconductor chip 800 is installed on the electronic control board 900 by reflow soldering.

[0045] The semiconductor chip mounting method on the control board 900 provided in this embodiment relies on the aforementioned semiconductor chip without traditional pin structures. Connection is achieved through the first mounting point 400 and the second mounting point 902 on the control board 900, using a reflow soldering method (the soldering method of surface mount devices going through a reflow oven). This process perfectly aligns with the core workflow of SMT and can be performed simultaneously with the mounting of other components on the control board 900. This embodiment uses SMT technology to replace the traditional wave soldering method for through-hole semiconductor chips with pins (traditional wave soldering requires pin insertion, a cumbersome and time-consuming process). It enables rapid positioning and placement of semiconductor chips using automated mounting equipment, significantly shortening the installation process time and improving efficiency. The solder paste used in the method for mounting the semiconductor chip on the control board 900 provided in this embodiment can be either solder paste or silver paste. During the reflow soldering process, the solder paste melts and solidifies uniformly at high temperature, which enables a strong electrical connection and mechanical fixation between the first mounting point 400 and the second mounting point 902. Compared with wave soldering, this method can reduce soldering defects such as cold solder joints and missing solder joints, and improve the stability of the connection between the semiconductor chip and the control board 900. The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of the present invention.

Claims

1. A semiconductor chip, characterized in that, include: A substrate, one side of which serves as an arrangement surface, and extension portions extending outward are formed on both sides of the substrate. A chip functional layer is disposed on the arrangement surface, and the chip functional layer extends along the extension to a side away from the arrangement surface to form a chip functional layer extension end; An insulating layer is disposed between the chip functional layer and the substrate; A plurality of first mounting sites are disposed on the extended end of the chip functional layer and are electrically connected to the chip functional layer.

2. The semiconductor chip according to claim 1, characterized in that, A gap is formed between the extended end of the chip's functional layer and the side surface of the substrate.

3. The semiconductor chip according to claim 1, characterized in that, Several first mounting sites are spaced apart.

4. The semiconductor chip according to claim 1, characterized in that, The substrate is a metal substrate, and a heat dissipation structure is formed on the side away from the arrangement surface. The heat dissipation structure is fixedly connected to the substrate.

5. The semiconductor chip according to claim 4, characterized in that, The heat dissipation structure consists of an array of heat dissipation fins, which are fixedly connected to the substrate.

6. The semiconductor chip according to claim 1, characterized in that, The chip functional layer includes a circuit wiring layer and a circuit component assembly. The circuit wiring layer is disposed on the arrangement surface and extends along the extension portion to a side away from the arrangement surface, forming a circuit wiring layer extension end. The insulating layer is disposed between the circuit wiring layer and the substrate. The first mounting point is disposed on the circuit wiring layer extension end and is electrically connected to the circuit wiring layer. The circuit component assembly is disposed on the circuit wiring layer located on the arrangement surface and is electrically connected to the circuit wiring layer.

7. The semiconductor chip according to claim 6, characterized in that, The circuit wiring layer is provided with a green solder mask layer, which is used to protect the circuit wiring layer.

8. The semiconductor chip according to claim 6, characterized in that, The circuit component assembly is connected to the circuit wiring layer via wires.

9. The semiconductor chip according to claim 1, characterized in that, The semiconductor chip also includes a molding compound that covers the chip's functional layer, and the first mounting point extends out of the molding compound.

10. A method for mounting a semiconductor chip as described in any one of claims 1 to 9, characterized in that, The electronic control board has semiconductor chip mounting holes and a plurality of second mounting points corresponding to the first mounting points. The second mounting points are located on both sides of the semiconductor chip mounting holes. The mounting method includes the following steps: Apply solder paste to the first mounting point; Align the semiconductor chip with the semiconductor chip mounting hole, and align the first mounting point with the second mounting point; The semiconductor chip is mounted on the electronic control board; The semiconductor chip is installed on the electronic control board by reflow soldering.

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